Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the same include: a substrate including a plurality of unit regions, each unit region including first, second, third, and fourth raised structures arranged along a first direction, the first raised structure including a first region and a second region, the fourth raised structure including a third region and a fourth region, the central axes of the first and second regions not overlapping, and the central axes of the third and fourth regions not overlapping; and first, second, third, and fourth gate structures located on the substrate, the first gate structure spanning the first region, the second raised structure, and the third raised structure, the second gate structure spanning the third region, the third gate structure spanning the second region, and the fourth gate structure spanning the second raised structure, the third raised structure, and the fourth region, the central axes of the first and second gate structures overlapping in the first direction, and the central axes of the third and fourth gate structures overlapping in the first direction. The semiconductor structure has a relatively small area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] Static Random-Access Memory (SRAM) has the characteristics of high speed and low power consumption, and is widely used in personal communications and consumer electronics.

[0003] A basic unit of a static random access memory generally includes six transistors: two pull-up transistors (PU), two pull-down transistors (PD), and two pass-gate transistors (PG). The six transistors are formed on four fins.

[0004] However, the area of the existing static random access memory needs to be further optimized to achieve a smaller size. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure so as to optimize the area of a static random access memory.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a plurality of unit areas, the unit area comprising a first convex structure, a second convex structure, a third convex structure and a fourth convex structure arranged in sequence along a first direction, the first convex structure, the second convex structure, the third convex structure and the fourth convex structure are parallel to a second direction, the first direction and the second direction are parallel to the substrate surface, and the second direction is perpendicular to the first direction, the first convex structure comprises a first area and a second area arranged along an extension direction of the first convex structure, the fourth convex structure comprises a third area and a fourth area arranged along an extension direction of the fourth convex structure, the central axes of the first area and the second area in the second direction do not overlap, and the central axes of the third area and the fourth area in the second direction are parallel to each other. do not overlap, the spacing between the second area and the second protruding structure is greater than the spacing between the first area and the second protruding structure, and the spacing between the fourth area and the third protruding structure is greater than the spacing between the third area and the third protruding structure; a first gate structure, a second gate structure, a third gate structure and a fourth gate structure are located on the substrate parallel to the first direction, the first gate structure spans the first area, the second protruding structure and the third protruding structure, the second gate structure spans the third area, the third gate structure spans the second area, the fourth gate structure spans the second protruding structure, the third protruding structure and the fourth area, the central axes of the first gate structure and the second gate structure in the first direction coincide, and the central axes of the third gate structure and the fourth gate structure in the first direction coincide.

[0007] Optionally, it further includes: a first isolation structure and a second isolation structure located on the substrate, the first isolation structure is located between the first gate structure and the second gate structure, and the second isolation structure is located between the third gate structure and the fourth gate structure.

[0008] Optionally, the first protruding structure includes a plurality of first channel layers that are separate and vertically stacked, and the first channel layer includes at least two layers; the second protruding structure includes a plurality of second channel layers that are separate and vertically stacked, and the second channel layer includes at least two layers; the third protruding structure includes a plurality of third channel layers that are separate and vertically stacked, and the third channel layer includes at least two layers; the fourth protruding structure includes a plurality of fourth channel layers that are separate and vertically stacked, and the fourth channel layer includes at least two layers; the first area and the second area of the first protruding structure are not adjacent, and the third area and the fourth area of the fourth protruding structure are not adjacent.

[0009] Optionally, the first channel layer includes nanowires or nanosheets; the second channel layer includes nanowires or nanosheets; the third channel layer includes nanowires or nanosheets; and the fourth channel layer includes nanowires or nanosheets.

[0010] Optionally, the first gate structure surrounds each layer of the first channel layer, each layer of the second channel layer and each layer of the third channel layer; the second gate structure surrounds each layer of the fourth channel layer; the third gate structure surrounds each layer of the first channel layer; and the fourth gate structure surrounds each layer of the fourth channel layer, each layer of the third channel layer and each layer of the second channel layer.

[0011] Optionally, the first area and the second area of the first protruding structure are adjacent to each other, and the third area and the fourth area of the fourth protruding structure are adjacent to each other.

[0012] Optionally, the unit area includes a first unit area and a second unit area adjacent to each other in the first direction, the first unit area and the second unit area are mirror-symmetrical along the second direction, and the fourth protruding structure in the first unit area is adjacent to the fourth protruding structure in the second unit area.

[0013] Optionally, the second gate structure on the first cell area is connected to the second gate structure on the second cell area.

[0014] Optionally, the method further includes: a third isolation structure located between the fourth gate structure of the first unit region and the fourth gate structure of the second unit region.

[0015] Optionally, the length of the second protruding structure is smaller than the length of the fourth protruding structure, the length of the third protruding structure is smaller than the length of the first protruding structure, the second protruding structure includes a first end and a second end opposite to each other, the fourth gate structure is located on the second end, the third protruding structure includes a third end and a fourth end opposite to each other, and the first gate structure is located on the third end.

[0016] Optionally, it also includes: a first source-drain doping region located in the first protruding structure, the first source-drain doping region is located on both sides of the first gate structure and the third gate structure; a second source-drain doping region located in the second protruding structure, the second source-drain doping region is located on both sides of the first gate structure and the fourth gate structure; a third source-drain doping region located in the third protruding structure, the third source-drain doping region is located on both sides of the first gate structure and the fourth gate structure; a fourth source-drain doping region located in the fourth protruding structure, the fourth source-drain doping region is located on both sides of the second gate structure and the fourth gate structure.

[0017] Optionally, it also includes: a first connection layer and a second connection layer located on the substrate parallel to the first direction, the first connection layer electrically connecting the first source and drain doping regions and the second source and drain doping regions, the second connection layer electrically connecting the third source and drain doping regions and the fourth source and drain doping regions, the first connection layer is located between the first gate structure and the third gate structure and the fourth gate structure, and the second connection layer is located between the fourth gate structure, the second gate structure and the first gate structure.

[0018] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of unit areas, the unit area comprising a first convex structure, a second convex structure, a third convex structure and a fourth convex structure arranged in sequence along a first direction, the first convex structure, the second convex structure, the third convex structure and the fourth convex structure are parallel to a second direction, the first direction and the second direction are parallel to the substrate surface, and the second direction is perpendicular to the first direction, the first convex structure comprises an initial first area and an initial second area arranged along an extension direction of the first convex structure, the fourth convex structure comprises an initial third area and an initial fourth area arranged along an extension direction of the fourth convex structure; removing part of the initial first area along the first direction to form a first area, removing part of the initial second area along the first direction to form a second area, removing part of the initial third area along the first direction to form a third area, removing part of the initial fourth area along the first direction to form a third area A fourth region is formed in the region, the central axes of the first region and the second region in the second direction do not overlap, the central axes of the third region and the fourth region in the second direction do not overlap, the spacing between the second region and the second protruding structure is greater than the spacing between the first region and the second protruding structure, and the spacing between the fourth region and the third protruding structure is greater than the spacing between the third region and the third protruding structure; a first gate structure, a second gate structure, a third gate structure and a fourth gate structure are formed on the substrate parallel to the first direction, the first gate structure spans the first region, the second protruding structure and the third protruding structure, the second gate structure spans the third region, the third gate structure spans the second region, the fourth gate structure spans the second protruding structure, the third protruding structure and the fourth region, the central axes of the first gate structure and the second gate structure in the first direction overlap, and the central axes of the third gate structure and the fourth gate structure overlap in the first direction.

[0019] Optionally, the first protruding structure includes a plurality of first vertical stacking structures, the first vertical stacking structure includes a first channel layer and a first sacrificial layer located on the first channel layer; the second protruding structure includes a plurality of second vertical stacking structures, the second vertical stacking structure includes a second channel layer and a second sacrificial layer located on the second channel layer; the third protruding structure includes a plurality of third vertical stacking structures, the third vertical stacking structure includes a third channel layer and a third sacrificial layer located on the third channel layer; the fourth protruding structure includes a plurality of fourth vertical stacking structures, the fourth vertical stacking structure includes a fourth channel layer and a fourth sacrificial layer located on the fourth channel layer; the initial first area and the initial second area of the first protruding structure are not adjacent, and the initial third area and the initial fourth area of the fourth protruding structure are not adjacent.

[0020] Optionally, before forming the first region, the second region, the third region and the fourth region, it also includes: forming a first dummy gate structure and a second dummy gate structure parallel to the first direction on the substrate, the first dummy gate structure spanning the initial first region, the second protruding structure, the third protruding structure and the initial third region, and the second dummy gate structure spanning the initial second region, the second protruding structure, the third protruding structure and the initial fourth region; forming a dielectric structure on the substrate, the first dummy gate structure, the second dummy gate structure, the first protruding structure, the second protruding structure, the third protruding structure and the fourth protruding structure are located within the dielectric structure.

[0021] Optionally, the method further includes: forming a first isolation structure and a second isolation structure on the substrate, wherein the first isolation structure is located between the first gate structure and the second gate structure, and the second isolation structure is located between the third gate structure and the fourth gate structure.

[0022] Optionally, the method of forming the first isolation structure and the second isolation structure includes: removing a portion of the first pseudo gate structure between the third protruding structure and the fourth protruding structure, forming a first groove in the dielectric structure, and the first groove passes through the first pseudo gate structure along the second direction; removing a portion of the second pseudo gate structure between the first protruding structure and the second protruding structure, and forming a second groove in the dielectric structure, and the second groove passes through the second pseudo gate structure along the second direction; forming a first isolation structure in the first groove, and forming a second isolation structure in the second groove.

[0023] Optionally, the method for forming the first region, the second region, the third region and the fourth region includes: removing the first dummy gate structure, forming a first opening and a second opening in the dielectric structure, the first opening and the second opening being located on both sides of the first isolation structure, the first opening exposing the sidewall surface and the top surface of the initial first region, the sidewall surface and the top surface of the second protruding structure portion, and the sidewall surface and the top surface of the third protruding structure portion, and the second opening exposing the sidewall surface and the top surface of the initial third region; removing the second dummy gate structure, forming a third opening and a fourth opening in the dielectric structure, the third opening and the fourth opening being located on both sides of the second isolation structure, the third opening exposing the sidewall surface and the top surface of the initial second region, the fourth opening exposing the sidewall surface and the top surface of the second protruding structure portion, the sidewall surface and the top surface of the third protruding structure portion, and the sidewall surface and the top surface of the initial fourth region; removing the portion of the first channel layer exposed in the initial first region to form the first region, removing the portion of the first channel layer exposed in the initial second region to form the second region, removing the portion of the fourth channel layer exposed in the initial third region to form the third region, and removing the portion of the fourth channel layer exposed in the initial fourth region to form the fourth region.

[0024] Optionally, the method of removing the portion of the first channel layer exposed in the initial first region to form the first region, removing the portion of the first channel layer exposed in the initial second region to form the second region, removing the portion of the fourth channel layer exposed in the initial third region to form the third region, and removing the portion of the fourth channel layer exposed in the initial fourth region to form the fourth region includes: forming a first filling layer in the first opening, the first filling layer exposing the portion of the sidewall of the initial first region facing away from the second protruding structure; forming a second filling layer in the second opening, the second filling layer exposing the portion of the sidewall of the initial third region facing toward the third protruding structure; forming a third filling layer in the third opening, the third filling layer exposing the portion of the sidewall of the initial third region facing away from the third protruding structure; Exposing a portion of the initial second region sidewall facing the second protruding structure; forming a fourth filling layer in the fourth opening, the fourth filling layer exposing a portion of the initial fourth region sidewall facing away from the third protruding structure; using the first filling layer as a mask to remove a portion of the first channel layer to form a first region, using the second filling layer as a mask to remove a portion of the fourth channel layer to form a third region, using the third filling layer as a mask to remove a portion of the first channel layer to form a second region, and using the fourth filling layer as a mask to remove a portion of the fourth channel layer to form a fourth region; after forming the first region, the second region, the third region and the fourth region, removing the first filling layer, the second filling layer, the third filling layer and the fourth filling layer.

[0025] Optionally, the method for forming the first gate structure, the second gate structure, the third gate structure and the fourth gate structure includes: after forming the first region, the second region, the third region and the fourth region, removing the first sacrificial layer, the second sacrificial layer and the third sacrificial layer exposed by the first opening, removing the fourth sacrificial layer exposed by the second opening, removing the first sacrificial layer exposed by the third opening, and removing the fourth sacrificial layer, the second sacrificial layer and the third sacrificial layer exposed by the fourth opening; forming a first gate structure in the first opening, the first gate structure surrounding each layer of the first channel layer, each layer of the second channel layer and each layer of the third channel layer; forming a second gate structure in the second opening, the second gate structure surrounding each layer of the fourth channel layer; forming a third gate structure in the third opening, the third gate structure surrounding each layer of the first channel layer; forming a fourth gate structure in the fourth opening, the fourth gate structure surrounding each layer of the fourth channel layer, each layer of the third channel layer and each layer of the second channel layer.

[0026] Optionally, the initial first region and the initial second region of the first protruding structure are adjacent to each other, and the initial third region and the initial fourth region of the fourth protruding structure are adjacent to each other.

[0027] Optionally, the method of removing part of the initial first region along the first direction to form the first region, removing part of the initial second region along the first direction to form the second region, removing part of the initial third region along the first direction to form the third region, and removing part of the initial fourth region along the first direction to form the fourth region includes: forming a mask layer on the substrate, the mask layer exposing part of the surface of the initial first region facing away from the second convex structure, part of the surface of the initial second region facing the second convex structure, part of the surface of the initial third region facing the third convex structure, and part of the surface of the initial fourth region facing away from the third convex structure; using the mask layer as a mask to remove the exposed part of the initial first region, part of the initial second region, part of the initial third region, and part of the initial fourth region to form the first region, the second region, the third region, and the fourth region.

[0028] Optionally, after forming the first region, the second region, the third region and the fourth region, the method further includes: forming a dielectric structure, a first gate structure, a second gate structure, a third gate structure and a fourth gate structure on the substrate, wherein the first gate structure, the second gate structure, the third gate structure and the fourth gate structure are located within the dielectric structure.

[0029] Optionally, the method further includes: forming a first isolation structure between the first gate structure and the second gate structure, and forming a second isolation structure between the third gate structure and the fourth gate structure.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] In the semiconductor structure of the present invention, because the central axes of the first and second regions in the second direction do not overlap, the spacing between the first region and the second protruding structure is smaller than the spacing between the second region and the second protruding structure. Furthermore, because the central axes of the third and fourth regions in the second direction do not overlap, the spacing between the third region and the third protruding structure is larger than the spacing between the fourth region and the third protruding structure. Consequently, when the mirror-symmetrical first and second unit regions are subsequently formed, the spacing between the fourth gate structure of the first unit region and the fourth gate structure of the second unit region is limited by established design rules. This allows the spacing between the third region of the first unit region and the third region of the second unit region to be smaller than the spacing between the fourth region of the first unit region and the fourth region of the second unit region, thereby reducing the size of the semiconductor structure composed of multiple unit regions in the first direction and achieving a smaller semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of a semiconductor structure in one embodiment;

[0033] Figures 2 to 12is a schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present invention;

[0034] Figures 13 to 16 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0035] As described in the background art, the area of existing static random access memory needs to be further optimized.

[0036] Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure in one embodiment.

[0037] Please refer to Figure 1 , comprising: a substrate 100, the substrate comprising a first unit area I and a second unit area II adjacent to each other in a first direction X, the first unit area I and the second unit area II being mirror-symmetrical along a second direction Y, the first unit area I comprising a first convex structure 101, a second convex structure 102, a third convex structure 103 and a fourth convex structure 104 arranged in sequence along the first direction X, the first convex structure 101, the second convex structure 102, the third convex structure 103 and the fourth convex structure 104 being parallel to the second direction Y, the first direction X and the second direction Y being parallel to the surface of the substrate 100, and the second direction Y being perpendicular to the first direction X; a first gate structure 107, a second gate structure 108, a third gate structure 109 and a fourth gate structure 110 being located on the substrate 100 and parallel to the first direction X, the first gate structure 107 spanning the first convex structure 101, the second convex structure 102 and the third convex structure 103, the second gate structure 108 spanning the fourth convex structure 104, the first gate structure 107 spanning the first convex structure 101, the second convex structure 102 and the third convex structure 103, the second gate structure 108 spanning the fourth convex structure 104, the first gate structure 107 spanning the first convex structure 101, the second convex structure 102 and the third convex structure 103, the second gate structure 108 spanning the fourth convex structure 104, the first gate structure 107 spanning the first convex structure 101 The three-gate structure 109 spans the first protruding structure 101, and the fourth gate structure 110 spans the second protruding structure 102, the third protruding structure 103, and the fourth protruding structure 104. The central axes of the first gate structure 107 and the second gate structure 108 in the first direction X coincide with each other, and the central axes of the third gate structure 109 and the fourth gate structure 110 in the first direction X coincide with each other. A first connecting layer 111 and a second connecting layer 112 are located on the substrate 100 and are parallel to the first direction X. The first connecting layer 111 electrically connects the first source and drain doped regions (not shown) in the first protruding structure 101 on both sides of the first gate structure 107 and the second source and drain doped regions (not shown) in the second protruding structure 102 on both sides of the first gate structure 107. The second connecting layer 112 electrically connects the fifth source and drain doped regions (not shown) in the third protruding structure 103 on both sides of the fourth gate structure 110 and the sixth source and drain doped regions (not shown) in the fourth protruding structure 104 on both sides of the fourth gate structure 110.

[0038] The semiconductor structure further includes: a first isolation structure (not shown) located between the first gate structure 107 and the second gate structure 108; a second isolation structure (not shown) located between the third gate structure 109 and the fourth gate structure 110; and a third isolation structure (not shown) located between the fourth gate structure 110 of the first cell region I and the fourth gate structure 110 of the second cell region II. Due to etching accuracy, the first, second, and third isolation structures have a minimum first dimension d1 in the first direction X. Furthermore, to ensure that the gate structure can completely cover the sidewalls of the fin structure and thus guarantee the performance of the semiconductor structure, the fourth gate structure 104 between the third isolation structure and the fourth protruding structure 104 has a minimum second dimension d2, the second gate structure 108 between the first isolation structure and the fourth protruding structure 104 has a minimum second dimension d2, and the third gate structure 109 between the second isolation structure and the first protruding structure 101 has a minimum second dimension d2. Therefore, the size of the semiconductor structure in the first direction X is limited by the first size d1 and the second size d2 and cannot be further reduced, and a smaller area cannot be achieved.

[0039] To address the above-mentioned issues, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. Because the central axes of the first and second regions in the second direction do not overlap, the spacing between the first and second protruding structures is smaller than the spacing between the second region and the second protruding structures. Furthermore, because the central axes of the third and fourth regions in the second direction do not overlap, the spacing between the third region and the third protruding structures is larger than the spacing between the fourth region and the third protruding structures. Consequently, when subsequently forming the mirror-symmetrical first and second unit regions, the spacing between the fourth gate structure of the first unit region and the fourth gate structure of the second unit region is limited by established design rules. This allows the spacing between the third region of the first unit region and the third region of the second unit region to be smaller than the spacing between the fourth region of the first unit region and the fourth region of the second unit region, thereby reducing the size of the semiconductor structure formed by the multiple unit regions in the first direction. This allows for a smaller semiconductor structure.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 12 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment of the present invention.

[0042] Please refer to Figure 2 and Figure 3 , Figure 2 yes Figure 3A top view of Figure 3 for Figure 2 A cross-sectional view along section line MM1 is provided, wherein a substrate 200 is provided. The substrate 200 includes a plurality of unit areas, wherein the unit area includes a first protruding structure 201, a second protruding structure 202, a third protruding structure 203, and a fourth protruding structure 204 arranged in sequence along a first direction X. The first protruding structure 201, the second protruding structure 202, the third protruding structure 203, and the fourth protruding structure 204 are parallel to a second direction Y. The first direction X and the second direction Y are parallel to the surface of the substrate 200, and the second direction Y is perpendicular to the first direction X. The first protruding structure 201 includes an initial first region A' and an initial second region B' arranged along the extension direction of the first protruding structure 201. The fourth protruding structure 204 includes an initial third region C' and an initial fourth region D' arranged along the extension direction of the fourth protruding structure 204.

[0043] In this embodiment, the first protruding structure 201 includes a plurality of first vertical stacking structures, each of which includes a first channel layer 210 and a first sacrificial layer 211 located on the first channel layer 210; the second protruding structure 202 includes a plurality of second vertical stacking structures, each of which includes a second channel layer 212 and a second sacrificial layer 213 located on the second channel layer 212; the third protruding structure 203 includes a plurality of third vertical stacking structures, each of which includes a third channel layer 214 and a third sacrificial layer 215 located on the third channel layer 214; and the fourth protruding structure 204 includes a plurality of fourth vertical stacking structures, each of which includes a fourth channel layer 216 and a fourth sacrificial layer 217 located on the fourth channel layer 216.

[0044] The first channel layer 210 , the second channel layer 212 , the third channel layer 214 and the fourth channel layer 216 are made of silicon or silicon germanium; the first sacrificial layer 211 , the second sacrificial layer 213 , the third sacrificial layer 215 and the fourth sacrificial layer 217 are made of silicon or silicon germanium.

[0045] The first channel layer 210 includes nanowires or nanosheets; the second channel layer 212 includes nanowires or nanosheets; the third channel layer 214 includes nanowires or nanosheets; and the fourth channel layer 216 includes nanowires or nanosheets. In this embodiment, the first channel layer 210 includes nanowires; the second channel layer 212 includes nanowires; the third channel layer 214 includes nanowires; and the fourth channel layer 216 includes nanowires.

[0046] The materials of the first channel layer 210, the second channel layer 212, the third channel layer 214 and the fourth channel layer 216 are different from the materials of the first sacrificial layer 211, the second sacrificial layer 213, the third sacrificial layer 215 and the fourth sacrificial layer 217, so that when the first sacrificial layer 211, the second sacrificial layer 213, the third sacrificial layer 215 and the fourth sacrificial layer 217 are subsequently removed, the removal process causes less damage to the first channel layer 210, the second channel layer 212, the third channel layer 214 and the fourth channel layer 216.

[0047] In this embodiment, the material of the first sacrificial layer 211 , the second sacrificial layer 213 , the third sacrificial layer 215 and the fourth sacrificial layer 217 includes silicon germanium; the material of the first channel layer 210 , the second channel layer 212 , the third channel layer 214 and the fourth channel layer 216 includes silicon.

[0048] In this embodiment, the initial first region A′ and the initial second region B′ of the first protruding structure 201 are not adjacent to each other, and the initial third region C′ and the initial fourth region D′ of the fourth protruding structure 204 are not adjacent to each other.

[0049] In this embodiment, the unit area includes a first unit area I and a second unit area II adjacent to each other in the first direction X. The first unit area I and the second unit area II are mirror-symmetrical along the second direction Y. The fourth protruding structure 204 of the first unit area I is adjacent to the fourth protruding structure 204 of the second unit area II.

[0050] In this embodiment, the length of the second protruding structure 202 is smaller than that of the fourth protruding structure 204, and the length of the third protruding structure 203 is smaller than that of the first protruding structure 201. The second protruding structure 202 includes a first end and a second end opposite to each other, and the third protruding structure 203 includes a third end and a fourth end opposite to each other.

[0051] In this embodiment, the substrate 200 is made of silicon.

[0052] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0053] Please refer to Figure 4 and Figure 5 , Figure 4 yes Figure 5 The top view of the dielectric structure 280 is omitted. Figure 5 for Figure 4In the cross-sectional view along the section line MM1, a first dummy gate structure 218 and a second dummy gate structure 219 are formed on the substrate 200 parallel to the first direction X. The first dummy gate structure 218 spans the initial first region A', the second protruding structure 202, the third protruding structure 203 and the initial third region C', and the second dummy gate structure 219 spans the initial second region B', the second protruding structure 202, the third protruding structure 203 and the initial fourth region D'.

[0054] In this embodiment, the first dummy gate structure 218 spans the first cell region I and the second cell region II, and the second dummy gate structure 219 spans the first cell region I and the second cell region II.

[0055] Please continue to refer to Figure 4 and Figure 5 A dielectric structure 280 is formed on the substrate 200 , wherein the first dummy gate structure 218 , the second dummy gate structure 219 , the first protruding structure 201 , the second protruding structure 202 , the third protruding structure 203 and the fourth protruding structure 204 are located in the dielectric structure 280 .

[0056] In this embodiment, the material of the dielectric structure 280 includes silicon oxide.

[0057] Please continue to refer to Figure 4 and Figure 5 , a first isolation structure 220 and a second isolation structure 221 are formed on the substrate 200.

[0058] In this embodiment, while forming the first isolation structure 220 and the second isolation structure 221 on the substrate 200 , a third isolation structure 222 is also formed on the substrate 200 .

[0059] The method for forming the first isolation structure 220, the second isolation structure 221, and the third isolation structure 222 includes: removing a portion of the first dummy gate structure 218 between the third protruding structure 203 and the fourth protruding structure 204 on the first cell area I and the second cell area II, forming a first groove (not shown) in the dielectric structure 280, wherein the first groove penetrates the first dummy gate structure 218 along the second direction Y; removing a portion of the second dummy gate structure 219 between the first protruding structure 201 and the second protruding structure 202 on the first cell area I and the second cell area II, and ...; A second groove (not shown) is formed in the dielectric structure 280, and the second groove passes through the second dummy gate structure 219 along the second direction Y; a portion of the second dummy gate structure 219 between the fourth protruding structure 204 on the first unit area I and the fourth protruding structure 204 on the second unit area II is removed, and a third groove (not shown) is formed in the dielectric structure 280, and the third groove passes through the second dummy gate structure 219 along the second direction Y; a first isolation structure 220 is formed in the first groove, a second isolation structure 221 is formed in the second groove, and a third isolation structure 222 is formed in the third groove.

[0060] The materials of the first isolation structure 220, the second isolation structure 221 and the third isolation structure 222 include dielectric materials, and the dielectric materials include one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbide nitride.

[0061] In this embodiment, the material of the first isolation structure 220 , the second isolation structure 221 , and the third isolation structure 222 includes silicon nitride.

[0062] Next, a portion of the initial first area A' is removed along the first direction X to form a first area A, a portion of the initial second area B' is removed along the first direction X to form a second area B, a portion of the initial third area C' is removed along the first direction X to form a third area C, and a portion of the initial fourth area D' is removed along the first direction X to form a fourth area D. The central axes of the first area A and the second area B in the second direction Y do not overlap, the central axes of the third area C and the fourth area D in the second direction Y do not overlap, the spacing between the second area B and the second protruding structure 202 is greater than the spacing between the first area A and the second protruding structure 202, and the spacing between the fourth area D and the third protruding structure 203 is greater than the spacing between the third area C and the third protruding structure 203. Please refer to the formation process of the first area A, the second area B, the third area C and the fourth area D. Figure 6 and Figure 7 .

[0063] Please refer to Figure 6 , Figure 6 For Figure 5Schematic diagram of the structure based on the present invention, the first dummy gate structure 218 is removed, and a first opening 223 and a second opening 224 are formed in the dielectric structure 280. The first opening 223 and the second opening 224 are located on both sides of the first isolation structure. The first opening 223 exposes the side wall surface and top surface of the initial first region A', part of the side wall surface and top surface of the second protruding structure 202, and part of the side wall surface and top surface of the third protruding structure 203. The second opening 224 exposes the side wall surface and top surface of the initial third region C'.

[0064] Please continue to refer to Figure 6 , the second dummy gate structure 219 is removed, and a third opening (not shown) and a fourth opening (not shown) are formed in the dielectric structure 280. The third opening and the fourth opening are located on both sides of the second isolation structure 221. The third opening exposes the sidewall surface and top surface of the initial second region B', and the fourth opening exposes a portion of the sidewall surface and top surface of the second protruding structure 202, a portion of the sidewall surface and top surface of the third protruding structure 203, and the sidewall surface and top surface of the initial fourth region D'.

[0065] Next, the portion of the first channel layer 210 exposed in the initial first region A' is removed to form the first region, the portion of the first channel layer 210 exposed in the initial second region B' is removed to form the second region, the portion of the fourth channel layer 216 exposed in the initial third region C' is removed to form the third region, and the portion of the fourth channel layer 216 exposed in the initial fourth region D' is removed to form the fourth region. Figure 7 .

[0066] Please refer to Figure 7 A first filling layer 225 is formed in the first opening 223, and the first filling layer 225 exposes a portion of the initial first region A' sidewall facing away from the second protruding structure 202; a second filling layer 226 is formed in the second opening 224, and the second filling layer 226 exposes a portion of the initial third region C' sidewall facing the third protruding structure 203; a third filling layer (not shown) is formed in the third opening, and the third filling layer exposes a portion of the initial second region B' sidewall facing the second protruding structure 202; and a fourth filling layer (not shown) is formed in the fourth opening, and the fourth filling layer exposes a portion of the initial fourth region D' sidewall facing away from the third protruding structure 203.

[0067] In this embodiment, the materials of the first filling layer 225 , the second filling layer 226 , the third filling layer and the fourth filling layer include photoresist or amorphous carbon, so as to be easily removed later.

[0068] Please continue to refer to Figure 7, using the first filling layer 225 as a mask to remove part of the first channel layer 210 to form a first region A (such as Figure 9 As shown), a portion of the fourth channel layer 216 is removed using the second filling layer 226 as a mask to form a third region C (as shown Figure 9 As shown), a portion of the first channel layer 210 is removed using the third filling layer as a mask to form a second region B (as shown Figure 9 As shown), a portion of the fourth channel layer 216 is removed using the fourth filling layer as a mask to form a fourth region D (as shown Figure 9 shown).

[0069] The process of removing the first channel layer 210 and the fourth channel layer 216 includes a wet etching process. The wet etching process has a relatively large etching selectivity between the first channel layer 210 and the fourth channel layer 216 and the first sacrificial layer 211 and the fourth sacrificial layer 215, thereby causing minimal damage to the first sacrificial layer 211 and the fourth sacrificial layer 215 while removing the first channel layer 210 and the fourth channel layer 216.

[0070] Next, a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are formed on the substrate 200 parallel to the first direction X. The first gate structure spans the first region A, the second protruding structure 202, and the third protruding structure 203. The second gate structure spans the third region C. The third gate structure spans the second region B. The fourth gate structure spans the second protruding structure 202, the third protruding structure 203, and the fourth region D. The central axes of the first gate structure and the second gate structure in the first direction X coincide, and the central axes of the third gate structure and the fourth gate structure in the first direction X coincide. For the formation process of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, please refer to Figures 8 to 11 .

[0071] After the first region A, the second region B, the third region C, and the fourth region D are formed, the first filling layer 225 , the second filling layer 226 , the third filling layer, and the fourth filling layer are removed.

[0072] Please refer to Figure 8 and Figure 9 , Figure 9 yes Figure 8 The top view of the dielectric structure 280 is omitted. Figure 8 for Figure 9In the cross-sectional view along the section line MM1, after removing the first filling layer 225, the second filling layer 226, the third filling layer and the fourth filling layer, the first sacrificial layer 211, the second sacrificial layer 213 and the third sacrificial layer 215 exposed by the first opening 223 are removed, the fourth sacrificial layer 217 exposed by the second opening 224 is removed, the first sacrificial layer 211 exposed by the third opening is removed, and the fourth sacrificial layer 217, the second sacrificial layer 213 and the third sacrificial layer 215 exposed by the fourth opening are removed.

[0073] The process of removing the first sacrificial layer 211, the second sacrificial layer 213, the third sacrificial layer 215 and the fourth sacrificial layer 217 includes a wet etching process, which can cleanly remove the first sacrificial layer 211, the second sacrificial layer 213, the third sacrificial layer 215 and the fourth sacrificial layer 217, while causing less damage to the first channel layer 210, the second channel layer 212, the third channel layer 214 and the fourth channel layer 216.

[0074] Please refer to Figure 10 and Figure 11 , Figure 11 yes Figure 10 The top view of the dielectric structure 280 is omitted. Figure 10 for Figure 11 In the cross-sectional view along the section line MM1, a first gate structure 227 is formed in the first opening 223, and the first gate structure 227 surrounds each layer of the first channel layer 210, each layer of the second channel layer 212, and each layer of the third channel layer 214; a second gate structure 228 is formed in the second opening 224, and the second gate structure 228 surrounds each layer of the fourth channel layer 216; a third gate structure 229 is formed in the third opening, and the third gate structure 229 surrounds each layer of the first channel layer 210; a fourth gate structure 230 is formed in the fourth opening, and the fourth gate structure 230 surrounds each layer of the fourth channel layer 216, each layer of the third channel layer 214, and each layer of the second channel layer 212.

[0075] In this embodiment, the second protruding structure 202 includes a first end and a second end opposite each other, and the fourth gate structure 230 is located on the second end. The third protruding structure 203 includes a third end and a fourth end opposite each other, and the first gate structure 227 is located on the third end. The second gate structure 228 on the first cell region I is connected to the second gate structure 228 on the second cell region II.

[0076] The first isolation structure 220 is located between the first gate structure 227 and the second gate structure 228, and the second isolation structure 221 is located between the third gate structure 229 and the fourth gate structure 230. The third isolation structure 222 is located between the fourth gate structure 230 of the first cell region I and the fourth gate structure 230 of the second cell region II.

[0077] The first gate structure 227 includes a first gate dielectric layer (not shown) and a first gate layer (not shown) located on the first gate dielectric layer; the second gate structure 228 includes a second gate dielectric layer (not shown) and a second gate layer (not shown) located on the second gate dielectric layer; the third gate structure 229 includes a third gate dielectric layer (not shown) and a third gate layer (not shown) located on the third gate dielectric layer; the fourth gate structure 230 includes a fourth gate dielectric layer (not shown) and a fourth gate layer (not shown) located on the fourth gate dielectric layer.

[0078] The materials of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer include high dielectric constant materials, the dielectric constant of the high dielectric constant materials is greater than 3.9, and the high dielectric constant materials include aluminum oxide or hafnium oxide; the materials of the first gate layer, the second gate layer, the third gate layer and the fourth gate layer include metals, and the metals include tungsten.

[0079] In the semiconductor structure thus formed, because the central axes of the first and second regions A and B do not overlap in the second direction Y, the distance between the first region A and the second protruding structure 202 is smaller than the distance between the second region B and the second protruding structure 202. Furthermore, because the central axes of the third and fourth regions C and D do not overlap in the second direction Y, the distance between the third region C and the third protruding structure 203 is larger than the distance between the fourth region D and the third protruding structure 203. Consequently, in the mirror-symmetrical first and second cell regions I and II, the distance between the fourth gate structure 230 of the first cell region I and the fourth gate structure 230 of the second cell region II is limited by established design rules. This reduces the size of the semiconductor structure formed by the multiple cell regions in the first direction X, resulting in a smaller semiconductor structure.

[0080] Please refer to Figure 12A first source-drain doped region 251 is formed in the first protruding structure 201, and the first source-drain doped region 251 is located on both sides of the first gate structure 227 and the third gate structure 229; a second source-drain doped region 252 is formed in the second protruding structure 202, and the second source-drain doped region 252 is located on both sides of the first gate structure 227 and the fourth gate structure 230; a third source-drain doped region 253 is formed in the third protruding structure 203, and the third source-drain doped region 253 is located on both sides of the first gate structure 227 and the fourth gate structure 230; a fourth source-drain doped region 254 is formed in the fourth protruding structure 204, and the fourth source-drain doped region 254 is located on both sides of the second gate structure 228 and the fourth gate structure 230.

[0081] Please continue to refer to Figure 12 A first connection layer 255 and a second connection layer 256 are formed on the substrate 200 parallel to the first direction X, wherein the first connection layer 255 electrically connects the first source-drain doping region 251 and the second source-drain doping region 252, and the second connection layer 256 electrically connects the third source-drain doping region 253 and the fourth source-drain doping region 254. The first connection layer 255 is located between the first gate structure 227 and the third gate structure 229 and the fourth gate structure 230, and the second connection layer 256 is located between the fourth gate structure 230, the second gate structure 228 and the first gate structure 227.

[0082] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 12 ,include:

[0083] The substrate 200 includes a plurality of unit areas, wherein the unit area includes a first protruding structure 201, a second protruding structure 202, a third protruding structure 203, and a fourth protruding structure 204 arranged in sequence along a first direction X. The first protruding structure 201, the second protruding structure 202, the third protruding structure 203, and the fourth protruding structure 204 are parallel to a second direction Y. The first direction X and the second direction Y are parallel to the surface of the substrate 200, and the second direction Y is perpendicular to the first direction X. The first protruding structure 201 includes a first protruding structure 202, a second protruding structure 203, and a fourth protruding structure 204 arranged in sequence along a first direction X. The first and second regions are arranged in the extending direction of the fourth protruding structure 201, the fourth protruding structure 204 includes a third region and a fourth region arranged along the extending direction of the fourth protruding structure 204, the central axes of the first and second regions in the second direction Y do not overlap, the central axes of the third and fourth regions in the second direction Y do not overlap, the spacing between the second region and the second protruding structure 202 is greater than the spacing between the first region and the second protruding structure 202, and the spacing between the fourth region and the third protruding structure 203 is greater than the spacing between the third region and the third protruding structure 203;

[0084] A first gate structure 227, a second gate structure 228, a third gate structure 229, and a fourth gate structure 230 are located on the substrate 200 and parallel to the first direction X. The first gate structure 227 spans the first region, the second protruding structure 202, and the third protruding structure 203. The second gate structure 228 spans the third region. The third gate structure 229 spans the second region. The fourth gate structure 230 spans the second protruding structure 202, the third protruding structure 203, and the fourth region. The central axes of the first gate structure 227 and the second gate structure 228 in the first direction X coincide with each other, and the central axes of the third gate structure 229 and the fourth gate structure 230 in the first direction X coincide with each other.

[0085] In this embodiment, it also includes: a first isolation structure 220 and a second isolation structure 221 located on the substrate 200, the first isolation structure 220 is located between the first gate structure 227 and the second gate structure 228, and the second isolation structure 221 is located between the third gate structure 229 and the fourth gate structure 230.

[0086] In this embodiment, the first protruding structure 201 includes a plurality of mutually separate and vertically stacked first channel layers, wherein the first channel layers include at least two layers; the second protruding structure 202 includes a plurality of mutually separate and vertically stacked second channel layers, wherein the second channel layers include at least two layers; the third protruding structure 203 includes a plurality of mutually separate and vertically stacked third channel layers, wherein the third channel layers include at least two layers; the fourth protruding structure 204 includes a plurality of mutually separate and vertically stacked fourth channel layers, wherein the fourth channel layers include at least two layers; the first area and the second area of the first protruding structure 201 are not adjacent to each other, and the third area and the fourth area of the fourth protruding structure 204 are not adjacent to each other.

[0087] In this embodiment, the first channel layer includes nanowires; the second channel layer includes nanowires; the third channel layer includes nanowires; and the fourth channel layer includes nanowires.

[0088] In other embodiments, the first channel layer includes a nanosheet; the second channel layer includes a nanosheet; the third channel layer includes a nanosheet; and the fourth channel layer includes a nanosheet.

[0089] In this embodiment, the first gate structure 227 surrounds each layer of the first channel layer, each layer of the second channel layer and each layer of the third channel layer; the second gate structure 228 surrounds each layer of the fourth channel layer; the third gate structure 229 surrounds each layer of the first channel layer; and the fourth gate structure 230 surrounds each layer of the fourth channel layer, the third channel layer and the second channel layer.

[0090] In this embodiment, the unit area includes a first unit area I and a second unit area II adjacent to each other in the first direction X. The first unit area I and the second unit area II are mirror-symmetrical along the second direction Y. The fourth protruding structure 204 of the first unit area I is adjacent to the fourth protruding structure 204 of the second unit area II.

[0091] In this embodiment, the second gate structure 228 on the first cell region I is connected to the second gate structure 228 on the second cell region II.

[0092] In this embodiment, the present invention further includes: a third isolation structure 222 located between the fourth gate structure 230 of the first cell region I and the fourth gate structure 230 of the second cell region II.

[0093] In this embodiment, the length of the second protruding structure 202 is smaller than that of the fourth protruding structure 204, and the length of the third protruding structure 203 is smaller than that of the first protruding structure 201. The second protruding structure 202 includes a first end and a second end opposite to each other, and the fourth gate structure 230 is located on the second end. The third protruding structure 203 includes a third end and a fourth end opposite to each other, and the first gate structure 227 is located on the third end.

[0094] In this embodiment, the present invention further includes: a first source-drain doped region 251 located in the first protruding structure 201, the first source-drain doped region 251 being located on both sides of the first gate structure 227 and the third gate structure 229; a second source-drain doped region 252 located in the second protruding structure 202, the second source-drain doped region 252 being located on both sides of the first gate structure 227 and the fourth gate structure 230; a third source-drain doped region 253 located in the third protruding structure 203, the third source-drain doped region 253 being located on both sides of the first gate structure 227 and the fourth gate structure 230; and a fourth source-drain doped region 254 located in the fourth protruding structure 204, the fourth source-drain doped region 254 being located on both sides of the second gate structure 228 and the fourth gate structure 230.

[0095] In this embodiment, it also includes: a first connection layer 255 and a second connection layer 256 located on the substrate 200 parallel to the first direction X, the first connection layer 255 electrically connecting the first source-drain doping region 251 and the second source-drain doping region 252, the second connection layer 256 electrically connecting the third source-drain doping region 253 and the fourth source-drain doping region 254, the first connection layer 255 is located between the first gate structure 227 and the third gate structure 229 and the fourth gate structure 230, and the second connection layer 256 is located between the fourth gate structure 230, the second gate structure 228 and the first gate structure 227.

[0096] Figures 13 to 16 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0097] Please refer to Figure 13 A substrate 300 is provided, wherein the substrate 300 includes a plurality of unit areas, wherein the unit area includes a first protruding structure 301, a second protruding structure 302, a third protruding structure 303, and a fourth protruding structure 304 arranged in sequence along a first direction X, wherein the first protruding structure 301, the second protruding structure 302, the third protruding structure 303, and the fourth protruding structure 304 are parallel to a second direction Y, the first direction X and the second direction Y are parallel to the surface of the substrate 300, and the second direction Y is perpendicular to the first direction X, the first protruding structure 301 includes an initial first region A' and an initial second region B' arranged along an extension direction of the first protruding structure 301, and the fourth protruding structure 304 includes an initial third region C' and an initial fourth region D' arranged along an extension direction of the fourth protruding structure 304.

[0098] In this embodiment, the initial first region A′ and the initial second region B′ of the first protruding structure 301 are adjacent to each other, and the initial third region C′ and the initial fourth region D′ of the fourth protruding structure 304 are adjacent to each other.

[0099] In this embodiment, the material of the first protruding structure 301 , the second protruding structure 302 , the third protruding structure 303 and the fourth protruding structure 304 is silicon.

[0100] In other embodiments, the materials of the first, second, third, and fourth protruding structures include silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0101] In this embodiment, the unit area includes a first unit area I and a second unit area II adjacent to each other in the first direction X. The first unit area I and the second unit area II are mirror-symmetrical along the second direction Y. The fourth protruding structure 304 of the first unit area I is adjacent to the fourth protruding structure 304 of the second unit area II.

[0102] In this embodiment, the length of the second protruding structure 302 is smaller than that of the fourth protruding structure 304, and the length of the third protruding structure 303 is smaller than that of the first protruding structure 301. The second protruding structure 302 includes a first end and a second end opposite to each other, and the third protruding structure 303 includes a third end and a fourth end opposite to each other.

[0103] Please refer to Figure 14 A portion of the initial first area A' is removed along the first direction X to form a first area A, a portion of the initial second area B' is removed along the first direction X to form a second area B, a portion of the initial third area C' is removed along the first direction X to form a third area C, and a portion of the initial fourth area D' is removed along the first direction X to form a fourth area D. The central axes of the first area A and the second area B in the second direction Y do not overlap, and the central axes of the third area C and the fourth area D in the second direction Y do not overlap. The distance between the second area B and the second protruding structure 302 is greater than the distance between the first area A and the second protruding structure 302, and the distance between the fourth area D and the third protruding structure 303 is greater than the distance between the third area C and the third protruding structure 303.

[0104] The method of removing a portion of the initial first region A' along the first direction X to form the first region A, removing a portion of the initial second region B' along the first direction X to form the second region B, removing a portion of the initial third region C' along the first direction X to form the third region C, and removing a portion of the initial fourth region D' along the first direction X to form the fourth region D includes: forming a mask layer (not shown) on the substrate 300, the mask layer exposing a portion of the surface of the initial first region A' facing away from the second protruding structure 302, a portion of the surface of the initial second region B' facing the second protruding structure 302, a portion of the surface of the initial third region C' facing the third protruding structure 303, and a portion of the surface of the initial fourth region D' facing away from the third protruding structure 303; and removing the exposed portions of the initial first region A', the initial second region B', the initial third region C', and the initial fourth region D' using the mask layer as a mask to form the first region A, the second region B, the third region C, and the fourth region D.

[0105] Please refer to Figure 15 After forming the first region A, the second region B, the third region C, and the fourth region D, the method further includes: forming a dielectric structure (not shown) and a first gate structure 307, a second gate structure 308, a third gate structure 309, and a fourth gate structure 310 parallel to the first direction X on the substrate 300, wherein the first gate structure 307, the second gate structure 308, the third gate structure 309, and the fourth gate structure 310 are located within the dielectric structure, the first gate structure 307 spans the first region A, the second protruding structure 302, and the third protruding structure 303, the second gate structure 308 spans the third region C, the third gate structure 309 spans the second region B, and the fourth gate structure 310 spans the second protruding structure 302, the third protruding structure 303, and the fourth region D, and the central axes of the first gate structure 307 and the second gate structure 308 in the first direction X coincide with each other, and the central axes of the third gate structure 309 and the fourth gate structure 310 in the first direction X coincide with each other.

[0106] In this embodiment, the second gate structure 308 on the first cell region I is connected to the second gate structure 308 on the second cell region.

[0107] Please continue to refer to Figure 15 , further comprising: forming a first isolation structure 305 on the substrate 300 and located between the first gate structure 307 and the second gate structure 308, forming a second isolation structure 306 between the third gate structure 309 and the fourth gate structure 310, and forming a third isolation structure 311 between the fourth gate structure 310 of the first unit area I and the fourth gate structure 310 of the second unit area II.

[0108] The method for forming the first isolation structure 305, the second isolation structure 306, and the third isolation structure 311 includes: forming a first dummy gate structure and a second dummy gate structure parallel to the first direction X on the substrate 300, wherein the first dummy gate structure spans the first region A, the second protruding structure 302, the third protruding structure 303, and the third region C on the first cell region I and the second cell region II, and the second dummy gate structure spans the second region B, the second protruding structure 302, the third protruding structure 303, and the fourth region D on the first cell region I and the second cell region II; forming a dielectric structure on the substrate 300, wherein the first dummy gate structure, the second dummy gate structure, the first protruding structure 301, the second protruding structure 302, the third protruding structure 303, and the fourth protruding structure 304 are located in the dielectric structure; removing the third protruding structure on the first cell region I and the second cell region II. A portion of the first dummy gate structure between the protruding structure 303 and the fourth protruding structure 304 forms a first groove in the dielectric structure, and the first groove penetrates the first dummy gate structure along the second direction Y; a portion of the second dummy gate structure between the first protruding structure 301 and the second protruding structure 302 on the first unit area I and the second unit area II is removed, and a second groove is formed in the dielectric structure, and the second groove penetrates the second dummy gate structure along the second direction Y; a portion of the second dummy gate structure between the fourth protruding structure 304 on the first unit area I and the fourth protruding structure 304 on the second unit area II is removed, and a third groove is formed in the dielectric structure, and the third groove penetrates the second dummy gate structure along the second direction Y; a first isolation structure 305 is formed in the first groove, a second isolation structure 306 is formed in the second groove, and a third isolation structure 311 is formed in the third groove.

[0109] The method for forming the first gate structure 307, the second gate structure 308, the third gate structure 309 and the fourth gate structure 310 includes: removing the first dummy gate structure, forming a first opening and a second opening in the dielectric structure, the first opening and the second opening being located on both sides of the first isolation structure 305, the first opening exposing the sidewall surface and the top surface of the first region A, a portion of the sidewall surface and the top surface of the second protruding structure 302, and a portion of the sidewall surface and the top surface of the third protruding structure 303, and the second opening exposing the sidewall surface and the top surface of the third region C; removing the second dummy gate structure, forming a third opening and a fourth opening in the dielectric structure, the third opening and the fourth opening being located on both sides of the second isolation structure 306, the third opening exposing the sidewall surface and the top surface of the second region B, The fourth opening exposes a portion of the sidewall surface and top surface of the second protruding structure 302, a portion of the sidewall surface and top surface of the third protruding structure 303, and the sidewall surface and top surface of the fourth region D; a first gate structure 307 is formed in the first opening, and the first gate structure 307 spans the first region A, the second protruding structure 302, and the third protruding structure 303; a second gate structure 308 is formed in the second opening, and the second gate structure 308 spans the fourth protruding structure 304; a third gate structure 309 is formed in the third opening, and the third gate structure 309 spans the first protruding structure 301; and a fourth gate structure 310 is formed in the fourth opening, and the fourth gate structure 310 spans the fourth protruding structure 304, the second protruding structure 302, and the third protruding structure 303.

[0110] In this embodiment, the second protruding structure 302 includes a first end and a second end opposite to each other, and the fourth gate structure 310 is located on the second end; the third protruding structure 303 includes a third end and a fourth end opposite to each other, and the first gate structure 307 is located on the third end.

[0111] The first isolation structure 305 is located between the first gate structure 307 and the second gate structure 308, and the second isolation structure 306 is located between the third gate structure 309 and the fourth gate structure 310. The third isolation structure 311 is located between the fourth gate structure 310 of the first cell region I and the fourth gate structure 310 of the second cell region II.

[0112] Please refer to Figure 16A first source-drain doped region 351 is formed in the first protruding structure 301, and the first source-drain doped region 351 is located on both sides of the first gate structure 307 and the third gate structure 309; a second source-drain doped region 352 is formed in the second protruding structure 302, and the second source-drain doped region 352 is located on both sides of the first gate structure 307 and the fourth gate structure 310; a third source-drain doped region 353 is formed in the third protruding structure 303, and the third source-drain doped region 353 is located on both sides of the first gate structure 307 and the fourth gate structure 310; a fourth source-drain doped region 354 is formed in the fourth protruding structure 304, and the fourth source-drain doped region 354 is located on both sides of the second gate structure 308 and the fourth gate structure 310.

[0113] The first source-drain doping region 351 and the fourth source-drain doping region 354 are relatively large in volume, so that the first source-drain doping region 351 located in the first region A and the second region B respectively can be merged together, and the fourth source-drain doping region 354 located in the third region C and the fourth region D respectively can be merged together to realize the subsequent electrical interconnection of the first connection layer and the second connection layer.

[0114] Please continue to refer to Figure 16 A first connection layer 355 and a second connection layer 356 are formed on the substrate 200 parallel to the first direction X, wherein the first connection layer 355 electrically connects the first source-drain doping region 351 and the second source-drain doping region 352, and the second connection layer 356 electrically connects the third source-drain doping region 353 and the fourth source-drain doping region 354. The first connection layer 355 is located between the first gate structure 307 and the third gate structure 309 and the fourth gate structure 310, and the second connection layer 356 is located between the fourth gate structure 310, the second gate structure 308 and the first gate structure 307.

[0115] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 16 ,include:

[0116] The substrate 300 includes a plurality of unit areas, wherein the unit area includes a first protruding structure 301, a second protruding structure 302, a third protruding structure 303, and a fourth protruding structure 304 arranged in sequence along a first direction X. The first protruding structure 301, the second protruding structure 302, the third protruding structure 303, and the fourth protruding structure 304 are parallel to a second direction Y. The first direction X and the second direction Y are parallel to the surface of the substrate 300, and the second direction Y is perpendicular to the first direction X. The first protruding structure 301 includes a first protruding structure 302, a second protruding structure 303, and a fourth protruding structure 304 arranged in sequence along a first direction X. The first and second regions are arranged in the extending direction Y of the fourth protruding structure 301, the fourth protruding structure 304 includes a third region and a fourth region arranged along the extending direction of the fourth protruding structure 304, the central axes of the first and second regions in the second direction Y do not overlap, the central axes of the third and fourth regions in the second direction Y do not overlap, the spacing between the second region and the second protruding structure 302 is greater than the spacing between the first region and the second protruding structure 302, and the spacing between the fourth region and the third protruding structure 303 is greater than the spacing between the third region and the third protruding structure 303;

[0117] A first gate structure 307, a second gate structure 308, a third gate structure 309, and a fourth gate structure 310 are located on the substrate 300 and parallel to the first direction X. The first gate structure 307 spans the first region, the second protruding structure 302, and the third protruding structure 303. The second gate structure 308 spans the third region. The third gate structure 309 spans the second region. The fourth gate structure 310 spans the second protruding structure 302, the third protruding structure 303, and the fourth region. The central axes of the first gate structure 307 and the second gate structure 308 in the first direction X coincide with each other, and the central axes of the third gate structure 309 and the fourth gate structure 310 in the first direction X coincide with each other.

[0118] In this embodiment, the first isolation structure 305 and the second isolation structure 306 are further included on the substrate 300 . The first isolation structure 305 is located between the first gate structure 307 and the second gate structure 308 . The second isolation structure 306 is located between the third gate structure 309 and the fourth gate structure 310 .

[0119] In this embodiment, the first area and the second area of the first protruding structure 301 are adjacent to each other, and the third area and the fourth area of the fourth protruding structure 304 are adjacent to each other.

[0120] In this embodiment, the unit area includes a first unit area I and a second unit area II adjacent to each other in the first direction X. The first unit area I and the second unit area II are mirror-symmetrical along the second direction Y. The fourth protruding structure 304 of the first unit area I is adjacent to the fourth protruding structure 304 of the second unit area II.

[0121] In this embodiment, the second gate structure 308 on the first cell region I is connected to the second gate structure 308 on the second cell region II.

[0122] In this embodiment, the present invention further includes: a third isolation structure 311 located between the fourth gate structure 310 of the first cell region I and the fourth gate structure 310 of the second cell region II.

[0123] In this embodiment, the length of the second protruding structure 302 is smaller than that of the fourth protruding structure 304, and the length of the third protruding structure 303 is smaller than that of the first protruding structure 301. The second protruding structure 302 includes a first end and a second end opposite to each other, and the fourth gate structure 310 is located on the second end. The third protruding structure 303 includes a third end and a fourth end opposite to each other, and the first gate structure 307 is located on the third end.

[0124] In this embodiment, the present invention further includes: a first source-drain doped region 351 located in the first protruding structure 301, the first source-drain doped region 351 being located on both sides of the first gate structure 307 and the third gate structure 309; a second source-drain doped region 352 located in the second protruding structure 302, the second source-drain doped region 352 being located on both sides of the first gate structure 307 and the fourth gate structure 310; a third source-drain doped region 353 located in the third protruding structure 303, the third source-drain doped region 353 being located on both sides of the first gate structure 307 and the fourth gate structure 310; and a fourth source-drain doped region 354 located in the fourth protruding structure 304, the fourth source-drain doped region 354 being located on both sides of the second gate structure 308 and the fourth gate structure 310.

[0125] In this embodiment, it also includes: a first connection layer 355 and a second connection layer 356 located on the substrate 300 and parallel to the first direction X, the first connection layer 355 electrically connects the first source-drain doping region 351 and the second source-drain doping region 352, the second connection layer 356 electrically connects the third source-drain doping region 353 and the fourth source-drain doping region 354, the first connection layer 355 is located between the first gate structure 307 and the third gate structure 309 and the fourth gate structure 310, and the second connection layer 356 is located between the fourth gate structure 310, the second gate structure 308 and the first gate structure 307.

[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate, the substrate comprising a plurality of unit areas, the unit areas comprising a first protruding structure, a second protruding structure, a third protruding structure, and a fourth protruding structure arranged in sequence along a first direction, the first protruding structure, the second protruding structure, the third protruding structure, and the fourth protruding structure being parallel to a second direction, the first and second directions being parallel to a surface of the substrate, and the second direction being perpendicular to the first direction, the first protruding structure comprising a first region and a second region arranged along an extension direction of the first protruding structure, the fourth protruding structure comprising a third region and a fourth region arranged along an extension direction of the fourth protruding structure, the central axes of the first and second regions in the second direction not coinciding, the central axes of the third and fourth regions not coinciding in the second direction, the spacing between the second region and the second protruding structure being greater than the spacing between the first region and the second protruding structure, the spacing between the third region and the third protruding structure being greater than the spacing between the fourth region and the third protruding structure; a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure located on the substrate and parallel to the first direction, wherein the first gate structure spans the first region, the second protruding structure, and the third protruding structure, the second gate structure spans the third region, the third gate structure spans the second region, and the fourth gate structure spans the second protruding structure, the third protruding structure, and the fourth region, wherein the central axes of the first gate structure and the second gate structure in the first direction coincide with each other, and the central axes of the third gate structure and the fourth gate structure in the first direction coincide with each other; A first isolation structure and a second isolation structure are located on the substrate, wherein the first isolation structure is located between the first gate structure and the second gate structure, the first isolation structure is located between the third region and the third protruding structure, the second isolation structure is located between the third gate structure and the fourth gate structure, and the second isolation structure is located between the second region and the second protruding structure.

2. The semiconductor structure according to claim 1, wherein The first protruding structure includes a plurality of first channel layers that are separated from each other and vertically stacked, and the first channel layer includes at least two layers; the second protruding structure includes a plurality of second channel layers that are separated from each other and vertically stacked, and the second channel layer includes at least two layers; the third protruding structure includes a plurality of third channel layers that are separated from each other and vertically stacked, and the third channel layer includes at least two layers; the fourth protruding structure includes a plurality of fourth channel layers that are separated from each other and vertically stacked, and the fourth channel layer includes at least two layers; the first area and the second area of the first protruding structure are not adjacent, and the third area and the fourth area of the fourth protruding structure are not adjacent.

3. The semiconductor structure according to claim 2, wherein: The first channel layer includes nanowires or nanosheets; the second channel layer includes nanowires or nanosheets; the third channel layer includes nanowires or nanosheets; and the fourth channel layer includes nanowires or nanosheets.

4. The semiconductor structure according to claim 2, wherein: The first gate structure surrounds each layer of the first channel layer, each layer of the second channel layer, and each layer of the third channel layer; the second gate structure surrounds each layer of the fourth channel layer; the third gate structure surrounds each layer of the first channel layer; the fourth gate structure surrounds each layer of the fourth channel layer, each layer of the third channel layer, and each layer of the second channel layer.

5. The semiconductor structure according to claim 1, wherein The first area and the second area of the first protruding structure are adjacent to each other, and the third area and the fourth area of the fourth protruding structure are adjacent to each other.

6. The semiconductor structure according to claim 1, wherein The unit area includes a first unit area and a second unit area adjacent to each other in a first direction. The first unit area and the second unit area are mirror-symmetrical along a second direction. The fourth protruding structure in the first unit area is adjacent to the fourth protruding structure in the second unit area.

7. The semiconductor structure according to claim 6, wherein: The second gate structure on the first cell area is connected to the second gate structure on the second cell area.

8. The semiconductor structure according to claim 7, wherein: Also includes: A third isolation structure is located between the fourth gate structure of the first cell region and the fourth gate structure of the second cell region.

9. The semiconductor structure according to claim 1, wherein: The length of the second protruding structure is smaller than that of the fourth protruding structure, and the length of the third protruding structure is smaller than that of the first protruding structure. The second protruding structure includes a first end and a second end opposite to each other, and the fourth gate structure is located on the second end. The third protruding structure includes a third end and a fourth end opposite to each other, and the first gate structure is located on the third end.

10. The semiconductor structure according to claim 1, wherein: Also includes: a first source-drain doped region located in the first protruding structure, wherein the first source-drain doped region is located on both sides of the first gate structure and on both sides of the third gate structure; A second source-drain doped region is located in the second protruding structure, and the second source-drain doped region is located on both sides of the first gate structure and the fourth gate structure; a third source-drain doped region is located in the third protruding structure, and the third source-drain doped region is located on both sides of the first gate structure and the fourth gate structure; a fourth source-drain doped region is located in the fourth protruding structure, and the fourth source-drain doped region is located on both sides of the second gate structure and the fourth gate structure.

11. The semiconductor structure according to claim 10, wherein: Also includes: A first connection layer and a second connection layer are located on the substrate parallel to the first direction, the first connection layer electrically connects the first source-drain doping region and the second source-drain doping region, the second connection layer electrically connects the third source-drain doping region and the fourth source-drain doping region, the first connection layer is located between the first gate structure and the third gate structure and the fourth gate structure, and the second connection layer is located between the fourth gate structure, the second gate structure and the first gate structure.

12. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, the substrate comprising a plurality of unit areas, the unit areas comprising a first convex structure, a second convex structure, a third convex structure, and a fourth convex structure arranged in sequence along a first direction, the first convex structure, the second convex structure, the third convex structure, and the fourth convex structure being parallel to a second direction, the first and second directions being parallel to a surface of the substrate, and the second direction being perpendicular to the first direction, the first convex structure comprising an initial first region and an initial second region arranged along an extension direction of the first convex structure, and the fourth convex structure comprising an initial third region and an initial fourth region arranged along an extension direction of the fourth convex structure; A first area is formed by removing a portion of the initial first area along the first direction, a second area is formed by removing a portion of the initial second area along the first direction, a third area is formed by removing a portion of the initial third area along the first direction, and a fourth area is formed by removing a portion of the initial fourth area along the first direction. The central axes of the first area and the second area in the second direction do not overlap, the central axes of the third area and the fourth area in the second direction do not overlap, the distance between the second area and the second protruding structure is greater than the distance between the first area and the second protruding structure, and the distance between the third area and the third protruding structure is greater than the distance between the fourth area and the third protruding structure. A first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are formed on the substrate parallel to the first direction, wherein the first gate structure spans the first region, the second protruding structure, and the third protruding structure, the second gate structure spans the third region, the third gate structure spans the second region, and the fourth gate structure spans the second protruding structure, the third protruding structure, and the fourth region, wherein the central axes of the first gate structure and the second gate structure in the first direction coincide with each other, and the central axes of the third gate structure and the fourth gate structure in the first direction coincide with each other.

13. The method for forming a semiconductor structure according to claim 12, wherein: The first protruding structure includes a plurality of first vertical stacking structures, each of which includes a first channel layer and a first sacrificial layer located on the first channel layer; the second protruding structure includes a plurality of second vertical stacking structures, each of which includes a second channel layer and a second sacrificial layer located on the second channel layer; the third protruding structure includes a plurality of third vertical stacking structures, each of which includes a third channel layer and a third sacrificial layer located on the third channel layer; the fourth protruding structure includes a plurality of fourth vertical stacking structures, each of which includes a fourth channel layer and a fourth sacrificial layer located on the fourth channel layer; the initial first area and the initial second area of the first protruding structure are not adjacent to each other, and the initial third area and the initial fourth area of the fourth protruding structure are not adjacent to each other.

14. The method for forming a semiconductor structure according to claim 13, wherein: Before forming the first region, the second region, the third region and the fourth region, the method further includes: forming a first dummy gate structure and a second dummy gate structure parallel to the first direction on the substrate, the first dummy gate structure spanning the initial first region, the second protruding structure, the third protruding structure and the initial third region, and the second dummy gate structure spanning the initial second region, the second protruding structure, the third protruding structure and the initial fourth region; forming a dielectric structure on the substrate, the first dummy gate structure, the second dummy gate structure, the first protruding structure, the second protruding structure, the third protruding structure and the fourth protruding structure being located within the dielectric structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: Also includes: A first isolation structure and a second isolation structure are formed on the substrate, wherein the first isolation structure is located between the first gate structure and the second gate structure, and the second isolation structure is located between the third gate structure and the fourth gate structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: The method for forming the first isolation structure and the second isolation structure includes: removing a portion of the first dummy gate structure between the third protruding structure and the fourth protruding structure, forming a first groove in the dielectric structure, and the first groove penetrates the first dummy gate structure along the second direction; removing a portion of the second dummy gate structure between the first protruding structure and the second protruding structure, and forming a second groove in the dielectric structure, and the second groove penetrates the second dummy gate structure along the second direction; forming a first isolation structure in the first groove, and forming a second isolation structure in the second groove.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the first region, the second region, the third region and the fourth region includes: removing the first dummy gate structure, forming a first opening and a second opening in the dielectric structure, the first opening and the second opening being located on both sides of the first isolation structure, the first opening exposing the sidewall surface and the top surface of the initial first region, the sidewall surface and the top surface of the second protruding structure portion, and the sidewall surface and the top surface of the third protruding structure portion, and the second opening exposing the sidewall surface and the top surface of the initial third region; removing the second dummy gate structure, forming a third opening and a fourth opening in the dielectric structure, the third opening and the fourth opening being located on both sides of the second isolation structure, the third opening exposing the sidewall surface and the top surface of the initial second region, the fourth opening exposing the sidewall surface and the top surface of the second protruding structure portion, the sidewall surface and the top surface of the third protruding structure portion, and the sidewall surface and the top surface of the initial fourth region; removing the portion of the first channel layer exposed in the initial first region to form the first region, removing the portion of the first channel layer exposed in the initial second region to form the second region, removing the portion of the fourth channel layer exposed in the initial third region to form the third region, and removing the portion of the fourth channel layer exposed in the initial fourth region to form the fourth region.

18. The method for forming a semiconductor structure according to claim 17, wherein: The method of removing a portion of the first channel layer exposed in the initial first area to form the first area, removing a portion of the first channel layer exposed in the initial second area to form the second area, removing a portion of the fourth channel layer exposed in the initial third area to form the third area, and removing a portion of the fourth channel layer exposed in the initial fourth area to form the fourth area comprises: forming a first filling layer in the first opening, wherein the first filling layer exposes a portion of the sidewall of the initial first area facing away from the second protruding structure; forming a second filling layer in the second opening, wherein the second filling layer exposes a portion of the sidewall of the initial third area facing toward the third protruding structure; forming a third filling layer in the third opening, wherein the third filling layer exposes a portion of the initial second region sidewall facing the second protruding structure; a fourth filling layer is formed in the fourth opening, the fourth filling layer exposing a portion of the initial fourth region sidewall facing away from the third protruding structure; a portion of the first channel layer is removed using the first filling layer as a mask to form a first region, a portion of the fourth channel layer is removed using the second filling layer as a mask to form a third region, a portion of the first channel layer is removed using the third filling layer as a mask to form a second region, and a portion of the fourth channel layer is removed using the fourth filling layer as a mask to form a fourth region; after forming the first region, the second region, the third region and the fourth region, the first filling layer, the second filling layer, the third filling layer and the fourth filling layer are removed.

19. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the first gate structure, the second gate structure, the third gate structure and the fourth gate structure includes: after forming the first region, the second region, the third region and the fourth region, removing the first sacrificial layer, the second sacrificial layer and the third sacrificial layer exposed by the first opening, removing the fourth sacrificial layer exposed by the second opening, removing the first sacrificial layer exposed by the third opening, and removing the fourth sacrificial layer, the second sacrificial layer and the third sacrificial layer exposed by the fourth opening; forming a first gate structure in the first opening, the first gate structure surrounding each layer of the first channel layer, the second channel layer and the third channel layer; forming a second gate structure in the second opening, the second gate structure surrounding each layer of the fourth channel layer; forming a third gate structure in the third opening, the third gate structure surrounding each layer of the first channel layer; forming a fourth gate structure in the fourth opening, the fourth gate structure surrounding each layer of the fourth channel layer, the third channel layer and the second channel layer.

20. The method for forming a semiconductor structure according to claim 12, wherein: The initial first region and the initial second region of the first protruding structure are adjacent to each other, and the initial third region and the initial fourth region of the fourth protruding structure are adjacent to each other.

21. The method for forming a semiconductor structure according to claim 20, wherein: The method of removing part of the initial first region along the first direction to form the first region, removing part of the initial second region along the first direction to form the second region, removing part of the initial third region along the first direction to form the third region, and removing part of the initial fourth region along the first direction to form the fourth region includes: forming a mask layer on the substrate, the mask layer exposing part of the surface of the initial first region facing away from the second convex structure, part of the surface of the initial second region facing the second convex structure, part of the surface of the initial third region facing the third convex structure, and part of the surface of the initial fourth region facing away from the third convex structure; using the mask layer as a mask to remove the exposed part of the initial first region, part of the initial second region, part of the initial third region, and part of the initial fourth region to form the first region, the second region, the third region, and the fourth region.

22. The method for forming a semiconductor structure according to claim 21, wherein: After forming the first region, the second region, the third region and the fourth region, the method further includes: forming a dielectric structure, a first gate structure, a second gate structure, a third gate structure and a fourth gate structure on the substrate, wherein the first gate structure, the second gate structure, the third gate structure and the fourth gate structure are located in the dielectric structure.

23. The method for forming a semiconductor structure according to claim 22, wherein: Also includes: A first isolation structure is formed between the first gate structure and the second gate structure, and a second isolation structure is formed between the third gate structure and the fourth gate structure.

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