Semiconductor structure and preparation method thereof

Abstract

An embodiment of the present application provides a semiconductor structure and a method for preparing the same, wherein the method for preparing the semiconductor structure includes: forming a stacked structure on a substrate having an array region and a peripheral region; forming a first mask layer on the stacked structure; wherein the first mask layer corresponding to the array region has a first pattern; ion doping the first mask layer on the array region to obtain a doped first mask layer; and etching the stacked structure through the doped first mask layer to transfer the first pattern to the stacked structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to, but not limited to, a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) consists of an array area consisting of multiple memory cells and a peripheral area where the control circuitry resides. With the rapid development of semiconductor memory technology, the market has placed higher demands on the storage capacity of semiconductor memory products. For DRAM, the distribution density of storage capacitors and the storage capacity of individual capacitors restrict the storage capacity and stability of capacitor memory. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0005] forming a stacked structure on a substrate having an array region and a peripheral region;

[0006] forming a first mask layer on the stacked structure; wherein the first mask layer corresponding to the array area has a first pattern;

[0007] performing ion doping on the first mask layer on the array region to obtain a doped first mask layer;

[0008] The stacked structure is etched through the doped first mask layer to transfer the first pattern into the stacked structure.

[0009] In some embodiments, forming a first mask layer on the stacked structure includes:

[0010] forming a first initial mask layer and a second initial mask layer in sequence on the stacked structure; wherein the first pattern is formed in the second initial mask layer;

[0011] Etching the first initial mask layer through the second initial mask layer to transfer the first pattern into the first initial mask layer to form the first mask layer;

[0012] Wherein, the first mask layer exposes a portion of the surface of the stacked structure.

[0013] In some embodiments, the method further comprises:

[0014] After forming the first mask layer, the second initial mask layer is removed.

[0015] In some embodiments, ion doping the first mask layer on the array region to obtain the doped first mask layer includes:

[0016] depositing a sacrificial layer on the first mask layer and the portion of the stacked structure;

[0017] Etching the sacrificial layer on the array area to expose a portion of the first mask layer on the array area;

[0018] Ion doping is performed on the exposed first mask layer to obtain a doped first mask layer.

[0019] In some embodiments, etching the sacrificial layer on the array region to expose a portion of the first mask layer on the array region includes:

[0020] forming a second mask layer on the sacrificial layer;

[0021] patterning the second mask layer to expose the sacrificial layer corresponding to the array area;

[0022] The exposed portion of the sacrificial layer is removed by etching to expose a portion of the first mask layer.

[0023] In some embodiments, the method further comprises:

[0024] After ion doping is performed on the exposed first mask layer, the second mask layer and the remaining sacrificial layer on the peripheral region are removed to expose the first mask layer on the peripheral region.

[0025] In some embodiments, an etching selectivity ratio between the doped first mask layer and the stacked structure is greater than an etching selectivity ratio between the first mask layer and the stacked structure.

[0026] In some embodiments, the first mask layer corresponding to the peripheral area has a second pattern, and a pattern density of the second pattern is less than a pattern density of the first pattern.

[0027] In some embodiments, the first pattern is a capacitor hole pattern, and a contact structure corresponding to the capacitor hole pattern is formed in the substrate.

[0028] In some embodiments, the stacked structure includes a first sacrificial layer, a first supporting layer, a second sacrificial layer, and a second supporting layer stacked in sequence from bottom to top.

[0029] In some embodiments, etching the stacked structure through the doped first mask layer to transfer the first pattern into the stacked structure includes:

[0030] Sequentially etching the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer through the doped first mask layer to transfer the capacitor hole pattern to the stacked structure, thereby forming a plurality of capacitor holes and etched pillars located between two adjacent capacitor holes in the stacked structure;

[0031] Wherein, the capacitor hole exposes a portion of the contact structure.

[0032] In some embodiments, the method further comprises:

[0033] After forming the capacitor hole, the first mask layer is removed.

[0034] In some embodiments, the method further comprises:

[0035] The etched pillars are processed to form capacitor structures.

[0036] In some embodiments, processing the etched pillar to form a capacitor structure includes:

[0037] forming a first electrode layer on the inner wall of the capacitor hole and the surface of the etched column;

[0038] forming a first opening in the second supporting layer;

[0039] removing the second sacrificial layer through the first opening;

[0040] forming a second opening in the first supporting layer;

[0041] The first sacrificial layer is removed through the second opening.

[0042] A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer to form the capacitor structure.

[0043] In a second aspect, an embodiment of the present application provides a semiconductor structure, wherein the semiconductor structure is prepared by the above-mentioned semiconductor structure preparation method, and the semiconductor structure at least includes: a substrate and a capacitor structure;

[0044] wherein the substrate includes a contact structure;

[0045] The capacitor structure is located on the surface of the substrate, and the capacitor structure is in contact with the contact structure.

[0046] The semiconductor structure and its preparation method provided in an embodiment of the present application include: forming a stacked structure on a substrate having an array region and a peripheral region; forming a first mask layer on the stacked structure; the first mask layer corresponding to the array region having a first pattern; ion doping the first mask layer on the array region to obtain a doped first mask layer; etching the stacked structure through the doped first mask layer to transfer the first pattern to the stacked structure. In the embodiment of the present application, by doping the first mask layer on the array region, the first mask layer on the array region and the first mask layer on the peripheral region have different etching selectivities. In this way, the etching load effect brought about by the first mask layers on different regions during the etching process can be offset, thereby improving the integrity of the capacitor pattern and the capacity of the formed capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0048] Figures 1a to 1c A schematic diagram of a semiconductor structure forming process according to an embodiment of the present application;

[0049] Figure 2 A schematic structural diagram of a method for preparing a semiconductor structure provided in another embodiment of the present application;

[0050] Figures 3a to 3n A schematic diagram of a semiconductor structure preparation process according to an embodiment of the present application;

[0051] Figure 4 A cross-sectional view of a semiconductor structure provided in accordance with an embodiment of the present application;

[0052] Description of reference numerals:

[0053] 100 / 200 - substrate; 101 / 201 - stacked structure; 102 - first hard mask layer; 103 - second hard mask layer; 101-1 / B - peripheral region; 100-2 / A - array region; 102a - first hard mask layer after first etching; 102b - first hard mask layer after second etching; 101a - capacitor pattern; 201a - first sacrificial layer; 201b / 213 - first supporting layer; 201c - second sacrificial layer; 201d / 214 - second supporting layer; 200a - contact structure; 200b - insulating layer; 202a - first initial mask layer; 203a - second initial mask layer ;202-first mask layer;202b-first mask layer after doping;204-sacrificial layer;205-second mask layer;205a-dielectric anti-reflective coating;205b-bottom anti-reflective coating;205c-photoresist layer;206c-patterned photoresist layer;206b-patterned bottom anti-reflective coating;206a-patterned dielectric anti-reflective coating;204a-partial sacrificial layer;207-capacitor hole;208-etched column;209-first electrode layer;210-dielectric layer;211-second electrode layer;212-conductive material;40-semiconductor structure;D-first opening;E-second opening. DETAILED DESCRIPTION

[0054] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0055] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0056] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0057] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] Before introducing in detail the method for forming a semiconductor structure provided in an embodiment of the present application, the formation process of the semiconductor structure in the related art is first described.

[0060] Figures 1a to 1c A schematic diagram of a semiconductor structure forming process according to an embodiment of the present application is shown in FIG. Figure 1a As shown, a stacked structure 101 is formed on the surface of a substrate 100, and a first hard mask layer 102 and a second hard mask layer 103 are formed on the surface of the stacked structure 101, wherein the second hard mask layer 103 has a pattern for forming capacitor holes. The substrate 100 includes a peripheral region 100-1 and an array region 100-2, wherein the pattern density of the capacitor hole pattern in the second hard mask layer in the array region 100-2 is greater than the pattern density of the capacitor hole pattern in the second hard mask layer in the peripheral region 100-1.

[0061] The formation process of the semiconductor structure includes two pattern transfer processes. The first pattern transfer process is: etching the first hard mask layer through the second hard mask layer to transfer the capacitor hole pattern in the second hard mask layer to the first hard mask layer. Figure 1b As shown, the first pattern transfer obtains the first hard mask layer 102a after the first etching. During the first pattern transfer process, due to the etching load effect, the thickness t1 of the second hard mask layer 103 located on the array area 100-2 is less than the thickness t2 of the second hard mask layer 103 located on the peripheral area 100-1. The second pattern transfer process is: etching the stacked structure 101 through the first hard mask layer 102a after the first etching to achieve the transfer of the capacitor hole pattern to the stacked structure 101; before performing the second pattern transfer, the second hard mask layer 103 needs to be removed. Figure 1c As shown, the second pattern transfer process forms a capacitor pattern 101a and a first hard mask layer 102b after the second etching, wherein the capacitor pattern (Bar) 101a has a top dimension B and a height D, and the distance between two adjacent capacitor patterns is S. During the removal of the second hard mask layer 103 and the second pattern transfer process, due to the etching load effect, the thickness t3 of the first hard mask layer located on the array region 100-2 is less than the thickness t4 of the first hard mask layer located on the peripheral region 100-1, and the first hard mask layer on the array region 100-2 and the first hard mask layer on the peripheral region 100-1 have different roughness.

[0062] After the capacitor hole pattern is transferred to the stacked structure, the first hard mask layer 102 b after the second etching needs to be removed.

[0063] Another embodiment of the present application provides a semiconductor structure and a method for preparing the same, wherein the method for preparing the semiconductor structure includes: forming a stacked structure on a substrate having an array region and a peripheral region; forming a first mask layer on the stacked structure; the first mask layer corresponding to the array region having a first pattern; ion doping the first mask layer on the array region to obtain a doped first mask layer; etching the stacked structure through the doped first mask layer to transfer the first pattern to the stacked structure. In the embodiment of the present application, by doping the first mask layer on the array region, the first mask layer on the array region and the first mask layer on the peripheral region have different etching selectivities, thereby offsetting the etching load effect brought about by the first mask layers on different regions during the etching process, thereby improving the integrity of the capacitor pattern and the capacity of the formed capacitor structure.

[0064] Figure 2 A structural diagram of a method for preparing a semiconductor structure provided in another embodiment of the present application is shown in FIG. Figure 2 As shown, the following steps are included:

[0065] Step S201: forming a stacked structure on a substrate having an array region and a peripheral region.

[0066] The stacked structure is used to form a capacitor structure and includes a first sacrificial layer, a first supporting layer, a second sacrificial layer, and a second supporting layer stacked in order from bottom to top. The first sacrificial layer and the second sacrificial layer can be oxide layers, such as silicon oxide layers; and the first supporting layer and the second supporting layer can be silicon nitride layers.

[0067] The substrate includes an array region and a peripheral region. The array region is used to form a storage device of the semiconductor memory cell, for example, a storage capacitor; and the peripheral region is used to form a peripheral control circuit.

[0068] In the embodiment of the present application, the substrate includes at least a contact structure, which is used to electrically connect to the formed capacitor structure. In the embodiment of the present application, the material of the contact structure can be any conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0069] In other embodiments, the base may further include a semiconductor substrate, a wordline structure located within the semiconductor substrate, a bitline structure located on a surface of the semiconductor substrate, and an insulating layer covering the contact structure. The material of the semiconductor substrate may be any one of silicon (Si), silicon-germanium alloy (SiGe), silicon carbide (SiC), aluminum oxide (Al2O3), aluminum nitride (AlN), zinc oxide (ZnO), gallium oxide (Ga2O3), or lithium aluminate (LiAlO2).

[0070] Step S202 : forming a first mask layer on the stacked structure; wherein the first mask layer corresponding to the array area has a first pattern.

[0071] In the embodiment of the present application, the first mask layer can be any hard mask layer, for example, a polysilicon layer, a silicon nitride layer or a spin-on carbon layer. The first pattern can be a capacitor hole pattern or other patterns.

[0072] In some embodiments, the first mask layer corresponding to the peripheral area has a second pattern, and the second pattern may also be a capacitor hole pattern or other patterns.

[0073] It should be noted that, in the embodiment of the present application, the pattern density of the second pattern is less than the pattern density of the first pattern.

[0074] Step S203 : performing ion doping on the first mask layer on the array region to obtain a doped first mask layer.

[0075] In an embodiment of the present application, the ions doped into the first mask layer on the array area can be any ions that can increase the difficulty of etching the first mask layer, for example, P-type ions or other types of ions. In this way, the first mask layer on the array area and the first mask layer on the peripheral area will have different etching selectivity ratios.

[0076] Step S204 , etching the stacked structure through the doped first mask layer to transfer the first pattern into the stacked structure.

[0077] Figures 3a to 3n This is a schematic diagram of a semiconductor structure preparation process provided in one embodiment of the present application. Figures 3a to 3n The method for preparing the semiconductor structure provided in the embodiments of the present application is further described in detail.

[0078] First, step S201 is performed to form a stacked structure on a substrate having an array region and a peripheral region.

[0079] like Figure 3a As shown, a stacked structure 201 is formed on a substrate 200. The stacked structure 201 includes a first sacrificial layer 201a, a first supporting layer 201b, a second sacrificial layer 201c, and a second supporting layer 201d stacked sequentially from bottom to top. The substrate 200 includes an array region A and a peripheral region B. A contact structure 200a and an insulating layer 200b covering the contact structure 200a are formed in the substrate 200.

[0080] Next, step S202 is performed to form a first mask layer on the stacked structure; wherein the first mask layer corresponding to the array region has a first pattern.

[0081] In some embodiments, step S202 may be performed by:

[0082] Step S2021 : sequentially forming a first initial mask layer and a second initial mask layer on the stacked structure; wherein a first pattern is formed in the second initial mask layer.

[0083] like Figure 3b As shown, a first initial mask layer 202a and a second initial mask layer 203a are sequentially formed on the surface of the stacked structure 201, wherein a first pattern is formed in the second initial mask layer 203a corresponding to the array region A.

[0084] In the embodiment of the present application, a second pattern is formed in the second initial mask layer 203 a corresponding to the peripheral area B, and the pattern density of the second pattern is lower than the pattern density of the first pattern.

[0085] In an embodiment of the present application, the first initial mask layer and the second initial mask layer can be formed by any suitable deposition process, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process or a coating process.

[0086] Step S2022 : Etching the first initial mask layer through the second initial mask layer to transfer the first pattern into the first initial mask layer to form a first mask layer.

[0087] Please continue to see Figure 3b , the first initial mask layer 202a is etched through the second initial mask layer 203a to transfer the first pattern in the second initial mask layer 203a to the first initial mask layer 202a, and the following is obtained: Figure 3c The first mask layer 202 is shown. The first mask layer 202 exposes a portion of the surface of the stacked structure 201.

[0088] It is worth noting that in the process of etching the first initial mask layer 202a through the second initial mask layer 203a, due to the etching load effect caused by the different pattern densities of the patterns on the array area A and the peripheral area B, the thickness h1 of the second initial mask layer on the array area A is smaller than the thickness h2 of the second initial mask layer on the peripheral area B.

[0089] In some embodiments, the method for preparing a semiconductor structure further includes: after forming the first mask layer, removing the second initial mask layer.

[0090] like Figure 3d As shown, the second initial mask layer 203a may be removed by a dry or wet etching process.

[0091] Next, step S203 is performed to perform ion doping on the first mask layer on the array region to obtain a doped first mask layer.

[0092] In some embodiments, step S203 may include the following steps:

[0093] Step S2031 : depositing a sacrificial layer on the first mask layer and a portion of the stacked structure.

[0094] In the embodiment of the present application, the sacrificial layer may be a spin-on hard mask layer (SOH), a spin-on carbon layer, or other hard mask layers.

[0095] Please continue to see Figure 3d, a film is formed on the first mask layer 202 and a portion of the stacked structure 201. Figure 3e The sacrificial layer 204 is shown. In the embodiment of the present application, the sacrificial layer 204 can be formed by any suitable deposition process.

[0096] Step S2032: Etching the sacrificial layer on the array area to expose a portion of the first mask layer on the array area.

[0097] In some embodiments, step S2032 may be performed by:

[0098] Step S10: forming a second mask layer on the sacrificial layer.

[0099] In an embodiment of the present application, the second mask layer includes an anti-reflective coating (ARC) and a photoresist layer (PR), and the anti-reflective coating includes a dielectric anti-reflective coating (DARC) and a bottom anti-reflective coating (BARC).

[0100] Please continue to see Figure 3e , forming a Figure 3f The second mask layer 205 shown includes a dielectric anti-reflective coating 205a, a bottom anti-reflective coating 205b, and a photoresist layer 205c stacked sequentially from bottom to top. In the embodiment of the present application, the dielectric anti-reflective coating 205a, the bottom anti-reflective coating 205b, and the photoresist layer 205c can be formed by any suitable deposition process.

[0101] Step S11 : patterning the second mask layer to expose the sacrificial layer corresponding to the array area.

[0102] Please continue to see Figure 3f and 3g , using a preset mask C, the photoresist layer 205c, the bottom anti-reflective coating 205b and the dielectric anti-reflective coating 205a are exposed to obtain the following Figure 3g The patterned photoresist layer 206 c , the patterned bottom anti-reflective coating layer 206 b , and the patterned dielectric anti-reflective coating layer 206 a are shown to expose the sacrificial layer 204 corresponding to the array region A.

[0103] Step S12: etching and removing a portion of the exposed sacrificial layer to expose a portion of the first mask layer.

[0104] like Figure 3hAs shown, the partially exposed sacrificial layer is removed by etching, and a portion of the sacrificial layer 204a located on the peripheral region B is retained, exposing the first mask layer 202. Here, the partially exposed sacrificial layer can be removed by etching using a dry etching process or a wet etching process.

[0105] Step S2033 , performing ion doping on the exposed first mask layer to obtain a doped first mask layer.

[0106] In an embodiment of the present application, the process of ion doping the exposed first mask layer may be: using a specific ion generator to generate high-speed ions, and bombarding the surface of the exposed first mask layer with high-speed ions, thereby achieving doping of the exposed first mask layer. Here, the type of ions doped on the exposed first mask layer may be P-type ions, for example, boron ions. That is, in an embodiment of the present application, before ion doping, regardless of whether the first mask layer is undoped, N-type ion doped, or P-type ion doped, the exposed first mask layer is doped with P-type ions, so that the etching rate of the first mask layer after P-type ion doping is slower than that of the first mask layer before ion doping.

[0107] In some embodiments, the thickness of the first mask layer is between 500 nm and 800 nm, the energy of ion doping on the exposed first mask layer is between 10 kiloelectron volts (Kev) and 100 Kev, and the dose of ion doping on the exposed first mask layer is between 10 13 atoms / cm 2 to 10 15 atoms / cm 2 between.

[0108] It should be noted that, in the embodiment of the present application, the degree of doping of the exposed first mask layer is such that the etching selectivity of the doped first mask layer relative to the stacked structure is greater than the etching selectivity of the undoped first mask layer relative to the stacked structure.

[0109] Please continue to see Figure 3h , ion doping is performed on the first mask layer exposed on the array area A to obtain the following Figure 3i The doped first mask layer 202b is shown located on the array region A. Since the surface of the first mask layer in the peripheral region B is covered with a portion of the sacrificial layer 204a, the patterned photoresist layer 206c, the patterned bottom anti-reflective coating 206b, and the patterned dielectric anti-reflective coating 206a, the first mask layer 202 in the peripheral region B is not ion-doped.

[0110] In the embodiment of the present application, the etching selectivity ratio between the doped first mask layer 202 b and the stacked structure 201 is greater than the etching selectivity ratio between the non-ion-doped first mask layer 202 and the stacked structure 201 .

[0111] In some embodiments, after ion doping the exposed first mask layer, the method for preparing the semiconductor structure further includes: removing the second mask layer and the remaining sacrificial layer on the peripheral region to expose the first mask layer on the peripheral region.

[0112] like Figure 3j As shown, after obtaining the doped first mask layer 202b, the second mask layer (i.e., the patterned photoresist layer 206c, the patterned bottom anti-reflective coating 206b, and the patterned dielectric anti-reflective coating 206a) and the remaining sacrificial layer on the peripheral area B can be etched away by wet or dry etching technology to expose the first mask layer 202 on the peripheral area B.

[0113] In an embodiment of the present application, the purpose of ion doping the first mask layer on the array area is to increase the difficulty of etching the first mask layer on the array area, so that the etching selectivity ratio between the doped first mask layer and the stacked structure is greater than the etching selectivity ratio between the first mask layer that has not been ion doped and the stacked structure.

[0114] Next, step S204 is performed to etch the stacked structure through the doped first mask layer to transfer the first pattern into the stacked structure.

[0115] In some embodiments, the first pattern may be a capacitor hole pattern, and step S204 may include the following steps:

[0116] Through the doped first mask layer, the second supporting layer, the second sacrificial layer, the first supporting layer and the first sacrificial layer are etched in sequence to transfer the capacitor hole pattern to the stacked structure, forming multiple capacitor holes and etched columns located between two adjacent capacitor holes in the stacked structure; wherein the capacitor holes expose part of the contact structure.

[0117] Please continue to see Figure 3j , through the doped first mask layer 202b, the second supporting layer 201d, the second sacrificial layer 201c, the first supporting layer 201b, the first sacrificial layer 201a and part of the insulating layer 200b are etched in sequence to form Figure 3k The plurality of capacitor holes 207 and the etched pillars (ie, patterns defining the capacitor holes) 208 located between two adjacent capacitor holes are shown. Each capacitor hole 207 exposes the contact structure 200a.

[0118] In some embodiments, after forming the capacitor hole, the method for preparing the semiconductor structure further includes: removing the first mask layer.

[0119] like Figure 3l As shown, after the capacitor hole 207 is formed, the first mask layer (including the doped first mask layer 202b located on the array area A and the undoped first mask layer 202 located on the peripheral area B) is removed by a dry etching process, exposing the top surface of the etched column 208.

[0120] In the embodiment of the present application, since the etching selectivity ratio between the doped first mask layer located in the array area and the stacked structure is greater than the etching selectivity ratio between the non-ion-doped first mask layer located in the peripheral area and the stacked structure, the etching load effect brought about by the first mask layer on different areas during the etching process can be offset. In this way, when the first mask layer is subsequently etched to remove, the etching column will not be damaged, and the capacity of the formed capacitor structure will not be affected.

[0121] In some embodiments, after removing the first mask layer, the method for preparing the semiconductor structure further includes: processing the etched pillars to form a capacitor structure.

[0122] In some embodiments, processing the etched pillar to form a capacitor structure includes:

[0123] Step S20 , forming a first electrode layer on the inner wall of the capacitor hole and the surface of the etched column.

[0124] The first electrode layer may be a titanium nitride layer.

[0125] Step S21 : forming a first opening in the second supporting layer.

[0126] Step S22 : removing the second sacrificial layer through the first opening.

[0127] Step S23: forming a second opening in the first supporting layer.

[0128] Step S24 , removing the first sacrificial layer through the second opening.

[0129] like Figure 3m As shown, a first electrode layer 209 is formed on the inner wall of the capacitor hole 207 and the surface of the etched column; a first opening D is formed in the second supporting layer, and the second sacrificial layer is removed through the first opening D; a second opening E is formed in the first supporting layer, and the first sacrificial layer is removed through the first opening E.

[0130] In the embodiment of the present application, a dry etching technology, for example, a plasma etching technology, may be used to form the first opening D and the second opening E.

[0131] In the embodiment of the present application, a wet etching technology may be used, for example, using corrosive solutions such as sulfuric acid, hydrofluoric acid, and nitric acid to remove the second sacrificial layer and the first sacrificial layer.

[0132] Step S25 : depositing a dielectric layer and a second electrode layer in sequence on the surface of the first electrode layer to form a capacitor structure.

[0133] like Figure 3n As shown, a dielectric layer 210 and a second electrode layer 211 are formed on the surface of the first electrode layer 209. In the embodiment of the present application, the dielectric layer 210 can be a zirconium oxide layer and / or an aluminum oxide layer, or a layer of other high dielectric constant materials; the second electrode layer 211 can be the same as or different from the first electrode layer 209.

[0134] In some embodiments, the method for forming the semiconductor structure further includes: depositing a conductive material between the second electrode layers. The conductive material may be polysilicon or any other suitable conductive material, such as tungsten, cobalt, or doped polysilicon.

[0135] The method for preparing a semiconductor structure provided in an embodiment of the present application dopes the first mask layer on the array area so that the first mask layer on the array area and the first mask layer on the peripheral area have different etching selectivities. In this way, the etching load effect brought about by the first mask layers on different areas during the etching process can be offset, thereby improving the integrity of the capacitor pattern and the capacity of the formed capacitor structure.

[0136] In addition, an embodiment of the present application further provides a semiconductor structure, which is prepared by the semiconductor structure preparation method provided by the above embodiment. Figure 4 A cross-sectional view of a semiconductor structure provided in one embodiment of the present application, such as Figure 4 As shown, the semiconductor structure 40 includes: a substrate 200 and a capacitor structure; wherein the substrate 200 includes a contact structure 200a and an insulating layer covering the contact structure 200a, and the contact structure 200a is used to be electrically connected to the formed capacitor structure.

[0137] In the embodiment of the present application, the substrate 200 includes an array region A and a peripheral region B, and the capacitor structure is located on the surface of the array region A of the substrate 200 .

[0138] Please continue to see Figure 4 The capacitor structure includes a first electrode layer 209 , a dielectric layer 210 and a second electrode layer 211 stacked in sequence, and conductive material 212 is filled between adjacent second electrode layers 211 .

[0139] In an embodiment of the present application, the capacitor structure is a cup-shaped structure, and the capacitor structure also includes a first support layer 213 and a second support layer 214 arranged in parallel; wherein the first support layer 213 is arranged on the middle periphery of the capacitor structure, and the second support layer 214 is arranged on the top periphery of the capacitor structure, and the first support layer 213 and the second support layer 214 are jointly used to support the capacitor structure.

[0140] In some embodiments, the thickness h3 of the second supporting layer 214 is greater than the thickness h4 of the first supporting layer 213 , so that a better supporting effect can be achieved.

[0141] The semiconductor structure in the embodiment of the present application is similar to the preparation method of the semiconductor structure in the above embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the above embodiment for understanding, and no further details will be given here.

[0142] The semiconductor structure provided in the embodiment of the present application has a complete capacitor pattern, so the capacity of the formed capacitor structure can be increased.

[0143] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in non-targeted ways. The device embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, other division methods may be used, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not implemented. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0144] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0145] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0146] The above are only some implementation methods of the embodiments of this application, but the scope of protection of the embodiments of this application is not limited thereto. Any person skilled in the art can easily conceive of changes or substitutions within the technical scope disclosed in the embodiments of this application, and they should be included in the scope of protection of the embodiments of this application. Therefore, the scope of protection of the embodiments of this application should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: forming a stacked structure on a substrate having an array region and a peripheral region; forming a first mask layer on the stacked structure; wherein the first mask layer corresponding to the array region has a first pattern, the first pattern being a capacitor hole pattern, and a contact structure corresponding to the capacitor hole pattern is formed in the substrate; performing ion doping on the first mask layer on the array region to obtain a doped first mask layer; The stacked structure is etched through the doped first mask layer to transfer the first pattern into the stacked structure.

2. The method according to claim 1, characterized in that forming a first mask layer on the stacked structure, comprising: forming a first initial mask layer and a second initial mask layer in sequence on the stacked structure; wherein the first pattern is formed in the second initial mask layer; Etching the first initial mask layer through the second initial mask layer to transfer the first pattern into the first initial mask layer to form the first mask layer; Wherein, the first mask layer exposes a portion of the surface of the stacked structure.

3. The method according to claim 2, characterized in that The method further comprises: After forming the first mask layer, the second initial mask layer is removed.

4. The method according to claim 2 or 3, characterized in that The step of performing ion doping on the first mask layer on the array region to obtain the doped first mask layer includes: depositing a sacrificial layer on the first mask layer and the portion of the stacked structure; Etching the sacrificial layer on the array area to expose a portion of the first mask layer on the array area; Ion doping is performed on the exposed first mask layer to obtain a doped first mask layer.

5. The method according to claim 4, characterized in that The etching of the sacrificial layer on the array region to expose a portion of the first mask layer on the array region includes: forming a second mask layer on the sacrificial layer; patterning the second mask layer to expose the sacrificial layer corresponding to the array area; The exposed portion of the sacrificial layer is removed by etching to expose a portion of the first mask layer.

6. The method according to claim 5, characterized in that The method further comprises: After ion doping is performed on the exposed first mask layer, the second mask layer and the remaining sacrificial layer on the peripheral region are removed to expose the first mask layer on the peripheral region.

7. The method according to claim 6, characterized in that The etching selectivity ratio between the doped first mask layer and the stacked structure is greater than the etching selectivity ratio between the first mask layer and the stacked structure.

8. The method according to any one of claims 5 to 7, characterized in that The first mask layer corresponding to the peripheral area has a second pattern, and a pattern density of the second pattern is smaller than a pattern density of the first pattern.

9. The method according to claim 1, characterized in that The stacked structure includes a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer stacked in sequence from bottom to top.

10. The method according to claim 9, characterized in that The etching of the stacked structure through the doped first mask layer to transfer the first pattern into the stacked structure includes: Sequentially etching the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer through the doped first mask layer to transfer the capacitor hole pattern to the stacked structure, thereby forming a plurality of capacitor holes and etched pillars located between two adjacent capacitor holes in the stacked structure; Wherein, the capacitor hole exposes a portion of the contact structure.

11. The method according to claim 10, characterized in that The method further comprises: After forming the capacitor hole, the first mask layer is removed.

12. The method according to claim 11, characterized in that The method further comprises: The etched pillars are processed to form capacitor structures.

13. The method according to claim 12, characterized in that The processing of the etched pillar to form a capacitor structure includes: forming a first electrode layer on the inner wall of the capacitor hole and the surface of the etched column; forming a first opening in the second supporting layer; removing the second sacrificial layer through the first opening; forming a second opening in the first supporting layer; removing the first sacrificial layer through the second opening; A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer to form the capacitor structure.

14. A semiconductor structure, characterized in that The semiconductor structure is prepared by the semiconductor structure preparation method according to any one of claims 1 to 13, and the semiconductor structure at least comprises: a substrate and a capacitor structure; wherein the substrate includes a contact structure; The capacitor structure is located on the surface of the substrate, and the capacitor structure is in contact with the contact structure.

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