A method of fabricating a semiconductor structure and a memory

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor structure and a memory, including: providing a substrate; forming an isolation layer on the substrate; forming a first sacrificial layer and a second sacrificial layer extending along a first direction in the isolation layer, and the first sacrificial layer at least partially wrapping the second sacrificial layer; removing part of the first sacrificial layer and part of the isolation layer along a second direction to form a word line trench; forming a third sacrificial layer in the word line trench; wherein the second sacrificial layer, the third sacrificial layer, the retained isolation layer and the first sacrificial layer constitute a layer of stacked layers; continuing to form a plurality of layers of stacked layers to form a stacked structure comprising at least one layer of stacked layers; removing the third sacrificial layer in the stacked structure to expose the word line trench; and forming a word line structure in the word line trench. The embodiment of the present disclosure can simplify the process of preparing a horizontal word line.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a preparation method of a semiconductor structure and a memory. BACKGROUND

[0002] With the development of semiconductor technology, as the next generation technology of Fin Field-Effect Transistor (FinFet), Gate All Around (GAA) can further save space. On this basis, the use of Three Dimensional (3D) structure further expands the structure of semiconductor memory upward, which is of great help to the development of Dynamic Random Access Memory (DRAM) and other memories.

[0003] Among them, DRAM is a semiconductor device commonly used in computers and other electronic devices, which is composed of a plurality of memory cells, each memory cell usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0004] With the continuous miniaturization of the structure of DRAM and other memories, great challenges have been brought to the manufacturing process and yield of three-dimensional memory. SUMMARY

[0005] In a first aspect, the embodiments of the present disclosure provide a preparation method of a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming an isolation layer on the substrate;

[0008] forming a first sacrificial layer and a second sacrificial layer extending along a first direction in the isolation layer, and the first sacrificial layer at least partially wrapping the second sacrificial layer;

[0009] removing part of the first sacrificial layer and part of the isolation layer along a second direction to form a word line trench;

[0010] forming a third sacrificial layer in the word line trench; wherein the second sacrificial layer, the third sacrificial layer, the retained isolation layer and the first sacrificial layer constitute a stack layer;

[0011] continuing to form a plurality of layers of the stack layer to form a stack structure comprising at least one layer of the stack layer;

[0012] removing the third sacrificial layer in the stack structure to expose the word line trench;

[0013] forming a word line structure in the word line trench.

[0014] In some embodiments, forming the first and second sacrificial layers in the isolation layer includes:

[0015] forming a first trench in the isolation layer extending along a first direction;

[0016] forming the first sacrificial layer on a bottom and a side of the first trench;

[0017] forming the second sacrificial layer in a remaining portion of the first trench.

[0018] In some embodiments, an upper surface of the first sacrificial layer, an upper surface of the second sacrificial layer, and an upper surface of the isolation layer are flush.

[0019] In some embodiments, forming the first and second sacrificial layers in the isolation layer includes:

[0020] forming a first trench in the isolation layer extending along a first direction;

[0021] forming a first sub-sacrificial layer on a bottom and a side of the first trench;

[0022] forming an initial second sacrificial layer in a remaining portion of the first trench;

[0023] removing a portion of the initial second sacrificial layer to form a second trench, the remaining initial second sacrificial layer forming the second sacrificial layer;

[0024] forming a second sub-sacrificial layer in the second trench;

[0025] wherein the first sub-sacrificial layer and the second sub-sacrificial layer form the first sacrificial layer.

[0026] In some embodiments, an upper surface of the first sacrificial layer and an upper surface of the isolation layer are flush.

[0027] In some embodiments, before removing the third sacrificial layer in the stack structure, the method further includes:

[0028] removing the second sacrificial layer in the stack structure to form a channel trench;

[0029] forming a channel structure in the channel trench.

[0030] In some embodiments, the word line trench exposes a channel region of the channel structure; before forming the word line structure in the word line trench, the method further comprises:

[0031] forming a gate oxide layer on a surface of the channel region.

[0032] In some embodiments, along the first direction, the channel structure comprises the channel region and first and second doped regions located on two sides of the channel region; after forming the word line structure in the word line trench, the method further comprises:

[0033] removing the first sacrificial layer to expose the first and second doped regions;

[0034] performing a doping process on the first and second doped regions to form a source and a drain.

[0035] In some embodiments, removing part of the first sacrificial layer and part of the isolation layer along a second direction to form a word line trench comprises:

[0036] forming a word line mask layer above a top surface plane of the isolation layer, the word line mask layer having a word line pattern extending along a second direction;

[0037] performing a pattern transfer with the word line mask layer as a mask to remove part of the first sacrificial layer and part of the isolation layer to form the word line trench;

[0038] removing the word line mask layer.

[0039] In some embodiments, when performing the pattern transfer with the word line mask layer as a mask, a isotropic etching process is used to remove part of the first sacrificial layer.

[0040] In some embodiments, the first and second sacrificial layers form a sacrificial structure, wherein:

[0041] along a third direction, the sacrificial structures in adjacent stack layers are misaligned; and / or, along the third direction, adjacent third sacrificial layers are misaligned;

[0042] wherein the first, second and third directions are mutually intersected, and the first, second and third directions are not located in the same plane.

[0043] In some embodiments, the material of the first sacrificial layer, the material of the second sacrificial layer and the material of the third sacrificial layer are respectively selected from one or more of the following: polysilicon, carbon, monocrystalline silicon, silicon oxide, silicon nitride.

[0044] In some embodiments, the material of the word line structure comprises a conductive material, and the word line structure is a stepped word line structure.

[0045] In some embodiments, the etching selectivity ratio between the first sacrificial layer, the second sacrificial layer, the third sacrificial layer, and the isolation layer is greater than or equal to a preset ratio, wherein the preset ratio is 10:1.

[0046] In a second aspect, the embodiments of the present disclosure provide a semiconductor structure prepared by the method according to any one of the first aspect.

[0047] The embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof. The method comprises the following steps: providing a substrate; forming an isolation layer on the substrate; forming a first sacrificial layer and a second sacrificial layer extending along a first direction in the isolation layer, and the first sacrificial layer at least partially wrapping the second sacrificial layer; removing part of the first sacrificial layer and part of the isolation layer along a second direction to form a word line trench; forming a third sacrificial layer in the word line trench; wherein the second sacrificial layer, the third sacrificial layer, the remaining isolation layer, and the first sacrificial layer constitute a stack layer; continuing to form a plurality of stack layers to form a stack structure comprising at least one stack layer; removing the third sacrificial layer in the stack structure to expose the word line trench; and forming a word line structure in the word line trench. In this way, in the preparation of the semiconductor structure, the horizontal word line is prepared by using the multi-sacrificial layer method, which can be prepared by a simple and easy-to-implement process, and the manufacturing process is simplified, the internal resistance of the memory is reduced, and the manufacturing yield and the electrical performance of the memory are improved. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 A flowchart of a semiconductor structure preparation method provided by the embodiments of the present disclosure is provided.

[0049] Figures 2 to 38 A schematic diagram of a structure obtained in the process of preparing a semiconductor structure by the method provided by the embodiments of the present disclosure is provided.

[0050] Figure 39 A top view schematic diagram of a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0051] Figure 40 A schematic diagram of a component structure of a memory provided by the embodiments of the present disclosure is provided.

[0052] The reference signs are as follows:

[0053] Substrate (101); Isolation layer (102); First mask layer (103); First trench (104); First sacrificial layer (105); Second sacrificial layer (106); Initial first sacrificial layer (1051); Second mask layer (107); Second sacrificial trench (108); Initial second sacrificial layer (1061); First sub-sacrificial layer (1052); Second sub-sacrificial layer (1053); Third mask layer (109); Second trench (110); Word line mask layer (111); Word line trench (112); Third sacrificial layer (113); Channel trench (114); Channel structure (115); First doped region (1151); Channel region (1153); Second doped region (1152); Gate oxide layer (116); Word line structure (117). DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only for explaining the related disclosure, and not for limiting the disclosure. In addition, it should be noted that, for the convenience of description, only the parts related to the disclosure are shown in the drawings.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing the embodiments of the present disclosure only and is not intended to limit the present disclosure.

[0056] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0057] It should be noted that the terms "first", "second", "third" involved in the embodiments of the present disclosure are only to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0058] The density of 3D DRAM is increased, which is a development trend of future memory. With the size of memory structure such as DRAM being shrunk, the vertical word line structure will cause the internal resistance of the memory to be too high, which affects the electrical performance of the memory. When a horizontal word line (WL) is prepared, a selective atomic layer deposition (Selective ALD Dep) method needs to be used. However, the Selective ALD Dep technology is not mature, which makes it difficult to implement the horizontal WL.

[0059] Therefore, the present disclosure provides a method for preparing a semiconductor structure, which comprises the following steps: providing a substrate; forming an isolation layer on the substrate; forming a first sacrificial layer and a second sacrificial layer extending along a first direction in the isolation layer, and the first sacrificial layer at least partially wrapping the second sacrificial layer; removing part of the first sacrificial layer and part of the isolation layer along a second direction to form a word line trench; forming a third sacrificial layer in the word line trench; wherein the second sacrificial layer, the third sacrificial layer, the remaining isolation layer and the first sacrificial layer constitute a stack layer; continuing to form a plurality of stack layers to form a stack structure comprising at least one stack layer; removing the third sacrificial layer in the stack structure to expose the word line trench; and forming a word line structure in the word line trench. In this way, when the semiconductor structure is prepared, the horizontal word line can be prepared by using the multi-sacrificial layer method with a simple and easy-to-implement process, which realizes the simplification of the manufacturing process while reducing the internal resistance of the memory, thereby improving the manufacturing yield and the electrical performance of the memory.

[0060] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0061] In an embodiment of the present disclosure, referring to Figure 1 which shows a flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 1 , the method can comprise the following steps:

[0062] S101: providing a substrate 101.

[0063] It should be noted that the method provided by the embodiments of the present disclosure is applied to prepare a semiconductor structure, which can be a 3D semiconductor structure, and is mainly applied to a semiconductor memory such as DRAM. When the semiconductor structure is prepared, a substrate 101 is first provided. Referring to Figure 2 which shows a schematic diagram of a substrate 101 provided by an embodiment of the present disclosure. The substrate 101 can be a silicon substrate or other suitable substrate material such as doped or undoped monocrystalline silicon substrate, polycrystalline silicon substrate, etc., and the embodiments of the present disclosure do not make specific limitations thereto.

[0064] S102: Form an isolation layer 102 on the substrate 101.

[0065] It should be noted that, Figure 3 is a schematic view of the structure after forming the isolation layer 102. As Figure 3 shown, the isolation layer 102 is formed above the substrate 101. The method for forming the isolation layer 102 can include deposition, etc. The material of the isolation layer 102 can include silicon oxide, silicon dioxide, and other insulating materials.

[0066] S103: Form a first sacrificial layer 105 and a second sacrificial layer 106 extending along the first direction in the isolation layer 102, and the first sacrificial layer 105 at least partially wraps the second sacrificial layer 106.

[0067] It should be noted that the first sacrificial layer 105 partially or completely wraps the second sacrificial layer 106 in a surrounding manner. When the first sacrificial layer 105 completely wraps the second sacrificial layer 106, the first sacrificial layer 105 forms a closed loop around the second sacrificial layer 106; when the first sacrificial layer 105 partially wraps the second sacrificial layer 106, the first sacrificial layer 105 forms an open loop around the second sacrificial layer 106.

[0068] In the case where the first sacrificial layer 105 partially wraps the second sacrificial layer 106, forming the first sacrificial layer 105 and the second sacrificial layer 106 extending along the first direction in the isolation layer 102 can include:

[0069] forming a first trench 104 extending along the first direction in the isolation layer 102;

[0070] forming the first sacrificial layer 105 on the bottom and side of the first trench 104;

[0071] forming the second sacrificial layer 106 in the remaining first trench 104.

[0072] Wherein, forming the first trench 104 extending along the first direction in the isolation layer 102 can include:

[0073] forming a first mask layer 103 above the isolation layer 102, the first mask layer 103 having a pattern extending along the first direction;

[0074] performing pattern transfer with the first mask layer 103 as a mask, removing part of the isolation layer 102 to form the first trench 104;

[0075] removing the first mask layer 103.

[0076] It should be noted that, Figure 4 is a schematic view of the structure after forming the first mask layer 103. As Figure 4As shown, the first mask layer 103 is formed above the isolation layer 102, and the first mask layer 103 has a pattern extending along a first direction, which exposes the part of the isolation layer 102 that needs to be removed. Here, the first direction is a direction parallel to the top surface plane of the isolation layer 102.

[0077] It should be further noted that the mask layers (the first mask layer 103, the second mask layer 107, the third mask layer 109, and the word line mask layer 111) involved in the embodiments of the present disclosure can be single-layer masks or multi-layer composite masks, etc., and the materials of the mask layers can include photoresist (PR) and / or hard mask composition, etc., the formation of the mask layers can be deposition, etc., and the removal of the mask layers can be etching, etc., which will not be specifically described later.

[0078] When performing pattern transfer, the isolation layer 102 covered by the first mask layer 103 is retained, and the isolation layer 102 exposed by the first mask layer 103 is removed along a third direction to a certain depth. Here, the third direction is a direction intersecting the top surface plane of the isolation layer 102, and in the embodiment of the present disclosure, the third direction is perpendicular to the top surface plane of the isolation layer 102. Figure 5 It should be noted that the isolation layer 102 will not be removed completely here.

[0079] Figure 5 A schematic diagram of the structure obtained after forming the first trench 104 and removing the first mask layer 103. As shown, Figure 5 the thickness of the isolation layer 102 is H0, the depth of the first trench 104 is H1, and H1 < H0. After performing pattern transfer, the isolation layer 102 with a thickness of (H0-H1) is retained below the first trench 104. Here, the removal of the isolation layer 102 can be etching.

[0080] Then, the first sacrificial layer 105 and the second sacrificial layer 106 are formed in the first trench 104. Figure 6 A schematic diagram of the structure obtained after forming the first sacrificial layer 105. As shown, Figure 6 the first sacrificial layer 105 is formed at the bottom and the side of the first trench 104. Here, the formation of the first sacrificial layer 105 can be deposition.

[0081] Figure 7 A schematic diagram of a structure obtained after forming the second sacrificial layer 106. As shown, Figure 7 the second sacrificial layer 106 completely fills the remaining first trench 104, and the upper surface of the first sacrificial layer 105, the upper surface of the second sacrificial layer 106, and the upper surface of the isolation layer 102 are flush.

[0082] Here, the second sacrificial layer 106 can be directly formed in the first trench 104 by deposition (for example, ALD).Figure 6 The first sacrificial layer 105 is shown, and further deposition is performed in the remaining first trench 104 to form the first sacrificial layer 105 as shown. Figure 7 The second sacrificial layer 106 is shown, but due to limitations of actual process conditions and the like, direct deposition of the first sacrificial layer 105 and the second sacrificial layer 106 is often difficult to achieve or results in excessively high process costs.

[0083] Therefore, in an implementation, forming the first sacrificial layer 105 at the bottom and side of the first trench 104, and forming the second sacrificial layer 106 in the remaining first trench 104 can include:

[0084] forming an initial first sacrificial layer 1051 on the surface of the isolation layer 102 and in the first trench 104;

[0085] forming a second mask layer 107 on the initial first sacrificial layer 1051;

[0086] performing pattern transfer with the second mask layer 107 as a mask to remove part of the initial first sacrificial layer 1051 and form a second sacrificial trench 108 in the initial first sacrificial layer 1051;

[0087] removing the second mask layer 107;

[0088] forming an initial second sacrificial layer 1061 in the second sacrificial trench 108;

[0089] performing chemical mechanical polishing on the initial first sacrificial layer 1051 and the initial second sacrificial layer 1061 until flush with the top surface of the isolation layer 102 to obtain the first sacrificial layer 105 and the second sacrificial layer 106.

[0090] It should be noted that, Figure 8 is a schematic diagram of the structure obtained after forming the initial first sacrificial layer 1051. As shown, Figure 8 When depositing the initial first sacrificial layer 1051, the initial first sacrificial layer 1051 is often formed on the surface of the entire isolation layer 102 and inside the first trench 104. At this time, part of the initial first sacrificial layer 1051 inside the first trench 104 needs to be further removed, and only the initial first sacrificial layer 1051 at the bottom and side of the first trench 104 is retained to obtain the first sacrificial layer 105.

[0091] Figure 9 is a schematic diagram of the structure obtained after forming the second mask layer 107. As shown, Figure 9 The second mask layer 107 is formed above the initial first sacrificial layer 1051, and the second mask layer 107 has a pattern extending in the first direction, which exposes the part of the initial first sacrificial layer 1051 that needs to be removed.

[0092] In the process of pattern transfer, the initial first sacrificial layer 1051 exposed by the second mask layer 107 is removed along the third direction to a certain depth to form the second sacrificial trench 108, and a certain thickness of the initial first sacrificial layer 1051 is reserved, and finally the second mask layer 107 is removed. Figure 10 A schematic view of the structure obtained after forming the second sacrificial trench 108. The way of removing the initial first sacrificial layer 1051 can be etching.

[0093] The initial second sacrificial layer 1061 is formed in the second sacrificial trench 108 to obtain the structure as shown in FIG. 6B. Figure 11 Then, the initial first sacrificial layer 1051 and the initial second sacrificial layer 1061 are subjected to chemical mechanical polishing (CMP) treatment with the top surface of the isolation layer 102 as the polishing stop layer, the initial first sacrificial layer 1051 is processed into the first sacrificial layer 105, and the initial second sacrificial layer 1061 is processed into the second sacrificial layer 106 to obtain the structure as shown in FIG. 6C. Figure 7

[0094] It should be further noted that only the way of forming the first sacrificial layer 105 and the second sacrificial layer 106 is exemplarily shown here, and in actual production, other suitable ways can also be selected to form the first sacrificial layer 105 and the second sacrificial layer 106 according to the process conditions, which are not specifically limited. For example, in another implementation, the first sacrificial layer is formed at the bottom and the side of the first trench; and the second sacrificial layer is formed in the remaining first trench, which can include:

[0095] forming the initial first sacrificial layer on the surface of the isolation layer and in the first trench;

[0096] subjecting the initial first sacrificial layer to chemical mechanical polishing treatment until the top surface of the isolation layer is flush;

[0097] forming the second mask layer above the initial first sacrificial layer;

[0098] performing pattern transfer with the second mask layer as a mask to remove part of the initial first sacrificial layer, forming the second sacrificial trench in the initial first sacrificial layer, and obtaining the first sacrificial layer;

[0099] removing the second mask layer;

[0100] forming the initial second sacrificial layer in the second sacrificial trench;

[0101] subjecting the initial second sacrificial layer to chemical mechanical polishing treatment until the top surface of the isolation layer is flush to obtain the second sacrificial layer.

[0102] It should be noted that this implementation is similar to the previous implementation, and therefore no further schematic view is shown here. ​

[0103] As Figure 7 shown, for the first and second sacrificial layers 105 and 106 obtained in this case, among the four sides of the second sacrificial layer 106, three sides are wrapped by the first sacrificial layer 105, and the top surface of the second sacrificial layer 106 is not covered by the first sacrificial layer 105. In addition, in the actual process, the second sacrificial layer 106 does not necessarily present a perfect four sides, and the side wrapped by the first sacrificial layer 105 can present an arc or other shape as a whole, but the final shape is that the top surface is not covered by the first sacrificial layer 105.

[0104] In the case where the first sacrificial layer 105 completely wraps the second sacrificial layer 106, forming the first and second sacrificial layers 105 and 106 extending along the first direction in the isolation layer 102 can include:

[0105] forming the first trench 104 extending along the first direction in the isolation layer 102;

[0106] forming the first sub-sacrificial layer 1052 on the bottom and side of the first trench 104;

[0107] forming the initial second sacrificial layer 1061 in the remaining first trench 104;

[0108] removing part of the initial second sacrificial layer 1061 to form the second trench 110, and the remaining initial second sacrificial layer 1061 forms the second sacrificial layer 106;

[0109] forming the second sub-sacrificial layer 1053 in the second trench 110;

[0110] wherein the first and second sub-sacrificial layers 1052 and 1053 constitute the first sacrificial layer 105.

[0111] It should be noted that the way of forming the first trench 104 is consistent with the foregoing, and specific reference is made to Figure 4 , Figure 5 and related descriptions. Figure 12 is a schematic diagram of the structure obtained after forming the first sub-sacrificial layer 1052. It can be seen that Figure 12 and Figure 6 show the same structure, except that Figure 12 in the first sub-sacrificial layer 1052 formed on the bottom and side wall of the first trench 104. The way of forming the first sub-sacrificial layer 1052 in Figure 12 is consistent with the way of forming the first sacrificial layer 105 described above, which will not be described here.

[0112] Figure 13 is a schematic diagram of another structure obtained after forming the initial second sacrificial layer 1061. It can be seen that Figure 13The initial second sacrificial layer 1061 and Figure 11 The initial second sacrificial layer is different. Figure 13 Having the same characteristics as the aforementioned Figure 7 Same structure, Figure 13 The initial second sacrificial layer 1061 and Figure 7 The second sacrificial layer 106 in the middle has the same structure, for Figure 13 The formation method of the initial second sacrificial layer 1061 can be referred to Figure 7 The formation method of the second sacrificial layer 106 in the middle will not be described in detail here.

[0113] Then, a portion of the initial second sacrificial layer 1061 is removed to form the second trench 110. The removal of a portion of the initial second sacrificial layer 1061 to form the second trench 110 may include:

[0114] A third mask layer 109 is formed above the top plane of the isolation layer 102; the third mask layer 109 has a pattern extending along a first direction;

[0115] Pattern transfer is performed using the third mask layer 109 as a mask, and part of the initial second sacrificial layer 1061 is removed to form the second trench 110.

[0116] Remove the third mask layer 109.

[0117] It should be noted that, Figure 14 This is a schematic diagram of the structure obtained after forming the third mask layer 109. (See diagram below.) Figure 14 As shown, the third mask layer 109 has a pattern extending along a first direction, which covers the first sub-sacrificial layer 1052 and the isolation layer 102, and exposes the initial second sacrificial layer 1061.

[0118] During pattern transfer, the initial second sacrificial layer 1061 exposed by the third mask layer 109 is removed to a certain depth along the third direction to form the second trench 110, and the initial second sacrificial layer 1061 of a certain thickness is retained as the second sacrificial layer 106. Finally, the third mask layer 109 is removed. Figure 15 This is a schematic diagram of the structure obtained after forming the second trench 110. The initial second sacrificial layer 1061 can be removed by etching. A second sub-sacrificial layer 1053 is formed within the second trench 110, resulting in... Figure 16 The structure shown.

[0119] It should be noted that the first sub-sacrifice layer 1052 and the second sub-sacrifice layer 1053 together constitute the first sacrifice layer 105, and the first sub-sacrifice layer 1052 and the second sub-sacrifice layer 1053 are often made of the same material. Therefore, there is no clear boundary between the first sub-sacrifice layer 1052 and the second sub-sacrifice layer 1053, but because the first sub-sacrifice layer 1052 and the second sub-sacrifice layer 1053 are not formed at the same time, the first sub-sacrifice layer 1052 and the second sub-sacrifice layer 1053 can be distinguished by the boundary line shown in Figure 16 .

[0120] Briefly, after forming the substrate 101, the embodiment deposits silicon oxide as the isolation layer 102 on the substrate 101, and etches the isolation layer 102 to form the first trench 104, and then deposits the first sacrifice layer material as the sidewall (the first sub-sacrifice layer 1051), and then deposits the second sacrifice layer material (for example, silicon nitride) as the sacrifice layer of the channel (the second sacrifice layer 106), and performs CMP processing, and then etches a part of the second sacrifice layer 106 to form the second trench 110, and deposits the first sacrifice layer material in the second trench 110 to obtain the second sub-sacrifice layer 1052.

[0121] Further, Figure 17 is another schematic diagram of the structure obtained after forming the first sacrifice layer 105 and the second sacrifice layer 106. In Figure 17 , the first sub-sacrifice layer 1052 and the second sub-sacrifice layer 1053 are no longer distinguished, and only the first sacrifice layer 105 is marked. As Figure 17 shown, for the first sacrifice layer 105 and the second sacrifice layer 106 obtained in this case, the four sides of the second sacrifice layer 106 are all wrapped by the first sacrifice layer 105.

[0122] As Figure 17 shown, the upper surface of the first sacrifice layer 105 is flush with the upper surface of the isolation layer 102.

[0123] In subsequent steps, the implementation of the embodiment is further described based on the structure shown in Figure 17 .

[0124] S104: Remove part of the first sacrifice layer 105 and part of the isolation layer 102 along the second direction to form the word line trench 112.

[0125] It should be noted that in the embodiments of the present disclosure, the first direction, the second direction and the third direction intersect with each other, and the first direction, the second direction and the third direction are not located in the same plane. For example, the first direction and the second direction intersect and are located in the same plane, and the plane is denoted as a first plane, the third direction intersects the first plane, and the first direction and the second direction can be located in the first plane, and the third direction intersects the plane in which the first direction and the second direction are located. Specifically, the first plane can be a horizontal plane, the first direction and the second direction are not parallel, and the two directions intersect at a certain angle, and the third direction is a direction that is not parallel to the first plane and has a certain angle with the first plane.

[0126] In the drawings of the embodiments of the present disclosure, a three-dimensional orthogonal coordinate system is taken as an example for illustration, in which the first direction, the second direction and the third direction intersect with each other, but this does not constitute a limitation on the semiconductor structure. In addition, in the drawings, the first direction, the second direction and the third direction are all provided with arrows, but this is only for the purpose of showing the spatial relationship of the three directions, and it can be understood that the reverse direction of the arrow can still represent the direction. For example, the first direction can be understood as an east-west direction, the second direction can be understood as a north-south direction, and the third direction can be understood as an up-down direction.

[0127] For the manner of forming the word line trench 112, in some embodiments, removing part of the first sacrificial layer 105 and part of the isolation layer 102 along the second direction to form the word line trench 112 can include:

[0128] forming a word line mask layer 111 above the top surface of the isolation layer 102, the word line mask layer 111 having a word line pattern extending along the second direction;

[0129] performing pattern transfer with the word line mask layer 111 as a mask to remove part of the first sacrificial layer 105 and part of the isolation layer 102 to form the word line trench 112;

[0130] removing the word line mask layer 111.

[0131] It should be noted that, Figure 18 is a schematic view of the structure obtained after forming the word line mask layer 111. As Figure 18 shown, the word line mask layer 111 has a word line pattern extending along the second direction, and the word line pattern exposes part of the isolation layer 102 and the first sacrificial layer 105 that needs to be removed.

[0132] During pattern transfer, etching can be used. The isolation layer 102 and the first sacrificial layer 105 are typically made of different materials with different etching selectivity ratios. In this case, the isolation layer 102 can be removed to a certain depth. Specifically, the isolation layer 102 exposed by the word line mask layer 111 can be removed until it is flush with the bottom surface of the first sacrificial layer 105; or the isolation layer 102 can be removed below the bottom surface of the first sacrificial layer 105, but without completely removing the exposed isolation layer 102 along a third direction to ensure insulation from the substrate 101. Simultaneously, the isolation layer 102 located below the first sacrificial layer 105 can also be partially removed to ensure the bottom of the word line trench is flush with the substrate.

[0133] Figure 19 This is a schematic diagram of the structure obtained after removing part of the isolation layer 102 using the word line mask layer 111 as a mask. Further, the already exposed first sacrificial layer 105 is removed, thereby exposing the second sacrificial layer 106. It should be noted that here, one ring of the first sacrificial layer 105 surrounding the second sacrificial layer 106 is removed, thus exposing all four sides of the second sacrificial layer 106 within the word line groove 112. Finally, the word line mask layer 111 is removed. Figure 20 This is a schematic diagram of the structure obtained after forming the word line trench 112 and removing the word line mask layer 111. The first sacrificial layer 105 can be removed by etching.

[0134] It should also be noted that when performing pattern transfer using the word line mask layer 111 as a mask, an isotropic etching process can be used to remove part of the first sacrificial layer 105. Due to the characteristics of isotropic etching, the first sacrificial layer 105 is often partially removed in the first direction, resulting in a structure as shown in the figure. Figure 20 As shown.

[0135] In simple terms, in this embodiment, the isolation layer 102 and the first sacrificial layer 105 are etched to form word line trenches 112 (WLTrench). Since it is necessary to remove the first sacrificial layer 105 at the bottom of the second sacrificial layer 106, isotropic etching is adopted, so that the first sacrificial layer 105 on the sidewalls and top will also be etched and removed at the same time.

[0136] S105: A third sacrificial layer 113 is formed in the word line groove 112; wherein, the second sacrificial layer 106, the third sacrificial layer 113, the retained isolation layer 102 and the first sacrificial layer 105 constitute a stacked layer.

[0137] It should be noted that, Figure 21 In order to be in Figure 20 Based on this, a schematic diagram of the structure obtained after forming the third sacrificial layer 113 is shown. (See diagram below.) Figure 21As shown, the third sacrificial layer 113 completely fills the word line trench 112. At this time, a layer of stack is obtained. The third sacrificial layer 113 can be formed by depositing a third sacrificial layer material.

[0138] In the embodiments of the present disclosure, the material of the first sacrificial layer 105, the material of the second sacrificial layer 106 and the material of the third sacrificial layer 113 can be selected from one or more of the following: polysilicon (Poly), carbon (Carbon), monocrystalline silicon, silicon oxide, silicon nitride, spin-on hard mask (SOH), other oxides (Oxide), silicon dioxide (SiO2), other nitrides (Nitride), etc., or new materials.

[0139] In the embodiments of the present disclosure, the material of the first sacrificial layer 105, the material of the second sacrificial layer 106 and the material of the third sacrificial layer 113 can be selected from one or more of the following: polysilicon (Poly), carbon (Carbon), monocrystalline silicon, silicon oxide, silicon nitride, spin-on hard mask (SOH), other oxides (Oxide), silicon dioxide (SiO2), other nitrides (Nitride), etc., or new materials.

[0140] In the embodiments of the present disclosure, the material of the first sacrificial layer 105, the material of the second sacrificial layer 106 and the material of the third sacrificial layer 113 can be selected from one or more of the following: polysilicon (Poly), carbon (Carbon), monocrystalline silicon, silicon oxide, silicon nitride, spin-on hard mask (SOH), other oxides (Oxide), silicon dioxide (SiO2), other nitrides (Nitride), etc., or new materials.

[0141] S106: Continue to form a plurality of layers of stack to form a stack structure including at least one layer of stack.

[0142] It should be noted that the embodiments of the present disclosure are mainly used to form a 3D semiconductor structure, and therefore, the steps of S102 to S105 are continued to be executed until a required number of layers of stack are formed, and a 3D stack structure is obtained. The layers of stack are collectively referred to as a stack structure. It can be understood that when the step S102 is repeatedly executed, the isolation layer 102 is formed above the lower layer of stack.

[0143] In this way, the 3D stack structure is obtained by forming the layers of stack one by one. Figure 22 FIG. 3 shows a schematic diagram of a structure obtained after forming a stack structure according to the embodiments of the present disclosure.

[0144] Further, referring to the left drawing in FIG. 4, a schematic diagram of a structure obtained after forming a stack structure according to another embodiment of the present disclosure is shown. For ease of description, the left drawing in FIG. 4 is described as follows. Figure 23 Figure 23 ​In the left figure, the effect of isotropic etching on the first sacrificial layer 105 is ignored. Furthermore, to ensure structural reliability, an isolation layer 102 can be formed on top of the stacked structure, resulting in... Figure 23 The structure shown in the right figure.

[0145] It should also be noted that, for Figure 23 The structure shown exhibits high parasitic capacitance and severe coupling during subsequent word line formation. To address this issue, in some embodiments, the first sacrificial layer 105 and the second sacrificial layer 106 constitute a sacrificial structure, wherein:

[0146] Along the third direction, the sacrificial structures in adjacent stacked layers are misaligned; and / or, along the third direction, the adjacent third sacrificial layers 113 are misaligned.

[0147] It should be noted that if the semiconductor structure includes N stacked layers, where N is an integer greater than 1, for the (i+1)th stacked layer (i is an integer greater than 0 and less than or equal to N), in this embodiment, when forming the (i+1)th stacked layer, the sacrificial structure of the (i+1)th layer is not aligned with the sacrificial structure of the ith layer, but is offset by a certain distance in the second direction. This results in the sacrificial structures in adjacent stacked layers not being aligned in the third direction, but being misaligned, forming a misaligned arrangement. The resulting structure is as follows: Figure 24 As shown.

[0148] Alternatively, in this embodiment of the present disclosure, when forming the (i+1)th stacked layer, the third sacrificial layer 113 of the (i+1)th layer is not aligned with the third sacrificial layer 113 of the i-th layer, but is offset by a certain distance in the first direction, so that in the third direction, the third sacrificial layers 113 in adjacent stacked layers are not aligned, but are misaligned, forming a misaligned arrangement structure, the resulting structure is as follows. Figure 25 As shown.

[0149] Alternatively, in this embodiment, both the sacrificial structure and the third sacrificial layer 113 can be staggered, resulting in a structure as follows: Figure 26 As shown.

[0150] In this way, by staggering the arrangement, parasitic capacitance can be reduced and the problem of severe coupling can be improved when transistors and / or word lines are formed in the future.

[0151] S107: Remove the third sacrificial layer 113 in the stacked structure to expose the word line trench 112.

[0152] It should be noted that in this step and subsequent steps, the following applies: Figure 23 Based on the three-dimensional structure shown, the subsequent steps are described in conjunction with sections AA', BB', CC', DD', and the top view.Figure 23 The corresponding cross-sectional diagram is as follows Figure 27 As shown. The top view is... Figure 23 Based on the left figure, the schematic diagrams of each section are as follows: Figure 23 Based on the right figure in the middle, and in Figure 27 In the accompanying drawings, only the relevant cross-sections of the stacked structure are shown; the substrate 101 is not shown. Additionally, if... Figure 7 Based on the sacrificial structure, the cross-section in the CC' direction is as follows: Figure 28 As shown.

[0153] In some embodiments, the method may further include, prior to removing the third sacrificial layer 113 in the stacked structure:

[0154] Remove the second sacrificial layer 106 in the stacked structure to form the channel trench 114;

[0155] A channel structure 115 is formed within the channel 114.

[0156] It should be noted that, Figure 29 This is a schematic diagram of the cross-sections corresponding to the structure obtained after removing the second sacrificial layer 106. The second sacrificial layer 106 can be removed by etching. It can be understood that when the first sacrificial layer 105 completely encloses the second sacrificial layer 106, the trench 114 is the aforementioned second sacrificial trench 108.

[0157] A channel structure 115 is formed within the channel groove 114, and the schematic diagrams of the corresponding cross-sections of the resulting structure are shown below. Figure 30 As shown. The trench structure 115 can be formed by depositing trench material within the trench 114, such as... Figure 30 As shown, the channel structure 115 completely fills the channel trench 114. Here, the channel structure 115 can serve as the active region of a semiconductor structure. The channel material can include silicon, etc.

[0158] like Figure 30 As shown, along the first direction (AA' direction), the channel structure 115 includes a first doped region 1151, a channel region 1153, and a second doped region 1152. Specifically, the first doped region 1151 and the second doped region 1152 are located on either side of the channel region 1153, which is the portion of the channel structure 115 covered by the third sacrificial layer 113. In subsequent fabrication processes, the first doped region 1151 and the second doped region 1152 can be doped to serve as the source and drain of the transistor, respectively. The channel region 1153 can serve as the channel of the transistor, and the gate of the transistor can be formed on its surface.

[0159] Figure 31 A schematic diagram of the structure obtained after removing the third sacrificial layer 113, as shown below. Figure 31As shown, after the third sacrificial layer 113 is removed, the word line trenches 112 are exposed. The third sacrificial layer 113 can be removed by etching.

[0160] That is, the embodiments of the present disclosure can first remove the second sacrificial layer 106, deposit a suitable channel material, and then remove the third sacrificial layer 113.

[0161] In this way, the embodiments of the present disclosure can remove all the third sacrificial layers 113 at one time after forming the required multi-layer stack, so that all the word line trenches 112 can be exposed by one etching operation, which simplifies the preparation process, saves costs, and is easy to implement.

[0162] S108: Forming a word line structure 117 in the word line trench 112.

[0163] It should be noted that not only the word line structure 117 (WL) but also the gate oxide layer 116 (GOX) is formed in the word line trench 112.

[0164] In some embodiments, the word line trench 112 exposes the channel region 1153 of the channel structure 115; before forming the word line structure 117 in the word line trench 112, the method can further include:

[0165] Forming a gate oxide layer 116 on the surface of the channel region 1153.

[0166] It should be noted that, Figure 32 is a schematic view of the structure obtained after forming the gate oxide layer 116. As shown, Figure 32 The gate oxide layer 116 is formed on the surface of the channel region 1153 of the channel structure 115. The gate oxide layer 116 can be formed by deposition or oxidation growth / in-situ growth, and the material of the gate oxide layer 116 can include silicon oxide. As shown, Figure 32 The gate oxide layer 116 surrounds the channel region 1153 and is used to form a GAA structure.

[0167] After forming the gate oxide layer 116, the word line structure 117 is formed in the remaining word line trench 112, and the structure shown in Figure 33 is obtained. As shown, Figure 33 The word line structure 117 completely fills the remaining word line trench 112. The word line structure 117 can be formed by deposition, and the material of the word line structure 117 can include conductive materials such as titanium nitride or metal (e.g., tungsten).

[0168] In short, the embodiments of the present disclosure first deposit the gate oxide layer 116 after removing the third sacrificial layer 113, and then deposit the metal word line to obtain the word line structure 117.

[0169] In this way, the word line structure 117 prepared in this way can be a horizontal word line structure, that is, the word line structure 117 extends along the first direction (horizontal plane).

[0170] It should be noted that the foregoing mentioned, in order to obtain better performance, reduce the parasitic capacitance, the embodiment of the present disclosure also proposes a staggered arrangement structure. Then, when based on the staggered structure as shown in Figure 24 , the cross-sectional schematic diagram of the finally obtained structure is as shown in Figure 34 ; similarly, when based on the staggered structure as shown in Figure 25 , the cross-sectional schematic diagram of the finally obtained structure is as shown in Figure 35 ; when based on the staggered structure as shown in Figure 26 , the cross-sectional schematic diagram of the finally obtained structure is as shown in Figure 36 .

[0171] In this way, the staggered structure obtained by using this staggered arrangement can also solve the problem of excessive parasitic capacitance and serious coupling of the channel structure and the word line structure, finally reduce the parasitic capacitance, improve the coupling, and improve the performance of the semiconductor structure.

[0172] Figure 37 The figure shows the cross-sectional schematic diagram of the structure obtained after step S108 based on the left figure in Figure 23 .

[0173] Further, in some embodiments, after forming the word line structure in the word line trench 112, the method can further include:

[0174] removing the first sacrificial layer 105 to expose the first doped region 1051 and the second doped region 1052;

[0175] doping the first doped region 1151 and the second doped region 1152 to form the source and the drain.

[0176] It should be noted that Figure 38 is the cross-sectional schematic diagram of the structure obtained after removing the first sacrificial layer 105. As shown by the arrow in Figure 38 , the doping treatment is performed in the direction indicated by the arrow. The doping treatment can be ion implantation, and the doping type can be P-type doping or N-type doping, which is not limited here.

[0177] Further, the capacitor, the stepped word line, etc. can be further processed or processed synchronously in the foregoing process, and the top view of the obtained structure can refer to Figure 39Wherein, BL represents Bit Line (BL), which can be seen as a vertical bit line; Staircase WL represents a staircase word line; CT represents a conductive contact structure such as a contact plug, which can connect the staircase word line structure with a peripheral circuit; CAP represents a capacitor; and the specific preparation process will not be described here in detail.

[0178] It should be further noted that the deposition methods involved in the embodiments of the present disclosure can include chemical vapor deposition (CVD), physical vapor deposition (PVD), and ALD, etc. The etching methods involved can include dry etching, wet etching, etc., which can be selected in combination with process conditions and material properties, and are not specifically limited here.

[0179] In summary, the embodiments of the present disclosure involve DRAM, in particular 3D DRAM, and utilize multiple sacrificial layers to prepare a semiconductor structure, thereby achieving the preparation of multiple 3D stacked structures together, and multiple implementation manners are exemplified. The etching selection ratio between each sacrificial layer material and the isolation layer 102 is different, and is greater than a preset ratio (for example: 10:1), so that when a certain sacrificial layer is removed, the isolation layer 102 and the remaining sacrificial layers will not be affected, ensuring the reliability of the etching process and avoiding affecting the morphology of the semiconductor structure.

[0180] The embodiments of the present disclosure provide a preparation method of a semiconductor structure, which comprises: providing a substrate; forming an isolation layer on the substrate; forming a first sacrificial layer and a second sacrificial layer extending along a first direction in the isolation layer, and the first sacrificial layer at least partially wrapping the second sacrificial layer; removing part of the first sacrificial layer and part of the isolation layer along a second direction to form a word line trench; forming a third sacrificial layer in the word line trench; wherein the second sacrificial layer, the third sacrificial layer, the retained isolation layer and the first sacrificial layer constitute a layer of stacked layers; continue to form a plurality of layers of stacked layers to form a stacked structure comprising at least one layer of stacked layers; remove the third sacrificial layer in the stacked structure to expose the word line trench; and form a word line structure in the word line trench. In this way, when preparing a semiconductor structure, a horizontal word line can be prepared by a simple and easy-to-implement process by using a multiple-sacrificial-layer method, which realizes the simplification of the manufacturing process while reducing the internal resistance of the memory, thereby improving the manufacturing yield and the electrical performance of the memory.

[0181] In another embodiment of the present disclosure, a semiconductor structure is provided, which is prepared according to the method of any one of the preceding embodiments. For example, the semiconductor structure can comprise: Figure 33 For example, the semiconductor structure can comprise: Figure 37 For example, the semiconductor structure can comprise:

[0182] a substrate 101;

[0183] a stack structure formed above the substrate 101, the stack structure comprising at least one stack layer;

[0184] wherein one stack layer comprises:

[0185] an isolation layer 102;

[0186] a channel structure 115 formed in the isolation layer 102, and the channel structure 115 extends along a first direction; wherein along the first direction, the channel structure 115 comprises a first doped region 1151, a channel region 1153 and a second doped region 1152;

[0187] a word line structure 117 formed in the isolation layer, the word line structure 117 extends along a second direction and wraps around the channel region 1153.

[0188] In some embodiments, the semiconductor structure further comprises a gate oxide layer 116 formed between the channel layer 1153 and the word line structure 117.

[0189] In some embodiments, along a third direction, the channel structures 116 in adjacent stack layers are staggered; and / or, along the third direction, the word line structures 117 in adjacent stack layers are staggered.

[0190] In some embodiments, the word line structure comprises a horizontal word line structure.

[0191] It should be noted that the semiconductor structure provided by the present embodiment is prepared by the preparation method provided by the foregoing embodiments, so that the semiconductor structure is easy to prepare, can not only reduce internal resistance, but also improve the coupling problem caused by excessive parasitic capacitance. For details not disclosed in the present embodiment, please refer to the description of the foregoing embodiments for understanding.

[0192] In still another embodiment of the present disclosure, see Figure 40 which shows a schematic diagram of the constituent structure of a memory provided by the present embodiment. As Figure 40 shown, the memory 40 comprises the semiconductor structure according to any one of the foregoing embodiments.

[0193] It should be noted that the memory 40 can be a semiconductor memory, such as a DRAM.

[0194] In the present embodiment, for DRAM, not only can it conform to the memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, etc., but also can conform to the memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., which are not limited here.

[0195] In this way, the parasitic capacitance of the memory 40 is small, coupling is improved, and performance is improved.

[0196] The above merely provides a preferred embodiment of the present disclosure, but is not intended to limit the protection scope of the present disclosure.

[0197] It should be noted that in the present disclosure, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0198] The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0199] The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

[0200] The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0201] The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0202] The above merely provides a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: providing a substrate; forming an isolation layer on the substrate; forming a first sacrificial layer and a second sacrificial layer extending along a first direction in the isolation layer, and the first sacrificial layer at least partially wrapping the second sacrificial layer; removing part of the first sacrificial layer and part of the isolation layer along a second direction to form a word line trench; forming a third sacrificial layer in the word line trench; wherein the second sacrificial layer, the third sacrificial layer, the remaining isolation layer and the first sacrificial layer form a stack layer; continuing to form a plurality of layers of the stack layer to form a stack structure comprising at least one layer of the stack layer; removing the third sacrificial layer in the stack structure to expose the word line trench; forming a word line structure in the word line trench.

2. The method of claim 1, wherein, The method of forming a first sacrificial layer and a second sacrificial layer extending along a first direction in the isolation layer comprises: forming a first trench extending along a first direction in the isolation layer; forming the first sacrificial layer on the bottom and side of the first trench; forming the second sacrificial layer in the remaining first trench.

3. The method of claim 2, wherein, The upper surface of the first sacrificial layer, the upper surface of the second sacrificial layer and the upper surface of the isolation layer are flush.

4. The method of claim 1, wherein, The method of forming a first sacrificial layer and a second sacrificial layer extending along a first direction in the isolation layer comprises: forming a first trench extending along a first direction in the isolation layer; forming a first sub-sacrificial layer on the bottom and side of the first trench; forming an initial second sacrificial layer in the remaining first trench; removing part of the initial second sacrificial layer to form a second trench, and the remaining initial second sacrificial layer forms the second sacrificial layer; forming a second sub-sacrificial layer in the second trench; wherein the first sub-sacrificial layer and the second sub-sacrificial layer form the first sacrificial layer.

5. The method of claim 4, wherein, The upper surface of the first sacrificial layer and the upper surface of the isolation layer are flush.

6. The method of claim 1, wherein, Before removing the third sacrificial layer in the stack structure, the method further comprises: removing the second sacrificial layer in the stack structure to form a channel trench; forming a channel structure in the channel trench.

7. The method of claim 6, wherein, The word line trench exposes a channel region of the channel structure; Before forming a word line structure in the word line trench, the method further comprises: forming a gate oxide layer on the surface of the channel region.

8. The method of claim 7, wherein, Along the first direction, the channel structure comprises the channel region and first and second doped regions located on both sides of the channel region; After forming a word line structure in the word line trench, the method further comprises: removing the first sacrificial layer to expose the first and second doped regions; performing a doping process on the first and second doped regions to form a source and a drain.

9. The method of claim 1, wherein, The method of removing part of the first sacrificial layer and part of the isolation layer along a second direction to form a word line trench comprises: forming a word line mask layer above the top surface of the isolation layer, the word line mask layer having a word line pattern extending along a second direction; performing pattern transfer with the word line mask layer as a mask to remove part of the first sacrificial layer and part of the isolation layer to form the word line trench; removing the word line mask layer.

10. The method of claim 9, wherein, In the pattern transfer with the word line mask layer as a mask, a part of the first sacrificial layer is removed by using an isotropic etching process.

11. The method according to any one of claims 1 to 10, characterized in that, The first sacrificial layer and the second sacrificial layer constitute a sacrificial structure, wherein: Along a third direction, the sacrificial structures in adjacent stack layers are arranged in a staggered manner; and / or, along the third direction, the third sacrificial layers are arranged in a staggered manner; The first direction, the second direction and the third direction are two by two intersected, and the first direction, the second direction and the third direction are not located in the same plane.

12. The method according to any one of claims 1 to 10, characterized in that, The material of the first sacrificial layer, the material of the second sacrificial layer and the material of the third sacrificial layer are respectively selected from one or more of polysilicon, carbon, monocrystalline silicon, silicon oxide and silicon nitride.

13. The method according to any one of claims 1 to 10, characterized in that, The material of the word line structure includes a conductive material, and the word line structure is a stepped word line structure.

14. The method according to any one of claims 1 to 10, characterized in that, The etching selection ratio between the first sacrificial layer, the second sacrificial layer, the third sacrificial layer and the isolation layer is greater than or equal to a preset ratio, wherein the preset ratio is 10:

1.

15. A memory, comprising: A semiconductor structure prepared by the method according to any one of claims 1 to 14.

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