Ferroelectric memory structure

Abstract

A ferroelectric memory structure includes a substrate, a ferroelectric capacitor structure, and a switching element. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, a plurality of first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the plurality of first dielectric layers are alternately stacked. The second electrode penetrates the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switching element is electrically connected to the ferroelectric capacitor structure.

Description

Technical Field

[0001] This invention relates to a memory structure, and more particularly to a ferroelectric memory structure. Background Technology

[0002] Ferroelectric memories (FEs) are a type of non-volatile memory, with the advantage that stored data is retained even after power loss. Furthermore, compared to other non-volatile memories, FEs offer higher reliability and faster operation speeds. However, the ongoing research focuses on enabling a single ferroelectric memory cell to have multiple storage states without increasing its area. Summary of the Invention

[0003] This invention provides a ferroelectric memory structure that allows a single ferroelectric memory cell to have multiple storage states without increasing the area of ​​the ferroelectric memory cell.

[0004] This invention proposes a ferroelectric memory structure, including a substrate, a ferroelectric capacitor structure, and a switching element. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, multiple first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the multiple first dielectric layers are alternately stacked. The second electrode passes through the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switching element is electrically connected to the ferroelectric capacitor structure.

[0005] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the ferroelectric capacitor structure can be disposed between the switching element and the substrate.

[0006] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the switching element may be a transistor. The switching element may include a channel layer, a third electrode, a fourth electrode, a fifth electrode, and a second dielectric layer. The channel layer is disposed on the ferroelectric capacitor structure. The third and fourth electrodes are disposed on the ferroelectric capacitor structure and are located on opposite sides of the channel layer. The fifth electrode is disposed on the channel layer. The second dielectric layer is disposed between the fifth electrode and the channel layer.

[0007] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the channel layer of the switching element can be electrically connected to the second electrode of the ferroelectric capacitor structure.

[0008] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the third electrode of the switching element can be electrically connected to the second electrode of the ferroelectric capacitor structure.

[0009] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the material of the channel layer may be an oxide semiconductor.

[0010] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), or cobalt oxide (CoO). x Nickel oxide (NiO) x ), SrCu2O x ), copper aluminum oxide (CuAlO2), copper indium oxide (CuInO2) or copper gallium oxide (CuGaO2).

[0011] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the materials of the third electrode and the fourth electrode can be N-type oxide semiconductor or P-type oxide semiconductor.

[0012] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the N-type oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO) or indium zinc oxide (IZO), and the N-type oxide semiconductor may have N-type dopants.

[0013] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the P-type oxide semiconductor includes cobalt oxide (CoO2). x Nickel oxide (NiO) x ), SrCu2O x P-type oxide semiconductors may contain P-type dopants.

[0014] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the switching element can be disposed between the ferroelectric capacitor structure and the substrate.

[0015] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the switching element may be a transistor. The switching element may include a third electrode, a second dielectric layer, a channel layer, a fourth electrode, and a fifth electrode. The third electrode is disposed on a substrate. The second dielectric layer is disposed on the third electrode and the substrate. The channel layer is disposed on the second dielectric layer and located above the third electrode. The fourth and fifth electrodes are disposed on the second dielectric layer and located on opposite sides of the channel layer.

[0016] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the channel layer of the switching element can be electrically connected to the second electrode of the ferroelectric capacitor structure.

[0017] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the fourth electrode of the switching element can be electrically connected to the second electrode of the ferroelectric capacitor structure.

[0018] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the fourth electrode and the fifth electrode may partially cover the channel layer.

[0019] According to one embodiment of the present invention, in the above-described ferroelectric memory structure, the material of the channel layer may be an oxide semiconductor.

[0020] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), or cobalt oxide (CoO). x Nickel oxide (NiO) x ), SrCu2O x ), copper aluminum oxide (CuAlO2), copper indium oxide (CuInO2) or copper gallium oxide (CuGaO2).

[0021] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the materials of the fourth electrode and the fifth electrode can be N-type oxide semiconductor or P-type oxide semiconductor.

[0022] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the N-type oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO) or indium zinc oxide (IZO), and the N-type oxide semiconductor may have N-type dopants.

[0023] According to an embodiment of the present invention, in the above-described ferroelectric memory structure, the P-type oxide semiconductor may include cobalt oxide (CoO2). x Nickel oxide (NiO) x ), SrCu2O x P-type oxide semiconductors may contain P-type dopants.

[0024] Based on the above, in the ferroelectric memory structure proposed in this invention, the ferroelectric capacitor structure includes at least one first electrode and multiple first dielectric layers stacked alternately, a second electrode passing through the first electrode, and a ferroelectric material layer disposed between the first and second electrodes. Furthermore, the first electrode can be used as a weighting state electrode. Therefore, when operating the ferroelectric memory structure, the impedance (e.g., capacitance) of the ferroelectric capacitor structure can be adjusted by applying voltages to the first and second electrodes respectively. In this way, a single ferroelectric memory cell can have multiple storage states without increasing the area of ​​the ferroelectric memory cell.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0026] Figure 1 This is a cross-sectional view of the ferroelectric memory structure according to some embodiments of the present invention;

[0027] Figure 2 for Figure 1 A three-dimensional schematic diagram of the ferroelectric capacitor structure in the image;

[0028] Figure 3 This is a cross-sectional view of the ferroelectric memory structure according to some embodiments of the present invention;

[0029] Figure 4 This is a cross-sectional view of the ferroelectric memory structure according to some embodiments of the present invention;

[0030] Figure 5 This is a cross-sectional view of the ferroelectric memory structure according to some embodiments of the present invention.

[0031] Symbol Explanation

[0032] 10,20: Ferroelectric memory structure

[0033] 100: Base

[0034] 102: Ferroelectric Capacitor Structure

[0035] 104, 204: Switching elements

[0036] 106, 110, 116, 118, 120, 216, 218, 220: Electrodes

[0037] 108,122,222: Dielectric layer

[0038] 112: Ferroelectric material layer

[0039] 114,214: Channel layer

[0040] FC: Ferroelectric capacitor

[0041] MC: Ferroelectric storage unit Detailed Implementation

[0042] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated by the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of explanation.

[0043] Figure 1 This is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention. Figure 2 for Figure 1 A three-dimensional schematic diagram of the ferroelectric capacitor structure. Figure 3 This is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention.

[0044] Please refer to Figure 1 and Figure 2 The ferroelectric memory structure 10 includes a substrate 100, a ferroelectric capacitor structure 102, and a switching element 104. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In this embodiment, the ferroelectric capacitor structure 102 may be disposed between the switching element 104 and the substrate 100, but the present invention is not limited thereto.

[0045] A ferroelectric capacitor structure 102 is disposed on a substrate 100. The ferroelectric capacitor structure 102 includes at least one electrode 106, a plurality of dielectric layers 108, an electrode 110, and a ferroelectric material layer 112. The at least one electrode 106 and the plurality of dielectric layers 108 are stacked alternately. The electrode 106 can be used as a weighted state electrode. The material of the electrode 106 is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or alloys thereof. The material of the dielectric layer 108 is, for example, silicon oxide, silicon nitride, hafnium nitride, or other dielectric materials. In this embodiment, the number of electrodes 106 is shown as a plurality, but the number of electrodes 106 is not limited to the number shown in the figure. As long as the number of electrodes 106 is at least one, it falls within the scope of this invention.

[0046] Electrode 110 passes through electrode 106. Furthermore, electrode 110 may pass through at least a portion of the plurality of dielectric layers 108. Electrode 110 can be used as a bulk electrode. The material of electrode 110 is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or alloys thereof.

[0047] A ferroelectric material layer 112 is disposed between electrode 106 and electrode 110. The material of the ferroelectric material layer 112 may include hafnium zirconium oxide (HfZrO).x HZO), lead zirconate titanate (Pb[Zr)) x Ti 1-x Strontium titanate (SrTiO3, PZT), barium titanate (BaTiO3, BTO), or bismuth ferrite (BiFeO3, BFO).

[0048] Furthermore, the ferroelectric capacitor structure 102 may include at least one ferroelectric capacitor FC, wherein each ferroelectric capacitor FC may include an electrode 106, an electrode 110, and a ferroelectric material layer 112. In this embodiment, the ferroelectric capacitor structure 102 is exemplified by including multiple ferroelectric capacitors FC electrically connected to each other, but the present invention is not limited thereto. In some embodiments, the multiple ferroelectric capacitors FC may share the electrode 110 and the ferroelectric material layer 112. Moreover, the number of ferroelectric capacitors FC is not limited to the number shown in the figures. As long as the number of ferroelectric capacitors FC is at least one, it falls within the scope of the present invention.

[0049] Switching element 104 is electrically connected to ferroelectric capacitor structure 102. In this embodiment, switching element 104 may be disposed on ferroelectric capacitor structure 102. In this embodiment, switching element 104 may be a transistor, but the present invention is not limited thereto. Switching element 104 may include channel layer 114, electrode 116, electrode 118, electrode 120, and dielectric layer 122. Channel layer 114 is disposed on ferroelectric capacitor structure 102. The material of channel layer 114 may be an oxide semiconductor. In some embodiments, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), or cobalt oxide (CoO). x Nickel oxide (NiO) x ), SrCu2O x ), copper aluminum oxide (CuAlO2), copper indium oxide (CuInO2) or copper gallium oxide (CuGaO2).

[0050] Electrodes 116 and 118 are disposed on the ferroelectric capacitor structure 102 and located on both sides of the channel layer 114. Electrodes 116 and 118 can be used as one of the source and the other as the drain, respectively. In this embodiment, electrode 116 can be used as the source and electrode 118 can be used as the drain. The materials of electrodes 116 and 118 can be N-type oxide semiconductors or P-type oxide semiconductors. In some embodiments, the N-type oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium zinc oxide (IZO), and the N-type oxide semiconductor may have N-type dopant. In some embodiments, the P-type oxide semiconductor includes cobalt oxide (CoO). x Nickel oxide (NiO) x), SrCu2O x The P-type oxide semiconductor may contain P-type dopants.

[0051] Electrode 120 is disposed on channel layer 114. Electrode 120 can be used as a gate. The material of electrode 120 is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or alloys thereof.

[0052] A dielectric layer 122 is disposed between the electrode 120 and the channel layer 114. In some embodiments, the dielectric layer 122 may also be disposed between the electrode 120 and the electrode 116, and between the electrode 120 and the electrode 118. The dielectric layer 122 can be used as a gate dielectric layer. The material of the dielectric layer 122 is, for example, a dielectric material such as silicon oxide, silicon nitride, or hafnium nitride.

[0053] In this embodiment, as Figure 1 As shown, the channel layer 114 of the switching element 104 can be electrically connected to the electrode 110 of the ferroelectric capacitor structure 102, thereby allowing the switching element 104 to be electrically connected to the ferroelectric capacitor structure 102. However, the invention is not limited thereto. In other embodiments, such as Figure 3 As shown, the electrode 116 of the switching element 104 can be electrically connected to the electrode 110 of the ferroelectric capacitor structure 102, thereby the switching element 104 can be electrically connected to the ferroelectric capacitor structure 102.

[0054] In addition, the ferroelectric memory structure 10 may also include other required dielectric layers (for isolation) and / or other required interconnect structures (for electrical connection), the description of which is omitted here.

[0055] The various storage states of the ferroelectric storage cell MC of the ferroelectric memory structure 10 are described below using Table 1. The ferroelectric storage cell MC of the ferroelectric memory structure 10 may include a ferroelectric capacitor structure 102 and a switching element 104 electrically connected to each other. By controlling the voltage applied to electrodes 106 and 110, the ferroelectric capacitor FC can be made to have a "positive (+) direction" polarization state or a "negative (-) direction" polarization state. When the ferroelectric capacitor FC has a "positive (+) direction" polarization state, the ferroelectric capacitor FC may have low impedance (e.g., low capacitance C). L When a ferroelectric capacitor FC has a "negative (-) direction" polarization state, the ferroelectric capacitor FC can have high impedance (e.g., high capacitance C). HTherefore, the impedance (e.g., capacitance) of each ferroelectric capacitor FC can be adjusted by applying voltages to electrodes 106 and 110. In this way, when operating the ferroelectric memory cell MC, electrode 106 can be used as a weighted state electrode, and the impedance (e.g., capacitance) of the ferroelectric capacitor structure 102 can be adjusted by applying voltages to electrodes 106 and 110 respectively, thereby allowing a single ferroelectric memory cell MC to have multiple storage states. In this embodiment, impedance is exemplified by capacitance, but the invention is not limited thereto.

[0056] For example, the ferroelectric capacitor structure 102 may include n electrodes 106, where n may be an integer greater than or equal to 1. As shown in Table 1, when the ferroelectric capacitor structure 102 includes n electrodes 106 (e.g., weighted state electrodes WE1 to WEn in Table 1), the ferroelectric capacitor structure 102 may include n ferroelectric capacitors FC electrically connected to each other. Thus, the ferroelectric memory cell MC of the ferroelectric memory structure 10 may have "n+1" storage states (i.e., "storage state 0" to "storage state n" in Table 1).

[0057] Table 1

[0058]

[0059] Based on the above embodiments, in the ferroelectric memory structure 10, the ferroelectric capacitor structure 102 includes at least one electrode 106 and a plurality of dielectric layers 108 stacked alternately, with an electrode 110 passing through the electrode 106, and a ferroelectric material layer 112 disposed between the electrode 106 and the electrode 110. Furthermore, the electrode 106 can be used as a weighted state electrode. Therefore, when operating the ferroelectric memory structure 10, the impedance (e.g., capacitance) of the ferroelectric capacitor structure 102 can be adjusted by applying voltages to the electrode 106 and the electrode 110 respectively. In this way, a single ferroelectric memory cell MC can have multiple storage states without increasing the area of ​​the ferroelectric memory cell MC.

[0060] Figure 4 This is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention. Figure 5 This is a cross-sectional view of a ferroelectric memory structure according to some embodiments of the present invention.

[0061] Please refer to Figure 1 and Figure 4 , Figure 4 Ferroelectric memory structure 20 and Figure 1 The differences in the ferroelectric memory structure 10 are as follows. Figure 4In the ferroelectric memory structure 20, the switching element 204 can be disposed between the ferroelectric capacitor structure 102 and the substrate 100. In this embodiment, the switching element 204 can be disposed on the substrate 100, and the ferroelectric capacitor structure 102 can be disposed on the switching element 204.

[0062] Switching element 204 is electrically connected to ferroelectric capacitor structure 102. In this embodiment, switching element 204 may be a transistor. Switching element 204 may include electrode 220, dielectric layer 222, channel layer 214, electrode 216, and electrode 218. Electrode 220 is disposed on substrate 100. Electrode 220 may be used as a gate. The material of electrode 220 may be, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or alloys thereof.

[0063] A dielectric layer 222 is disposed on the electrode 220 and the substrate 100. The dielectric layer 222 can be used as a gate dielectric layer. The material of the dielectric layer 222 is, for example, a dielectric material such as silicon oxide, silicon nitride, or hafnium nitride.

[0064] A channel layer 214 is disposed on the dielectric layer 222 and located above the electrode 220. The material of the channel layer 214 may be an oxide semiconductor. In some embodiments, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), or cobalt oxide (CoO). x Nickel oxide (NiO) x ), SrCu2O x ), copper aluminum oxide (CuAlO2), copper indium oxide (CuInO2) or copper gallium oxide (CuGaO2).

[0065] Electrodes 216 and 218 are disposed on dielectric layer 222 and located on both sides of channel layer 214. In some embodiments, electrodes 216 and 218 may partially cover channel layer 214. Electrodes 216 and 218 can be used as one of a source and the other as a drain, respectively. In this embodiment, electrode 216 can be used as a source, and electrode 218 can be used as a drain. The materials of electrodes 216 and 218 may be N-type oxide semiconductors or P-type oxide semiconductors. In some embodiments, the N-type oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium zinc oxide (IZO), and the N-type oxide semiconductor may have N-type dopant. In some embodiments, the P-type oxide semiconductor includes cobalt oxide (CoO). x Nickel oxide (NiO) x ), SrCu2O xThe P-type oxide semiconductor may contain P-type dopants.

[0066] In this embodiment, as Figure 4 As shown, the channel layer 214 of the switching element 204 can be electrically connected to the electrode 110 of the ferroelectric capacitor structure 102, thereby allowing the switching element 204 to be electrically connected to the ferroelectric capacitor structure 102. However, the invention is not limited thereto. For example, as... Figure 4 As shown, electrode 110 can be electrically connected to channel layer 214 through electrode 106 and dielectric layer 108. In other embodiments, such as Figure 5 As shown, electrode 216 of switching element 204 can be electrically connected to electrode 110 of ferroelectric capacitor structure 102, thereby enabling switching element 204 to be electrically connected to ferroelectric capacitor structure 102. For example, as Figure 5 As shown, electrode 110 can be electrically connected to electrode 216 through electrode 106 and dielectric layer 108.

[0067] Furthermore, the same or similar components in the ferroelectric memory structure 20 and the ferroelectric memory structure 10 are represented by the same or similar symbols, and the same or similar contents (e.g., operating methods) in the ferroelectric memory structure 20 and the ferroelectric memory structure 10 can be referred to the description of the ferroelectric memory structure 10 in the above embodiments, and will not be described again here. In addition, the ferroelectric memory structure 20 may also include other required dielectric layers (for isolation) and / or other required interconnect structures (for electrical connection), the description of which is omitted here.

[0068] Based on the above embodiments, in the ferroelectric memory structure 20, the ferroelectric capacitor structure 102 includes at least one electrode 106 and a plurality of dielectric layers 108 stacked alternately, with an electrode 110 passing through the electrode 106, and a ferroelectric material layer 112 disposed between the electrode 106 and the electrode 110. Furthermore, the electrode 106 can be used as a weighted state electrode. Therefore, when operating the ferroelectric memory structure 20, the impedance (e.g., capacitance) of the ferroelectric capacitor structure 102 can be adjusted by applying voltages to the electrode 106 and the electrode 110 respectively. In this way, a single ferroelectric memory cell MC can have multiple storage states without increasing the area of ​​the ferroelectric memory cell MC.

[0069] In summary, in the ferroelectric memory structure of the above embodiments, the ferroelectric capacitor structure includes at least one weighted state electrode and multiple dielectric layers stacked alternately, and the weighted state electrode can be used to adjust the impedance (e.g., capacitance) of the ferroelectric capacitor structure. Therefore, a single ferroelectric memory cell can have multiple storage states without increasing the area of ​​the ferroelectric memory cell.

[0070] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A ferroelectric memory structure, comprising: Base; A ferroelectric capacitor structure, disposed on the substrate, and comprising: At least one first electrode and a plurality of first dielectric layers are stacked alternately; A second electrode, passing through the first electrode; and A ferroelectric material layer is disposed between the first electrode and the second electrode; and A switching element is electrically connected to the ferroelectric capacitor structure. The second electrode is in direct contact with the ferroelectric material layer.

2. The ferroelectric memory structure as claimed in claim 1, wherein the ferroelectric capacitor structure is disposed between the switching element and the substrate.

3. The ferroelectric memory structure as described in claim 2, wherein the switching element is a transistor, and includes: A channel layer is disposed on the ferroelectric capacitor structure; The third and fourth electrodes are disposed on the ferroelectric capacitor structure and located on both sides of the channel layer; The fifth electrode is disposed on the channel layer; as well as A second dielectric layer is disposed between the fifth electrode and the channel layer.

4. The ferroelectric memory structure of claim 3, wherein the channel layer of the switching element is electrically connected to the second electrode of the ferroelectric capacitor structure.

5. The ferroelectric memory structure as claimed in claim 3, wherein the third electrode of the switching element is electrically connected to the second electrode of the ferroelectric capacitor structure.

6. The ferroelectric memory structure of claim 3, wherein the material of the channel layer comprises an oxide semiconductor.

7. The ferroelectric memory structure of claim 6, wherein the oxide semiconductor includes indium gallium zinc oxide, zinc oxide, indium zinc oxide, cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide, or copper gallium oxide.

8. The ferroelectric memory structure as claimed in claim 3, wherein the materials of the third electrode and the fourth electrode comprise N-type oxide semiconductors or P-type oxide semiconductors.

9. The ferroelectric memory structure of claim 8, wherein the N-type oxide semiconductor comprises indium gallium zinc oxide, zinc oxide, or indium zinc oxide, and the N-type oxide semiconductor has an N-type dopant.

10. The ferroelectric memory structure of claim 8, wherein the P-type oxide semiconductor comprises cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide, or copper gallium oxide, and the P-type oxide semiconductor has a P-type dopant.

11. The ferroelectric memory structure of claim 1, wherein the switching element is disposed between the ferroelectric capacitor structure and the substrate.

12. The ferroelectric memory structure of claim 11, wherein the switching element is a transistor, and comprises: A third electrode is disposed on the substrate; A second dielectric layer is disposed on the third electrode and the substrate; A channel layer is disposed on the second dielectric layer and located above the third electrode; as well as The fourth and fifth electrodes are disposed on the second dielectric layer and located on both sides of the channel layer.

13. The ferroelectric memory structure of claim 12, wherein the channel layer of the switching element is electrically connected to the second electrode of the ferroelectric capacitor structure.

14. The ferroelectric memory structure of claim 12, wherein the fourth electrode of the switching element is electrically connected to the second electrode of the ferroelectric capacitor structure.

15. The ferroelectric memory structure of claim 12, wherein the fourth electrode and the fifth electrode partially cover the channel layer.

16. The ferroelectric memory structure of claim 12, wherein the material of the channel layer comprises an oxide semiconductor.

17. The ferroelectric memory structure of claim 16, wherein the oxide semiconductor comprises indium gallium zinc oxide, zinc oxide, indium zinc oxide, cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide, or copper gallium oxide.

18. The ferroelectric memory structure of claim 12, wherein the material of the fourth electrode and the material of the fifth electrode comprise N-type oxide semiconductor or P-type oxide semiconductor.

19. The ferroelectric memory structure of claim 18, wherein the N-type oxide semiconductor comprises indium gallium zinc oxide, zinc oxide, or indium zinc oxide, and the N-type oxide semiconductor has an N-type dopant.

20. The ferroelectric memory structure of claim 18, wherein the P-type oxide semiconductor comprises cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide, or copper gallium oxide, and the P-type oxide semiconductor has a P-type dopant.

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