A method and device for processing graphic instructions

Abstract

A graph instruction processing method and device, relating to the field of computer technology, is used to improve the performance of a directed graph flow computing architecture. The method is applied in a processor, comprising: detecting whether a first input and a second input of a first graph instruction are in a ready state, the first input and / or the second input being a dynamic data input of the first graph instruction (S301); when both the first input and the second input are in a ready state, obtaining static data input information of the first graph instruction from a first register, the static data input information being used to indicate at least one input (S302), each of the at least one input being a constant input or a temporary constant input; processing the first graph instruction according to the first input, the second input and the at least one input, and obtaining a first processing result (S303).

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and device for processing graphic instructions. Background Art

[0002] The graph flow computing architecture converts data flow and control flow into a directed graph consisting of N nodes. The connection between nodes represents a data flow or a control flow. In the graph flow computing architecture, the parallelism of the data flow is triggered by detecting whether the input of each node in the graph flow computing architecture is ready, so that multiple nodes that are not on the same path can run concurrently.

[0003] In a directed graph flow computing architecture, most graph instructions usually have two data inputs and one or two output IDs. A small number of graph instructions have at least three data inputs or at least three output IDs, and the cache used to temporarily store the data input and output ID of a graph instruction is configured according to two data inputs and two output IDs. Among them, graph instructions with at least three data inputs generally compress multiple instructions that complete operations in multiple beats into a composite graph instruction that completes operations in one beat. Instructions with at least three output IDs usually need to output the operation results of the graph instruction to the inputs of multiple other graph instructions. For example, Figure 1 The graph instruction add-sll with three data inputs (i.e., i, j, and k) shown in (a) of FIG. 1 is a compound instruction compressed from the graph instructions add and sll; or Figure 1 As shown in (b) in FIG, there is a graph instruction with four output IDs (i.e., i1, i2, i3, and i4). Assuming that the calculation result of the graph instruction is i0, i0 needs to be output to i1, i2, i3, and i4.

[0004] In the prior art, graph instructions with at least three data inputs are usually processed in the following ways. The first is to multiplex the input port of the original graph instruction to the corresponding composite graph instruction. For example, the data inputs i, j and k of the graph instructions add and sll are read at the same time, and i, j and k are transmitted to the operation unit of add-sll. This method will increase the pressure of reading data inputs at the same time. In addition, since most instructions only need to read two data inputs, the difficulty of bypass logic will increase. The second method is to rewrite the input port of the original graph instruction to the operation unit of the composite graph instruction through rescheduling. For example, the writing of i, j and k is rescheduled to the operation unit of add-sll. This method requires the setting of a special rescheduling logic unit, which will increase the difficulty of hardware implementation and increase hardware costs.

[0005] For graph instructions with at least three output IDs, they are usually processed in the following ways. The first is to expand the number of bits occupied by the output ID, such as uniformly expanding the original 32 bits to 64 bits. However, since most graph instructions have only one or two output IDs, this will cause a waste of instruction space. The second is to use the CISC encoding method, that is, to adjust the encoding width by adding the number of output IDs in the graph instruction format, but this method will increase the difficulty of hardware decoding, thereby generating greater power consumption. The third is to use a method of limiting the output ID, that is, multiple output IDs share the same high-order bits and use different low-order bits respectively, but the multiple output IDs encoded in this way are adjacent, which will limit the position of the output ID, thereby greatly limiting the scheduling capability and reducing the performance of the computing architecture. Summary of the invention

[0006] The present application provides a graph instruction processing method and device for improving the performance of a directed graph flow computing architecture.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a method for processing a graph instruction is provided, which is applied to a processor, and the method includes: detecting whether a first input and a second input of a first graph instruction are in a ready state, the first input and / or the second input being a dynamic data input of the first graph instruction; when both the first input and the second input are in a ready state, obtaining static data input information of the first graph instruction from a first register, the static data input information being used to indicate at least one input, each of the at least one input being a constant input or a temporary constant input, and the temporary constant input being an input that does not change within a period of time; processing the first graph instruction according to the first input, the second input and at least one input to obtain a first processing result.

[0009] In the above technical scheme, for the first graph instruction with at least three data inputs, there are usually one or two dynamic data inputs and one or more static data inputs among the at least three data inputs. The one or more static data inputs can be stored in the first register. The subsequent processor can detect whether the first input and the second input of the first graph instruction are in a ready state, and when in the ready state, obtain the static data input of the first graph instruction from the first register to process the first graph instruction, thereby avoiding the interference of the intermediate state data of the first graph instruction on other data streams, and at the same time reducing the relocation operation of the static data input of the first graph instruction, increasing the reuse efficiency of the static data input, and thereby improving the performance of the directed graph flow computing architecture.

[0010] In a possible implementation of the first aspect, the first graph instruction is provided with an input pointer field segment, the input pointer field segment includes a first pointer, and the first pointer is used to indicate a first register. In the above possible implementation, the first pointer indicates the first register, so that the processor can quickly and effectively determine the first register, thereby obtaining the static data input stored in the first register.

[0011] In a possible implementation of the first aspect, the at least one input includes multiple inputs, and the method further includes: decoding the static data input information according to a preset decoding strategy associated with an operator of the first graph instruction to obtain the multiple inputs. In the above possible implementation, when the first register stores multiple inputs, the processor can decode according to the preset decoding strategy to obtain the multiple inputs.

[0012] In a possible implementation of the first aspect, the first graph instruction has at least three output addresses, the output address field of the first graph instruction is used to indicate one or two output addresses of the at least three output addresses, and the other output addresses except one or two output addresses of the at least three output addresses are stored in a second register, and the method further includes: sending the first processing result to one or two output addresses; obtaining the output address information of the first graph instruction from the second register, and sending the first processing result to the output address indicated by the output address information. In the above possible implementation, when the first graph instruction has at least three output addresses, one or more of the at least three output addresses can be stored in the second register, so that one or more output addresses of the first graph instruction can be obtained from the second register later, and the first processing result is sent to each output address, thereby realizing the result processing of the graph instruction with at least three output addresses.

[0013] In a possible implementation of the first aspect, the output address field includes an output address and a second pointer, and the second pointer is used to indicate a second register; or, the output address field includes two output addresses, and the first diagram instruction is further provided with an output pointer field, and the output pointer field includes a second pointer, and the second pointer is used to indicate a second register. In the above possible implementations, the second register is indicated by the second pointer included in the output address field or the output pointer field, which can improve the flexibility and diversity of indicating the second register.

[0014] In a possible implementation of the first aspect, the method further includes: decoding the output address information to obtain at least one output address; correspondingly, sending the first processing result to the output address indicated by the output address information, including: sending the first processing result to each of the at least one output address. In the above possible implementation, it can be ensured that the graph instructions with at least three output addresses in the instruction set are configured in a relatively regular format into the directed graph flow computing architecture.

[0015] In a second aspect, a method for processing a graph instruction is provided, the method comprising: determining a first processing result of a first graph instruction, the first graph instruction having at least three output addresses, the output address field of the first graph instruction being used to indicate one or two output addresses of the at least three output addresses, and the other output addresses except one or two output addresses of the at least three output addresses being stored in a second register; sending the first processing result to one or two output addresses; obtaining the output address information of the first graph instruction from the second register, and sending the first processing result to the output address indicated by the output address information.

[0016] In the above technical solution, when the first graph instruction has at least three output addresses, one or more of the at least three output addresses can be stored in the second register, so that the graph instructions with at least three output addresses in the instruction set can be configured into the directed graph flow computing architecture in a relatively regular format. Subsequently, when outputting the first processing result of the first graph instruction, one or more output addresses of the first graph instruction can be obtained from the second register, and the first processing result can be sent to each output address, thereby realizing the result processing of the graph instruction with at least three output addresses; at the same time, compared with the prior art, this method will not cause waste of instruction space, nor will it generate large power consumption, thereby ensuring that the computing architecture has better performance.

[0017] In a possible implementation of the second aspect, the output address field includes an output address and a second pointer, and the second pointer is used to indicate a second register; or, the output address field includes two output addresses, and the first diagram instruction is further provided with an output pointer field, and the output pointer field includes a second pointer, and the second pointer is used to indicate a second register. In the above possible implementations, the second register is indicated by the second pointer included in the output address field or the output pointer field, which can improve the flexibility and diversity of indicating the second register.

[0018] In a possible implementation of the second aspect, the method further includes: decoding the output address information to obtain at least one output address; accordingly, sending the first processing result to the output address indicated by the output address information, including: sending the first processing result to each of the at least one output address. In the above possible implementation, it can be ensured that the graph instructions with at least three output addresses in the instruction set are configured in a relatively regular format into the directed graph flow computing architecture.

[0019] In a third aspect, a graph instruction processing device is provided, the device comprising: a detection unit, used to detect whether a first input and a second input of a first graph instruction are in a ready state, the first input and / or the second input being a dynamic data input of the first graph instruction; a first operation unit, used to obtain static data input information of the first graph instruction from a first register when both the first input and the second input are in a ready state, the static data input information being used to indicate at least one input, each of the at least one input being a constant input or a temporary constant input, the temporary constant input being an input that does not change within a period of time; the first operation unit is also used to process the first graph instruction according to the first input, the second input and at least one input to obtain a first processing result.

[0020] In a possible implementation manner of the third aspect, the first graph instruction is provided with an input pointer field segment, the input pointer field segment includes a first pointer, and the first pointer is used to indicate a first register.

[0021] In a possible implementation of the third aspect, at least one input includes multiple inputs, and the first operation unit is further used to: decode static data input information according to a preset decoding strategy associated with an operator of the first graph instruction to obtain multiple inputs.

[0022] In a possible implementation of the third aspect, the first graph instruction has at least three output addresses, the output address field of the first graph instruction is used to indicate one or two output addresses of the at least three output addresses, and the other output addresses except one or two output addresses of the at least three output addresses are stored in a second register, and the device also includes: a second operation unit; the first operation unit is also used to send the first processing result to one or two output addresses; the second operation unit is used to obtain the output address information of the first graph instruction from the second register, and send the first processing result to the output address indicated by the output address information.

[0023] In a possible implementation of the third aspect, the output address field segment includes an output address and a second pointer, and the second pointer is used to indicate a second register; or, the output address field segment includes two output addresses, and the first diagram instruction is also provided with an output pointer field segment, and the output pointer field segment includes a second pointer, and the second pointer is used to indicate a second register.

[0024] In a possible implementation manner of the third aspect, the first operation unit is further used to: decode the output address information to obtain at least one output address; and send the first processing result to each output address of the at least one output address.

[0025] In a fourth aspect, a graph instruction processing device is provided, the device comprising: a first operation unit, used to determine a first processing result of a first graph instruction, the first graph instruction having at least three output addresses, the output address field of the first graph instruction being used to indicate one or two output addresses of the at least three output addresses, and the other output addresses except one or two output addresses of the at least three output addresses being stored in a second register; the first operation unit is also used to send the first processing result to the one or two output addresses; the second operation unit is used to obtain the output address information of the first graph instruction from the second register, and send the first processing result to the output address indicated by the output address information.

[0026] In a possible implementation of the fourth aspect, the output address field segment includes an output address and a second pointer, and the second pointer is used to indicate a second register; or, the output address field segment includes two output addresses, and the first diagram instruction is also provided with an output pointer field segment, and the output pointer field segment includes a second pointer, and the second pointer is used to indicate a second register.

[0027] In a possible implementation manner of the fourth aspect, the first operation unit is further used to: decode the output address information to obtain at least one output address; and send the first processing result to each output address of the at least one output address.

[0028] In another aspect of the present application, a graph instruction processing device is provided, which may be a graph instruction processing device or a chip built into the graph instruction processing device. The device includes a processor, which is coupled to a memory, in which instructions are stored. When the processor runs the instructions in the memory, the device executes the method provided in the first aspect or any possible implementation of the first aspect.

[0029] In another aspect of the present application, a graph instruction processing device is provided, which may be a graph instruction processing device or a chip built into the graph instruction processing device. The device includes a processor, which is coupled to a memory, in which instructions are stored. When the processor runs the instructions in the memory, the device executes the method provided in the second aspect or any possible implementation of the second aspect.

[0030] In another aspect of the present application, a readable storage medium is provided, in which instructions are stored. When the readable storage medium is executed on a device, the device executes the method provided by the first aspect or any possible implementation of the first aspect.

[0031] In another aspect of the present application, a readable storage medium is provided, in which instructions are stored. When the readable storage medium is executed on a device, the device executes the method provided by the second aspect or any possible implementation of the second aspect.

[0032] In another aspect of the present application, a computer program product is provided. When the computer program product is run on a computer, the computer is enabled to execute the method provided by the first aspect or any possible implementation manner of the first aspect.

[0033] In another aspect of the present application, a computer program product is provided. When the computer program product is run on a computer, the computer is enabled to execute the method provided by the second aspect or any possible implementation manner of the second aspect.

[0034] It can be understood that any device, computer storage medium or computer program product of any of the above-mentioned graph instruction processing methods is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a graph instruction with multiple inputs and a graph instruction with multiple outputs;

[0036] Figure 2 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of different stages of a computing architecture provided in an embodiment of the present application;

[0039] Figure 5 A schematic diagram of different stages of another computing architecture provided in an embodiment of the present application;

[0040] Figure 6 A flowchart of a method for processing a graph instruction provided in an embodiment of the present application;

[0041] Figure 7 A schematic diagram of a graph instruction with multiple inputs provided in an embodiment of the present application;

[0042] Figure 8 A schematic diagram of a flow chart of another method for processing a graph instruction provided in an embodiment of the present application;

[0043] Fig. 9 A schematic diagram of a graph instruction with multiple outputs provided in an embodiment of the present application;

[0044] Fig.10 A schematic diagram of a register provided in an embodiment of the present application;

[0045] Fig.11 A flowchart of a method for processing a graph instruction provided in an embodiment of the present application;

[0046] Fig.12 A schematic diagram of a graph instruction provided in an embodiment of the present application;

[0047] Fig.13 A schematic diagram of the structure of a graph instruction processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple. In addition, in the embodiments of the present application, the words "first", "second" and the like do not limit the quantity and execution order.

[0049] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0050] First, before introducing the embodiments of the present application, the water pipeline structure and processor architecture of the instructions involved in the present application are illustrated.

[0051] Instruction pipeline refers to a method of dividing the operation of an instruction into multiple small steps for processing in order to improve the efficiency of the processor in executing instructions. Each step can be completed by a corresponding unit. Among them, the life cycle of an instruction in the pipeline structure may include instruction fetch pipeline → decoding pipeline → scheduling (issuance) pipeline → execution pipeline → memory access pipeline → write back pipeline, that is, the pipeline structure divides the execution process of an instruction into at least the following six stages.

[0052] Instruction fetch pipeline: used for instruction fetch, which is the process of reading instructions from memory.

[0053] Decoding pipeline: used for instruction decoding, which is the process of translating instructions taken out of the memory.

[0054] Scheduling (issuing) pipeline: used for instruction dispatch and issue, that is, reading registers to obtain operands, and sending the instruction to the corresponding execution unit for execution according to the type of instruction.

[0055] Execution pipeline: refers to the execution of instructions according to the type of instructions to complete the computing task. Instruction execution refers to the process of actually performing operations on instructions. For example, if the instruction is an addition instruction, the operands are added; if it is a subtraction instruction, a subtraction operation is performed; if it is a graph calculation, a graph calculation operation is performed.

[0056] Memory access pipeline: Memory access refers to the process of memory access instructions reading data from the memory or writing data into the memory, mainly executing read / write (load / store) instructions.

[0057] Write back pipeline: Write back refers to the process of writing the result of instruction execution back to the general register group. If it is a normal operation instruction, the result value comes from the result calculated in the "execution" stage; if it is a memory read instruction, the result comes from the data read from the memory in the "memory access" stage.

[0058] In the above pipeline structure, each instruction in the processor must go through the above operation steps, but different operation steps of multiple instructions can be executed simultaneously, thereby speeding up the instruction flow speed as a whole and shortening the program execution time.

[0059] Figure 2 The schematic diagram of the structure of a processor 10 provided in an embodiment of the present application, the processor 10 can be located in any electronic device, such as a computer, a mobile phone, a tablet, a personal digital assistant, a smart wearable device, a smart car or a smart home appliance. The processor 10 can specifically be a chip or a chipset or a circuit board equipped with a chip or a chipset. The chip or chipset or the circuit board equipped with a chip or a chipset can work under the necessary software drive.

[0060] Specifically, the processor 10 may include at least one processor core 101, and the processor core 101 may include an instruction scheduling unit 1011, a graph computing flow unit 1012 connected to the instruction scheduling unit 1011, and at least one general computing unit 1013. Among them, the instruction scheduling unit 1011 runs in the emission pipeline stage of the processor core 101 to complete the scheduling and distribution of the instructions to be executed; and the graph computing flow unit 1012 and at least one general computing unit 1013 are both executed as the execution unit (also referred to as the functional unit) of the processor 10 and run in the execution pipeline stage (execute stage) to complete various types of computing tasks. Specifically, the processor 10 can directly assign the graph computing tasks in the instructions to be executed to the graph computing flow unit 1012 for execution through the instruction scheduling unit 1011, so as to realize the function of accelerating the general processor through the graph computing mode; and the general computing tasks in the instructions to be executed are scheduled to the at least one general computing unit 1013 for execution to realize the general computing function. Optionally, the processor 10 may call the graph computing flow unit 1012 to execute the task alone, or call at least one general computing unit 1013 to execute the task alone, or call the graph computing flow unit 1012 and the at least one general computing unit 1013 to execute the task in parallel, depending on the computing task. It is understandable that the instruction scheduling unit 1011 may be connected to the graph computing flow unit 1012 and the at least one general computing unit 1013 via a bus or other means to communicate directly. Figure 1 The connection relationships shown in the figure do not limit the connection relationships between them.

[0061] In one possible implementation, Figure 3 A structural diagram of another processor 10 provided in an embodiment of the present application, the processor core 101 may also include an instruction acquisition unit 1015 and an instruction decoding unit 1016, which respectively run in the instruction fetch pipeline stage and the decoding pipeline stage, and complete the corresponding instruction fetch and instruction decoding functions.

[0062] Optional, such as Figure 3As shown, the at least one general-purpose operation unit 1013 may specifically include one or more of a memory read / write unit (load store unit, LSU) 1013A, a floating point unit (floating point unit, FPU) 1013B, a vector operation unit (single instruction multiple data, SIMD) 1013C, and an arithmetic and logic unit (arithmetic and logic unit, ALU) 1013D. The above-mentioned multiple general-purpose operation units (including 1013A, 1013B, 1013C, 1013D) and the graph calculation flow unit 1012 are all connected to the instruction scheduling unit 1011, and run in the execution pipeline stage as the execution unit of the processor core 101. The above-mentioned execution units receive different types of instructions scheduled by the instruction scheduling unit 1011, and then execute the operation tasks of the types they are good at based on their own different hardware structures. Further optionally, the processor core 101 of the processor 10 also includes a memory unit (memory) 1017 outside the core, and the above-mentioned memory read and write unit 1013A reads and writes data from the memory unit 1017 and runs in the memory access pipeline stage. Further optionally, the processor core 101 also includes a result write back unit 1014, which runs in the write back pipeline stage and is responsible for writing the calculation result of the instruction back to the destination register. Optionally, the memory unit 1017 is usually a power-off volatile memory, and the content stored thereon will be lost when the power is off. It can also be called memory (memory) or main memory. The memory unit 1017 can be used as a storage medium for temporary data of the operating system or other running programs in the processor 10. For example, the operating system running on the processor 10 transfers the data to be calculated from the memory unit 1017 to the processor core 101 for calculation, and the processor core 101 transmits the result after the calculation is completed. The memory unit 1017 may include one or more of dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), first level cache (L1 cache), second level cache (L2 cache), third level cache (L3 cache), etc.

[0063] It should be noted that Figure 3 The various functional modules in the processor can communicate with each other through a bus or other connection methods. Figure 3The connection relationship shown does not constitute a limitation on the connection relationship between them. Each functional module will be further described in the subsequent embodiments, which will not be described in detail here.

[0064] It can be understood that the pipeline structure and processor architecture of the above instructions are just some exemplary implementations provided in the embodiments of the present application. The pipeline structure and processor architecture in the embodiments of the present application include but are not limited to the above implementations.

[0065] The following is a detailed description of the directed graph flow computing architecture involved in this application. Figure 4 , the directed graph flow computing architecture in this application can be abstracted into N fully connected computing nodes (corresponding to the vertices of the graph). Each node can place an instruction, perform an operation, and pass the result to itself or other nodes. The directed graph flow computing architecture can be divided into two stages of repeated switching:

[0066] 1. Graph building stage: read N instructions of the graph building block from the instruction memory, configure one operation instruction and up to two target nodes for each node in the graph building block, assuming that when N is equal to 16, there are 0 to 15 computing nodes in total. Once the graph building is completed, the operation and connection of each node are solidified (read-only). For example, the operation instruction in computing node 0 is the add instruction, that is, the addition operation is performed; the operation instruction in computing node 1 is the sll instruction, that is, the shift operation; the operation instruction of computing node 3 is the xor instruction, that is, the exclusive or operation. For computing node 5, the operation results of computing node 0 and computing node 1 are used as the input of the computing node, thereby performing the ld operation (i.e., the instruction fetch operation); for computing node 6, the operation results of computing node 2 and computing node 3 are used as the input of the computing node, thereby performing the add operation (i.e., the addition operation), and so on. The operation process of other computing nodes will not be described one by one.

[0067] 2. Execution phase (graph execute): The external module passes in input (liveIn) to start the data flow. All computing nodes run in parallel. For each node, as long as its input arrives, it can perform calculations and pass the results to the next computing node; if the input does not arrive, it is in a waiting state. The operation continues until the data flow reaches the end node (tm). Because the input parameters of some computing nodes (such as computing nodes 0, 1, 2, and 3) are input externally, that is, the startup data needs to be input from the external memory unit 1017; and the other computing nodes (such as computing nodes 5, 6, 8, 9, 10, 11, 12, 13, 14, and 15) need to obtain the calculation results output by the computing nodes with which they are connected from the inside, and then they can perform calculations and input the results of the calculations to the computing nodes associated with them.

[0068] Based on the directed graph flow computing architecture provided by the present application, when the instruction scheduling unit 1011 in the processor 10 schedules control instructions to the graph computing flow unit 1012 to execute instruction tasks, it includes control instructions of various functions, thereby instructing the graph computing flow unit 1012 to execute corresponding graph computing functions. In terms of the order of timing, the control instructions provided by the present application mainly include start graph composition instructions → parameter transmission instructions → start graph computing instructions → parameter return instructions.

[0069] Among them, the start composition instruction carries a target address. When the graph calculation flow unit 1012 receives the start composition instruction, it can read the composition block information from the memory unit 1017 according to the target address. The composition block information can include the operation method of each of the N computing nodes in the directed graph flow computing architecture, and the connection and sequence information between the N computing nodes. The parameter transmission instruction can carry the identifiers of M computing nodes and the input parameters corresponding to the identifiers of the M computing nodes. The M computing nodes are part or all of the N nodes. When the graph calculation flow unit 1012 receives the parameter transmission instruction, it can input the input parameters corresponding to the identifiers of the M computing nodes into the M computing nodes. After receiving the start graph calculation instruction, the graph calculation flow unit 1012 can determine whether the current composition has been completed; if completed, the corresponding computing task is started. The return parameter instruction can carry the identifiers of K computing nodes and the result registers corresponding to the identifiers of these K computing nodes. The graph computing flow unit 1012 can control the calculation results of these K computing nodes to be sent to the result write back unit 1014 respectively, and the result write back unit 1014 writes the results of the corresponding computing nodes in the corresponding result registers.

[0070] For example, Figure 5 Schematic diagram of different control instructions provided in the embodiment of the present application. Figure 5 In the example, the start composition instruction is gfb 0x600960, where gfb is an operation code, 0x600960 is an operand and is an address in the memory unit 1017, and the graph computing flow unit 1012 can obtain the composition block information corresponding to the address 0x600960 from the memory unit 1012 according to the start composition instruction to start composition. Figure 5In the graph computing execution phase, the parameter passing instructions include "gfmov x0, 1r", "gfmov x1, 101", "gfmov x8, 21" and "gfmov x9, 151". The first parameter passing instruction means to use the parameter value in register x0 as the right input parameter in computing node 1, the second parameter passing instruction means to use the parameter value in register x1 as the left input parameter in computing node 10, and so on.<GBB_address> , triggering the graph computation flow unit 1012 to check whether the GFU composition is completed, and the composition block address previously started<GBB_address> Is it consistent with the executed composition block? If the composition block is inconsistent, it is necessary to restart the composition unit to recompose. Figure 1 Once the graph is completed, the graph calculation can be started immediately. Figure 5 In the example, the return parameter instruction is "gfmov101, x2", and the graph computation flow unit 1012 can send the left input parameter of the computation node 10 to the result write back unit 1014 so that the result is written into the register x2.

[0071] After introducing the directed graph flow computing architecture, the following is an introduction to the graph instructions in the directed graph computing architecture. In the directed graph computing architecture, most graph instructions usually have two data inputs and one or two output addresses, and a small number of graph instructions have at least three data inputs or at least three output addresses, and the data input used to temporarily store a graph instruction and the instruction format used to indicate the output address are configured according to two data inputs and two output addresses. That is, a graph instruction is only provided with a cache space for two inputs. For example, if the cache space for one input is 64 bits, then the cache space corresponding to a graph instruction is 128 bits; the instruction format of a graph instruction is usually instruction ID+opcode (operator)+dest0+dest1, and dest0 and dest1 are the two output addresses.

[0072] Among them, for a graph instruction with two data inputs or a graph instruction with two output addresses, the processor can process the corresponding graph instruction according to the existing configuration. For a graph instruction with at least three data inputs, there are usually one or two dynamic data inputs and one or more static data inputs among the at least three data inputs. Under the configuration of the existing data input cache, the embodiment of the present application implements the processing of the graph instruction by storing the one or more static data inputs in a register. The specific process is described as follows. For a graph instruction with at least three output addresses, under the configuration of the existing instruction format, the embodiment of the present application implements the processing of the graph instruction by storing one or more output addresses in a register. The specific process is described as follows.

[0073] Figure 6 A flowchart of a method for processing a graph instruction provided in an embodiment of the present application is provided. The method can be applied to the processor provided above, and the method includes the following steps.

[0074] S301: Detect whether the first input and the second input of the first image instruction are in a ready state, the first input and / or the second input being the dynamic data input of the first image instruction.

[0075] Among them, the graph instruction may refer to a graph instruction in a directed graph computing architecture instruction set, and the instruction set may include multiple graph instructions. The first graph instruction may be a graph instruction with at least three inputs in the instruction set. For example, the first graph instruction may be a composite graph instruction compressed by multiple graph instructions. The at least three inputs of the first graph instruction may include dynamic data input and static data input. The dynamic data input may refer to dynamically changing data input, and dynamically changing data may also be called a variable. The static data input may refer to data input that does not change, or data input that does not change within a period of time. Data that does not change may also be called a constant, and data that does not change within a period of time may also be a temporary constant.

[0076] In addition, the first graph instruction may correspond to one or more ready fields and one or more valid fields. The valid field of the first graph instruction may be used to indicate whether the first graph instruction needs to input data flow information, and the data flow information may include two of the at least three inputs of the first graph instruction. The two inputs may be the first input and the second input, respectively, and the first input and the second input may both be dynamic data inputs, or one of the first input and the second input may be a dynamic data input and the other may be a static data input (for example, the first graph instruction has only one dynamic data input). The first input and the second input may also be referred to as the left input and the right input, respectively. The ready field of the first graph instruction may be used to indicate whether the data flow information of the first graph instruction is ready, for example, indicating whether the first input and the second input in the data flow information are ready. For example, taking a graph instruction of an AND operation "a+b+2" as an example, the valid field of the graph instruction may be used to indicate that the data flow information required by the graph instruction includes the first input a and the second input b, and the ready field of the graph instruction may be used to indicate whether a and b are ready.

[0077] Furthermore, whether the first input and the second input of the first graph instruction in the embodiment of the present application are in the ready state may mean that the first input and the second input are both ready (also referred to as both arrived). For example, the ready field of the first graph instruction indicates that the first input and the second input of the first graph instruction have both arrived, that is, the first input and the second input of the first graph instruction are both in the ready state.

[0078] Specifically, the processor may detect whether the first input and the second input of the first diagram instruction are ready (also referred to as whether they have arrived), and when both the first input and the second input are ready (for example, the ready field of the first diagram instruction indicates that both the left input and the right input of the first diagram instruction have arrived), the processor may determine that both the first input and the second input of the first diagram instruction are in a ready state. If both the first input and the second input of the first diagram instruction are not ready or one of them is not ready, the processor may determine that both the first input and the second input of the first diagram instruction are not in a ready state.

[0079] S302: When the first input and the second input are both in a ready state, static data input information of the first graph instruction is obtained from the first register, where the static data input information is used to indicate at least one input.

[0080] The first register may be a register for storing static data input of the first image instruction, and the static data input of the first image instruction may be stored in the first register in the composition stage. The at least one input may refer to other inputs of the at least three inputs of the first image instruction except the first input and the second input.

[0081] In addition, the first graph instruction may be provided with an input pointer field segment, and the input pointer field segment may include a first pointer, and the first pointer may be used to indicate the first register. For example, in the graphing stage, when the processor stores the at least one input in the first register, the input pointer field segment of the first graph instruction may be set to the first pointer used to indicate the first register.

[0082] Specifically, when the first input and the second input are both in a ready state, the processor can determine the first register according to the first pointer, and obtain the static data input information of the first graph instruction from the first register. When the at least one input indicated by the static data input information includes only one input, the processor can directly obtain the one input from the first register. When the at least one input indicated by the static data input information includes at least multiple inputs (i.e., two or more inputs), the processor can also decode the static data input information according to the preset decoding strategy associated with the operator of the first graph instruction to obtain the multiple inputs. The preset decoding strategy associated with the operator of the first graph instruction here can be used to indicate the dependency relationship between the multiple operators included in the first graph instruction, as well as the relevant indication information of the data input corresponding to each operator, etc.

[0083] For example, Figure 7As shown, assuming that the first graph instruction is a composite graph instruction compressed from four graph instructions, these four graph instructions and their dependencies are specifically: the first sli instruction with a left input of i and a right input of 2, the second sli instruction with a left input of j and a right input of 16, the add instruction with a left input of the output of the first sli instruction and a right input of the output of the second sli instruction, and the ld instruction with a left input of the output of the add instruction and a right input of A. The composite graph instruction compressed from these four graph instructions may be an sll-add-ld instruction with five data inputs, i, 2, j, 16 and A, of which i and j may be dynamic data inputs, and 2, 16 and A may be static data inputs. In the present application, the operator corresponding to the composite graph instruction may be represented as ld.p, with i and j as the first input and the second input, respectively, and 2, 16 and A stored in the first register. Specifically, when the processor detects that i and j of the graph instruction are both in the ready state, the processor can obtain the static data input information of the graph instruction from the first register, and decode the obtained static data input information into 2, 16 and A according to the preset decoding strategy corresponding to ld.p.

[0084] S303: Process the first graph instruction according to the first input, the second input and the at least one input to obtain a first processing result.

[0085] Specifically, when the processor obtains the at least one input, the processor can process the first graph instruction according to the first input, the second input and the at least one input, that is, the processor can complete the related calculations of the multiple operators in sequence according to the dependency relationship between the multiple operators of the first graph instruction and the data input corresponding to each operator to obtain the first processing result. Figure 7 Taking 2, 16 and A as an example, when the processor obtains 2, 16 and A, the processor can first process the first sli instruction according to i and 2, process the second sli instruction according to j and 16, and then process the add instruction according to the operation result of the first sli instruction and the operation result of the second sli instruction, and finally process the ld instruction according to the operation result of the add instruction and A to obtain the first processing result.

[0086] In an embodiment of the present application, for a first graph instruction having at least three inputs, the first input and the second input of the first graph instruction can be input through an input port, the first input and the second input can be dynamic data inputs, and at least one other input can be stored in a first register. Subsequently, the processor can detect whether the first input and the second input are in a ready state, and obtain at least one input from the first register when it is in a ready state, so as to process the first graph instruction based on the first input, the second input and the at least one input. In this way, interference of the intermediate state data of the first graph instruction with other data streams can be avoided, and at the same time, the relocation operation of the static data input of the first graph instruction can be reduced, thereby increasing the multiplexing efficiency of the static data input.

[0087] Furthermore, the first diagram instruction may have at least three output addresses, the output address field of the first diagram instruction may include one or two output addresses of the at least three output addresses, and the other output addresses of the at least three output addresses except one or two output addresses are stored in the second register. Figure 8 As shown, the method also includes S304-S305.

[0088] S304: Send the first processing result to the one or two output addresses.

[0089] Among them, the first diagram instruction may be correspondingly provided with an output address field segment, and the bit width of the output address field segment may be fixed, for example, the bit width of the output address field segment may be 32 bits. The output address field segment may include one output address or two output addresses. When the output address field segment includes one output address, which is the first output address, the processor may send the first processing result to the first output address; when the output address field segment includes two output addresses, which are the first output address and the second output address, the processor may send the first processing result to the first output address and the second output address respectively.

[0090] Exemplarily, when the processor includes multiple operation units, and the operation unit that processes the first graph instruction is the first operation unit, the first operation unit may specifically send the first processing result to the one or two output addresses.

[0091] S305: Obtain output address information of the first image instruction from the second register, and send the first processing result to the output address indicated by the output address information.

[0092] The second register may be used to store other output addresses of the at least three output addresses except the one or two output addresses. For example, in the patterning stage, the processor may store other output addresses of the at least three output addresses except the one or two output addresses in the second register.

[0093] In addition, when the output address field includes one output address, the output address field may also include a second pointer, and the second pointer may be used to indicate a second register. When the output address field includes two output addresses, the first graph instruction may also be provided with an output pointer field, and the output pointer field may include a second pointer, and the second pointer may be used to indicate a second register.

[0094] Specifically, the processor can determine the second register according to the second pointer, and obtain the output address information of the first image instruction from the second register. The processor can also decode the output address information to obtain one or more output addresses, and the one or more output addresses are the other output addresses of the at least three output addresses except the one or two output addresses. The processor can then send the first processing result to each of the one or more output addresses.

[0095] Optionally, when the processor includes multiple operation units, and the operation unit that processes the first graph instruction is the first operation unit, the first operation unit can specifically send the first processing result to the second operation unit among the multiple operation units, and the second operation unit can send the first processing result to each of the one or more output addresses. The second operation unit can make full use of the bus bandwidth and use idle bus resources without disturbing other data flows to send the first processing result to the one or more output addresses, thereby achieving efficient use of the bus communication load. The first operation unit and the second operation unit here can specifically be the graph computing flow units in the processor architecture provided above.

[0096] like Fig. 9 As shown, assuming that the first processing result is i, the instruction for implementing sending the first processing result to the one or more output addresses is copym, the bit width of the second register R1 is 64 bits and the output address information stored is 21458976, then when the copym instruction receives the first processing result i, the copym instruction will be issued to the second operation unit, and the second operation unit obtains the output address information 21458976 from the second register and parses it into use2, use1, use4, use5, use8, use9, use7 and use6. The second operation unit can send the first processing result i to use2, use1, use4, use5, use8, use9, use7 and use6 respectively.

[0097] Further, when the first diagram instruction has multiple input and multiple output addresses, the first register and the second register may be the same register, so that the first pointer and the second pointer may be the same pointer. Fig.10 As shown, assuming that the first instruction has three static data inputs and three output addresses, the three static data inputs are opc2, imm0 and imm1, the three output addresses are dest0, dest1 and dest2, the corresponding register is R1, and the pointer corresponding to R1 is ptr, then the format of the first instruction can be opcode+dest0+dest1+ptr, and opc2, imm0, imm1 and dest2 can be stored in R1. Fig.10 In the example, the cache width corresponding to the instruction in the first figure is 32 bits and R1 is 64 bits. Opcode represents the operator.

[0098] In an embodiment of the present application, for a first graph instruction having at least three data inputs, there are usually one or two dynamic data inputs and one or more static data inputs among the at least three data inputs. The one or more static data inputs can be stored in a first register. A subsequent processor can detect whether the first input and the second input of the first graph instruction are in a ready state, and when in the ready state, obtain the static data input of the first graph instruction from the first register to process the first graph instruction, thereby avoiding interference of the intermediate state data of the first graph instruction with other data streams, and at the same time reducing the relocation operation of the static data input of the first graph instruction, increasing the multiplexing efficiency of the static data input, and thereby improving the performance of the directed graph flow computing architecture.

[0099] Furthermore, when the first graph instruction has at least three output addresses, one or more of the at least three output addresses can be stored in the second register, so that the graph instructions with at least three output addresses in the instruction set can be configured into the directed graph flow computing architecture in a relatively regular format. When the first processing result of the first graph instruction is subsequently output, one or more output addresses of the first graph instruction can be obtained from the second register, and the first processing result can be sent to each output address, thereby realizing the result processing of the graph instruction with at least three output addresses; at the same time, compared with the prior art, this method does not cause waste of instruction space, nor does it generate large power consumption, thereby ensuring that the computing architecture has better performance.

[0100] Fig.11 A flowchart of a method for processing a graph instruction provided in an embodiment of the present application is provided. The method can be applied to the processor provided above, and the method includes the following steps.

[0101] S401: Determine a first processing result of a first graph instruction, where the first graph instruction has at least three output addresses.

[0102] Among them, the first graph instruction can be any graph instruction in the directed graph computing architecture instruction set, for example, the first graph instruction can be a graph instruction with two inputs, or a graph instruction with at least three inputs. Specifically, when the first graph instruction is a graph instruction with two inputs, the processor can determine the first processing result of the first graph instruction according to the method of the prior art; when the first graph instruction is a graph instruction with at least three inputs, the processor can determine the first processing result of the first graph instruction according to the graph instruction processing method with multiple inputs provided in this application.

[0103] In addition, the first diagram instruction may be provided with an output address field segment corresponding thereto, and the bit width of the output address field segment may be fixed, for example, the bit width of the output address field segment may be 32 bits. For at least three output addresses of the first diagram instruction, the output address field segment of the first diagram instruction may be used to indicate one or two output addresses of the at least three output addresses, and the other output addresses of the at least three output addresses except the one or two output addresses may be stored in the second register. For example, when the output address field segment includes one output address, and the output address is the first output address, the other output addresses of the at least three output addresses except the first output address may be stored in the second register. When the output address field segment includes two output addresses, and the two output addresses are the first output address and the second output address, the other output addresses of the at least three output addresses except the first output address and the second output address may be stored in the second register.

[0104] S402: Send the first processing result to one or two output addresses included in the output address domain.

[0105] Specifically, when the output address field segment of the first graph instruction includes the first output address, the processor can send the first processing result to the first output address; when the output address field segment of the first graph instruction includes the first output address and the second output address, the processor can send the first processing result to the first output address and the second output address respectively.

[0106] Exemplarily, when the processor includes multiple operation units, and the operation unit that processes the first graph instruction is the first operation unit, the first operation unit can specifically send the first processing result to the first output address, or the first output address and the second output address.

[0107] S403: Obtain output address information of the first image instruction from the second register, and send the first processing result to the output address indicated by the output address information.

[0108] Wherein, in the composition stage, the processor may store the other output addresses of the at least three output addresses except the one or two output addresses in the second register. When the output address field segment includes one output address, the output address field segment may also include a second pointer, and the second pointer may be used to indicate the second register. When the output address field segment includes two output addresses, the first graph instruction may also be provided with an output pointer field segment, and the output pointer field segment may include a second pointer, and the second pointer may be used to indicate the second register.

[0109] Specifically, the processor can determine the second register according to the second pointer, and obtain the output address information of the first image instruction from the second register. The processor can also decode the output address information to obtain one or more output addresses, and the one or more output addresses are the other output addresses of the at least three output addresses except the one or two output addresses. The processor can then send the first processing result to each of the one or more output addresses.

[0110] Optionally, when the processor includes multiple operation units, and the operation unit that processes the first graph instruction is the first operation unit, the first operation unit can specifically send the first processing result to the second operation unit among the multiple operation units, and the second operation unit can send the first processing result to each of the one or more output addresses. The second operation unit can make full use of the bus bandwidth and use idle bus resources without disturbing other data flows to send the first processing result to the one or more output addresses, thereby achieving efficient use of the bus communication load. The first operation unit and the second operation unit here can specifically be the graph computing flow units in the processor architecture provided above.

[0111] For example, it is assumed that the directed graph instruction set includes multiple graph instructions such as Fig.12 As shown, the 5th, 10th, 11th, 17th and 20th graph instructions in these multiple graph instructions have at least three output addresses. Taking the output address field segment including an output address and a pointer as an example, the output addresses of these graph instructions except dest0 can be stored in registers. Specifically, the output addresses dest1 to dest3 of the 5th graph instruction are stored in a register with a pointer of 0, the output addresses dest1 to dest5 of the 10th graph instruction are stored in a register with a pointer of 1, the output addresses dest1 and dest2 of the 11th graph instruction are stored in a register with a pointer of 2, the output addresses dest1 and dest2 of the 17th graph instruction are stored in a register with a pointer of 3, and the output addresses dest1 to dest4 of the 20th graph instruction are stored in a register with a pointer of 4. Fig.12 Here, op represents the operator of the graph instruction.

[0112] In an embodiment of the present application, when the first graph instruction has at least three output addresses, one or more of the at least three output addresses can be stored in the second register, so that the graph instructions with at least three output addresses in the instruction set can be configured into the directed graph flow computing architecture in a relatively regular format. When the first processing result of the first graph instruction is subsequently output, one or more output addresses of the first graph instruction can be obtained from the second register, and the first processing result can be sent to each output address, thereby realizing the result processing of the graph instruction with at least three output addresses; at the same time, compared with the prior art, this method does not cause waste of instruction space, nor does it generate large power consumption, thereby ensuring that the computing architecture has better performance.

[0113] The embodiment of the present application can divide the functional modules of the graph instruction processing device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation.

[0114] In the case of dividing each functional module into corresponding functional modules, Fig.13 A possible structural diagram of a graph instruction processing device involved in the above embodiments is shown, and the device may be a processor or a graph instruction processing device including a processor. Fig.13 The device includes: a detection unit 501, a first operation unit 502 and a second operation unit 503.

[0115] In a possible embodiment, the detection unit 501 is used to support the device to execute S301 in the above method embodiment, the first operation unit 502 is used to support the device to execute S302, S303 and S304 in the above method embodiment, and the second operation unit 503 is used to support the device to execute S305 in the above method embodiment. In another possible embodiment, the first operation unit 502 is used to support the device to execute S401 and S402 in the above method embodiment, and the second operation unit 503 is used to support the device to execute S403 in the above method embodiment.

[0116] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0117] On the basis of hardware implementation, the detection unit 501 in the present application may be an instruction scheduling unit, and the first operation unit 502 and the second operation unit 503 may be graph computing flow units.

[0118] The present application also provides a graphics instruction processing device. The specific structure of the device is as follows: Figure 2 or Figure 3 As shown. Figure 2 For example, the device includes: an instruction scheduling unit 1011, a graph computing flow unit 1012 and a general operation unit 1013.

[0119] Among them, in one possible embodiment, the instruction scheduling unit 1011 is used to support the device to execute S301 in the above method embodiment; the graph computing flow unit 1012 may include two, one graph computing flow unit 1012 is used to support the device to execute S302, S303 and S304 in the above method embodiment, and the other graph computing flow unit 1012 is used to support the device to execute S305 in the above method embodiment. In another possible embodiment, the graph computing flow unit 1012 may include two, one graph computing flow unit 1012 is used to support the device to execute S401 and S402 in the above method embodiment, and the other graph computing flow unit 1012 is used to support the device to execute S403 in the above method embodiment.

[0120] In an embodiment of the present application, for a first graph instruction having at least three data inputs, there are usually one or two dynamic data inputs and one or more static data inputs among the at least three data inputs. The one or more static data inputs can be stored in a first register. A subsequent processor can detect whether the first input and the second input of the first graph instruction are in a ready state, and when in the ready state, obtain the static data input of the first graph instruction from the first register to process the first graph instruction, thereby avoiding interference of the intermediate state data of the first graph instruction with other data streams, and at the same time reducing the relocation operation of the static data input of the first graph instruction, increasing the multiplexing efficiency of the static data input, and thereby improving the performance of the directed graph flow computing architecture.

[0121] Furthermore, when the first graph instruction has at least three output addresses, one or more of the at least three output addresses can be stored in the second register, so that the graph instructions with at least three output addresses in the instruction set can be configured into the directed graph flow computing architecture in a relatively regular format. When the first processing result of the first graph instruction is subsequently output, one or more output addresses of the first graph instruction can be obtained from the second register, and the first processing result can be sent to each output address, thereby realizing the result processing of the graph instruction with at least three output addresses; at the same time, compared with the prior art, this method does not cause waste of instruction space, nor does it generate large power consumption, thereby ensuring that the computing architecture has better performance.

[0122] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0123] Based on this, the embodiment of the present application further provides a readable storage medium, in which instructions are stored. When the readable storage medium is run on a device, the device executes the above Figure 6 or Figure 8 One or more steps in a method embodiment are provided.

[0124] The embodiment of the present application also provides a readable storage medium, in which instructions are stored. When the readable storage medium is run on a device, the device executes the above Fig.11 One or more steps in a method embodiment are provided.

[0125] The present application also provides a computer program product, which, when executed on a computer, enables the computer to execute the above Figure 6 or Figure 8 One or more steps in a method embodiment are provided.

[0126] In another aspect of the present application, a computer program product is provided. When the computer program product is run on a computer, the computer is caused to execute the above Fig.11 One or more steps in a method embodiment are provided.

[0127] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for processing a graph instruction, characterized in that: The method comprises: Detecting whether a first input and a second input of a first graph instruction are in a prepared state, wherein the first input and / or the second input are dynamic data inputs of the first graph instruction, and the first graph instruction is a composite graph instruction in a directed graph flow computing architecture; When both the first input and the second input are in the ready state, acquiring static data input information of the first graph instruction from a first register, wherein the static data input information is used to indicate at least one input; The first graph instruction is processed according to the first input, the second input and the at least one input to obtain a first processing result.

2. The method according to claim 1, characterized in that The first graph instruction is provided with an input pointer field segment, and the input pointer field segment includes a first pointer, and the first pointer is used to indicate the first register.

3. The method according to claim 1 or 2, characterized in that: Each of the at least one input is a constant input or a temporary constant input; The temporary constant input refers to an input that does not change within a period of time.

4. The method according to claim 1, characterized in that: The at least one input comprises a plurality of inputs, the method further comprising: The static data input information is decoded according to a preset decoding strategy associated with the operator of the first graph instruction to obtain the multiple inputs.

5. The method according to claim 1, characterized in that The first graph instruction has at least three output addresses, the output address field of the first graph instruction is used to indicate one or two output addresses of the at least three output addresses, and the other output addresses of the at least three output addresses except the one or two output addresses are stored in a second register, and the method further includes: Sending the first processing result to the one or two output addresses; The output address information of the first graph instruction is obtained from the second register, and the first processing result is sent to the output address indicated by the output address information.

6. The method according to claim 5, characterized in that The output address field includes an output address and a second pointer, where the second pointer is used to indicate the second register.

7. The method according to claim 5, characterized in that The output address field includes two output addresses. The first graph instruction is also provided with an output pointer field. The output pointer field includes a second pointer. The second pointer is used to indicate the second register.

8. The method according to any one of claims 5 to 7, characterized in that: The method further comprises: decoding the output address information to obtain at least one output address; Correspondingly, sending the first processing result to the output address indicated by the output address information includes: sending the first processing result to each output address of the at least one output address.

9. A method for processing a graph instruction, characterized in that: The method comprises: Determine a first processing result of a first graph instruction, wherein the first graph instruction is a composite graph instruction in a directed graph flow computing architecture, the first graph instruction has at least three output addresses, the output address field of the first graph instruction is used to indicate one or two output addresses of the at least three output addresses, and the other output addresses of the at least three output addresses except the one or two output addresses are stored in a second register; Sending the first processing result to the one or two output addresses; The output address information of the first graph instruction is obtained from the second register, and the first processing result is sent to the output address indicated by the output address information.

10. The method according to claim 9, characterized in that The output address field includes an output address and a second pointer, where the second pointer is used to indicate the second register.

11. The method according to claim 9, characterized in that The output address field includes two output addresses. The first graph instruction is also provided with an output pointer field. The output pointer field includes a second pointer. The second pointer is used to indicate the second register.

12. The method according to any one of claims 9 to 11, characterized in that: The method further comprises: decoding the output address information to obtain at least one output address; Correspondingly, sending the first processing result to the output address indicated by the output address information includes: sending the first processing result to each output address of the at least one output address.

13. A graph instruction processing device, characterized in that: The device comprises: a detection unit, configured to detect whether a first input and a second input of a first graph instruction are in a ready state, wherein the first input and / or the second input are dynamic data inputs of the first graph instruction, and the first graph instruction is a composite graph instruction in a directed graph flow computing architecture; a first operation unit, configured to obtain static data input information of the first graph instruction from a first register when both the first input and the second input are in the ready state, wherein the static data input information is used to indicate at least one input; The first operation unit is further used to process the first graph instruction according to the first input, the second input and the at least one input to obtain a first processing result.

14. The device according to claim 13, characterized in that The first graph instruction is provided with an input pointer field segment, and the input pointer field segment includes a first pointer, and the first pointer is used to indicate the first register.

15. The device according to claim 13 or 14, characterized in that Each of the at least one input is a constant input or a temporary constant input; The temporary constant input refers to an input that does not change within a period of time.

16. The device according to claim 13, characterized in that The at least one input includes a plurality of inputs, and the first computing unit is further configured to: The static data input information is decoded according to a preset decoding strategy associated with the operator of the first graph instruction to obtain the multiple inputs.

17. The device according to claim 13, characterized in that The first graph instruction has at least three output addresses, the output address field of the first graph instruction is used to indicate one or two output addresses of the at least three output addresses, and the other output addresses of the at least three output addresses except the one or two output addresses are stored in a second register, and the device further includes: a second operation unit; The first operation unit is further used to send the first processing result to the one or two output addresses; The second operation unit is used to obtain the output address information of the first graph instruction from the second register, and send the first processing result to the output address indicated by the output address information.

18. The device according to claim 17, characterized in that The output address field includes an output address and a second pointer, where the second pointer is used to indicate the second register.

19. The device according to claim 17, characterized in that The output address field includes two output addresses. The first graph instruction is also provided with an output pointer field. The output pointer field includes a second pointer. The second pointer is used to indicate the second register.

20. The device according to any one of claims 17 to 19, characterized in that The first computing unit is further configured to: decoding the output address information to obtain at least one output address; The first processing result is sent to each output address of the at least one output address.

21. A graph instruction processing device, characterized in that: The device comprises: A first operation unit is used to determine a first processing result of a first graph instruction, wherein the first graph instruction is a composite graph instruction in a directed graph flow computing architecture, the first graph instruction has at least three output addresses, the output address field of the first graph instruction is used to indicate one or two output addresses of the at least three output addresses, and the other output addresses of the at least three output addresses except the one or two output addresses are stored in a second register; The first operation unit is further used to send the first processing result to the one or two output addresses; The second operation unit is used to obtain the output address information of the first image instruction from the second register, and send the first processing result to the output address indicated by the output address information.

22. The device according to claim 21, characterized in that The output address field includes an output address and a second pointer, where the second pointer is used to indicate the second register.

23. The device according to claim 21, characterized in that The output address field includes two output addresses. The first graph instruction is also provided with an output pointer field. The output pointer field includes a second pointer. The second pointer is used to indicate the second register.

24. The device according to any one of claims 21 to 23, characterized in that The first computing unit is further configured to: decoding the output address information to obtain at least one output address; The first processing result is sent to each output address of the at least one output address.

25. A graph instruction processing device, characterized in that: The device comprises a processor, wherein the processor is coupled to a memory, wherein instructions are stored in the memory, and when the processor runs the instructions in the memory, the device executes the method according to any one of claims 1 to 12.

26. A readable storage medium, characterized in that: The readable storage medium stores instructions, and when the readable storage medium is run on a device, the device executes the method according to any one of claims 1 to 12.

27. A computer program product, characterized in that When the computer program product is run on a computer, the computer is enabled to execute the method according to any one of claims 1 to 12.

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