Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes first and second nitride-based semiconductor layers and a gate structure. The gate structure includes an outer spacer, an inner spacer, and a gate electrode. The outer spacer has at least two opposing inner sidewalls to define a gate trench. The inner spacer is located within the gate trench. The gate electrode is disposed within the gate trench and is covered by the inner spacer, wherein the inner spacer and the gate electrode extend downward to collectively form a bottom of the gate structure, the bottom having a first width that is greater than a second width of a bottom surface of the gate electrode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to nitride-based semiconductor devices. More specifically, the present disclosure relates to a nitride-based semiconductor device having a gate trench. BACKGROUND

[0002] In recent years, there has been a great deal of interest in high-electron-mobility transistors (HEMTs), particularly in high-power switching and high-frequency applications. III-nitride HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2DEG) region, satisfying the demands of high-power / frequency devices. In addition to HEMTs, examples of devices with heterostructures also include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), and modulation-doped FETs. SUMMARY

[0003] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a gate structure. The second nitride-based semiconductor layer is disposed above the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap that is greater than a bandgap of the first nitride-based semiconductor. The gate structure is disposed above the first nitride-based semiconductor layer. The gate structure includes an outer spacer, an inner spacer, and a gate electrode. The outer spacer is disposed above the second nitride-based semiconductor layer and has at least two opposing inner sidewalls to define a gate trench. The inner spacer is disposed above the first nitride-based semiconductor layer and within the gate trench. The gate electrode is disposed within the gate trench and is covered by the inner spacer. At least the inner spacer and the gate electrode extend downward to collectively form a bottom of the gate structure.

[0004] According to one aspect of the present disclosure, a method of fabricating a semiconductor device is provided. The method includes the following steps. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed over the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor. A dummy gate is formed on the second nitride-based semiconductor layer. A spacer cap layer is formed to cover the dummy gate. A portion of the spacer cap layer is removed to expose the dummy gate, and at least a portion of the spacer cap layer remains on outer sidewalls of the dummy gate as an outer spacer layer. The dummy gate is removed to form a gate trench. An inner spacer is formed within the gate trench. A gate electrode is formed within the gate trench such that a width of a bottom of the gate electrode is less than a width of the gate trench.

[0005] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, an outer spacer, an inner spacer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor. The outer spacer is disposed on the first nitride-based semiconductor layer and defines a gate trench. The inner spacer is disposed on the first nitride-based semiconductor layer and within the gate trench. The inner spacer extends downward with an extension length greater than a thickness of the outer spacer. The gate electrode is disposed within the gate trench with the inner spacer between the outer spacer and the gate electrode.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, and a gate structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor. The source electrode and the drain electrode are disposed on the first nitride-based semiconductor layer. The gate structure is disposed on the first nitride-based semiconductor layer and is confined between the source electrode and the drain electrode. The gate structure includes a gate spacer layer, an etch stop layer, and a gate electrode. The gate spacer layer is disposed on the second nitride-based semiconductor layer. The etch stop layer is disposed between the gate spacer layer and the second nitride-based semiconductor layer and collectively defines a gate trench with the gate spacer layer. The gate electrode is disposed within the gate trench.

[0007] According to one aspect of the present disclosure, a method of fabricating a semiconductor device is provided. The method includes the following steps. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor. An etch stop capping layer is formed on the second nitride-based semiconductor layer. A dummy gate is formed on the etch stop capping layer. A spacer capping layer is formed to cover the dummy gate and the etch stop capping layer. A portion of the spacer capping layer is removed to expose the dummy gate. At least a portion of the spacer capping layer is removed to expose the dummy gate, and at least a portion of the spacer capping layer remains on outer sidewalls of the dummy gate as a gate spacer layer. A first etch process is performed to remove the dummy gate, thereby exposing the etch stop capping layer. A second etch process is performed to remove at least a portion of the etch stop capping layer, thereby forming a gate trench that exposes one of the first and second nitride-based semiconductor layers. A gate electrode is formed in the gate trench.

[0008] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a gate structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor. The second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor. The gate structure is disposed on the first nitride-based semiconductor layer. The gate structure includes a gate spacer layer, an etch stop layer, a gate electrode, and two doped nitride-based semiconductor layers. The gate spacer layer is disposed on the second nitride-based semiconductor layer. The etch stop layer is disposed between the gate spacer layer and the second nitride-based semiconductor layer and collectively defines a gate trench with the gate spacer layer. The gate electrode is disposed in the gate trench. The two doped nitride-based semiconductor layers are respectively located on two opposite sides of the gate structure. Each of the doped nitride-based semiconductor layers horizontally / laterally extends to outer sidewalls of the gate spacer layer and the etch stop layer, such that the gate electrode is separated from the two doped nitride-based semiconductor layers by the gate spacer layer and the etch stop layer.

[0009] With the above configuration, in the present disclosure, by modifying the gate structure of the semiconductor device, the semiconductor device can achieve better performance at a lower manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0010] Aspects of the present disclosure can be more readily understood, by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that various features can not be drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of providing an easier description. Embodiments of the present disclosure are described below in the context of the following drawings in which:

[0011] Figure 1 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0012] Figure 2A ,Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F 、 Figure 2G and Figure 2H shows different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 3 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0015] Figure 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0017] Figure 7 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0018] Figure 8 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0019] Figure 9 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0020] Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E 、 Figure 10F and Figure 10G shows different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0021] Figure 11A and Figure 11B shows different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0022] Figure 12 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0023] Figure 13 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0024] Figure 14is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0025] Figure 15 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0026] Figure 16 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and

[0027] Figure 17 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] In all of the drawings and detailed descriptions, the same reference symbols are used to represent the same or similar components. By following the detailed description with reference to the accompanying drawings, embodiments of the present disclosure will become apparent.

[0029] In spatial descriptions, terms such as "upper," "lower," "above," "below," "left," "right," "upward," "downward," "top," "bottom," "vertical," "horizontal," "lateral," "longitudinal," "transverse," "one side," "higher," "lower," "upper," "over," "under," and the like can be used where a particular component or group of components is positioned in relation to a particular plane or group of planes. It will be understood that spatial descriptions used herein are for purposes of illustration only and that practical implementations of structures described herein can be oriented in any direction or manner in space, provided that the advantages of embodiments of the present disclosure are not departed from.

[0030] In addition, it is noted that the actual shapes of various structures depicted as approximately rectangular can be curved, have rounded edges, or have some non-uniform thickness, etc., due to the conditions of manufacturing of the devices. The use of straight lines and right angles in the present disclosure is used only for the convenience of representing the layers and technical features.

[0031] In the following description, semiconductor devices / chips / packages and methods of manufacturing the same, etc. are listed as preferred examples. Those skilled in the art will understand that modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of the present disclosure. Particular details can be omitted in order not to obscure the disclosure; however, the present disclosure is intended to be illustrative of the teachings of the present disclosure rather than limiting.

[0032] Figure 1is a vertical view of a semiconductor device 1A according to some embodiments of the present disclosure. Semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14A, doped nitride-based semiconductor layers 20, 22, electrodes 30, 32, a gate structure 40A, and a passivation layer 50.

[0033] Substrate 10 can be a semiconductor substrate. Exemplary materials of substrate 10 can include, for example and without limitation, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide, p-type doped silicon, n-type doped silicon, sapphire, semiconductor-on-insulator (e.g., silicon on insulator (SOI)), or other suitable substrate materials. In some embodiments, substrate 10 can include, for example and without limitation, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, substrate 10 can include, for example and without limitation, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or a combination thereof.

[0034] In some embodiments, semiconductor device 1A can further include a buffer layer (not shown). The buffer layer can be disposed on / over / above substrate 10. The buffer layer can be located between substrate 10 and nitride-based semiconductor layers 12. The buffer layer can be configured to reduce lattice and thermal mismatches between substrate 10 and nitride-based semiconductor layers 12, thereby healing defects due to the mismatches / differences. Exemplary materials of the buffer layer can further include, for example and without limitation, gallium nitride (GaN), aluminum nitride (AIN), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), or a combination thereof.

[0035] In some embodiments, semiconductor device 1A can further include a nucleation layer (not shown). The nucleation layer can be formed between substrate 10 and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate mismatches / differences between substrate 10 and the III-nitride layer of the buffer layer. Exemplary materials of the nucleation layer can include, for example and without limitation, aluminum nitride (AIN) or any alloy thereof.

[0036] A nitrogen-based semiconductor layer 12 can be disposed on / over / above the substrate 10. The nitrogen-based semiconductor layer 12 can be in contact with the substrate 10. An exemplary material of the nitrogen-based semiconductor layer 12 can include, for example but not limited to, a nitride or a III-V compound, such as gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), In x Al y Ga （1–x–y） N (wherein x + y < 1), Al y Ga （1–y） N (wherein y < 1). An exemplary material of the nitrogen-based semiconductor layer 12 can include, for example but not limited to, a nitride or a III-V compound, such as gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), In x Al y Ga （1–x–y） N (wherein x + y < 1), Al y Ga （1–y） N (wherein y < 1).

[0037] The exemplary materials of the nitrogen-based semiconductor layers 12 and 14A are selected such that the bandgap (i.e., the width of the forbidden band) of the nitrogen-based semiconductor layer 14A is greater / higher than that of the nitrogen-based semiconductor layer 12, which results in their electron affinities being different from each other and forming a heterojunction therebetween. For example, when the nitrogen-based semiconductor layer 12 is an undoped gallium nitride (GaN) layer having a bandgap of about 3.4 eV, the nitrogen-based semiconductor layer 14A can be selected as a gallium aluminum nitride (AlGaN) layer having a bandgap of about 4.0 eV. In this way, the nitrogen-based semiconductor layers 12 and 14A can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the junction interface between the channel layer and the barrier layer, such that electrons accumulate in the triangular well, thereby creating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A can be used for a high-electron-mobility transistor (HEMT) including at least one gallium nitride-based (GaN-based) HEMT.

[0038] Each of the doped nitrogen-based semiconductor layers 20 and 22 can extend through the nitrogen-based semiconductor layer 14A and into the nitrogen-based semiconductor layer 12, such that portions 122, 142A of the nitrogen-based semiconductor layers 12 and 14A are sandwiched between the doped nitrogen-based semiconductor layers 20 and 22.

[0039] The doped nitrogen-based semiconductor layers 20 and 22 can be n-type doped III-V semiconductor layers. Exemplary materials of the doped nitrogen-based semiconductor layers 20, 22 can include, for example but not limited to, n-type doped III-V nitride semiconductor materials such as n-type gallium nitride (n-GaN), n-type aluminum gallium nitride (n-AlGaN), n-type indium nitride (n-InN), n-type aluminum indium nitride (n-AlInN), n-type indium gallium nitride (n-InGaN), n-type aluminum indium gallium nitride (n-AlInGaN), or combinations thereof. In some embodiments, the n-doped materials are achieved by using n-type impurities / dopants such as silicon (Si) or germanium (Ge). In some embodiments, each of the doped nitrogen-based semiconductor layers 20 and 22 can be n-type heavily doped in order to reduce contact resistance. In some embodiments, the doping concentration of the n-type impurities / dopants can be in the range of 10 to

[0040] The electrodes 30 and 32 are disposed on / over / above the nitrogen-based semiconductor layer 12. The electrodes 30, 32 can be in contact with the doped nitrogen-based semiconductor layers 20, 22, respectively. The area where the doped nitrogen-based semiconductor layers 20, 22 are located can be defined as an electrode region. In some embodiments, the electrode 30 can function as a source electrode. In some embodiments, the electrode 30 can function as a drain electrode. In some embodiments, the electrode 32 can function as a source electrode. In some embodiments, the electrode 32 can function as a drain electrode. The roles of the electrodes 30 and 32 depend on the device design.

[0041] ​In some embodiments, the electrodes 30 and 32 can include, for example but not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds (e.g., silicides and nitrides), other conductor materials, or combinations thereof. Exemplary materials of the electrodes 30 and 32 can include, for example but not limited to, titanium (Ti), aluminum silicon (AlSi), titanium nitride (TiN), or combinations thereof. Each of the electrodes 30 and 32 can be a single layer or multiple layers with the same or different compositions. The electrodes 30 and 32 form an ohmic contact with the nitride-based semiconductor layer 14A. Further, the ohmic contact can be achieved by applying titanium (Ti), aluminum (Al), or other suitable materials to the electrodes 30 and 32. In some embodiments, each of the electrodes 30 and 32 is formed of at least one conformal layer and a conductive filler. The conformal layer can wrap the conductive filler. Exemplary materials of the conformal layer can include, for example but not limited to, titanium (Ti), tantalum (Ta), titanium nitride (TiN), aluminum (Al), gold (Au), aluminum silicon (AlSi), nickel (Ni), platinum (Pt), or combinations thereof. Exemplary materials of the conductive filler can include, for example but not limited to, aluminum silicon (AlSi), aluminum copper (AlCu), or combinations thereof.

[0042] HEMT devices have been applied in various fields. For different requirements, device parameters will be adjusted to meet device conditions. For example, the gate length (i.e., channel length) can be adjusted to match different purposes of the device. Therefore, a way to reduce the channel length is needed. In order to reduce the channel length, expensive and high-requirement photolithography devices are usually applied in the manufacturing process of the device, resulting in high manufacturing cost. In addition, the shrinkage of the gate length will make the exposure and etching process more complicated.

[0043] At least to avoid the above problems, the present disclosure aims to develop a new structure for a semiconductor device.

[0044] The gate structure 40A is disposed on / over / above the portion 122 of the nitride-based semiconductor layer 12 and the portion 142A of the nitride-based semiconductor layer 14A. The gate structure 40A is in contact with the portion 142A of the nitride-based semiconductor layer 14A, and thus the area where the portion 142A of the nitride-based semiconductor layer 14A is located can be defined as a gate region. The gate structure 40A is disposed / between the electrodes 30, 32 (or the doped nitride-based semiconductor layers 20, 22). The gate structure 40A includes outer spacers (including portions 401A and 402A), inner spacers (including portions 404A and 405A), and a gate electrode 406A. The detailed configuration of the gate structure 40A will be fully described as follows.

[0045] Portions 401 A and 402A of the outer spacer are disposed on / over / above portions 122 of the nitrogen-based semiconductor layer 12 and portions 142A of the nitrogen-based semiconductor layer 14A. Portions 401 A and 402A are separated from each other by portions 404A, 405A of the inner spacer and the gate electrode 406A. Each of portions 401 A and 402A extends downward to contact portions 142A of the nitrogen-based semiconductor layer 14A. Portions 401 A and 402A of the outer spacer each include opposing inner sidewalls 403 to bound the gate trench GT.

[0046] The doped nitrogen-based semiconductor layer 20 is against portions 401 A of the outer spacer, portions 142A of the nitrogen-based semiconductor layer 14A, and portions 122 of the nitrogen-based semiconductor layer 12. The entire bottom surface of the doped nitrogen-based semiconductor layer 20 is under portions 401 A of the inner spacer. The doped nitrogen-based semiconductor layer 22 is against portions 402A of the outer spacer, portions 142A of the nitrogen-based semiconductor layer 14A, and portions 122 of the nitrogen-based semiconductor layer 12. The entire bottom surface of the doped nitrogen-based semiconductor layer 22 is under portions 402A of the inner spacer.

[0047] Portions 404A and 405A of the inner spacer are disposed on / over / above portions 122 of the nitrogen-based semiconductor layer 12 and portions 142A of the nitrogen-based semiconductor layer 14. Portions 404A and 405A of the inner spacer are separated from each other by the gate electrode 406A. Each of portions 404A and 405A extends downward to contact portions 142A of the nitrogen-based semiconductor layer 14. Each of portions 404A and 405A has a bottom end surface in contact with the nitrogen-based semiconductor layer 14A. Portions 404A and 405A of the inner spacer are connected to two opposing inner sidewalls 403 of the outer spacer, respectively. The entire of each of the inner sidewalls 403 of the outer spacer is covered by portions 404A or 405A of the inner spacer. Each of the doped nitrogen-based semiconductor layers 20 and 22 has a bottom surface, the entirety of which is under portions 404A and 405A of the inner spacer.

[0048] Portions 404A and 405A of the inner spacer and the gate electrode 406A are disposed in the gate trench GT. The gate electrode 406A is covered by the inner spacer. Opposite side surfaces of the gate electrode 406A are covered by portions 404A and 405A of the inner spacer. The gate electrode 406A is between portions 404A and 405A of the inner spacer.

[0049] The portion 404A of the inner spacer is located / disposed between the portion 401A of the outer spacer and the gate electrode 406A, such that the gate electrode 406B is separated from the portion 401A of the outer spacer by the portion 404A of the inner spacer. The portion 405A of the inner spacer is located / disposed between the portion 402A of the outer spacer and the gate electrode 406A, such that the gate electrode 406B is separated from the portion 402A of the outer spacer by the portion 405A of the inner spacer. The outer spacer, the inner spacer, and the gate electrode 406A extend downward to jointly form a bottom of the gate structure 40A, which has a width Wl. The width Wl of the bottom of the gate structure 40A is greater than a width W2 of a bottom surface of the gate electrode 406A. In the present embodiment, each of the portions 404A and 405A of the inner spacer extends a length that is substantially the same as a thickness of each of the portions 401A and 402A of the outer spacer.

[0050] With the above configuration, since the portions 404A and 405A of the inner spacer and the gate electrode 406A can jointly fill the gate trench GT, a portion of the gate trench GT is occupied by at least the portions 404A and 405A of the inner spacer, thereby defining the width W2 of the gate electrode 406A to be less than the width Wl of the bottom of the gate structure 40A (or the width of the gate trench GT). Thus, the effect of reducing the gate electrode length without using an expensive device can be achieved. The manufacturing cost of the semiconductor device 1A can be greatly reduced. The electrical characteristics of the semiconductor device 1A, such as the current gain cutoff frequency, the maximum frequency of oscillation, the output conductance, the gate-source capacitance, can be improved, such that the semiconductor device 1A can have good performance due to the reduced gate electrode length. Thus, the semiconductor device 1A can meet high frequency requirements.

[0051] Furthermore, the doped nitrogen-based semiconductor layers 20 and 22 are separated from the gate electrode 406A by the outer spacer and the inner spacer. The outer spacer and the inner spacer can jointly provide good insulation between the doped nitrogen-based semiconductor layer 20 and the gate electrode 406A and between the doped nitrogen-based semiconductor layer 22 and the gate electrode 406, such that gate leakage can be significantly reduced.

[0052] Further, portions 401 A and 402A of the outer spacers have a substantially constant width. The width of portion 401 A is substantially the same as the width of portion 402A. Each of portions 404A and 405A of the inner spacers has a substantially constant width. The width of portion 404A is substantially the same as the width of portion 405A. The width of each of portions 401 A and 402A of the outer spacers is greater than the width of each of portions 404A and 405A of the inner spacers. Gate electrode 406A is wider than each of portions 404A and 405A of the inner spacers.

[0053] In some embodiments, the relationship between the widths of portions 401 A, 402A of the outer spacers, 404A, 405A of the inner spacers, and 406A of the gate electrode can be varied to fabricate semiconductor devices having different electrical properties. These width parameters can be further fine-tuned, which facilitates providing more design flexibility.

[0054] Exemplary materials of the outer spacers and the inner spacers can include, for example but are not limited to, a dielectric material. For example, the dielectric material can include, for example but is not limited to, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), an oxide, a nitride, a plasma enhanced oxide (PEOX), or a combination thereof.

[0055] Exemplary materials of gate electrode 406A can include a metal or a metal compound. Gate electrode 406A can be formed as a single layer or multiple layers having the same or different compositions. Exemplary materials of the metal or the metal compound can include, for example but are not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), a metal alloy or a compound thereof, or other metal compounds.

[0056] Passivation layer 50 covers nitrogen-based semiconductor layer 14A and doped nitrogen-based semiconductor layers 20, 22. Exemplary materials of passivation layer 50 can include, for example but are not limited to, a dielectric material. For example, the dielectric material can include, for example but is not limited to, silicon nitride (SiN x ), silicon oxide (SiO xsilicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon boron nitride (SiBN), silicon boron carbon nitride (SiCBN), oxide, nitride, plasma enhanced oxide (PEOX), or a combination thereof.

[0057] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H different stages of a method of fabricating a semiconductor device 1A are shown, as described below. Hereinafter, deposition techniques can include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

[0058] Referring to Figure 2A , a substrate 10 is provided. By using deposition techniques, a nitrogen-based semiconductor cap layer 60 and 62 can be formed sequentially on / over / above the substrate 10. A dielectric cap layer 64 can be formed on / over / above the nitrogen-based semiconductor cap layer 62. The formation stages of the nitrogen-based semiconductor cap layers 60 and 62 and the dielectric cap layer 62 can include deposition techniques. In some embodiments, deposition techniques can be performed to form blanket layers.

[0059] Referring to Figure 2B , a patterning process can be performed on the dielectric cap layer 64 such that its excess portions are removed, thereby leaving at least a portion of the dielectric cap layer 64 on the nitrogen-based semiconductor cap layer 62. The remaining portion of the dielectric cap layer 64 can act as a dummy gate DG. Thus, the dummy gate DG is formed on the nitrogen-based semiconductor cap layer 62.

[0060] Referring to Figure 2CA spacer cap layer 66 is formed to cover the top surface of the dummy gate DG and the nitride-based semiconductor cap layer 62.

[0061] Referring to Figure 2D A portion of the spacer cap layer 66 is removed to expose a portion of the nitride-based semiconductor cap layer 62. The nitride-based semiconductor cap layers 60 and 62 are then patterned so that the nitride-based semiconductor layer 14A with two vias TH1 and the nitride-based semiconductor layer 12 with two recesses R can be formed. The two recesses R are respectively aligned with the two vias TH1.

[0062] Afterwards, doped nitride-based semiconductor layers 20 and 22 are formed in the vias TH1 and the recesses R. Each of the doped nitride-based semiconductor layers 20, 22 can extend through the nitride-based semiconductor layer 14A. Each of the doped nitride-based semiconductor layers 20 and 22 can extend into the nitride-based semiconductor layer 12. Portions 142A of the nitride-based semiconductor layer 14A and portions 122 of the nitride-based semiconductor layer 12 can be well defined between the doped nitride-based semiconductor layers 22 and 20.

[0063] Next, another portion of the spacer cap layer 66 is removed to expose the top surface of the dummy gate DG, and some portions of the spacer cap layer 66 remain on two opposite outer sidewalls of the dummy gate DG as portions 401A and 402A of the outer spacers. A passivation cap layer is then formed to cover the nitride-based semiconductor layer 14A, the doped nitride-based semiconductor layers 20 and 22, the portions 401A and 402A, and the dummy gate DG. In some embodiments, excess portions of the passivation cap layer are removed to expose the top surfaces of the portions 401A and 402A and the dummy gate DG.

[0064] Afterwards, an etching process is performed on the passivation cap layer to form a plurality of vias to expose the top surfaces of the doped nitride-based semiconductor layers 20 and 22. Thus, a passivation layer 50 is formed. The passivation layer 50 is formed to cover the nitride-based semiconductor layer 14A and the doped nitride-based semiconductor layers 20 and 22. Next, an electrode cap layer is formed to cover the structure. The electrode cap layer is formed to contact the doped nitride-based semiconductor layers 20 and 22 through the plurality of vias of the passivation layer. An etching process is performed on the electrode cap layer to remove excess portions thereof to form electrodes 30, 32 with T-shaped profiles. The electrodes 30 and 32 are respectively formed on / over / above the doped nitride-based semiconductor layers 20 and 22.

[0065] To achieve different electrical characteristics of the semiconductor device, in some embodiments, the electrodes 30, 32 can be formed to have rectangular profiles.

[0066] Referring to Figure 2E The dummy gate DG is removed to form a gate trench GT between the portions 401A and 402A of the outer spacers.

[0067] Referring to Figure 2F , a spacer cap layer 68 is formed to cover Figure 2E the resultant structure such that a portion 68P of the spacer cap layer 68 is formed to extend into the gate trench GT. The portion 68P is conformal to the profile constituted by the portions 401A and 402A of the outer spacer and the nitrogen-based semiconductor layer 14A.

[0068] Referring to Figure 2G , a patterning process is performed on the spacer cap layer 68 to remove excess portions of the spacer cap layer 68, thereby forming portions 404A, 405A of the inner spacer in the gate trench GT.

[0069] Referring to Figure 2H , a gate electrode layer 69 is formed to cover Figure 2G the resultant structure. Thereafter, an etching process is performed on the gate electrode layer 69 to remove excess portions of the gate electrode layer, thereby forming a gate electrode 406A (i.e., the gate electrode 406A in Figure 1 ) in the gate trench GT. The gate electrode 406A has a bottom with a width smaller than the width of the gate trench GT. It should be noted that the dummy gate DG in Figure 2C is wider than the gate electrode 406. Thus, the semiconductor device 1A as shown in Figure 1 is obtained.

[0070] Figure 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A described and shown with reference to Figure 1 , except that the gate structure 40A can be replaced by a gate structure 40B, and the nitrogen-based semiconductor layer 14A can be replaced by a nitrogen-based semiconductor layer 14B.

[0071] Referring to Figure 3 , with respect to the semiconductor device 1B, a portion 142B of the nitrogen-based semiconductor layer 14B can have a recess R1. The portion 142B can have portions P1, P2 of different thicknesses, where the thickness of the portion P1 is greater than the thickness of the portion P2. The thinner portion P2 is located between two thicker portions P1. Thus, the top surface of the portion P2 and the inner sidewalls of the two portions P1 collectively define the profile of the recess R1. The gate trench GT is collectively defined by the inner sidewalls of the portions 401B, 402B of the outer spacer and the inner sidewalls of the portion 142B of the nitrogen-based semiconductor layer 14B (i.e., the inner sidewalls of the two thicker portions P2).

[0072] The portions 401B, 402B of the outer spacers can be disposed on / over / above the two thicker portions PI of the portion 142B of the nitrogen-based semiconductor layer 14B, respectively. The portions 401B, 402B of the outer spacers can be in contact with the two thicker portions PI of the portion 142B of the nitrogen-based semiconductor layer 14B, respectively.

[0073] Each of the portions 404B, 405B of the inner spacers can be disposed on / over / above the thinner portion P2 of the portion 142B of the nitrogen-based semiconductor layer 14B. Each of the portions 404B, 405B of the inner spacers extends downward to a location below the entire outer spacers, such that a bottom end surface of the portion 404B / 405B can be in contact with the thinner portion P2 of the portion 142B. The portions 404B / 405B of the inner spacers have a downward extending length greater than a thickness of the outer spacers, such that the bottom end surface of the portions 404B, 405B of the inner spacers is lower than the bottom end surface of the portions 401B, 402B of the outer spacers. The bottom end surface of the portions 404B, 405B of the inner spacers is within a thickness of the nitrogen-based semiconductor layer 14B.

[0074] Similarly, the gate electrode 406B can be disposed on / over / above the thinner portion P2 of the portion 142B of the nitrogen-based semiconductor layer 14B, such that a bottom end surface of the gate electrode 406A can be in contact with the thinner portion P2 in the portion 142B. The gate electrode 406B has a downward extending length greater than a thickness of the outer spacers, such that the bottom end surface of the gate electrode 406A is lower than the bottom end surface of the portions 401B, 402B of the outer spacers. The bottom end surface of the portions 404B, 405B of the inner spacers is within a thickness of the nitrogen-based semiconductor layer 14B.

[0075] The bottom end surface of the portions 404B, 405B of the inner spacers and the bottom end surface of the gate electrode 406B are at the same height level. The portions 404B, 405B of the inner spacers and the gate electrode 406B extend downward to collectively form a bottom portion of the gate structure 40B. The recess Rl of the nitrogen-based semiconductor layer 14B can receive the bottom portion of the gate structure 40B.

[0076] During the fabrication of the semiconductor device IB, the dummy gate DG and a portion of the nitrogen-based semiconductor cap layer 62 are removed to collectively form a gate trench GT. Thereafter, the portions 404B, 405B of the inner spacers and the gate electrode 406B are formed to collectively fill the gate trench GT.

[0077] According to the configuration of the present embodiment, the interface formed between the portions 404B, 405B of the inner spacers and the portion 142B of the nitrogen-based semiconductor layer 14B can be misaligned with the interface formed between the portions 401B, 402B of the outer spacers and the portion 142A of the nitrogen-based semiconductor layer 14A, so the path of at least one potential leakage current is further extended, and thus the leakage current problem can be improved.

[0078] Figure 4 FIG. 1C is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A described and shown with reference to FIG. 1A, except that the gate structure 40A can be replaced by a gate structure 40C, and the nitrogen-based semiconductor layer 14A can be replaced by a nitrogen-based semiconductor layer 14C. Figure 1

[0079] Referring to FIG. 1C, with respect to the semiconductor device 1C, the portion 142C of the nitrogen-based semiconductor layer 14C can have a via TH2. The gate trench GT is jointly defined by the inner sidewalls of the portions 401C, 402C of the outer spacers and the inner sidewalls of the portion 142C of the nitrogen-based semiconductor layer 14C. Figure 4

[0080] Each of the portions 404C, 405C of the inner spacers extends downward to a location below the entire outer spacers. The portions 404C / 405C of the inner spacers have a downward extension length greater than the thickness of the outer spacers.

[0081] Similarly, the gate electrode 406C extends downward to a location below the entire outer spacers.

[0082] The bottom end surfaces of the portions 404C, 405C of the inner spacers and the bottom end surface of the gate electrode 406C are at the same height level. The portions 404C, 405C of the inner spacers and the gate electrode 406C extend downward to jointly form the bottom of the gate structure 40C. The portions 404C, 405C of the inner spacers and the gate electrode 406C can extend into the via TH2 to contact the top surface of the nitrogen-based semiconductor layer 12.

[0083] During the fabrication of the semiconductor device 1C, the dummy gate DG and a portion of the nitrogen-based semiconductor cap layer 62 are removed to jointly form the gate trench GT. The gate trench GT exposes the top surface of the nitrogen-based semiconductor layer 12. Thereafter, the portions 404C, 405C of the inner spacers and the gate electrode 406C are formed to jointly fill the gate trench GT and contact the top surface of the nitrogen-based semiconductor layer 12.

[0084] ​​According to the configuration of the present embodiment, the interface formed between the portion 404C, 405C of the inner spacer and the nitrogen-based semiconductor layer 12 can be misaligned with the interface formed between the portion 401C, 402C of the outer spacer and the nitrogen-based semiconductor layer 14C, and thus the path of at least one potential leakage current is further extended. Therefore, the leakage current problem can be improved.

[0085] Figure 5 is a vertical cross-sectional view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1A described and shown with reference to Figure 1 The semiconductor device 1A described and shown with reference to

[0086] Referring to Figure 5 With respect to the semiconductor device 1D, the width of each of the portions 404D and 405D of the inner spacer gradually increases along the vertical direction VD; the width of the gate electrode 406D gradually decreases along the vertical direction VD due to the fact that the gate trench GT is co-filled by the inner spacer and the gate electrode 406D.

[0087] Each of the portions 404D, 405D of the inner spacer has a curved surface CS1, where the curved surface CS1 can be a convex surface towards the gate electrode 406D. The gate electrode 406D has a curved surface CS2, where the shape of the curved surface CS2 is complementary to the shape of the curved surface CS1. The interface formed between the portion 404D (or 405D) of the inner spacer and the gate electrode 406D is curved. Due to the above curved design, the stress in the gate structure 40D can be evenly distributed.

[0088] In addition, the portion 401D of the outer spacer has a curved surface towards the electrode 30. The portion 402D of the outer spacer has a curved surface towards the electrode 32, and the curved surfaces of the portions 401D, 402D of the outer spacer can evenly distribute the stress from the passivation layer 50D.

[0089] During the manufacturing process of the semiconductor device 1D, the outer spacer and the inner spacer can be formed to have curved surfaces by adjusting at least one parameter, such as a selected etchant, temperature, or pressure.

[0090] Figure 6 is a vertical cross-sectional view of a semiconductor device 1E according to some embodiments of the present disclosure. The semiconductor device 1E is similar to the semiconductor device 1D described and shown with reference to Figure 5 The semiconductor device 1D described and shown with reference to

[0091] Referring to Figure 6With respect to semiconductor device 1E, portion 142E of nitrogen-based semiconductor layer 14E can have recess R2. Portion 142B can have different portions PI, P2 of different thicknesses, where portion PI has a greater thickness than portion P2. Thinner portion P2 is located between two thicker portions PI. Thus, the top surface of portion P2 and the inner sidewalls of the two portions PI collectively define the profile of recess R2. Gate trench GT is collectively defined by the inner sidewalls of portions 401E, 402E of outer spacers and the inner sidewalls of portion 142E of nitrogen-based semiconductor layer 14E.

[0092] Each of portions 404E, 405E of inner spacers can be disposed on / over / above thinner portion P2 of portion 142E of nitrogen-based semiconductor layer 14E. Each of portions 404E, 405E of inner spacers extends downward to a location below the entire outer spacer, such that the bottom end surface of portion 404E / 405E can be in contact with thinner portion P2 of portion 142E. Portion 404E / 405E of inner spacers has a greater downward extension length than the thickness of outer spacer, such that the bottom end surface of portions 401E, 402E of inner spacers is lower than portions 401, 402E of outer spacers. The bottom end surface of portions 404E, 405E of inner spacers is within the thickness of nitrogen-based semiconductor layer 14E.

[0093] Similarly, gate electrode 406E can be disposed on / over / above thinner portion P2 of portion 142E of nitrogen-based semiconductor layer 14, such that the bottom end surface of gate electrode 406E can be in contact with thinner portion P2 in portion 142E. Gate electrode 406E has a greater downward extension length than the thickness of outer spacer, such that the bottom end surface of gate electrode 406E is lower than the bottom end surface of portions 401E, 402E of outer spacers. The bottom end surface of portions 404E, 405E of inner spacers is within the thickness of nitrogen-based semiconductor layer 14E.

[0094] The bottom end surface of portions 404E, 405E of inner spacers and the bottom end surface of gate electrode 406E are at the same height level. Portions 404E, 405E of inner spacers and gate electrode 406E extend downward to collectively form the bottom of gate structure 40E. Recess R2 of nitrogen-based semiconductor layer 14E can receive the bottom of gate structure 40E.

[0095] During fabrication of semiconductor device 1E, a portion of dummy gate DG and nitrogen-based semiconductor cap layer 62 is removed to collectively form gate trench GT. Thereafter, portions 404E, 405E of inner spacers and gate electrode 406E are formed to collectively fill gate trench GT.

[0096] Figure 7is a vertical cross-sectional view of a semiconductor device 1F according to some embodiments of the present disclosure. The semiconductor device 1F is similar to the semiconductor device 1A with reference to Figure 5 The semiconductor device 1D is described and shown, except that the nitride-based semiconductor layer 14D is replaced by a nitride-based semiconductor layer 14F, and the gate structure 40D can be replaced by a gate structure 40F.

[0097] Referring to Figure 7 With respect to the semiconductor device 1F, the portion 142F of the nitride-based semiconductor layer 14F can have a via TH3. The gate trench GT is jointly defined by the inner sidewalls of the portions 401F, 402F of the outer spacers and the inner sidewall of the portion 142F of the nitride-based semiconductor layer 14F.

[0098] Each of the portions 404F, 405F of the inner spacers extends downward to a location below the entire outer spacer. Each of the portions 404F, 405F of the inner spacers has a downward extension length greater than the thickness of the outer spacer.

[0099] Similarly, the gate electrode 406F extends downward to a location below the entire portions 401F, 402F of the outer spacer.

[0100] The bottom end surfaces of the portions 404F, 405F of the inner spacers and the bottom end surface of the gate electrode 406F are at the same height level. The portions 404F, 405F of the inner spacers and the gate electrode 406F extend downward to jointly form a bottom portion of the gate structure 40F. The portions 404F, 405F of the inner spacers and the gate electrode 406F can extend into the via TH3 to contact the top surface of the nitride-based semiconductor layer 12.

[0101] During the fabrication of the semiconductor device 1F, a portion of the dummy gate DG and the nitride-based semiconductor cap layer 62 are removed to jointly form the gate trench GT. The gate trench GT exposes the top surface of the nitride-based semiconductor layer 12. Thereafter, the portions 404F, 405F of the inner spacers and the gate electrode 406C are formed to jointly fill the gate trench GT to contact the top surface of the nitride-based semiconductor layer 12.

[0102] Figure 8 is a vertical cross-sectional view of a semiconductor device 1G according to some embodiments of the present disclosure. The semiconductor device 1G is similar to the semiconductor device 1A with reference to Figure 7 The semiconductor device 1F is described and shown, except that the gate structure 40F can be replaced by a gate structure 40G, and the semiconductor device 1G further includes a cap layer CL. The cap layer CL includes two separate portions CL1, CL2.

[0103] Referring to Figure 8With respect to semiconductor device 1G, portion CL1 of cap layer CL is disposed between portion 401G of outer spacer and portion 142G of nitrogen-based semiconductor layer 14G. Portion CL2 of cap layer CL is disposed between portion 402G of outer spacer and portion 142G of nitrogen-based semiconductor layer 14G. Widths of portions CL1, CL2 of cap layer CL are substantially the same as widths of bottom end surfaces of portions 401G, 402G of outer spacer, respectively. Portions CL1, CL2 of cap layer CL abut portions 404G, 405G of inner spacer, respectively.

[0104] Gate trench GT is defined by inner sidewalls of portions 401G, 402G of outer spacer, inner sidewalls of portions CL1, CL2 of cap layer CL, and inner sidewall of portion 142G of nitrogen-based semiconductor layer 14G. Portion 404G of inner spacer is in contact with inner sidewalls of portion 401G of outer spacer, inner sidewall of portion CL1 of cap layer CL, and inner sidewall of portion 142G of nitrogen-based semiconductor layer 14G. Portion 405G of inner spacer is in contact with inner sidewalls of portion 402G of outer spacer, inner sidewall of portion CL2 of cap layer CL, and inner sidewall of portion 142G of nitrogen-based semiconductor layer 14G.

[0105] An exemplary material of cap layer CL can be a dielectric material. For example, the dielectric material can include, for example but not limited to, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon boron nitride (SiBN), silicon boron carbon nitride (SiCBN), oxide, nitride, plasma enhanced oxide (PEOX), or a combination thereof.

[0106] During fabrication of semiconductor device 1G, a cap cover layer (not shown) is formed between nitrogen-based semiconductor cover layer 62 and dielectric cover layer 64. Then, a portion of the cap cover layer and dummy gate is removed such that two separate portions of the cap cover layer (i.e., portions CL1, CL2 of cap layer CL) remain under two separate portions 401G and 402G of outer spacer.

[0107] In embodiments involving inner spacers having curved surfaces, yield of gate electrodes can be improved since the curved profile can facilitate patterning of the fill of gate electrode layer into gate electrodes.

[0108] In the exemplary fabrication stage of the above embodiment, dummy gates are used to define the gate trenches. The dummy gates are removed by using an etching process before forming the gate electrodes. However, due to the characteristics of the etching process, the barrier layer (or channel layer) underneath the dummy gates can be over-etched, such that the electrical performance of the semiconductor device will be deteriorated. In addition, after the etching process, the top surface of the layer (e.g., the barrier layer) underneath the dummy gates will be rough due to the high etching rate, resulting in poor electrical contact between the gate electrodes and the barrier layer.

[0109] At least to avoid the above problems, the present disclosure aims to develop a new structure of semiconductor device.

[0110] Figure 9 is a vertical cross-sectional view of a semiconductor device 1H according to some embodiments of the present disclosure. The semiconductor device 1H includes a substrate 10, nitride-based semiconductor layers 12H and 14H, doped nitride-based semiconductor layers 20H and 22H, electrodes 30 and 32, a gate structure 40H, and a passivation layer 50. Here, the descriptions of the above-mentioned same or similar layers are omitted.

[0111] The gate structure 40H is disposed on / over / above a portion 142H of the nitride-based semiconductor layer 14H and a portion 122H of the nitride-based semiconductor layer 12H. The gate structure 40H is disposed between the electrodes 30 and 32. The gate structure 40H is confined between the electrodes 30 and 32 (or the doped nitride-based semiconductor layers 20 and 22). The gate structure 40H includes a gate spacer layer (including two separate portions 401H and 402H), an etch stop layer (including two separate portions 404H and 405H), and a gate electrode 406H. The detailed mechanisms will be described as follows.

[0112] In the present disclosure, before forming the gate structure 40H, a plurality of dielectric material layers can be formed on / over / above the nitride-based semiconductor layer 14H as a stack structure, wherein the dielectric material layers include at least one etch stop capping layer. The etch stop capping layer has different chemical / physical properties from other dielectric material layers. In some embodiments, the chemical composition of the etch stop capping layer is selected such that its etching rate with respect to an etchant is slower than the etching rate of other dielectric material layers with respect to the same etchant. In some embodiments, the physical properties of the etch stop capping layer are selected to have an etching rate with respect to a dry etcher (e.g., a plasma etcher) slower than the etching rate of other dielectric material layers with respect to the same dry etcher.

[0113] Then, during formation of the gate trench GT, an etching process is performed on the stack structure, and then the etching process will stop or be delayed at the etch stopper cover layer of the stack structure due to its chemical / physical properties. Thereafter, another etching process is performed on the etched stack structure again to etch the etched etch stopper cover layer again to achieve the gate trench GT with a predetermined depth. Therefore, the portions of the etch stopper cover layer (i.e., the etch stopper layer portions 404H, 405H) remain on / over / above the nitrogen-based semiconductor layer 14H.

[0114] Based on the above, due to the presence of the etch stopper cover layer, the first etching process will stop / delay at a position higher than the top surface of the portion 142H of the nitrogen-based semiconductor layer 14H. Thereafter, the second etching process is performed to etch the remaining etch stopper cover layer to form the gate trench GT. The etch stopper cover layer can protect the top surface of the nitrogen-based semiconductor layer 14H; therefore the uniformity of the top surface of the nitrogen-based semiconductor layer 14H (i.e., the barrier layer) can be improved. In addition, the leakage current due to the surface traps of the nitrogen-based semiconductor layer 14H can be avoided, thereby reducing the on-resistance of the semiconductor device 1H.

[0115] Furthermore, the etch stopper cover layer provides better control of the etching thickness, such that the formed gate trench GT can achieve the desired / predetermined depth. The variation of the on-resistance and the variation of the threshold voltage of the semiconductor device due to inaccurate etching thickness can be avoided. The reliability and performance of the semiconductor device 1H can be improved.

[0116] The detailed configuration of the gate structure 40H will be described as follows.

[0117] The portions 401H, 402H of the gate spacer layer are disposed on / over / above the portion 142H of the nitrogen-based semiconductor layer 14H and the portion 122H of the nitrogen-based semiconductor layer 12H. Each of the portions 401H, 402H of the gate spacer layer has a width that is substantially constant. An exemplary material of the gate spacer layer can be, for example, silicon oxide (Si3O4).

[0118] Portions 404H, 405H of the etch stop layer (i.e., the remaining portions of the etch stop cap layer) are disposed on / over / above portions 142H of the nitrogen-based semiconductor layer 14H. The portions 404H, 405H of the etch stop layer are in contact with the portions 142H of the nitrogen-based semiconductor layer 14H. Each of the portions 404H, 405H of the etch stop layer is disposed between the gate spacer layer and the nitrogen-based semiconductor layer 14H. The separate portions 404H and 405H of the etch stop layer are disposed under the two separate portions 401H, 402H of the gate spacer layer, respectively. Each of the portions 404H, 405H of the etch stop layer has a width that is substantially constant. The width of the portion 404H of the etch stop layer is substantially the same as the width of the portion 401H of the gate spacer layer. The width of the portion 405H of the etch stop layer is substantially the same as the width of the portion 402H of the gate spacer layer.

[0119] An exemplary material of the etch stop layer can be, for example, aluminum nitride (AIN), aluminum oxide (AI2O3), silicon nitride (SiN), or a combination thereof.

[0120] The portions 404H, 405H of the etch stop layer collectively define the gate trench GT with the portions 401H, 402H of the gate spacer layer. More specifically, the gate trench GT has a boundary, and the boundary of the gate trench GT is defined by the inner sidewalls of the portions 401H and 402H of the gate spacer layer and the inner sidewalls of the portions 404H and 405H of the etch stop layer.

[0121] The gate electrode 406H is disposed in the gate trench GT. The gate electrode 406H extends downward into the gate trench GT such that the gate electrode 406H can be in contact with the nitrogen-based semiconductor layer 14H. The bottom surface of the gate electrode 406H and the bottom surfaces of the portions 404H and 405H of the etch stop layer are at the same height level.

[0122] The doped nitrogen-based semiconductor layers 20H and 22H are located on two opposite sides of the gate structure 40H, respectively. Each of the doped nitrogen-based semiconductor layers 20H and 22H can extend through the nitrogen-based semiconductor layer 14H and into the nitrogen-based semiconductor layer 12H such that portions 122H, 142H of the nitrogen-based semiconductor layers 12H and 14H are sandwiched / between the doped nitrogen-based semiconductor layers 20H and 20H. The doped nitrogen-based semiconductor layer 20H is disposed between the electrode 30 and the nitrogen-based semiconductor layer 12H. The doped nitrogen-based semiconductor layer 22H is disposed between the electrode 32 and the nitrogen-based semiconductor layer 12H.

[0123] The doped nitrogen-based semiconductor layer 20H extends horizontally / laterally to the outer sidewall of the portion 401H of the gate spacer layer, the outer sidewall of the portion 404H of the etch stop layer, the outer sidewall of the portion 142H of the nitrogen-based semiconductor layer 14H, and the outer sidewall of the portion 122H of the nitrogen-based semiconductor layer 12H. The doped nitrogen-based semiconductor layer 20H abuts against the portion 401H of the gate spacer layer, the portion 404H of the etch stop layer, the portion 142H of the nitrogen-based semiconductor layer 14H, and the portion 122H of the nitrogen-based semiconductor layer 12H.

[0124] The doped nitrogen-based semiconductor layer 22H extends horizontally / laterally to the outer sidewall of the portion 402H of the gate spacer layer, the outer sidewall of the portion 405H of the etch stop layer, the outer sidewall of the portion 142H of the nitrogen-based semiconductor layer 14H, and the outer sidewall of the portion 122H of the nitrogen-based semiconductor layer 12H. The doped nitrogen-based semiconductor layer 22H abuts against the portion 402H of the gate spacer layer, the portion 405H of the etch stop layer, the portion 142H of the nitrogen-based semiconductor layer 14H, and the portion 122H of the nitrogen-based semiconductor layer 12H.

[0125] The gate electrode 406H is separated from the doped nitrogen-based semiconductor layers 20H, 22H by the gate spacer layer and the etch stop layer. The gate spacer layer and the etch stop layer can jointly provide a good insulation between the doped nitrogen-based semiconductor layers 20H / 22H and the gate electrode 406H, so that the gate leakage current can be significantly reduced.

[0126] Different stages of a method for manufacturing the semiconductor device 1H are illustrated in Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E 、 Figure 10F and Figure 10G as described below. In the following, the deposition techniques can include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

[0127] Reference is made toFigure 10A A substrate 10 is provided. Nitride-based semiconductor cap layers 60 and 62 can be formed in succession on / over / onto the substrate 10 by using deposition techniques. An etch stop cap layer 70 can be formed on / over / onto the nitride-based semiconductor cap layer 62. A dielectric layer 72 can be formed on / over / onto the etch stop cap layer 70. The formation of the nitride-based semiconductor cap layers 60 and 62, the stop cap layer 70 and the dielectric layer 70 can include deposition techniques. In some embodiments, deposition techniques can be performed to form the cap layers. In some embodiments, exemplary materials of the dielectric layer 72 can include, for example, silicon dioxide (Si02), while exemplary materials of the etch stop cap layer 70 can include, for example, aluminum nitride (AIN), aluminum oxide (AI2O3), silicon nitride (SiN), or combinations thereof.

[0128] Referring to Figure 10B A patterning process can be performed on the dielectric layer 70 such that its excess portions are removed, thereby leaving at least a portion of the dielectric layer 72 on the etch stop cap layer 70. The remaining portion of the dielectric layer 72 can serve as a dummy gate DG.

[0129] Referring to Figure 10C A spacer cap layer 66 is formed to cover the top surface of the dummy gate DG and the etch stop cap layer 70. In some embodiments, exemplary materials of the spacer cap layer 66 can include, for example, silicon oxide (S13O4).

[0130] Referring to Figure 10D A portion of the spacer cap layer 66 is removed to expose a portion of the nitride-based semiconductor cap layer 62. Then, a patterning process is performed on the nitride-based semiconductor cap layers 60 and 62, thereby the nitride-based semiconductor layer 14H having two through holes TH1 and the nitride-based semiconductor layer 12H having two recesses R can be formed. The two recesses R are respectively aligned with the two through holes TH1.

[0131] Afterwards, doped nitride-based semiconductor layers 20H and 22H are formed in the through holes TH1 and the recesses R, respectively. Each of the doped nitride-based semiconductor layers 20H and 22H can extend through the nitride-based semiconductor layer 14H and into the nitride-based semiconductor layer 12H. Portions 142H of the nitride-based semiconductor layer 14H and portions 122H of the nitride-based semiconductor layer 12H can be well defined / restricted between the doped nitride-based semiconductor layers 20H and 22H.

[0132] Next, another portion of the spacer capping layer 66 is removed to expose the top surface of the dummy gate DG, and some remaining portions of the spacer capping layer remain at two opposite outer sidewalls of the dummy gate DG as portions 40 IH and 402H of the gate spacer layer. A passivation capping layer is formed to cover the nitrogen-based semiconductor layer 14H, the doped nitrogen-based semiconductor layers 20H and 22H, the portions 40 IH and 402H, and the dummy gate DG. In some embodiments, excess portions of the passivation capping layer are removed, thereby exposing the top surface of the portions 40 IH and 402H and the dummy gate DG.

[0133] Thereafter, an etching process is performed on the passivation capping layer to form a plurality of vias to expose the top surfaces of the doped nitrogen-based semiconductor layers 20H and 22H. Thus, a passivation layer 50 is formed. The passivation layer 50 is formed to cover the nitrogen-based semiconductor layer 14H and the doped nitrogen-based semiconductor layers 20H and 22H. Then, an electrode capping layer is formed to cover the structure, such that a portion of the electrode capping layer fills the vias of the passivation layer 50. The electrode capping layer is formed and it is in contact with the doped nitrogen-based semiconductor layers 20H and 22H through the vias in the passivation layer 50. An etching process is performed on the electrode capping layer to remove excess portions thereof, thereby forming electrodes 30, 32 having a T-shaped profile. The electrodes 30 and 32 are formed on / over / above the doped nitrogen-based semiconductor layers 20H and 22H, respectively.

[0134] Reference is made to Figure 10E A first etching process is performed on the dummy gate DG. After the first etching process, the dummy gate DG is removed such that a portion P of the etch stop capping layer 70 is exposed.

[0135] In some embodiments, the first etching process can be performed by using a wet etching process. An etchant is applied to the wet etching process. The etch selectivity between the etch stop capping layer 70 and the dummy gate DG can be achieved by the desired etchant. For example, during the wet etching process, the etch rate of the etch stop capping layer 70 relative to the etchant is much smaller than the etch rate of the dummy gate DG relative to the same etchant.

[0136] In some embodiments, the first etching process can be performed by using a dry etching process. A dry etcher (e.g., a plasma etcher) can be applied to the dry etching process. In some embodiments, the etch selectivity between the etch stop capping layer 70 and the dummy gate DG can be achieved by material selection. For example, the materials of the etch stop capping layer 70 and the dummy gate DG are well selected such that the density of the etch stop capping layer is much greater than the dummy gate DG.

[0137] Thus, during the dry etching process, the etch rate of the etch stop capping layer 70 relative to the dry etcher is much smaller than the etch rate of the dummy gate DG relative to the same dry etcher.

[0138] Accordingly, in response to the etching selectivity described above, the first etching process can stop / delay at the etching stopper layer 70 (i.e., at a position higher than the nitrogen-based semiconductor layer 14H).

[0139] Reference Figure 10F The second etching process is performed on the portion P of the etching stopper layer 70 to remove at least a portion P of the etching stopper layer 70 so that the gate trench GT is formed, where the gate trench GT exposes a top surface of the nitrogen-based semiconductor layer 14H. After the second etching process, portions 404H, 405H of the etching stopper layer are formed. The portions 404H, 405H of the etching stopper layer can be formed to have the same width as the portions 401H, 402H of the gate spacer layer, respectively.

[0140] In some embodiments, the first etching process can include a dry etching process or a wet etching process, and the second etching process can include a dry etching process or a wet etching process. The selection of the dry or wet etching process can change the morphology of the inner sidewalls of the portions 404H, 405H of the etching stopper layer and the portions 401H, 402H of the gate spacer layer.

[0141] In some embodiments, the first etching process can be a dry etching process, and the second etching process can be a dry etching process. Accordingly, the inner sidewalls of the portions 404H, 405H of the etching stopper layer and the portions 401H, 402H of the gate spacer layer can be flat.

[0142] In some embodiments, the first etching process can be a wet etching process, and the second etching process can be a dry etching process. Accordingly, the inner sidewalls of the portions 401H, 402H of the gate spacer layer can be inwardly recessed, and the inner sidewalls of the portions 404H, 405H of the etching stopper layer 407 can be flat.

[0143] In some embodiments, the first etching process can be a dry etching process, and the second etching process can be a wet etching process. Accordingly, the inner sidewalls of the portions 401H, 402H of the gate spacer layer can be flat, and the inner sidewalls of the portions 404H, 405H of the etching stopper layer can be inwardly recessed.

[0144] In some embodiments, the first etching process can be a wet etching process, and the second etching process can be a wet etching process. Accordingly, the inner sidewalls of the portions 404H, 405H of the etching stopper layer and the portions 401H, 402H of the gate spacer layer can be inwardly recessed.

[0145] The morphology of the inner sidewalls of the etch stop layer and the gate spacer layer can be determined by a combination of dry etching process and wet etching process, thereby further achieving different electrical performance and having greater design flexibility.

[0146] Reference is made to Figure 10G , the gate electrode layer 70 is formed to cover the structure as formed in FIG. 10H. Thereafter, an etching process is performed on the gate electrode layer 70 to remove the excess portion of the gate electrode layer 70, thereby forming the gate electrode 406H in the gate trench GT. Thus, the semiconductor device 1H as shown in FIG. 10I is obtained. Figure 9

[0147] Different stages of the method of manufacturing the semiconductor device are shown in Figure 11A and Figure 11B , as described below.

[0148] Continuing from the manufacturing stage of Figure 10A , reference is made to Figure 11A , a patterning process is performed on the etch stop cover layer 70 and the dielectric layer 72, such that the dummy gate DG and the etch stop layer 407’ can be formed in a single manufacturing stage. The width of the etch stop layer 407’ is formed to be substantially the same as the width of the dummy gate DG. Thus, the manufacturing cost of the semiconductor device can be further reduced.

[0149] Reference is made to Figure 11B , similar to the manufacturing stage of Figure 10D , the nitrogen-based semiconductor layer 14H, the doped nitrogen-based semiconductor layers 20H and 22H, the electrodes 30, 32 and the portions 401H and 402H of the gate spacer layer are formed, except that the portions 401H and 402H of the gate spacer layer remain on the outer sidewalls of the dummy gate DG and the etch stop layer 407’. The etch stop layer 407’ is formed between the portions 401H and 402H of the gate spacer layer.

[0150] Figure 12 is a vertical cross-sectional view of a semiconductor device 1I according to some embodiments of the present disclosure. The semiconductor device 1I is similar to the semiconductor device 1H described and shown with reference to Figure 9 , except that the gate structure 40H can be replaced by a gate structure 40I, and the nitrogen-based semiconductor layer 14H can be replaced by a nitrogen-based semiconductor layer 14I.

[0151] Reference is made to Figure 12 , with respect to the semiconductor device 1I, the portion 142I of the nitrogen-based semiconductor layer 14I can have a recess R3. The portion 142I can have different portions P1, P2 of different thicknesses, wherein the thickness of the portion P1 is greater than the portion P2. The thinner portion P2 is located between the two thicker portions P1. Thus, the top surface of the portion P2 and the inner sidewalls of the two portions P1 collectively define the profile of the recess R3. ​

[0152] The portions 404I, 405I of the etch stop layer can be disposed on / over / above the two thicker portions PI of the portion 142I of the nitrogen-based semiconductor layer 14I, respectively. The portions 404I, 405I of the etch stop layer can be in contact with the two thicker portions PI of the portion 142I of the nitrogen-based semiconductor layer 14I, respectively. The portions 401I, 402I of the gate spacer layer can be in contact with the top surfaces of the portions 404I, 405I of the etch stop layer, respectively. The gate trench GT is collectively defined by the inner sidewalls of the portions 401I, 402I of the gate spacer layer, the inner sidewalls of the portions 404I, 405I of the etch stop layer, and the inner sidewalls of the portion 142I of the nitrogen-based semiconductor layer 14I (i.e., the inner sidewalls of the two thicker portions P2).

[0153] The gate electrode 406I is disposed on the thinner portion P2 of the portion 142I of the nitrogen-based semiconductor layer 14I. The gate electrode 406I is disposed in the gate trench GT. The gate electrode 406I extends downward into the nitrogen-based semiconductor layer 14I such that a bottom surface of the gate electrode 406I is located at a position lower than a bottom surface of the portions 404I, 405I of the etch stop layer. The bottom surface of the gate electrode 406I is in contact with the thinner portion P2 of the portion 142I of the nitrogen-based semiconductor layer 14I. The bottom surface of the gate electrode 406I is within the thickness of the nitrogen-based semiconductor layer 14I.

[0154] During the fabrication of the semiconductor device 1I, a portion of the dummy gate DG, a portion of the portion P of the etch stop capping layer 70, and a portion of the nitrogen-based semiconductor capping layer 62 are removed, thereby forming the nitrogen-based semiconductor layer 14I with the recess R3, into which the bottom of the gate electrode 406I can be received.

[0155] Figure 13 is a vertical cross-sectional view of a semiconductor device 1J according to some embodiments of the present disclosure. The semiconductor device 1J is similar to the semiconductor device 1H described and shown with reference to Figure 9 The semiconductor device 1H described and shown with reference to

[0156] Reference is made to Figure 13 With respect to the semiconductor device 1J, the portion 142J of the nitrogen-based semiconductor layer 14J can have a via TH4. The gate trench GT is collectively defined by the inner sidewalls of the portions 401J, 402J of the gate spacer layer, the inner sidewalls of the portions 404J, 405J of the etch stop layer, and the inner sidewalls of the portion 142J of the nitrogen-based semiconductor layer 14J.

[0157] The gate electrode 406J is disposed on / over / above the nitrogen-based semiconductor layer 12J. The gate electrode 406J is disposed in the gate trench GT. The gate electrode 406J extends downward into the nitrogen-based semiconductor layer 14J such that a bottom surface of the gate electrode 406J is located at a position lower than a bottom surface of the portions 404J, 405J of the etch stop layer. The gate electrode 406J penetrates the nitrogen-based semiconductor layer 14J through the via TH4 such that a bottom surface of the gate electrode 406J is in contact with the nitrogen-based semiconductor layer 12J.

[0158] During the fabrication of the semiconductor device 1J, a portion of the dummy gate DG, a portion of the portion P of the etch stop capping layer 70, and a portion of the nitrogen-based semiconductor capping layer 62 are removed, thereby forming the nitrogen-based semiconductor layer 14J with the via TH4 to expose the top surface of the nitrogen-based semiconductor layer 12J. The gate trench GT is formed and the gate trench GT exposes the top surface of the nitrogen-based semiconductor layer 12J. Since the etch stop capping layer 70 can protect the top surface of the nitrogen-based semiconductor layer 12J; the uniformity of the top surface of the nitrogen-based semiconductor layer 12J (i.e., the channel layer) can be improved. Thereafter, the gate electrode 406J is formed to fill the gate trench GT to be in contact with the nitrogen-based semiconductor layer 12J.

[0159] Figure 14 is a vertical cross-sectional view of a semiconductor device 1K in accordance with some embodiments of the present disclosure. The semiconductor device 1K is similar to the semiconductor device 1H described and shown with reference to Figure 9 The semiconductor device 1H described and shown with reference to

[0160] Referring to Figure 14 With respect to the semiconductor device 1K, the width of the portions 401K / 402K of the gate spacer layer has a width that gradually increases along the vertical direction VD.

[0161] The portion 401K of the gate spacer layer has a curved surface facing the electrode 30. The portion 402K of the gate spacer layer has a curved surface facing the electrode 32. The curved surfaces of the gate spacer layer 401K, 402K can uniformly distribute the stress of the passivation layer 50K. The interface formed between the portions 401K / 402K of the gate spacer layer and the passivation layer 50K is curved. The curved surfaces can uniformly distribute the stress from the passivation layer 50K.

[0162] During the fabrication of the semiconductor device 1K, each of the portions 401K, 402K of the gate spacer layer can be formed to have a curved surface by adjusting at least one parameter (e.g., a selected etchant, temperature, or pressure).

[0163] Figure 15is a vertical cross-sectional view of a semiconductor device 1L according to some embodiments of the present disclosure. The semiconductor device 1L is similar to the semiconductor device 1K described and shown with reference to Figure 14 The semiconductor device 1K described and shown, except that the gate electrode 406K can be replaced by the gate electrode 406L.

[0164] Referring to Figure 15 With respect to the semiconductor device 1L, the portion 142I of the nitrogen-based semiconductor layer 14I can have a recess R4. The portion 142L can have different portions PI, P2 of different thicknesses, where the thickness of the portion PI is greater than the thickness of the portion P2. The thinner portion P2 is located between the two thicker portions PI. Thus, the top surface of the portion P2 and the inner sidewalls of the two portions PI collectively define the profile of the recess R4.

[0165] The portions 404L, 405L of the etch stop layer can be disposed on the two thicker portions PI of the portion 142L of the nitrogen-based semiconductor layer 14L, respectively. The portions 404L, 405L of the etch stop layer can be in contact with the two thicker portions PI of the portion 142L of the nitrogen-based semiconductor layer 14L, respectively. The portions 401L, 402L of the gate spacer layer can be in contact with the top surfaces of the portions 404L, 405L of the etch stop layer, respectively. The gate trench GT is collectively defined by the inner sidewalls of the portions 401L, 402L of the gate spacer layer, the inner sidewalls of the portions 404L, 405L of the etch stop layer, and the inner sidewalls of the portion 142L of the nitrogen-based semiconductor layer 14I (i.e., the inner sidewalls of the two thicker portions PI).

[0166] The gate electrode 406L is disposed on the thinner portion P2 of the portion 142L of the nitrogen-based semiconductor layer 14L. The gate electrode 406L is disposed in the gate trench GT. The gate electrode 406L extends downward into the nitrogen-based semiconductor layer 14L such that the bottom surface of the gate electrode 406R is located at a position lower than the bottom surfaces of the portions 404L, 405L of the etch stop layer. The bottom surface of the gate electrode 406L is in contact with the thinner portion P2 of the portion 142L of the nitrogen-based semiconductor layer 14L. The bottom surface of the gate electrode 406L is within the thickness of the nitrogen-based semiconductor layer 14L.

[0167] During the fabrication of the semiconductor device 1L, the bottom of the gate electrode 406L can be received by the recess R4, with the removal of the dummy gate DG, a portion of the portion P of the etch stop capping layer 70, and a portion of the nitrogen-based semiconductor capping layer 62.

[0168] Figure 16 is a vertical cross-sectional view of a semiconductor device 1M according to some embodiments of the present disclosure. The semiconductor device 1M is similar to the semiconductor device 1L described and shown with reference to Figure 14 The semiconductor device 1K described and shown, except that the gate structure 40K can be replaced by the gate electrode 406K. The nitrogen-based semiconductor layer 14K can be replaced by the nitrogen-based semiconductor layer 14M.

[0169] Referring to Figure 16 , with respect to the semiconductor device 1M, the portion 142M of the nitrogen-based semiconductor layer 14M can have the via TH5. The gate trench GT is collectively defined by the inner sidewalls of the portions 401M, 402M of the gate spacer, the inner sidewalls of the portions 404M, 405M of the etch stop layer, the inner sidewalls of the portions 402M, 404M of the etch stop layer, and the inner sidewalls of the portion 142M of the nitrogen-based semiconductor layer 14M.

[0170] The gate electrode 406M is disposed on / over / above the nitrogen-based semiconductor layer 12M. The gate electrode 406M is disposed in the gate trench GT. The gate electrode 406M extends downward into the nitrogen-based semiconductor layer 14M such that a bottom surface of the gate electrode 406M is located at a position lower than a bottom surface of the portions 404M, 405M of the etch stop layer. The gate electrode 406M can extend into the via TH5 to contact a top surface of the nitrogen-based semiconductor layer 12M.

[0171] During fabrication of the semiconductor device 1M, a portion of the dummy gate DG, a portion of the portion P of the etch stop layer 70, and a portion of the nitrogen-based semiconductor cap layer 62 are removed, thereby forming the nitrogen-based semiconductor layer 14M with the via TH5 to expose the top surface of the nitrogen-based semiconductor layer 12M. The gate trench GT is formed, wherein the gate trench GT exposes the top surface of the nitrogen-based semiconductor layer 12M. Thereafter, the gate electrode 406M is formed to fill the gate trench GT to contact the nitrogen-based semiconductor layer 12M.

[0172] Figure 17 is a vertical cross-sectional view of a semiconductor device 1N according to some embodiments of the present disclosure. The semiconductor device 1N is similar to the semiconductor device 1H described and shown with reference to Figure 16 except that the gate structure 40M can be replaced by the gate structure 40N, and the semiconductor device 1G further includes a cap layer CL. The cap layer CL includes two separate portions CL1, CL2.

[0173] Referring to Figure 17 , with respect to the semiconductor device 1N, the portion CL1 of the cap layer CL is disposed between the portion 401N of the gate spacer and the portion 142N of the nitrogen-based semiconductor layer 14N. The portion CL2 of the cap layer CL is disposed between the portion 402N of the outer spacer and the portion 142N of the nitrogen-based semiconductor layer 14N. The widths of the portions CL1, CL2 of the cap layer CL are substantially the same as the widths of the bottom end surfaces of the portions 401N, 402N of the outer spacer, respectively. The portions CL1, CL2 of the cap layer CL are in abutment with the gate electrode 406N, respectively.

[0174] The gate trench GT is jointly defined by inner sidewalls of the portions 401N, 402N of the gate spacer layer, inner sidewalls of the portions 404N, 405N of the etch stop layer, inner sidewalls of the portions CL1, CL2 of the cap layer CL, and inner sidewalls of the portion 142N of the nitrogen-based semiconductor layer 14N. The portion 404N of the etch stop layer is disposed between the portion 401N of the gate spacer layer and the portion CL1 of the cap layer CL. The portion 405N of the etch stop layer is disposed between the portion 402N of the gate spacer layer and the portion CL2 of the cap layer CL.

[0175] An exemplary material of the cap layer CL can be a dielectric material. For example, the dielectric material can include, for example but not limited to, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), oxide, nitride, plasma enhanced oxide (PEOX), or a combination thereof.

[0176] During the manufacturing process of the semiconductor device 1N, a cap cover layer (not shown) is formed between the nitrogen-based semiconductor cover layer 62 and the etch stop cover layer 70. Then, a portion of the cap cover layer, a portion of the etch stop cover layer 70, and the dummy gate DG are removed, such that two separated portions of the cap cover layer (i.e., the portions CL1, CL2 of the cap layer CL) remain under the portions 404N, 405N of the etch stop layer 407N.

[0177] Through the above configuration, in the present disclosure, by pre-filling / introducing the inner spacer within the gate trench of the gate structure, and forming the gate electrode within the gate trench after the formation of the inner spacer, the gate length of the gate electrode can naturally be smaller than the width of the gate trench. Therefore, the semiconductor device can meet the high frequency requirement. Furthermore, the effect of reducing the channel length can be achieved without using expensive devices, and the electrical performance of the semiconductor device can be improved. In addition, the manufacturing cost of the semiconductor device can be greatly reduced.

[0178] On the other hand, in the present disclosure, by introducing at least one etch stop layer in the gate structure, due to the presence of the etch stop layer, the formation of the gate trench of the gate structure includes at least two etching processes. Due to its chemical / physical properties, the etch stop layer can effectively stop the first etching process; therefore, the probability of over-etching problem will be reduced. Therefore, the reliability and performance of the semiconductor device can be improved.

[0179] The foregoing description of the present disclosure has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.

[0180] As used herein and unless otherwise defined, the terms, such as "substantially," "substantial," "approximately," and "about," are used to describe and account for small variations. When utilized with an event or circumstance, the term can include instances of the event or circumstance occurring exactly, as well as instances of the event or circumstance occurring approximately. For example, when utilized with a numerical value, the term can include a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For the term "substantially coplanar," it can refer to two surfaces positioned along the same plane within a number of micrometers (pm), such as within 40 micrometers (pm), within 30 pm, within 20 pm, within 10 pm, or within 1 pm.

[0181] As used herein, the singular terms "a," "an," and "the" can include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, components provided "over" or "on" other components can include a state in which the other component is directly in contact with the component provided "over" or "on" the other component, as well as a state in which one or more intervening components are present between the other component and the component provided "over" or "on" the other component.

[0182] While the disclosure has been described and illustrated with reference to specific implementations thereof, these descriptions and illustrations have been made by way of example only. The skilled person will understand that various modifications and substitutions can be made without departing from the true spirit and scope of the disclosure as defined by the appended claims. The drawings are not necessarily to scale. Variations in the processes and dimensions of the devices presented in the disclosure can occur as a result of manufacturing processes and tolerances. Other embodiments of the disclosure can not be specifically described. The specification and drawings should be considered illustrative only. Modifications can be made to adapt a particular situation, material, composition of matter, method or process to the purpose, spirit and scope of the disclosure. All such modifications will be considered within the scope of the claims here appended. While the methods disclosed herein are described with reference to particular sequences for performing certain operations, it will be understood that these operations can be combined, sub-divided, or re-ordered to form equivalent methods, and such is not a departure from the teachings of the present disclosure. Accordingly, unless specifically indicated otherwise, the order and grouping of these operations are not limiting.

Claims

1. A semiconductor device, characterized by, comprising: a first nitride-based semiconductor layer; a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor layer; and a gate structure disposed over the first nitride-based semiconductor layer, wherein the gate structure comprises: an outer spacer disposed over the second nitride-based semiconductor layer and having at least two opposing inner sidewalls to bound a gate trench; an inner spacer disposed over the first nitride-based semiconductor layer and within the gate trench; and a gate electrode disposed within the gate trench and covered by the inner spacer, wherein the at least one inner spacer and the gate electrode extend downward to collectively form a bottom of the gate structure, the bottom having a first width greater than a second width of a bottom surface of the gate electrode; wherein, the inner spacer has a downward extension length greater than a thickness of the outer spacer; the inner spacer has a bottom end surface in contact with the second nitride-based semiconductor layer, and the bottom end surface of the inner spacer is located within a thickness of the second nitride-based semiconductor layer; the inner spacer extends downward to a location below the entire outer spacer. wherein the entire inner sidewalls of the outer spacer are covered by the inner spacer.

2. The semiconductor device according to claim 1, wherein wherein the gate electrode and the outer spacer are separated from each other by the inner spacer.

3. The semiconductor device of claim 1, wherein wherein the inner spacer comprises two portions separated from each other, and the gate electrode is located between the portions of the inner spacer and is wider than each of the two portions of the inner spacer.

4. The semiconductor device of claim 1, wherein wherein the second nitride-based semiconductor layer has a recess that receives the bottom of the gate structure.

5. The semiconductor device of claim 1, wherein wherein the inner spacer comprises two portions separated from each other, the two portions having a width that is substantially constant.

6. The semiconductor device of claim 1, wherein wherein the width of the inner spacer gradually increases in a vertical direction.

7. The semiconductor device of claim 1, wherein wherein an interface formed between the inner spacer and the gate electrode is curved.

8. The semiconductor device of claim 1, wherein further comprising a doped nitride-based semiconductor layer at least against the outer spacer, wherein an entire bottom surface of the doped nitride-based semiconductor layer is located below the inner spacer.

9. The semiconductor device of claim 8, wherein, further comprising:

10. The semiconductor device of claim 1, wherein a cap layer disposed between the outer spacer and the second nitride-based semiconductor layer and against the inner spacer. comprising:

11. A method of manufacturing a semiconductor device, characterized by forming a first nitride-based semiconductor layer; forming a second nitride-based semiconductor layer over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor layer; forming a dummy gate on the second nitride-based semiconductor layer; forming a spacer cap layer to cover the dummy gate; removing a portion of the spacer cap layer to expose the dummy gate, wherein at least a portion of the spacer cap layer remains on outer sidewalls of the dummy gate as an outer spacer; removing the dummy gate to form a gate trench; forming an inner spacer within the gate trench; and forming a gate electrode within the gate trench such that a width of a bottom of the gate electrode is less than a width of the gate trench; wherein, ​ ​ The gate trench exposes a portion of the first nitride-based semiconductor layer; The formed inner spacer extends downward with an extension length greater than a thickness of the outer spacer; A bottom end surface of the formed inner spacer is in contact with the second nitride-based semiconductor layer and is located within a thickness of the second nitride-based semiconductor layer.

12. The manufacturing method according to claim 11, wherein The inner spacer has a width gradually increasing in a vertical direction.

13. The manufacturing method according to claim 11, wherein The inner spacer is formed to have a curved surface.

14. The manufacturing method according to claim 11, wherein The dummy gate is wider than the gate electrode.

15. A semiconductor device, characterized by comprising: Comprising: a first nitride-based semiconductor layer; a second nitride-based semiconductor layer disposed above the first nitride-based semiconductor layer, wherein a bandgap of the second nitride-based semiconductor layer is greater than a bandgap of the first nitride-based semiconductor layer; an outer spacer disposed above the first nitride-based semiconductor layer and defining a gate trench; an inner spacer disposed above the first nitride-based semiconductor layer and within the gate trench, wherein the inner spacer extends downward with an extension length greater than a thickness of the outer spacer; and a gate electrode disposed within the gate trench, wherein the inner spacer is located between the outer spacer and the gate electrode; wherein, a bottom end surface of the inner spacer is in contact with the second nitride-based semiconductor layer and is located within a thickness of the second nitride-based semiconductor layer; the inner spacer extends downward to a location below the entire outer spacer.

16. The semiconductor device of claim 15, wherein, The gate electrode and the inner spacer extend downward to be in contact with the second nitride-based semiconductor layer.

17. The semiconductor device of claim 15, wherein, A width of a bottom of the gate electrode is greater than a thickness of a bottom of the inner spacer.

18. The semiconductor device of claim 17, wherein, Further comprising two electrodes disposed above the first nitride-based semiconductor layer, wherein the outer spacer, inner spacer, and gate electrode are located between the two electrodes.

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