Fabrication method of MEMS piezoelectric vector hydrophone chip with dual mass block polygonal structure

Abstract

This invention relates to a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass polygonal structure. The method includes fabricating a silicon substrate, a piezoelectric composite cantilever structure, a polygonal annular support structure, and upper and lower mass blocks. The piezoelectric composite cantilever structure comprises an integrated cantilever center and multiple piezoelectric composite cantilever beams; one end of each piezoelectric composite cantilever beam is connected to the mass block, and the other end is connected to the inner wall of one side of the polygonal annular support structure; the upper and lower mass blocks are symmetrically distributed at the center of the polygonal annular support structure; a gap is formed between two adjacent piezoelectric composite cantilever beams and the polygonal annular support structure; a hole is formed between the polygonal annular support structure and the lower mass block. This method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass polygonal structure exhibits good process stability, strong feasibility, and high yield.

Description

Technical Field

[0001] This invention relates to the field of sensing technology, and in particular to a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass block polygonal structure. Background Technology

[0002] Compared to traditional hydrophones, MEMS vector hydrophones have the advantages of small size, low power consumption, low cost, and easy arraying due to MEMS technology; the figure-eight directivity enables them to measure the vector information of underwater sound fields, such as particle displacement, velocity, and acceleration, which is beneficial for the identification of long-distance, multi-target underwater.

[0003] Good directivity is one of the important indicators for evaluating MEMS vector hydrophones. In existing technologies, vector hydrophones commonly use a cantilever beam structure with a single mass block, but its figure-eight directivity exhibits significant skewness. Research has shown that this skewness is mainly caused by the asymmetry of the sensitive structure. In practical applications, the cantilever beam structure with a single mass block has proven insufficient to meet current requirements for the directivity and sensitivity of hydrophones. Therefore, fabricating a MEMS piezoelectric vector hydrophone chip with good directivity and high sensitivity is an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to further improve the directivity and sensitivity of MEMS vector hydrophones. Compared with the problems caused by the asymmetry of the sensitive structure in the single-mass block cantilever beam structure used in the existing vector hydrophones, this invention provides a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass block polygonal structure. Using this method, a MEMS piezoelectric vector hydrophone chip with a dual-mass block polygonal structure can be fabricated stably and efficiently.

[0005] To address the asymmetry issue in sensitive structures inherent in traditional single-mass cantilever beam structures, this fabrication method first models a MEMS piezoelectric vector hydrophone chip with a dual-mass polygonal structure using simulation software. Based on the size and position of the lower mass block and its specific polygonal structure, the size and placement of the upper mass block are analyzed and optimized to ensure that the overall center of gravity of both mass blocks coincides with that of the piezoelectric composite cantilever structure. Subsequently, based on the simulation data, a uniform polygonal structure and symmetrical upper and lower mass blocks about the piezoelectric composite cantilever structure are fabricated to further ensure that the overall center of gravity of both mass blocks coincides with that of the piezoelectric composite cantilever structure. The MEMS piezoelectric vector hydrophone chip with a dual-mass polygonal structure fabricated using this method exhibits significantly improved sensitivity and directivity. Furthermore, because the overall center of gravity of the upper and lower mass blocks coincides with that of the piezoelectric composite cantilever structure, it displays unbiased figure-eight directivity in both the xz and yz planes, with excellent overlap and consistency in the directivity performance of the xz and yz planes.

[0006] The present invention discloses a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass block polygonal structure, the method comprising the following steps:

[0007] Step 1. Prepare the silicon substrate;

[0008] Step 2. Deposit an insulating layer on the surface of the silicon substrate;

[0009] Step 3. Deposit a metal film on the upper surface of the insulating layer and pattern the metal film to form the lower electrode;

[0010] Step 4. Prepare a piezoelectric film layer on the upper surface of the lower electrode and pattern the piezoelectric film layer to form a piezoelectric layer;

[0011] Step 5. Deposit a metal film on the upper surface of the piezoelectric layer and pattern the metal film to form the upper electrode;

[0012] Step 6. Coat the upper surface of the substrate silicon wafer with photoresist, and expose and pattern the pattern of multiple gaps to be etched on the photoresist. Perform wet etching or dry etching on the insulating layer and device silicon layer respectively to form multiple gaps, in preparation for the release of multiple cantilever and lower mass block.

[0013] Step 7. Prepare a bulk etching mask layer on the back side of the substrate silicon wafer and pattern the bulk etching mask layer;

[0014] Step 8. Perform wet etching or dry etching on the bottom of the substrate to form holes and release multiple cantilever and lower mass block; the base silicon layer in the middle of the holes is the lower mass block;

[0015] Step 9. A supermass block is attached or bonded to the upper surface of the piezoelectric composite cantilever structure, and the supermass block and the lower mass block are located at the same position on the upper and lower surfaces of the piezoelectric composite cantilever structure; the lower mass block (11) is made by etching, attaching or bonding.

[0016] As an improvement to the above technical solution, step 1 uses an SOI substrate or a regular silicon substrate as the substrate; the SOI silicon substrate includes, from top to bottom, the following layers stacked sequentially: a device silicon layer, an SOI buried oxide layer, and a base silicon layer; the regular silicon substrate includes, from top to bottom, the following layers stacked sequentially: a device silicon layer and a base silicon layer.

[0017] When an SOI substrate is used as the substrate, in step 8, the base silicon layer and SOI buried oxide layer of the SOI substrate are subjected to wet etching or dry etching from the outside to the inside.

[0018] When a common silicon substrate is used as the substrate, in step 8, the base silicon layer of the common silicon substrate is subjected to wet etching or dry etching.

[0019] As an improvement to the above technical solution, the insulating layer in step 2 is a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite layer formed from at least two of these.

[0020] As an improvement to the above technical solution, the metal film in steps 3 and 5 is aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed from at least two of these metals.

[0021] As an improvement to the above technical solution, the piezoelectric layer in step 4 is a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite piezoelectric film, an organic piezoelectric film, or a doped film formed by at least one of these piezoelectric films and a doping element, or a composite film formed by at least two of these piezoelectric films, or a certain piezoelectric film or composite film with an isolation layer on its surface; the isolation layer is a silicon nitride layer, a silicon dioxide layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite film formed by at least two of these.

[0022] The doping element is vanadium, iron, chromium, manganese, samarium, indium, lanthanum, praseodymium, cobalt, or niobium, but in practical applications it is not limited to these listed elements.

[0023] As an improvement to the above technical solution, the bulk etching mask layer in step 7 is a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, aluminum, gold, or a hard mask composed of a composite layer formed of at least two of these materials, or photoresist, or a composite mask layer composed of a hard mask and photoresist.

[0024] As an improvement to the above technical solution, the polygonal structure is a pentagon, hexagon, heptagon, octagon, nonagon, or decagon. Correspondingly, five, six, seven, eight, nine, or ten gaps are formed in step 6, and five, six, seven, eight, nine, or ten cantilever arms are released in step 8.

[0025] As one of the improvements to the above technical solution, the upper mass block and the lower mass block in step 9 have the same mass, so that the center of gravity of the upper and lower mass blocks as a whole coincides with the center of gravity of the piezoelectric composite cantilever structure.

[0026] As an improvement to the above technical solution, in order to ensure that the center of gravity of the upper and lower mass blocks coincides with the center of gravity of the piezoelectric composite cantilever structure, step 9 specifically includes:

[0027] The MEMS piezoelectric vector hydrophone chip with a dual-mass polygonal structure was modeled using simulation software. Based on the size and position of the lower mass block and the specific polygonal structure, the size and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks coincided with the center of gravity of the piezoelectric composite cantilever structure.

[0028] Fabrication of the upper mass block: A mask is designed based on the optimized size of the upper mass block; a double-sided polished ordinary silicon substrate is used as the substrate, a support layer is deposited, and a thicker photoresist is coated on the surface of the support layer; the other side of the silicon substrate is patterned using a mask, and the bulk silicon is subjected to wet etching or dry etching; the photoresist and support layer are removed to obtain the upper mass block;

[0029] The upper mass block is bonded or pasted onto the optimized position on the piezoelectric composite cantilever structure, so that the position of the upper mass block is symmetrical with that of the lower mass block and the positions are directly opposite each other, and the center of gravity of the upper and lower mass blocks as a whole coincides with the center of gravity of the piezoelectric composite cantilever structure.

[0030] The support layer is made of aluminum, gold, chromium, platinum, titanium, silicon dioxide, silicon nitride, or a composite film formed from at least two of these materials.

[0031] As an improvement to the above technical solution, the method prepares a MEMS piezoelectric vector hydrophone chip with a dual-mass polygonal structure; the center of gravity of the upper and lower mass blocks of the MEMS piezoelectric vector hydrophone chip with the dual-mass polygonal structure coincides with the center of gravity of the piezoelectric composite cantilever structure.

[0032] The beneficial effects of this invention are as follows: The fabrication process provided by this invention produces a MEMS piezoelectric vector hydrophone with a dual-mass polygonal structure exhibiting good directivity and high concave depth. The polygonal structure enables the cascading of multiple piezoelectric layers, improving sensitivity. Modeling and analysis of the shape and placement of the upper mass block ensures that the center of gravity of the fabricated upper and lower mass blocks coincides with the center of gravity of the piezoelectric composite cantilever structure, resulting in unbiased figure-eight directivity in both the xz and yz planes. Furthermore, the directivity performance of the xz and yz planes overlaps well, demonstrating excellent consistency. The fabrication method for the MEMS vector hydrophone provided by this invention exhibits good process stability, strong feasibility, and a high yield. Attached Figure Description

[0033] Figure 1 This is a three-dimensional schematic diagram of a MEMS piezoelectric vector hydrophone with a dual-mass block hexagonal structure on an SOI silicon wafer.

[0034] Figure 2 This is a cross-sectional view of an SOI silicon wafer;

[0035] Figure 3 Is Figure 2 A schematic diagram of the chip cross-section after the deposition of an insulating oxide layer on the surface;

[0036] Figure 4 Is Figure 3 A schematic cross-sectional view of the chip after the piezoelectric unit has been fabricated.

[0037] Figure 5 This is a schematic diagram of the chip cross-section after the deep silicon bulk etching mask layer of the SOI silicon wafer is patterned;

[0038] Figure 6 This is a schematic diagram of the cross-section of an SOI silicon wafer after etching the substrate silicon layer and the SOI buried oxide layer.

[0039] Figure 7 This is a cross-sectional view of the piezoelectric sensor chip after it has been fabricated on an SOI silicon wafer.

[0040] Figure 8 This is a three-dimensional schematic diagram of a MEMS piezoelectric vector hydrophone with a dual-mass block hexagonal structure on a silicon substrate.

[0041] Figure 9 This is a cross-sectional view of a silicon substrate;

[0042] Figure 10 Is Figure 9 A schematic diagram of the chip cross-section after the deposition of an insulating oxide layer on the surface;

[0043] Figure 11 Is Figure 10 A schematic cross-sectional view of the chip after the piezoelectric unit has been fabricated.

[0044] Figure 12 This is a schematic diagram of a chip cross-section after the deep silicon bulk etching mask layer of a silicon substrate is patterned.

[0045] Figure 13 This is a schematic diagram of the chip cross-section after the silicon layer of the substrate has been etched on the silicon substrate.

[0046] Figure 14 This is a cross-sectional view of the piezoelectric sensor chip after it has been fabricated on a silicon substrate.

[0047] Figure 15 This is a three-dimensional schematic diagram of a MEMS piezoelectric vector hydrophone with a dual-mass block pentagonal structure on an SOI silicon wafer.

[0048] Figure 16 This is a three-dimensional schematic diagram of a MEMS piezoelectric vector hydrophone with a dual-mass block octagonal structure on an SOI silicon wafer.

[0049] Attached image labels:

[0050] 1. Device silicon layer 2. SOI buried oxide layer

[0051] 3. Base silicon layer 4. Insulating layer

[0052] 5. Bulk etching mask layer 6. Lower electrode

[0053] 7. Piezoelectric layer 8. Top electrode

[0054] 9. Hole 10. Lower mass block

[0055] 11. Upper mass block 12. Gap Detailed Implementation

[0056] A method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass block polygonal structure includes the following steps:

[0057] 1) Cleaning the silicon substrate

[0058] First, boil the product using acidic and alkaline cleaning solutions respectively, then rinse it with deionized water, and finally dry it with nitrogen gas.

[0059] The silicon substrate can also be a no-wash substrate.

[0060] 2) Deposited insulating layer 4

[0061] An insulating layer 4 is deposited on the surface of a silicon substrate.

[0062] The insulating layer 4 is a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite layer thereof.

[0063] 3) Preparation of lower electrode 6

[0064] A metal film is deposited on the upper surface of the insulating layer 4 using a vacuum evaporation method, and the metal film is patterned using wet etching, dry etching, or lift-off processes to form the lower electrode 6.

[0065] The metal film is aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed from at least two of these metals.

[0066] 4) Fabrication of piezoelectric layer 7

[0067] A piezoelectric film is prepared on the upper surface of the lower electrode 6, and the piezoelectric film is patterned by wet etching, dry etching or lift-off process to form a piezoelectric layer 7.

[0068] The piezoelectric film is a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite piezoelectric film, an organic piezoelectric film, or a doped film thereof, or a composite film formed from at least two of the piezoelectric films, or a piezoelectric film or composite film with an isolation layer on its surface; the isolation layer is composed of a silicon nitride layer, a silicon dioxide layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite film formed from at least two of the piezoelectric films.

[0069] The doping elements include vanadium, iron, chromium, manganese, samarium, indium, lanthanum, praseodymium, cobalt, and niobium.

[0070] 5) Preparation of the upper electrode 8

[0071] A metal film is deposited on the upper surface of the piezoelectric layer 7 using a vacuum evaporation method, and the metal film is patterned using wet etching, dry etching, or lift-off processes to form the upper electrode 8.

[0072] The metal film is aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed from at least two of these metals.

[0073] 6) Etching of gap 12

[0074] Photoresist is coated on the upper surface of the substrate silicon wafer. After exposure and development, the pattern of multiple gaps 12 to be etched is exposed on the photoresist and patterned. The insulating layer 4 and the device silicon layer 1 are etched by dry etching method to form multiple gaps 12, which lays the foundation for the release of multiple piezoelectric composite cantilever beams and lower mass block 10.

[0075] 7) Fabrication and patterning of deep silicon bulk etching mask layer 5

[0076] A bulk etching mask layer 5 is prepared on the back side of the substrate silicon wafer, and the bulk etching mask layer 5 is patterned by wet etching, dry etching or photolithography; the bulk etching mask layer 5 may be a hard mask composed of a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, metallic aluminum, gold or a composite layer formed of at least two of these materials, or a photoresist, or a composite mask layer composed of a hard mask and a photoresist.

[0077] 8) Release of the multi-piezoelectric composite cantilever beam and the lower mass block 10

[0078] Wet etching or dry etching is used to etch or etch the substrate silicon layer 3 and SOI buried oxide layer 2 from the outside to the inside to form holes 9, and multiple piezoelectric composite cantilever beams and lower mass blocks 10 are released.

[0079] The piezoelectric composite cantilever beam includes a silicon layer 1, an insulating layer 4, and a piezoelectric unit;

[0080] The piezoelectric unit includes a lower electrode 6, a piezoelectric layer 7, and an upper electrode 8;

[0081] The base silicon layer 3 in the middle of the hole 9 is the lower mass block 10.

[0082] 9) Formation of the upper mass block 11

[0083] First, a MEMS piezoelectric vector hydrophone chip with a dual-mass polygonal structure was modeled using simulation software. Based on the size and position of the lower mass block and its specific polygonal structure, the size and placement of the upper mass block were analyzed and optimized to ensure that the overall center of gravity of the upper and lower mass blocks coincided with the center of gravity of the piezoelectric composite cantilever structure. Next, the upper mass block was fabricated. A photomask was designed based on the optimized upper mass block size. A double-sided polished ordinary silicon substrate was used as the substrate, a support layer was deposited, and a thick photoresist was coated on the surface of the support layer. The other side of the silicon substrate was patterned using a photomask, and the bulk silicon was etched using wet or dry etching. The photoresist and support layer were removed to obtain the upper mass block. Finally, the upper mass block was bonded or pasted onto the optimized position on the piezoelectric composite cantilever structure, ensuring that the position of the upper mass block is symmetrical to the lower mass block and directly opposite it, with the overall center of gravity of the upper and lower mass blocks coinciding with the center of gravity of the piezoelectric composite cantilever structure.

[0084] The support layer may be aluminum, gold, chromium, platinum, titanium, silicon dioxide, silicon nitride, or a composite film thereof.

[0085] The MEMS piezoelectric vector hydrophone chip can be fabricated using an SOI silicon substrate or a regular silicon substrate as the substrate.

[0086] The SOI silicon substrate includes a device silicon layer 1, an SOI buried oxide layer 2, and a substrate silicon layer 3;

[0087] The ordinary silicon substrate includes a device silicon layer 1 and a substrate silicon layer 3;

[0088] The polygonal structures are pentagonal, hexagonal, heptagonal, octagonal, nonagonal, and decagonal. Correspondingly, the piezoelectric composite cantilever beams are five, six, seven, eight, nine, and ten beams.

[0089] The lower mass block 10 can also be obtained by the same bonding or adhesive process as the upper mass block 11, rather than by etching.

[0090] The upper mass block 11 and the lower mass block 10 have the same mass and can be made of the same or different materials.

[0091] A method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass polygonal structure. The fabricated MEMS piezoelectric vector hydrophone chip includes: an upper mass block 11, a lower mass block 10, a piezoelectric composite cantilever structure, and a polygonal ring support structure. The piezoelectric composite cantilever structure includes an integrated cantilever center and multiple piezoelectric composite cantilever beams. The cantilever center is a polygonal cylinder and is concentric with the polygonal ring support structure. One end of each piezoelectric composite cantilever beam is integrally connected to each side of the cantilever center, and the other end is connected to the inner wall of one side of the polygonal ring support structure. A gap 12 is formed between two adjacent piezoelectric composite cantilever beams and the polygonal ring support structure. A hole 9 is formed between the polygonal ring support structure and the lower mass block 10.

[0092] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0093] The polygonal structures are illustrated using pentagonal, hexagonal, and octagonal structures as examples.

[0094] Example 1

[0095] Embodiment 1 of this invention provides a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass hexagonal structure using an SOI silicon substrate as the silicon substrate. The MEMS piezoelectric vector hydrophone chip includes: an upper mass block 11, a lower mass block 10, a piezoelectric composite cantilever structure, and a hexagonal annular column support structure. The piezoelectric composite cantilever structure includes an integrated cantilever center and six piezoelectric composite cantilever beams. The cantilever center is a hexagonal column and is concentrically hexagonal with the hexagonal annular column support structure. One end of each piezoelectric composite cantilever beam is integrally connected to one side of the cantilever center, and the other end is connected to the inner wall of one side of the hexagonal annular column support structure. A gap 12 is formed between two adjacent piezoelectric composite cantilever beams and the hexagonal annular support structure. A hole 9 is formed between the hexagonal annular support structure and the lower mass block 10.

[0096] The specific steps are as follows:

[0097] 1. Cleaning the silicon substrate:

[0098] The substrate silicon wafer is an SOI silicon wafer, which is first boiled and cleaned using acidic and alkaline cleaning solutions respectively, then cleaned with deionized water, and finally dried with nitrogen gas; the SOI silicon wafer is as follows: Figure 2 The layers shown from top to bottom are: device silicon layer 1, SOI buried oxide layer 2, and substrate silicon layer 3; the thickness of substrate silicon layer 3 is 800 μm; the thickness of SOI buried oxide layer 2 is 3.5 μm; and the thickness of device silicon layer 1 is 50 μm.

[0099] If the SOI silicon substrate is a no-wash substrate, it can be used directly in experiments.

[0100] 2. Deposited insulating layer 4:

[0101] like Figure 3 As shown, a 1μm thick thermally oxidized silicon dioxide layer is deposited on the surface of the substrate silicon wafer as an insulating layer 4.

[0102] 3. Preparation of lower electrode 6

[0103] A 0.1 μm thick aluminum film was deposited on the upper surface of the insulating layer using a vacuum evaporation method, and the aluminum film was patterned using a lift-off process to form the lower electrode 6.

[0104] 4. Fabrication of piezoelectric layer 7

[0105] A 10 μm thick zinc oxide film was prepared on the upper surface of the lower electrode 6, and the zinc oxide film was patterned by dry etching to form a piezoelectric layer.

[0106] 5. Preparation of the upper electrode 8

[0107] A 0.1 μm thick aluminum film is deposited on the upper surface of the piezoelectric layer 7 using a vacuum evaporation method, and the aluminum film is patterned using a lift-off process to form the upper electrode 8.

[0108] A schematic diagram of the chip cross-section after fabrication of the lower electrode, piezoelectric layer, and upper electrode is shown below. Figure 4 As shown.

[0109] 6. Etching of gap 12

[0110] Photoresist is coated on the upper surface of the substrate silicon wafer. After exposure and development, the pattern of six gaps to be etched is exposed on the photoresist and patterned. The insulating layer 4 and the device silicon layer 3 are etched by dry etching method to form six gaps 12, which lays the foundation for the release of six piezoelectric composite cantilever beams and lower mass block 10.

[0111] 7. Fabrication and Patterning of Deep Silicon Bulk Etching Mask Layer 5

[0112] A 10 μm thick silicon dioxide layer is prepared on the back side of the substrate silicon wafer as a bulk etching mask layer 5, and the bulk etching mask layer is patterned by dry etching.

[0113] A schematic diagram of the chip cross-section after patterning the deep silicon bulk etching mask layer 5 is shown below. Figure 5 As shown.

[0114] 8. Release of the piezoelectric composite cantilever beam and lower mass block 10

[0115] Dry etching is used to etch the substrate silicon layer 3 and the SOI buried oxide layer 2 from the outside to the inside to form holes 9, releasing the six piezoelectric composite cantilever beams and the lower mass block 10. Then, dry etching is used to remove the volume etching mask layer 5; the substrate silicon layer 3 in the middle of the holes 9 is the lower mass block 10.

[0116] A schematic diagram of the chip cross-section after etching the substrate silicon layer 3 and SOI buried oxide layer 2 is shown below. Figure 6 As shown.

[0117] 9. Formation of the upper mass block 11

[0118] The dimensions and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks coincided with the center of gravity of the piezoelectric composite cantilever structure. A double-sided polished ordinary silicon substrate was used as the substrate, and a 2μm thick aluminum film was sputtered as the support film. A 20μm thick photoresist was then coated on the surface of the aluminum film. The other side of the silicon substrate was patterned, and the bulk silicon was dry-etched. The photoresist was removed using acetone and ethanol. The aluminum film was removed by wet etching to obtain the upper mass block 11.

[0119] 10. Bond the mass block 11

[0120] The upper mass block 11 is bonded to the optimized position on the upper surface of the piezoelectric composite cantilever structure, ensuring that the upper mass block is symmetrical to the lower mass block and directly aligned with it, thus aligning the center of gravity of the upper and lower mass blocks with the center of gravity of the piezoelectric composite cantilever structure. Subsequently, the silicon wafer is cleaned and dried to complete the fabrication of the sensor chip.

[0121] A cross-sectional schematic diagram of the fabricated piezoelectric sensor chip is shown below. Figure 7 As shown in the figure. A three-dimensional schematic diagram of a MEMS piezoelectric vector hydrophone with a dual-mass hexagonal structure on an SOI silicon wafer is shown below. Figure 1 As shown, the piezoelectric composite cantilever beam, from top to bottom, consists of: upper electrode 8, piezoelectric layer 7, lower electrode 6, insulating layer 4, and device silicon layer 1; the hexagonal ring support structure, from top to bottom, consists of: insulating layer 4, device silicon layer 1, SOI buried oxide layer 2, and substrate silicon layer 3.

[0122] Example 2

[0123] Embodiment 2 of the present invention provides a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass hexagonal structure using a common silicon substrate as the silicon substrate. The MEMS piezoelectric vector hydrophone chip includes: an upper mass block 11, a lower mass block 10, a piezoelectric composite cantilever structure, and a hexagonal annular column support structure. The piezoelectric composite cantilever structure includes an integrated cantilever center and six piezoelectric composite cantilever beams. The cantilever center is a hexagonal column and is concentrically hexagonal with the hexagonal annular column support structure. One end of each piezoelectric composite cantilever beam is integrally connected to one side of the cantilever center, and the other end is connected to the inner wall of one side of the hexagonal annular column support structure. A gap 12 is formed between two adjacent piezoelectric composite cantilever beams and the hexagonal annular support structure. A hole 9 is formed between the hexagonal annular support structure and the lower mass block 10.

[0124] The specific steps are as follows:

[0125] 1. Cleaning the silicon substrate:

[0126] The substrate silicon wafer is a common silicon wafer, which is first boiled and cleaned using acidic and alkaline cleaning solutions respectively, then cleaned with deionized water, and finally dried with nitrogen gas; the common silicon wafer is as follows: Figure 9 The layers shown from top to bottom are: device silicon layer 1, substrate silicon layer 3; the thickness of substrate silicon layer 3 is 800 μm; the thickness of device silicon layer 1 is 50 μm.

[0127] If the SOI silicon substrate is a no-wash substrate, it can be used directly in experiments.

[0128] 2. Deposited insulating layer 4:

[0129] like Figure 10 As shown, a 1μm thick silicon nitride layer is deposited on the surface of the substrate silicon wafer.

[0130] 3. Preparation of lower electrode 6

[0131] A gold / chromium composite film is deposited on the upper surface of the insulating layer using a vacuum evaporation method. The thickness of the gold is 0.5 μm and the thickness of the chromium is 0.1 μm. The gold / chromium composite film is then patterned using dry etching to form the lower electrode 6.

[0132] 4. Fabrication of piezoelectric layer 7

[0133] A 20 μm thick aluminum nitride film was prepared on the upper surface of the lower electrode 6, and the zinc oxide film was patterned using a lift-off process to form a piezoelectric layer 7.

[0134] 5. Preparation of the upper electrode 8

[0135] A gold / chromium composite film is deposited on the upper surface of the piezoelectric layer 7 using a vacuum evaporation method. The thickness of the gold is 0.5 μm and the thickness of the chromium is 0.1 μm. The gold / chromium composite film is then patterned using dry etching to form the upper electrode 8.

[0136] A schematic diagram of the chip cross-section after fabrication of the lower electrode, piezoelectric layer, and upper electrode is shown below. Figure 11 As shown.

[0137] 6. Etching of gap 12

[0138] Photoresist is coated on the upper surface of the substrate silicon wafer. After exposure and development, the pattern of six gaps to be etched is exposed on the photoresist and patterned. The insulating layer 4 and the device silicon layer 3 are etched by dry etching method to form six gaps, laying the foundation for the release of six piezoelectric composite cantilever beams and lower mass block 10.

[0139] 7. Fabrication and Patterning of Deep Silicon Bulk Etching Mask Layer 5

[0140] A 2μm thick silicon nitride layer is prepared on the back side of the substrate silicon wafer as a bulk etching mask layer 5, and the bulk etching mask layer is patterned by wet etching.

[0141] A schematic diagram of the chip cross-section after patterning the deep silicon bulk etching mask layer 5 is shown below. Figure 12 As shown.

[0142] 8. Release of the multi-piezoelectric composite cantilever beam and lower mass block 10

[0143] Wet etching is used to etch the substrate silicon layer 3 from the outside in to form holes 9, releasing six piezoelectric composite cantilever beams and a lower mass block 10. Then, dry etching is used to remove the volume etching mask layer 5; the substrate silicon layer 3 in the middle of the holes 9 is the lower mass block 10.

[0144] A schematic diagram of the chip cross-section after etching the substrate silicon layer 3 is shown below. Figure 13 As shown.

[0145] 9. Formation of the upper mass block 11

[0146] The dimensions and placement of the upper mass block were analyzed and optimized to ensure that the overall center of gravity of the upper and lower mass blocks coincided with the center of gravity of the piezoelectric composite cantilever structure. A double-sided polished ordinary silicon substrate was used as the substrate, and a 2μm thick silicon dioxide film was sputtered as a support film. A 20μm thick photoresist was then coated on the surface of the silicon dioxide film. The other side of the silicon substrate was patterned, and the bulk silicon was dry etched. The photoresist was removed using acetone and ethanol. The silicon dioxide film was then removed by dry etching to obtain the upper mass block 11.

[0147] 10. Bond the mass block 11

[0148] The upper mass block 11 is bonded to the optimized position on the upper surface of the piezoelectric composite cantilever structure, ensuring that the upper mass block is symmetrical to the lower mass block and directly aligned with it, thus aligning the center of gravity of the upper and lower mass blocks with the center of gravity of the piezoelectric composite cantilever structure. Subsequently, the silicon wafer is cleaned and dried to complete the fabrication of the sensor chip.

[0149] A cross-sectional schematic diagram of the fabricated piezoelectric sensor chip is shown below. Figure 14 As shown in the figure. A three-dimensional schematic diagram of a MEMS piezoelectric vector hydrophone with a silicon substrate dual-mass hexagonal structure is shown in the figure. Figure 8 As shown, the piezoelectric composite cantilever beam, from top to bottom, consists of: upper electrode 8, piezoelectric layer 7, lower electrode 6, insulating layer 4, and device silicon layer 1; the hexagonal ring support structure, from top to bottom, consists of: insulating layer 4, device silicon layer 1, and substrate silicon layer 3.

[0150] Example 3

[0151] Embodiment 3 of the present invention provides a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass block pentagonal structure using an SOI silicon substrate as the substrate. The MEMS piezoelectric vector hydrophone chip includes: an upper mass block 11, a lower mass block 10, a piezoelectric composite cantilever structure, and a pentagonal annular column support structure. The piezoelectric composite cantilever structure includes an integrated cantilever center and five piezoelectric composite cantilever beams. The cantilever center is a pentagonal column and is concentric with the pentagonal annular column support structure. One end of each piezoelectric composite cantilever beam is integrally connected to one side of the cantilever center, and the other end is connected to the inner wall of one side of the pentagonal annular column support structure. A gap 12 is formed between two adjacent piezoelectric composite cantilever beams and the pentagonal annular support structure. A hole 9 is formed between the pentagonal annular support structure and the lower mass block 10.

[0152] The specific steps are as follows:

[0153] 1. Cleaning the silicon substrate:

[0154] The substrate silicon wafer is an SOI silicon wafer, which is first boiled and cleaned using acidic and alkaline cleaning solutions respectively, then cleaned with deionized water, and finally dried with nitrogen gas; the SOI silicon wafer is as follows: Figure 2 The layers shown from top to bottom are: device silicon layer 1, SOI buried oxide layer 2, and substrate silicon layer 3; the thickness of substrate silicon layer 3 is 900 μm; the thickness of SOI buried oxide layer 2 is 4 μm; and the thickness of device silicon layer 1 is 60 μm.

[0155] If the SOI silicon substrate is a no-wash substrate, it can be used directly in experiments.

[0156] 2. Deposited insulating layer 4:

[0157] like Figure 3 As shown, a 1.5 μm thick polycrystalline silicon layer is deposited on the surface of the substrate silicon wafer as an insulating layer 4.

[0158] 3. Preparation of lower electrode 6

[0159] A 0.1 μm thick molybdenum film was deposited on the upper surface of the insulating layer using a vacuum evaporation method, and the molybdenum film was patterned using a lift-off process to form the lower electrode 6.

[0160] 4. Fabrication of piezoelectric layer 7

[0161] A 10 μm thick lead zirconate titanate piezoelectric film was prepared on the upper surface of the lower electrode 6, and the lead zirconate titanate piezoelectric film was patterned by wet etching to form a piezoelectric layer.

[0162] 5. Preparation of the upper electrode 8

[0163] A 0.1 μm thick molybdenum film is deposited on the upper surface of the piezoelectric layer 7 using a vacuum evaporation method, and the molybdenum film is patterned using a lift-off process to form the upper electrode 8.

[0164] 6. Etching of gap 12

[0165] Photoresist is coated on the upper surface of the substrate silicon wafer. After exposure and development, the pattern of five gaps to be etched is exposed on the photoresist and patterned. The insulating layer 4 and the device silicon layer 3 are etched by dry etching method to form five gaps 12, which lays the foundation for the release of five piezoelectric composite cantilever beams and lower mass block 10.

[0166] 7. Fabrication and Patterning of Deep Silicon Bulk Etching Mask Layer 5

[0167] A 10 μm thick polycrystalline silicon layer is prepared on the back side of the substrate silicon wafer as a bulk etching mask layer 5, and the bulk etching mask layer is patterned by wet etching.

[0168] 8. Release of the piezoelectric composite cantilever beam and lower mass block 10

[0169] Wet etching is used to etch the substrate silicon layer 3 and the SOI buried oxide layer 2 from the outside to the inside to form holes 9, releasing the five piezoelectric composite cantilever beams and the lower mass block 10. Then, wet etching is used to remove the bulk etching mask layer 5; the substrate silicon layer 3 in the middle of the holes 9 is the lower mass block 10.

[0170] 9. Formation of the upper mass block 11

[0171] The dimensions and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks coincided with the center of gravity of the piezoelectric composite cantilever structure. A double-sided polished ordinary silicon substrate was used as the substrate, and a 2μm thick platinum and titanium film were sputtered as a composite support film. A 40μm thick photoresist was coated on the surface of the platinum / titanium composite film. The other side of the silicon substrate was patterned, and the bulk silicon was wet-etched. The photoresist was removed using acetone and ethanol. The platinum / titanium composite film was removed by wet etching to obtain the upper mass block 11.

[0172] 10. Attach the mass block 11

[0173] The upper mass block 11 is attached to the optimized position on the upper surface of the piezoelectric composite cantilever structure, ensuring that the upper mass block is symmetrical to the lower mass block and directly aligned with it, so that the center of gravity of the upper and lower mass blocks coincides with the center of gravity of the piezoelectric composite cantilever structure. Subsequently, the silicon wafer is cleaned and dried to complete the fabrication of the sensor chip.

[0174] A three-dimensional schematic diagram of the fabricated piezoelectric sensor chip is shown below. Figure 15 As shown, the piezoelectric composite cantilever beam, from top to bottom, consists of: upper electrode 8, piezoelectric layer 7, lower electrode 6, insulating layer 4, and device silicon layer 1; the pentagonal ring support structure, from top to bottom, consists of: insulating layer 4, device silicon layer 1, SOI buried oxide layer 2, and substrate silicon layer 3.

[0175] Example 4

[0176] Embodiment 4 of the present invention provides a method for fabricating a MEMS piezoelectric vector hydrophone chip with a dual-mass block octagonal structure using an SOI silicon substrate as the substrate silicon substrate. The MEMS piezoelectric vector hydrophone chip includes: an upper mass block 11, a lower mass block 10, a piezoelectric composite cantilever structure, and an octagonal annular column support structure. The piezoelectric composite cantilever structure includes an integrated cantilever center and eight piezoelectric composite cantilever beams. The cantilever center is an octagonal column and is concentric with the octagonal annular column support structure. One end of each piezoelectric composite cantilever beam is integrally connected to one side of the cantilever center, and the other end is connected to the inner wall of one side of the octagonal annular column support structure. A gap 12 is formed between two adjacent piezoelectric composite cantilever beams and the octagonal annular support structure. A hole 9 is formed between the octagonal annular support structure and the lower mass block 10.

[0177] The specific steps are as follows:

[0178] 1. Cleaning the silicon substrate:

[0179] The substrate silicon wafer is an SOI silicon wafer, which is first boiled and cleaned using acidic and alkaline cleaning solutions respectively, then cleaned with deionized water, and finally dried with nitrogen gas; the SOI silicon wafer is as follows: Figure 2The layers shown from top to bottom are: device silicon layer 1, SOI buried oxide layer 2, and substrate silicon layer 3; the thickness of substrate silicon layer 3 is 850 μm; the thickness of SOI buried oxide layer 2 is 3 μm; and the thickness of device silicon layer 1 is 50 μm.

[0180] If the SOI silicon substrate is a no-wash substrate, it can be used directly in experiments.

[0181] 2. Deposited insulating layer 4:

[0182] like Figure 3 As shown, a 3μm thick phosphosilicate glass layer is deposited on the surface of the silicon substrate as an insulating layer 4.

[0183] 3. Preparation of lower electrode 6

[0184] A platinum / titanium composite layer with a thickness of 0.5 μm and a titanium thickness of 0.1 μm is deposited on the upper surface of the insulating layer using a vacuum evaporation method. The platinum / titanium composite layer is then patterned using a dry etching process to form the lower electrode 6.

[0185] 4. Fabrication of piezoelectric layer 7

[0186] A 10 μm thick PMN-PT piezoelectric film was prepared on the upper surface of the lower electrode 6, and the PMN-PT piezoelectric film was patterned by dry etching to form a piezoelectric layer.

[0187] 5. Preparation of the upper electrode 8

[0188] A platinum / titanium composite layer is deposited on the upper surface of the piezoelectric layer 7 using a vacuum evaporation method. The thickness of the platinum is 0.5 μm and the thickness of the titanium is 0.1 μm. The platinum / titanium composite layer is then patterned using a dry etching process to form the upper electrode 8.

[0189] A schematic diagram of the chip cross-section after fabrication of the lower electrode, piezoelectric layer, and upper electrode is shown below. Figure 4 As shown.

[0190] 6. Etching of gap 12

[0191] Photoresist is coated on the upper surface of the substrate silicon wafer. After exposure and development, the pattern of eight gaps to be etched is exposed on the photoresist and patterned. The insulating layer 4 and the device silicon layer 3 are etched by dry etching method to form eight gaps 12, which lays the foundation for the release of eight piezoelectric composite cantilever beams and lower mass block 10.

[0192] 7. Fabrication and Patterning of Deep Silicon Bulk Etching Mask Layer 5

[0193] A 12 μm thick phosphosilicate glass layer is prepared on the back side of the substrate silicon wafer as a bulk etching mask layer 5, and the bulk etching mask layer is patterned by dry etching.

[0194] A schematic diagram of the chip cross-section after patterning the deep silicon bulk etching mask layer 5 is shown below. Figure 5 As shown.

[0195] 8. Release of the piezoelectric composite cantilever beam and lower mass block 10

[0196] Dry etching is used to etch the substrate silicon layer 3 and the SOI buried oxide layer 2 from the outside to the inside to form holes 9, releasing the eight piezoelectric composite cantilever beams and the lower mass block 10. Then, dry etching is used to remove the volume etching mask layer 5; the substrate silicon layer 3 in the middle of the holes 9 is the lower mass block 10.

[0197] A schematic diagram of the chip cross-section after etching the substrate silicon layer 3 and SOI buried oxide layer 2 is shown below. Figure 6 As shown.

[0198] 9. Formation of the upper mass block 11

[0199] The dimensions and placement of the upper mass block were analyzed and optimized to ensure that the center of gravity of the upper and lower mass blocks coincided with the center of gravity of the piezoelectric composite cantilever structure. A double-sided polished ordinary silicon substrate was used as the substrate, and a 2μm thick platinum and titanium film were sputtered as a composite support film. A 40μm thick photoresist was coated on the surface of the platinum / titanium composite film. The other side of the silicon substrate was patterned, and the bulk silicon was dry etched. The photoresist was removed using acetone and ethanol. The platinum / titanium composite film was removed by dry etching to obtain the upper mass block 11.

[0200] 10. Attach the mass block 11

[0201] The upper mass block 11 is attached to the optimized position on the upper surface of the piezoelectric composite cantilever structure, ensuring that the upper mass block is symmetrical to the lower mass block and directly aligned with it, so that the center of gravity of the upper and lower mass blocks coincides with the center of gravity of the piezoelectric composite cantilever structure. Subsequently, the silicon wafer is cleaned and dried to complete the fabrication of the sensor chip.

[0202] A cross-sectional schematic diagram of the fabricated piezoelectric sensor chip is shown below. Figure 7 As shown in the figure. A three-dimensional schematic diagram of a MEMS piezoelectric vector hydrophone with an SOI silicon wafer dual-mass block octagonal structure is shown in the figure. Figure 16 As shown, the piezoelectric composite cantilever beam, from top to bottom, consists of: upper electrode 8, piezoelectric layer 7, lower electrode 6, insulating layer 4, and device silicon layer 1; the octagonal ring support structure, from top to bottom, consists of: insulating layer 4, device silicon layer 1, SOI buried oxide layer 2, and substrate silicon layer 3.

[0203] It should be noted that:

[0204] The insulating layer 4 may be a thermally oxidized silicon dioxide layer, a low-temperature silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite layer formed from at least two of these; the thickness of the insulating layer 4 is 0.01 to 100 μm.

[0205] The upper and lower electrodes can be aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed from at least two of these metals; the materials of the lower and upper electrodes can be the same or different, and the electrode thickness is 0.01 to 100 μm.

[0206] The piezoelectric layer 7 may be a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite piezoelectric film, an organic piezoelectric film, or a doped film formed by at least one of these piezoelectric films and a doping element, or a composite film formed by at least two of these piezoelectric films, or a certain piezoelectric film or composite film with an isolation layer disposed on its surface; the isolation layer may be a silicon nitride layer, a silicon dioxide layer, a polycrystalline silicon layer, a phosphosilicate glass layer, or a composite film formed by at least two of these; the thickness of the piezoelectric layer is 0.01–600 μm.

[0207] The bulk etching mask layer 5 may be a hard mask composed of a silicon dioxide layer, a silicon nitride layer, a polycrystalline silicon layer, a phosphosilicate glass layer, metallic aluminum, gold, or a composite layer formed of at least two of these materials, or a photoresist, or a composite mask layer composed of a hard mask and a photoresist; the thickness of the hard mask is 0.01μm to 100μm, and the thickness of the photoresist is 0.01μm to 100μm.

[0208] The MEMS piezoelectric vector hydrophone chip can be fabricated using an SOI silicon substrate or a regular silicon substrate as the substrate.

[0209] The SOI silicon substrate includes a device silicon layer 1, an SOI buried oxide layer 2, and a substrate silicon layer 3;

[0210] The ordinary silicon substrate includes a device silicon layer 1 and a substrate silicon layer 3; the thickness of the device silicon layer 1 and the substrate silicon layer 3 is 10 to 5000 μm; the thickness of the SOI buried oxide layer 2 is 0.01 to 100 μm.

[0211] The polygonal structures are pentagonal, hexagonal, heptagonal, octagonal, nonagonal, and decagonal; correspondingly, the piezoelectric composite cantilever beams are five, six, seven, eight, nine, and ten in number.

[0212] The lower mass block can also be obtained through the same bonding or adhesive process as the upper mass block, rather than through etching; the upper and lower mass blocks have the same mass and can be made of the same or different materials.

[0213] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for preparing a MEMS piezoelectric vector hydrophone chip with a double mass polygonal structure, the method comprising the following steps: Step 1. Preparing a substrate silicon wafer; Step 2. Depositing an insulating layer (4) on the surface of the substrate silicon wafer; Step 3. Depositing a metal film on the upper surface of the insulating layer (4) and patterning the metal film to form a lower electrode (6); Step 4. Preparing a piezoelectric film layer on the upper surface of the lower electrode (6) and patterning the piezoelectric film layer to form a piezoelectric layer (7); Step 5. Depositing a metal film on the upper surface of the piezoelectric layer (7) and patterning the metal film to form an upper electrode (8); Step 6. Coating photoresist on the upper surface of the substrate silicon wafer and exposing a pattern of multiple slits (12) to be etched on the photoresist and patterning, respectively wet etching or dry etching the insulating layer (4) and the device silicon layer (1) to form multiple slits (12) to prepare for the release of multiple cantilevers and a lower mass (10); Step 7. Preparing a bulk etching mask layer (5) on the back of the substrate silicon wafer and patterning the bulk etching mask layer (5); Step 8. Wet etching or dry etching the bottom of the substrate silicon wafer to form a hole (9) and release multiple cantilevers and a lower mass (10); the substrate silicon layer (3) in the middle of the hole (9) is the lower mass (10); Step 9. Bonding or bonding an upper mass (11) on the upper surface of the piezoelectric composite cantilever structure, and the upper mass (11) and the lower mass (10) are located at the same position on the upper and lower surfaces of the piezoelectric composite cantilever structure; the upper mass (11) and the lower mass (10) have the same mass, so that the center of gravity of the upper and lower masses coincides with the center of gravity of the piezoelectric composite cantilever structure; The upper mass (11) is prepared by etching, bonding or bonding.

2. The method of claim 1, wherein the method further comprises: The substrate wafer in step 1 is an SOI wafer or a common silicon wafer; the SOI wafer comprises a device silicon layer (1), an SOI buried oxygen layer (2) and a substrate silicon layer (3) stacked from top to bottom; the common silicon wafer comprises a device silicon layer (1) and a substrate silicon layer (3) stacked from top to bottom; When the SOI wafer is used as the substrate wafer, the substrate silicon layer (3) and the SOI buried oxygen layer (2) of the SOI wafer are etched from the outside to the inside in step 8; When the common silicon wafer is used as the substrate wafer, the substrate silicon layer (3) of the common silicon wafer is etched in step 8.

3. The method of claim 1, wherein the method further comprises: The insulating layer (4) in step 2 is a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a phosphosilicate glass layer or a composite layer formed by at least two of them.

4. The method of claim 1, wherein the method further comprises: The metal film in steps 3 and 5 is aluminum, molybdenum, gold, chromium, platinum, titanium, or a composite film formed by at least two of them.

5. The method of claim 1, wherein the method further comprises: The piezoelectric layer (7) in step 4 is a zinc oxide piezoelectric film, an aluminum nitride piezoelectric film, a lead zirconate titanate piezoelectric film, a PMN-PT piezoelectric film, a perovskite piezoelectric film, an organic piezoelectric film, or a doped film formed by at least one of the piezoelectric films and a doping element, or a composite film formed by at least two of the piezoelectric films, or a certain piezoelectric film or composite film provided with an isolation layer on the surface; the isolation layer is a silicon nitride layer, a silicon dioxide layer, a polysilicon layer, a phosphosilicate glass layer, or a composite film formed by at least two of them.

6. The method of claim 1, wherein the method further comprises: The body etching mask layer (5) in step 7 is a hard mask composed of a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a phosphosilicate glass layer, aluminum, gold, or a composite layer formed by at least two of them, or a photoresist, or a composite mask layer composed of a hard mask and a photoresist.

7. The method of claim 1, wherein the method further comprises: The polygonal structure is a pentagon, a hexagon, a heptagon, an octagon, a nonagon, or a decagon, corresponding to five, six, seven, eight, nine, or ten slits (12) formed in step 6, respectively, and five, six, seven, eight, nine, or ten cantilevers released in step 8, respectively.

8. The method of claim 1, wherein the method further comprises: The step 9 specifically includes: Modeling the MEMS piezoelectric vector hydrophone chip with a double mass polygonal structure by simulation software, analyzing and optimizing the size and placement of the upper mass according to the size and position of the lower mass and the specific polygonal structure, to ensure that the center of gravity of the upper and lower masses coincides with the center of gravity of the piezoelectric composite cantilever structure; Preparation of the upper mass: design a mask according to the optimized size of the upper mass; use a double-polished ordinary silicon substrate as the substrate, deposit a support layer, and coat a thick photoresist on the surface of the support layer; use the mask to pattern the other side of the silicon substrate, and perform wet etching or dry etching on the bulk silicon; remove the photoresist and the support layer to obtain the upper mass; Bonding or pasting the upper mass on the optimized position of the piezoelectric composite cantilever structure, so that the upper mass position is symmetrical with the lower mass, and the position is directly opposite, and the center of gravity of the upper and lower masses coincides with the center of gravity of the piezoelectric composite cantilever structure; The support layer is aluminum, gold, chromium, platinum, titanium, silicon dioxide, silicon nitride, or a composite film formed by at least two of them.

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