Reference voltage source circuit and chip

Abstract

The present invention discloses a reference voltage source circuit and chip, comprising a bias current generating circuit for providing a bias current; a reference voltage generating circuit for generating a reference voltage with a zero temperature coefficient according to the bias current; and a reference voltage output circuit for generating a reference voltage according to the reference voltage, wherein the reference voltage source circuit also comprises a feedback path connected between the bias current generating circuit and the reference voltage output circuit, the feedback path being used to feed back the reference voltage to the bias current generating circuit, so that the bias current generating circuit generates the bias current according to the reference voltage, thereby being able to output a reference voltage with low temperature drift and low offset.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a reference voltage source circuit and a chip. Background Art

[0002] Reference voltage source circuits are widely used in integrated circuits and system-level chips. They are generally used to generate a reference voltage inside the chip that is less affected by temperature and is used as a reference voltage for other analog circuit units.

[0003] Figure 1 FIG. 4 shows a schematic diagram of a reference voltage source circuit according to the prior art. Figure 1 As shown, the reference voltage source circuit 100 includes transistors M1 and M2, an error amplifier OP, transistors Q1 and Q2, and resistors R0 and R1, wherein the transistors Q1 and Q2 are bipolar junction transistors (BJT), and the error amplifier OP is used to clamp the base-emitter voltage V of the transistors Q1 and Q2. BE , which mainly uses the base-emitter voltage V of the transistor BE Inversely proportional to the temperature, the base-emitter voltage difference ΔV between transistors Q1 and Q2 BE =V BE1 -V BE2 The characteristic is proportional to the temperature. BE With ΔV BE The reference voltage Vr1 with zero temperature coefficient is obtained by superimposing them in a certain proportional relationship.

[0004] Figure 2 FIG. 4 shows a schematic diagram of the structure of an error amplifier according to the prior art. Figure 2 As shown, the error amplifier OP includes PMOS transistors M3 and M4 and NMOS transistors M5 and M6. An offset voltage is generated between the positive and negative input terminals of the error amplifier OP, that is, between the control terminals VP and VN of the transistors M5 and M6. The offset voltage is amplified and superimposed on the reference voltage Vr1, making it difficult to reduce the offset voltage Vosr of the reference voltage Vr1, resulting in a large deviation of the reference voltage Vr1 between different wafers and between chips.

[0005] Specifically, the equivalent offset voltage Vos between the positive and negative input terminals of the error amplifier OP is:

[0006]

[0007] Among them, gmp and gmn are the transconductances of the PMOS tube and the NMOS tube respectively. Assuming that they are approximately equal, the equivalent offset voltage Vos is:

[0008] Vos≈Vosp+Vosn

[0009] When the reference voltage Vr1 is not superimposed with the equivalent offset voltage Vos, the expression of the reference voltage Vr1 is:

[0010]

[0011] After adding the equivalent offset voltage Vos, the expression of the final output reference voltage Vr1 is:

[0012]

[0013] Ignoring other reasons for offset, the offset voltage Vosr generated by the reference voltage Vr1 affected by the error amplifier OP is:

[0014]

[0015] The value of R1 / R0 is determined by the zero temperature coefficient of the reference voltage Vr1. In practical applications, transistors Q1 and Q2 are not separate transistors, but are generally formed by connecting multiple transistors in parallel. In the prior art, the ratio of the number of transistors Q1 to Q2 is mostly 1:8. When the ratio of the number of transistors Q1 to Q2 is 1:8, the value of R1 / R0 is usually between 50 and 70, which makes the offset voltage Vosr of the reference voltage Vr1 higher.

[0016] Therefore, a new reference voltage source circuit is needed to solve the above problems. Summary of the invention

[0017] In view of the above problems, an object of the present invention is to provide a reference voltage source circuit and chip, so as to output a reference voltage with low temperature drift and low offset.

[0018] According to one aspect of the present invention, there is provided a reference voltage source circuit, comprising a bias current generating circuit for providing a bias current; a reference voltage generating circuit for generating a reference voltage with a zero temperature coefficient according to the bias current; and a reference voltage output circuit for generating a reference voltage according to the reference voltage, wherein the reference voltage source circuit further comprises a feedback path connected between the bias current generating circuit and the reference voltage output circuit, the feedback path being used to feed back the reference voltage to the bias current generating circuit, so that the bias current generating circuit generates the bias current according to the reference voltage.

[0019] Optionally, the bias current generating circuit includes a first error amplifier, a negative input terminal connected to the reference voltage, and a positive input terminal connected to a first node voltage; a first transistor and a first resistor connected in sequence between a power supply and a ground terminal, a control terminal of the first transistor connected to an output terminal of the first error amplifier, wherein a drain terminal of the first transistor outputs the bias current, and the first node voltage is a common node voltage of the first transistor and the first resistor.

[0020] Optionally, the reference voltage generating circuit includes: a second transistor, a third transistor and a second resistor connected in sequence between a power supply and a ground terminal, the control terminal of the second transistor is connected to the control terminal of the first transistor, and the first terminal and the control terminal of the third transistor are connected, wherein the second transistor is used to replicate the bias current, and the third transistor is used to generate the reference voltage according to the bias current.

[0021] Optionally, the reference voltage output circuit includes: a second error amplifier, a negative input terminal connected to the reference voltage, and a positive input terminal connected to a second node voltage; a fourth transistor, a third resistor, a fourth resistor and a fifth resistor connected in sequence between a power supply and a ground terminal, the control terminal of the fourth transistor being connected to the output terminal of the second error amplifier, wherein a common node between the third resistor and the fourth resistor is used to output the reference voltage, and the second node voltage is a common node voltage between the fourth resistor and the fifth resistor.

[0022] Optionally, the resistance of the fourth resistor is adjustable, and the voltage value change of the reference voltage is achieved by adjusting the resistance of the fourth resistor.

[0023] Optionally, the third transistor is an NMOS transistor, and the first transistor, the second transistor and the fourth transistor are PMOS transistors.

[0024] Optionally, the reference voltage source circuit further includes a startup circuit for controlling the reference voltage to operate at a correct DC operating point.

[0025] Optionally, the bias current Wherein, μ is the carrier mobility of the third transistor, C ox is the gate oxide capacitance density of the third transistor, V TH is the threshold voltage of the third transistor, W is the channel width of the third transistor, and L is the channel length of the third transistor.

[0026] Optionally, the reference voltage is obtained by multiplying the temperature coefficient of the carrier mobility by a negative coefficient and superimposing it with the temperature coefficient of the threshold voltage, and the negative coefficient is obtained by adjusting The value of is realized, wherein Ibias is the bias current, W is the channel width of the third transistor, and L is the channel length of the third transistor.

[0027] According to another aspect of the present invention, a chip is provided, comprising the reference voltage source circuit described above.

[0028] The reference voltage source circuit and chip provided by the present invention utilize the characteristics that the carrier mobility and threshold voltage of the MOS tube are inversely proportional to the temperature, multiply the temperature coefficient of the carrier mobility by a negative coefficient and then superimpose it with the temperature coefficient of the threshold voltage, offset the negative temperature coefficient of the threshold voltage, and obtain a reference voltage with a zero temperature coefficient, thereby ensuring the low temperature drift characteristic of the output reference voltage. At the same time, the reference voltage generation circuit can generate the reference voltage without the need for an error amplifier, so that the reference voltage will not be detuned by the influence of the error amplifier, thereby ensuring the low offset characteristic of the output reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0030] Figure 1 A schematic diagram of the structure of a reference voltage source circuit according to the prior art is shown;

[0031] Figure 2 A schematic diagram of the structure of an error amplifier according to the prior art is shown;

[0032] Figure 3 A schematic diagram of the structure of a reference voltage source circuit according to an embodiment of the present invention is shown;

[0033] Figure 4 A circuit connection diagram of a reference voltage source circuit according to an embodiment of the present invention is shown;

[0034] Figure 5 A schematic diagram of offset voltage generation of a reference voltage source according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0035] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0036] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0037] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0038] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0039] In the present application, a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first end, a second end and a control end. When the MOS tube is in the on state, current flows from the first end to the second end. The first end, the second end and the control end of a PMOS tube are the source, the drain and the gate, respectively, and the first end, the second end and the control end of an NMOS tube are the drain, the source and the gate, respectively.

[0040] Figure 3 FIG. 4 shows a schematic diagram of a reference voltage source circuit according to an embodiment of the present invention. Figure 3 As shown, the reference voltage source circuit 200 includes a bias current generating circuit 210 , a reference voltage generating circuit 220 and a reference voltage output circuit 230 .

[0041] The bias current generating circuit 210 is used to provide a bias current Ibias, the reference voltage generating circuit 220 is used to generate a reference voltage Vr2 with a zero temperature coefficient according to the bias current Ibias, and the reference voltage output circuit 230 is used to generate a reference voltage Vo according to the reference voltage Vr2.

[0042] The reference voltage source circuit 200 further includes a feedback path connected between the bias current generating circuit 210 and the reference voltage output circuit 230, wherein the feedback path is used to feed back the reference voltage Vo to the bias current generating circuit 210, so that the bias current generating circuit 210 generates a bias current Ibias according to the reference voltage Vo.

[0043] Figure 4 FIG. 4 shows a circuit connection diagram of a reference voltage source circuit according to an embodiment of the present invention, as shown in FIG. Figure 4 As shown, the bias current generating circuit 210 includes an error amplifier OPA and a transistor MP1 and a resistor R0 connected in sequence between a power supply VDD and a ground terminal. The positive input terminal of the error amplifier OPA is connected to a reference voltage Vo, the negative input terminal is connected to a node A, and the output terminal is connected to a control terminal of the transistor MP1. The error amplifier OPA is used to control the drain current of the transistor MP1, i.e., the bias current Ibias, according to the error value between the reference voltage Vo and the node voltage Va of the node A, so that the node voltage Va is equal to the reference voltage Vo, wherein the node A is a common node of the transistor MP1 and the resistor R0, and the expression of the bias current Ibias is:

[0044]

[0045] The reference voltage generating circuit 220 includes a transistor MP2, a transistor MN1 and a resistor Rs which are sequentially connected between a power supply VDD and a ground terminal. The control terminal of the transistor MP2 is connected to the output terminal of the error amplifier OPA, wherein the drain current of the transistor MP2 is equal to the bias current Ibias. The first terminal of the transistor MN1 is connected to the control terminal to generate a reference voltage Vr2. The reference voltage Vr2 is output from a common node of the transistor MP2 and the transistor MN1. The transistor MP2 and the transistor MN1 both work in a saturation region. The expression of the bias current Ibias can also be:

[0046]

[0047] From this, the expression of reference voltage Vr2 is:

[0048] in,

[0049] The two sides of equation (3) are differentiated with respect to temperature T to obtain:

[0050]

[0051] Where, μ is the carrier mobility of transistor MN1, C ox is the gate oxide capacitance density of transistor MN1, V TH is the threshold voltage of transistor MN1, which are all process parameters and have nothing to do with the circuit structure. W is the channel width of transistor MN1, and L is the channel length of transistor MN1.

[0052] In CMOS technology, carrier mobility μ and threshold voltage V TH are inversely proportional to temperature, and their temperature coefficients are all negative. According to formula (4), the temperature coefficient of carrier mobility μ is multiplied by a negative coefficient and then multiplied by the threshold voltage V TH The temperature coefficient of the threshold voltage V TH The negative temperature coefficient of the reference voltage Vr2 is offset to obtain a zero temperature coefficient, wherein the negative coefficient is adjusted by The value of is realized.

[0053] The reference voltage output circuit 230 includes an error amplifier OPB and a transistor MP3, a resistor R3, a resistor R2 and a resistor R1 connected in sequence between a power supply VDD and a ground terminal. The negative input terminal of the error amplifier OPB is connected to the reference voltage Vr2, the positive input terminal is connected to the node B, and the output terminal is connected to the control terminal of the transistor MP3. The common node of the resistor R3 and the resistor R2 is used to output the reference voltage Vo. The error amplifier OPB is used to control the voltage drop of the transistor MP3 according to the error value between the reference voltage Vr2 and the node voltage Vb of the node B so that the node voltage Vb is equal to the reference voltage Vr2, wherein the node B is the common node of the resistor R2 and the resistor R1, and the expression of the reference voltage Vo is:

[0054]

[0055] Although the reference voltage generating circuit 220 in the reference voltage source circuit 200 provided by the present invention does not have an error amplifier OP, so that the reference voltage Vo provided by the present invention does not have an offset caused by the error amplifier OP, the circuit still has an offset voltage.

[0056] Figure 5 FIG. 4 shows a schematic diagram of generating an offset voltage of a reference voltage source according to an embodiment of the present invention. Figure 5 As shown, the offset voltage Vos1 of the reference voltage source circuit 200 is mainly composed of the offset voltage Vosp at the control end of the transistor MP2 multiplied by a certain coefficient and then added to the reference voltage Vo, and the offset voltage Vosn at the control end of the transistor MN1 is directly added to the reference voltage Vo. The expression is:

[0057]

[0058] Among them, gmp and gmn are the transconductances of transistor MP2 and transistor MN1 respectively. In order to facilitate comparison with the prior art, it is also assumed that they are approximately equal, then

[0059] Vos1=Vosp+Vosn(7),

[0060] By combining equation (7) with the offset voltage Vosr of the reference voltage Vr1 in the prior art, By comparison, it can be seen that the offset voltage Vos1 of the reference voltage Vo provided by the present invention is much smaller than the offset voltage Vosr of the reference voltage Vr1 in the prior art. Therefore, the reference voltage source circuit 200 provided by the present invention can effectively improve the offset voltage Vos1 of the output reference voltage Vo, thereby reducing the deviation of the reference voltage Vo between different wafers and between chips.

[0061] Furthermore, the resistor R2 in the reference voltage output circuit 230 is a selectable or variable resistor, and the voltage value of the reference voltage Vo can be changed by changing the resistance value of the resistor R2 to meet the requirements of different circuits for the reference voltage Vo.

[0062] Furthermore, the transistor MP1 , the transistor MP2 , and the transistor MP3 are all PMOS transistors, and the transistor MN1 is an NMOS transistor.

[0063] Furthermore, there is a positive feedback path of reference voltage Vr2 -reference voltage Vo-reference voltage Vr2 in the reference voltage source circuit 200 , and the positive feedback loop gain of the positive feedback path needs to be lower than 0 dB.

[0064] Furthermore, the reference voltage source circuit 200 further includes a startup circuit, which is used to ensure that the reference voltage Vr2 operates at a correct DC operating point. The startup circuit may be, for example, a timing control circuit.

[0065] The reference voltage source circuit 200 provided in the embodiment of the present invention utilizes the carrier mobility μ and the threshold voltage V TH The temperature coefficient of carrier mobility μ is multiplied by a negative coefficient and then multiplied by the threshold voltage V TH The temperature coefficient of the threshold voltage V TH The negative temperature coefficient of the reference voltage Vr2 is offset to obtain a reference voltage Vr2 with a zero temperature coefficient, thereby ensuring the low temperature drift characteristic of the output reference voltage Vo. At the same time, the reference voltage generating circuit 220 can generate the reference voltage Vr2 without the error amplifier OP, so that the reference voltage Vr2 will not be detuned by the influence of the error amplifier OP, thereby ensuring the low offset characteristic of the output reference voltage Vo.

[0066] Accordingly, the present invention further provides a chip, which may be a system-level chip, wherein the chip further includes the reference voltage source circuit 200 of the above embodiment.

[0067] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A reference voltage source circuit, comprising: A bias current generating circuit, used for providing a bias current; A reference voltage generating circuit, used for generating a reference voltage with a zero temperature coefficient according to the bias current; as well as A reference voltage output circuit is used to generate a reference voltage according to the reference voltage, The reference voltage source circuit further includes a feedback path connected between the bias current generating circuit and the reference voltage output circuit, wherein the feedback path is used to feed back the reference voltage to the bias current generating circuit so that the bias current generating circuit generates the bias current according to the reference voltage. The reference voltage generating circuit comprises: A second transistor, a third transistor and a second resistor are sequentially connected between a power supply and a ground terminal, a control terminal of the second transistor is connected to the bias current generating circuit, a first terminal of the third transistor is connected to the control terminal, The second transistor is used to replicate the bias current, and the third transistor is used to generate the reference voltage according to the bias current.

2. The reference voltage source circuit according to claim 1, wherein: The bias current generating circuit comprises: A first error amplifier, wherein a negative input terminal is connected to the reference voltage, and a positive input terminal is connected to the first node voltage; A first transistor and a first resistor are sequentially connected between a power supply and a ground terminal, wherein a control terminal of the first transistor is connected to an output terminal of the first error amplifier, The drain end of the first transistor outputs the bias current, the control end of the first transistor is connected to the control end of the second transistor, and the first node voltage is a common node voltage of the first transistor and the first resistor.

3. The reference voltage source circuit according to claim 2, wherein: The reference voltage output circuit comprises: A second error amplifier, wherein the negative input terminal is connected to the reference voltage, and the positive input terminal is connected to the second node voltage; a fourth transistor, a third resistor, a fourth resistor and a fifth resistor connected in sequence between a power supply and a ground terminal, wherein a control terminal of the fourth transistor is connected to an output terminal of the second error amplifier, The common node between the third resistor and the fourth resistor is used to output the reference voltage, and the second node voltage is the common node voltage between the fourth resistor and the fifth resistor.

4. The reference voltage source circuit according to claim 3, wherein: The resistance value of the fourth resistor is adjustable, and the voltage value change of the reference voltage is achieved by adjusting the resistance value of the fourth resistor.

5. The reference voltage source circuit according to claim 3, wherein: The third transistor is an NMOS transistor, and the first transistor, the second transistor and the fourth transistor are PMOS transistors.

6. The reference voltage source circuit according to claim 3, further comprising: The starting circuit is used to control the reference voltage to operate at a correct DC operating point.

7. The reference voltage source circuit according to claim 1, wherein: The bias current ,in, is the carrier mobility of the third transistor, is the gate oxide capacitance density of the third transistor, V TH is the threshold voltage of the third transistor, W is the channel width of the third transistor, L is the channel length of the third transistor, Vr2 is the reference voltage, and Rs is the second resistor.

8. The reference voltage source circuit according to claim 7, wherein: The reference voltage is obtained by multiplying the temperature coefficient of the carrier mobility by a negative coefficient and superimposing it on the temperature coefficient of the threshold voltage. The negative coefficient is obtained by adjusting The value of is realized, wherein Ibias is the bias current, W is the channel width of the third transistor, and L is the channel length of the third transistor.

9. A chip, comprising the reference voltage source circuit according to any one of claims 1 to 8.

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