Instruction storage system, method, device, computer device and readable storage medium

Abstract

The application discloses an instruction storage system, method, device, computer equipment and readable storage medium, the instruction storage system comprises a temporary storage module, and the temporary storage module is used for storing instruction data sent by a backfill processing module to provide target instructions to a fetch pipeline under the condition that the backfill processing module obtains access permission of an instruction cache module. Thus, by adding the temporary storage module, data backfilled by the backfill processing module into the instruction cache module is temporarily stored, and the required data is provided for the fetch pipeline, so that the backfill speed of the backfill processing module is effectively improved without causing pipeline stall.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an instruction storage system, method, apparatus, computer device, and readable storage medium. Background Technology

[0002] The instruction cache module is a cache structure used to store instructions. The instruction fetch pipeline accesses the instruction cache module based on the instruction address to retrieve the target instruction. If the instruction fetch pipeline does not retrieve the target instruction after accessing the instruction cache module, the backfilling module needs to retrieve the corresponding instruction data block, including the target instruction, from external memory and backfill it into the instruction cache module so that the instruction fetch pipeline can subsequently retrieve the instruction included in that instruction data block from the instruction cache module.

[0003] Instruction data blocks are typically divided into multiple instruction data segments. The instruction backfilling module needs to access the instruction cache module multiple times, backfilling one instruction data segment at a time. However, the instruction cache module can only process one access request per cycle. Therefore, the instruction backfilling module and the instruction fetch pipeline compete for access to the instruction cache module. Once the instruction fetch pipeline gains access, the instruction backfilling module cannot access the instruction cache module to backfill instruction data. In related technologies, the backfilling speed of the instruction backfilling module is slow, which affects the use of the bus. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in the related art. To this end, a first objective of this invention is to provide an instruction storage system to increase the backfilling speed of the backfilling processing module without causing pipeline interruptions.

[0005] The second objective of this invention is to provide an instruction storage method.

[0006] A third objective of this invention is to provide an instruction storage device.

[0007] The fourth objective of this invention is to provide a computer device.

[0008] The fifth objective of this invention is to provide a computer-readable storage medium.

[0009] To achieve the above objectives, a first aspect of the present invention provides an instruction storage system, comprising a temporary storage module; the temporary storage module is connected to a backfilling module; wherein the backfilling module is connected to an instruction cache module and is configured to, when the instruction fetch pipeline does not fetch a first target instruction from the instruction cache module, fetch an instruction data block including the first target instruction; when the instruction fetch pipeline does not have access to the instruction cache module, provide the first target instruction to the instruction fetch pipeline, and send the instruction data included in the instruction data block to the temporary storage module; the temporary storage module is configured to, when the backfilling module has access to the instruction cache module, store the instruction data block sent by the backfilling module, so as to provide a second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

[0010] According to one embodiment of the present invention, the backfilling processing module is further configured to receive address missing information provided by the instruction fetch pipeline, and send a corresponding target acquisition request to the external memory according to the address missing information, so as to acquire the instruction data block from the external memory; wherein, the address missing information is generated by the instruction fetch pipeline based on the instruction address of the first target instruction when the first target instruction is not acquired from the instruction cache module.

[0011] According to one embodiment of the present invention, the backfilling processing module is further configured to, when the acquired instruction data block corresponds to the address missing information, set the acquisition identifier corresponding to the address missing information to be available, so as to provide the first target instruction to the instruction fetch pipeline and send the instruction data to the temporary storage module; wherein, the acquisition identifier is used to indicate that the instruction fetch pipeline can acquire the first target instruction from the instruction data block.

[0012] According to one embodiment of the present invention, the backfilling processing module is further configured to send the instruction data to the temporary storage module when the instruction address corresponding to the instruction data corresponds to the instruction address of the second target instruction.

[0013] According to one embodiment of the present invention, the instruction data corresponds to first identification information, the first identification information being the sorting identifier of the instruction data in the instruction data block; the temporary storage module is further configured to provide the second target instruction to the instruction fetch pipeline according to the first identification information corresponding to the instruction data when the second identification information corresponding to the instruction data is valid; wherein, the second identification information being valid indicates that the instruction data is available.

[0014] According to one embodiment of the present invention, the instruction data includes a plurality of instructions; the temporary storage module is further configured to, when storing the instruction data, set the second identification information corresponding to the instruction data to be valid, and when all the plurality of instructions included in the instruction data are provided to the instruction fetch pipeline, set the second identification information corresponding to the instruction data to be invalid; wherein, the second identification information being valid indicates that the instruction data is available.

[0015] According to one embodiment of the present invention, the backfill processing module is further configured to obtain access permissions to the instruction cache module when the available space of the temporary storage module is not less than a preset data size, so as to provide the first target instruction to the instruction fetch pipeline and send the instruction data included in the instruction data block to the temporary storage module.

[0016] According to one embodiment of the present invention, the backfilling processing module has a permission priority, which is used to obtain the access permission according to the permission priority when the time when the backfilling processing module requests the access permission of the instruction cache module from the instruction cache module meets a preset time threshold condition.

[0017] According to one embodiment of the present invention, the backfilling processing module is further configured to write the instruction data block to the instruction cache module when it obtains access rights to the instruction cache module.

[0018] According to one embodiment of the present invention, the temporary storage module is used to store the instruction data sent by the backfill processing module, so as to provide the second target instruction to the instruction fetch pipeline, when the backfill processing module obtains permission to write data to the instruction cache module and the instruction fetch pipeline does not obtain permission to read data from the instruction cache module.

[0019] To achieve the above objectives, a second aspect of the present invention provides an instruction storage method applied to an instruction storage system, the instruction storage system including a temporary storage module; the temporary storage module is connected to a backfilling module; wherein the backfilling module is connected to an instruction cache module and is used to acquire an instruction data block including the first target instruction when the instruction fetch pipeline does not acquire the first target instruction from the instruction cache module; and to provide the first target instruction to the instruction fetch pipeline when the instruction fetch pipeline does not have access to the instruction cache module, and to send the instruction data included in the instruction data block to the temporary storage module; the method includes: when the backfilling module has access to the instruction cache module, storing the instruction data sent by the backfilling module in the temporary storage module, so that the temporary storage module provides a second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

[0020] To achieve the above objectives, a third aspect of the present invention provides an instruction storage device applied to an instruction storage system, the instruction storage system including a temporary storage module; the temporary storage module is connected to a backfilling module; wherein the backfilling module is connected to an instruction cache module and is used to acquire an instruction data block including the first target instruction when the instruction fetch pipeline does not acquire the first target instruction from the instruction cache module; to provide the first target instruction to the instruction fetch pipeline when the instruction fetch pipeline does not obtain access to the instruction cache module, and to send the instruction data included in the instruction data block to the temporary storage module; the device includes: a data storage module, used to store the instruction data sent by the backfilling module in the temporary storage module when the backfilling module obtains access to the instruction cache module, so that the temporary storage module provides a second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

[0021] To achieve the above objectives, a fourth aspect of the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the instruction storage method described in the foregoing embodiments.

[0022] To achieve the above objectives, a fifth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the instruction storage method described in the foregoing embodiments.

[0023] According to multiple embodiments provided by the present invention, by adding a temporary storage module to temporarily store the data backfilled by the backfill processing module to the instruction cache module and to provide the required data for the instruction fetch pipeline, the problem of pipeline stalling caused by the instruction fetch pipeline being unable to obtain the required data from the buffer register and the instruction cache module after the access permissions of the instruction cache module are transferred to the backfill processing module in order to improve the backfill speed is solved.

[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] Figure 1a This is a schematic diagram illustrating an application scenario provided according to the embodiments described in this specification.

[0026] Figure 1b This is a schematic diagram of an instruction storage system structure provided according to one embodiment of this specification.

[0027] Figure 2 This is a schematic diagram of an instruction storage system structure provided according to one embodiment of this specification.

[0028] Figure 3 This is a schematic diagram of a temporary storage module structure provided according to one embodiment of this specification.

[0029] Figure 4 This is a structural block diagram of an instruction storage device provided according to one embodiment of this specification.

[0030] Figure 5 This is a structural block diagram of a computer device provided according to one embodiment of this specification. Detailed Implementation

[0031] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0032] The instruction cache module (ICACHE) is a structure consisting of Tag RAM (for storing cache data index addresses) and Data RAM (for storing cache data). Based on the pipeline configuration of the instruction fetch module in the CPU, the instruction fetch module contains a pipeline stage for fetching instructions (hereinafter referred to as the fetch pipeline). The fetch pipeline accesses the Tag RAM and Data RAM of the instruction cache module according to the instruction address. The Tag RAM is used to determine whether the instruction address accessed by the fetch pipeline is hit in the instruction cache module, and the Data RAM is used to provide the data (i.e., instruction code) corresponding to the instruction address when the target instruction address accessed by the fetch pipeline is hit in the instruction cache module. It can be understood that the process of the fetch pipeline accessing the instruction cache module is the same as the process of the fetch pipeline reading from the instruction cache module. Typically, the instruction fetch pipeline read instruction cache module requires two cycles: In the first cycle, the instruction fetch pipeline sends the read address (i.e., the target instruction address) and read enable to the instruction cache module; therefore, the first cycle can be called the read cycle. In the second cycle, the instruction fetch pipeline obtains the data (i.e., the instruction code) corresponding to the read address; therefore, the second cycle can be called the data cycle. During the instruction fetch pipeline read instruction cache module process, if an instruction fetch pipeline misses, meaning the target instruction address accessed by that pipeline is not found in the instruction cache module, and the pipeline fails to fetch the target instruction, the instruction fetch module needs to send a request via the bus to external memory (e.g., main memory) to request the reading of an instruction data block the size of a cache line from external memory. A cache line refers to a contiguous address space that can be used to determine whether the target instruction address has been hit. It is understood that the instruction data block the size of a cache line read from external memory contains the target instruction.

[0033] Data read from external memory is returned via the bus and then retrieved by the instruction fetch module's fill-in module. The fill-in module needs to fill this data into the instruction cache module so that the fetch pipeline in the instruction fetch module can hit that cache line when accessing the instruction cache module subsequently. Since the size of a cache line is usually larger than the bus width, an instruction data block the size of a cache line is typically divided into multiple instruction data blocks of a predetermined size, which are returned to the fill-in module multiple times via the bus. The fill-in module needs to request access permissions from the instruction cache module multiple times to perform multiple write operations and complete the fill-in of these multiple instruction data blocks. However, because the instruction fetch pipeline requests access permissions from the instruction cache module every cycle to perform instruction fetch operations, and the instruction cache module can only process one access request per cycle, the fill-in module and the instruction fetch pipeline will compete for access permissions to the instruction cache module.

[0034] After the data read from the external memory is returned, it needs to be stored in the fill buffer register inside the instruction fetch module. In related technologies, there are two main methods for the fill processing module to fill the data in the fill buffer register into the instruction cache module: (1) First, if the target instruction address is hit in the fill buffer register, the corresponding instruction fetch pipeline can directly obtain the data in the fill buffer register. Second, the data in the fill buffer register of the fill processing module is obtained by the instruction fetch pipeline, and after requesting access to the instruction cache module, the data in the fill buffer register is filled into the instruction cache module; (2) First, the fill processing module requests access to the instruction cache module and fills the data in the fill buffer register into the instruction cache module. Second, the instruction fetch pipeline requests access to the instruction cache module and obtains the required data from the instruction cache module.

[0035] Taking a cache line size of 64 bytes, a bus width of 128 bits, a fill buffer register size of 128 bits, an instruction fetch size of 64 bits per fetch in the instruction fetch pipeline, and a missed instruction address of addr as an example, the instruction data block read from external memory can be divided according to the bus width to obtain four 128-bit instruction data blocks. Using the first method described above for fill, assuming that in cycle t, the bus returns the first 128-bit instruction data 1 starting at addr, the fill processing module stores it in the fill buffer register. Then, the instruction fetch pipeline can directly obtain the first 64 bits of instruction data 1 in its data cycle. In cycle t+1, the instruction fetch pipeline can directly obtain the last 64 bits of instruction data 1 based on the instruction address addr+8. In cycle t+2, the fill processing module fills instruction data 1 from the fill buffer register into the instruction cache module. If the bus returns the second 128-bit instruction data (2), the fill-in module stores it in the fill-in buffer register. Then, in cycle t+3, the data cycle of the instruction fetch pipeline can directly retrieve the first 64 bits of instruction data (2) based on the instruction address addr+16. Following this method, the fill-in module fills all four 128-bit instruction data entries into the instruction cache module. The subsequent cycle processes are not detailed here. This method has two drawbacks: First, it takes 12 cycles from the return of the first data entry in cycle t to the completion of the last data entry fill-in, making the fill-in process slow. Second, since the instruction fetch pipeline often experiences multiple misses, and these misses share a single fill-in buffer register, the fill-in module cannot receive new data from the bus until the data in the fill-in buffer register is filled into the instruction cache module, resulting in bus occupancy and affecting bus usage. Simultaneously, the data cache module (DCACHE), which shares the bus with the instruction cache module, becomes unresponsive, impacting processor performance.

[0036] Using the second method described above for backfilling, assuming that in cycle t, the bus returns the first 128-bit instruction data 1 starting at address addr, the backfilling module stores it in the backfill buffer register. The fetch pipeline's data cycle can directly retrieve the first 64 bits of instruction data 1. At this time, the backfilling module gains access to the instruction cache module, directly backfilling instruction data 1 into the instruction cache module, and can receive new data returned from the bus. In cycle t+1, the bus returns the second 128-bit instruction data 2, and the backfilling module stores it in the backfill buffer register. The backfilling module again gains access to the instruction cache module, directly backfilling instruction data 2 into the instruction cache module. However, because the fetch pipeline's read cycle does not gain access to the instruction cache module, and instruction data 1 in the backfill buffer register is overwritten by instruction data 2, the fetch pipeline cannot retrieve the last 64 bits of instruction data 1 from the instruction address addr+8, causing a pipeline stall and impacting processor performance.

[0037] To improve the backfill speed of the backfill processing module without causing pipeline interruptions, it is necessary to provide an instruction storage system. This system adds a temporary storage module to temporarily store data backfilled by the backfill processing module into the instruction cache module, allowing the instruction cache module to process backfill requests quickly. Simultaneously, the temporary storage module can replace the backfill buffer register of the backfill processing module to provide data to the instruction fetch pipeline. This achieves fast backfill processing while reducing pipeline congestion. This addresses the problem that after transferring access permissions from the instruction cache module to the backfill processing module to improve backfill speed, the data in the backfill buffer register is flushed by new data returned from the bus, causing the instruction fetch pipeline to be unable to obtain the necessary data from the backfill buffer register and the instruction cache module, leading to pipeline interruptions.

[0038] Figure 1a This diagram illustrates an application scenario of an instruction storage system, method, apparatus, computer device, and readable storage medium provided in this specification. Taking an instruction fetch module including a backfill processing module and a temporary storage module as an example, the backfill processing module is connected to the instruction cache module ICACHE and is used to backfill data to the instruction cache module ICACHE; the temporary storage module is connected to the backfill processing module and is used to store the data backfilled to the instruction cache module ICACHE by the backfill processing module. The backfill processing module includes a backfill buffer register to store data returned via the bus.

[0039] In this example scenario, the instruction cache module ICACHE is a standard 2-way instruction cache. The instruction fetch module also includes an instruction fetch pipeline for performing instruction fetch operations. The instruction fetch pipeline accesses the instruction cache module ICACHE based on the target instruction address to fetch the instruction. If the target instruction address is hit in the instruction cache module ICACHE, the instruction fetch pipeline can retrieve the target instruction from the instruction cache module ICACHE.

[0040] If the target instruction address is not found in the instruction cache module ICACHE, the instruction fetch pipeline can generate address missing information based on the missing target instruction address, data fetch request, etc., and send it to the backfilling module. The backfilling module sends the corresponding target fetch request, etc., to the external memory of the instruction cache module based on the address missing information, so as to retrieve the instruction data block including the target instruction from the external memory.

[0041] In this example scenario, the instruction data block is a data block the size of a cache line. The backfilling module sends a target fetch request to the external memory via the bus and retrieves the instruction data block containing the target instruction returned by the external memory via the bus. Since the size of the instruction data block is usually larger than the bus width, it is divided into several instruction data blocks of a predetermined size, which are returned separately over several cycles. The backfilling module receives one instruction data block of a predetermined size in one cycle and, if it has access to the instruction cache module, backfills the received instruction data into the instruction cache module, allowing the backfilling module to receive new instruction data and reducing bus occupancy. In some embodiments, the predetermined size can be the bus width.

[0042] After acquiring instruction data, the backfilling module stores the instruction data in the backfill buffer and requests access permission from the instruction cache module. If the backfilling module gains access, it can write the instruction data from the backfill buffer into the instruction cache module and send a copy of the instruction data from the backfill buffer to the temporary storage module for storage. At this point, the backfilling module can acquire new instruction data, and the temporary storage module can provide the corresponding target instruction to the instruction fetch pipeline that has experienced a miss. After acquiring the target instruction, the instruction fetch pipeline stores the acquired target instruction in the instruction buffer and sends it to the execution unit of the subsequent pipeline for execution.

[0043] In this scenario example, after sending a fetch request, the backfill processing module receives instruction data of a predetermined size returned via the bus. It can then directly provide the corresponding target instruction to the instruction fetch pipeline. Since the instruction fetch pipeline typically fetches less data than the instruction data each time, and the instruction data in the backfill buffer is flushed away by new instruction data received by the backfill processing module, it cannot be guaranteed that the subsequent instruction fetch pipeline will always retrieve the corresponding target instruction from the backfill buffer. Therefore, in later cycles, the temporary storage module can provide the corresponding target instruction to the instruction fetch pipeline.

[0044] In this scenario example, the instruction fetch pipeline may experience multiple misses within a certain period. The backfilling module can simultaneously send multiple target fetch requests to the external memory and internally maintain fetch flags corresponding to multiple address misses. The instruction data returned by the external memory includes fetch request information, allowing the backfilling module to determine whether each fetch request corresponds to an address miss sent by the instruction fetch pipeline. If a fetch request matches any address miss, the backfilling module sets the fetch flag corresponding to that address miss to "available," indicating that the instruction data containing the target instruction at that address has been fetched and stored in the backfill buffer. The instruction fetch pipeline can then fetch the corresponding target instruction from the backfill buffer.

[0045] Understandably, since the instruction data block corresponding to a target acquisition request needs to be divided into multiple instruction data of a predetermined size and returned multiple times via the bus, and instruction data belonging to the same instruction data block has its own sorting identifier information within that block, address missing information can correspond to multiple acquisition identifiers. The backfilling processing module can set the acquisition identifier corresponding to the corresponding address missing information to be available based on the instruction data acquisition request information and the sorting identifier information.

[0046] The instruction fetch pipeline examines the data in the backfill buffer and compares it with the fetch identifier corresponding to each missing address and the current target instruction address of the instruction fetch pipeline. If the fetch identifier corresponding to the instruction address that matches the current target instruction address of the instruction fetch pipeline is available, and the instruction address corresponding to the data in the backfill buffer matches the current target instruction address of the instruction fetch pipeline, the instruction fetch pipeline can retrieve the current target instruction corresponding to the current target instruction address from the backfill buffer.

[0047] For example, the cache line size is 64 bytes, the bus width is 128 bits, the backfill buffer register size is 128 bits, the instruction fetch pipeline fetches 64 bits of data per instruction, and the instruction data block is divided into four instruction data blocks of 128 bits each and returned separately via the bus. The backfill processing module's backfill operation and the process of the instruction fetch pipeline obtaining the target instruction may include:

[0048] Step 1: The instruction fetch pipeline's read cycle accesses the instruction cache module based on the current instruction address 32'h20;

[0049] Step 2: In the next cycle, the fetch pipeline reads the data from the instruction cache module. When the fetch pipeline determines that the current instruction address 32'h20 is not found in the instruction cache module based on the read data, it generates address missing information based on the missing instruction address 32'h20, the request to read data from external memory, memory attributes, etc., and sends it to the backfill processing module.

[0050] Step 3: In the next cycle, the backfilling module generates the corresponding target acquisition request 1 based on the address missing information, and sends the target acquisition request 1 to the external memory via the bus to request the acquisition of a 64-byte instruction data block 1, and starts waiting for the external memory to return the instruction data to the backfilling module via the bus.

[0051] Step 4: After several cycles, the external memory returns the first 128 bits of instruction data 1 from instruction data block 1 via the bus, along with the corresponding sorting identifier. The backfilling module retrieves instruction data 1 and stores it in the backfill buffer. Based on the fetch request information corresponding to instruction data 1, it can determine that instruction data 1 corresponds to address missing information 1, thus confirming that instruction data 1 is currently needed by the instruction fetch pipeline. The backfilling module can also determine, based on the sorting identifier, that instruction data 1 is the first 128 bits of data in its instruction data block, and then set the first fetch identifier corresponding to address missing information 1 to fetchable.

[0052] Step 5: In the next cycle, 1) The fetch pipeline checks instruction data 1 in the backfill buffer, determines that some data in the currently waiting instruction data block has been returned, and further, based on the fetch identifier corresponding to address missing information 1, and if the instruction address corresponding to instruction data 1 matches the current target instruction address of the fetch pipeline, the fetch pipeline directly retrieves the target instruction from instruction data 1 according to the target instruction address 32'h20 and stores it in the instruction buffer; 2) The backfill processing module obtains access to the instruction cache module and backfills the instruction data in the backfill buffer into the instruction cache module; 3) The backfill processing module sends instruction data 1 and its corresponding sorting identifier in the instruction data block to the temporary storage module for storage, as the source of the target instruction for the next cycle; 4) Since the backfill processing module can release the backfill buffer, it can receive instruction data 2 returned from the bus and store it in the backfill buffer;

[0053] Step Six: Repeat the above steps: 1) The subsequent instruction fetch pipeline checks the instruction data 1 in the temporary storage module. If the instruction fetch pipeline determines that the valid identifier corresponding to instruction data 1 in the temporary storage module is valid, it determines whether the required target instruction can be obtained from the temporary storage module based on the sorting identifier corresponding to instruction data 1. If it determines that the required target instruction can be obtained from the temporary storage module, it can directly obtain the corresponding target instruction based on the target instruction address (32'h20)+8 and store it in the instruction buffer; 2) At this time, the backfilling module still obtains the access permission of the instruction cache module and backfills the instruction data 2 in the backfilling buffer to the instruction cache module; 3) The backfilling module sends a copy of instruction data 2 in the backfilling buffer and its corresponding sorting identifier to the temporary storage module for storage; 4) Since the backfilling module can release the backfilling buffer, it can receive the new instruction data 3 returned on the bus and store it in the backfilling buffer until all four instruction data corresponding to target fetch request 1 are backfilled to the instruction cache module.

[0054] Therefore, when the instruction data block corresponding to the instruction data backed up by the backfilling module is the same instruction data block waiting for by the instruction fetch pipeline that corresponds to its missing address information, the backfilling module only needs 4 cycles to complete the backfilling of the 4 instruction data blocks included in that instruction data block. If backfilling is performed according to the first method described above, the backfilling module will need at least 12 cycles to complete the backfilling of the 4 instruction data blocks included in that instruction data block; if the backfilling priority of the backfilling module is increased according to the second method described above, then a pipeline pause of 4 cycles will be caused when the backfilling is completed in 4 cycles. Compared with the first method, the system provided in this specification can reduce bus usage by 8 cycles; compared with the second method, the system provided in this specification does not introduce a pipeline pause when the backfilling is completed in 4 cycles.

[0055] In some embodiments, the instruction fetch pipeline can check the data in the backfill buffer and the temporary storage module each cycle. After determining that the instruction data in the backfill buffer or the temporary storage module is the data currently needed by the instruction fetch pipeline, it can directly retrieve the required target instruction from the instruction data in the backfill buffer or the temporary storage module. If part of the instruction data in the backfill buffer has already been fetched by the instruction fetch pipeline, the backfill processing module can determine whether the address of the remaining instruction matches the target instruction address of the next cycle in the instruction fetch pipeline, thus determining whether the instruction in the remaining instruction data is the target instruction to be fetched in the next cycle. If the address of the remaining instruction matches the target instruction address of the next cycle in the instruction fetch pipeline, the backfill processing module can send the remaining instruction data to the temporary storage module.

[0056] In this scenario example, if all instructions in the instruction data stored in the temporary storage module have been fetched by the instruction fetch pipeline and have not been overwritten by new instruction data, the temporary storage module can invalidate the valid identifier corresponding to the instruction data so that the temporary storage module can store the new instruction data sent by the backfill processing module.

[0057] In some embodiments, the temporary storage module can be configured to store data that has been backfilled to the instruction cache module by the backfill processing module in the last two instances. In other embodiments, to save hardware resources, the temporary storage module can also adopt a smaller structure. The minimum size of the temporary storage module can be the same as the data size fetched by each instruction in the instruction fetch pipeline, which can also improve the backfill speed to some extent.

[0058] In this scenario example, to ensure that the backfilling processing module can backfill instruction data to the instruction cache module in a timely manner, thereby reducing bus occupancy and affecting bus usage, if the time when the backfilling processing module requests access rights from the instruction cache module meets certain conditions, the access rights of the instruction cache module can be forcibly transferred to the backfilling processing module, enabling the backfilling processing module to complete the backfilling operation and improve processor performance.

[0059] This specification provides an instruction storage system, which is described in the embodiments below. Figure 1b As shown, the instruction storage system 110 may include a temporary storage module 112; the temporary storage module 112 is connected to the backfill processing module 120; wherein, the backfill processing module 120 is connected to the instruction cache module 130, and is used to obtain an instruction data block including the first target instruction when the instruction fetch pipeline does not obtain the first target instruction from the instruction cache module 130; and to provide the first target instruction to the instruction fetch pipeline and send the instruction data including the instruction data block to the temporary storage module 112 when the instruction fetch pipeline does not obtain access to the instruction cache module 130.

[0060] The temporary storage module 112 is used to store the instruction data sent by the backfill processing module 120 when the backfill processing module 120 obtains access to the instruction cache module 130, so as to provide a second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

[0061] The instruction cache module is a Level 1 instruction cache (ICACHE). The target instruction is the instruction that the instruction fetch pipeline did not retrieve from the instruction cache module, and it has a corresponding target instruction address. The instruction data block is a block of instructions stored in a contiguous address space in external memory. The instruction address space is the contiguous address space corresponding to the instruction data block; further, the instruction address space is a cache line.

[0062] Understandably, in the case of sequential instruction fetching, if the address of the first target instruction accessed by the current instruction fetch pipeline misses, the addresses of subsequent instructions will usually also miss. Therefore, it is necessary to fetch instruction data blocks in the contiguous address space including the first target instruction of the current instruction fetch pipeline so that subsequent instruction fetch pipelines can fetch the required instructions.

[0063] In some cases, the size of the instruction fetch data in a single operation is often smaller than the instruction data block size fetched by the fill-in module. Therefore, the instruction data block fetched by the fill-in module is typically not fully fetched by the fetch pipeline after several cycles. The fill-in module can only receive new instruction data blocks after filling the fetched instruction data block into the instruction cache module. To ensure that the fetch pipeline's fetching of the target instruction and the fill-in module's fill-in operation can occur simultaneously without affecting pipeline efficiency and processor performance, a temporary storage module can be set up to store the instruction data filled into the instruction cache module by the fill-in module. This allows both the fill-in module and the temporary storage module to provide the necessary target instructions to the fetch pipeline when the instruction cache module's access rights are transferred to the fill-in module. Furthermore, to ensure consistency between the instruction data stored in the temporary storage module and the instruction data filled into the instruction cache module by the fill-in module, the fill-in module can send the instruction data included in the instruction data block to the temporary storage module when it gains access rights to the instruction cache module.

[0064] Specifically, during the instruction fetch operation, the instruction fetch pipeline first accesses the instruction cache module based on the first target instruction address. If the instruction fetch pipeline fails to retrieve the first target instruction corresponding to the first target instruction address from the instruction cache module (i.e., a first target instruction address miss), the fill-in module needs to send a request to the external memory to request the retrieval of an instruction data block containing the first target instruction. After retrieving the requested instruction data block, the fill-in module stores it and requests access permission from the instruction cache module. Once the fill-in module obtains access permission from the instruction cache module, it can provide the first target instruction to the instruction fetch pipeline and fill the instruction data block back into the instruction cache module. The backfilling module sends a copy of the instruction data included in the instruction data block to the temporary storage module. After receiving the instruction data sent by the backfilling module, the temporary storage module stores it. At this time, since the access permissions of the instruction cache module are transferred to the backfilling module, the instruction fetch pipeline does not have access permissions to the instruction cache module and cannot obtain the second target instruction from the instruction cache module. Therefore, in order to reduce pipeline pauses, the instruction fetch pipeline can directly obtain the required second target instruction from the instruction data stored in the temporary storage module. That is, the temporary storage module provides the second target instruction to the instruction fetch pipeline.

[0065] In some embodiments, the instruction data block may include all instruction data or only a portion of the instruction data. The portion of instruction data may include the target instruction that the instruction fetch pipeline might need during subsequent instruction fetching processes. The fill-in module and the temporary storage module may both be included in the instruction fetch module. After obtaining the requested instruction data block, the fill-in module can store it in a fill-in buffer register, allowing the instruction fetch pipeline to retrieve the required target instruction from the fill-in buffer register. The memory external to the instruction cache module may be a Level 2 cache, a Level 3 cache, main memory, etc., storing the target instruction.

[0066] It should be noted that the instructions in this specification can be instruction codes. When there is sufficient available space in the temporary storage module, after the instruction fetch pipeline retrieves the first target instruction from the backfill buffer register in the first cycle, subsequent cycles can directly retrieve the required second target instruction from the temporary storage module.

[0067] In the above embodiments, by adding a temporary storage module to store the instruction data backed up to the instruction cache module by the backfilling processing module, when the backfilling processing module gains access to the instruction cache module to perform the backfilling operation, the corresponding target instruction can be provided to the instruction fetch pipeline that has experienced a miss through both the temporary storage module and the backfilling processing module. The temporary storage module solves the problem that after transferring access to the instruction cache module to the backfilling processing module to improve backfilling speed, the instruction data block previously acquired by the backfilling processing module is flushed by the newly acquired instruction data block, preventing the provision of the corresponding target instruction to the instruction fetch pipeline and causing pipeline stalls. Therefore, the pipeline fetching will not be interrupted by waiting for backfilling to complete, while simultaneously improving backfilling speed, reducing bus occupancy time, and effectively improving processor performance.

[0068] In some implementations, reference Figure 2 As shown, the backfilling module 120 is also used to connect to the external memory 210. The backfilling module 120 is also used to receive address missing information provided by the instruction fetch pipeline, so as to send a corresponding target fetch request to the external memory 210 according to the address missing information, so as to fetch the instruction data block from the external memory 210; wherein, the address missing information is generated by the instruction fetch pipeline according to the instruction address of the first target instruction when it fails to fetch the first target instruction from the instruction cache module.

[0069] The external memory is a memory located outside the instruction cache module that stores the instruction data block containing the first target instruction. The target acquisition request can be generated by the backfilling processing module based on address missing information, etc.

[0070] The address of the target instruction is called the target instruction address. Specifically, the instruction fetch pipeline requires two cycles to access the instruction cache module: in the first cycle, the fetch pipeline sends the target instruction address and read enable to the instruction cache module; in the second cycle, the fetch pipeline obtains the data read from the instruction cache module. The first cycle is called the read cycle, and the second cycle is called the data cycle. During the data cycle, the fetch pipeline can determine whether the target instruction address has been hit in the instruction cache module based on the obtained data. If the first target instruction address is not hit in the instruction cache module, the fetch pipeline can generate corresponding address missing information based on the first target instruction address and send it to the fill-in module. Upon receiving the address missing information, the fill-in module needs to send a bus request to the external memory. The fill-in module can generate a corresponding target fetch request based on the address missing information and send it to the bus to request the fetch of the instruction data block containing the first target instruction from the external memory.

[0071] It should be noted that the time definitions for the read cycle and data cycle of the instruction fetch pipeline in this specification are independent of the time definition for the return cycle.

[0072] In some embodiments, the address missing information may include information needed for backfilling, such as the first target instruction address, a request to read data from external memory, and memory attributes. For example, the first target instruction address `addr` is 32'h20. In cycle t, the instruction fetch pipeline accesses the instruction cache module based on the first target instruction address 32'h20. In cycle t+1, data in the instruction cache module is read. When the instruction fetch pipeline determines that the first target instruction address 32'h20 is not found in the instruction cache module based on the read data, it generates address missing information based on address 32'h20, the request to read data from external memory, and memory attributes, and sends it to the backfilling module. In cycle t+2, the backfilling module generates a target fetch request corresponding to the address missing information based on address 32'h20, the request to read data from external memory, and memory attributes, and sends the target fetch request to the memory outside the instruction cache module via the bus, waiting for the external memory to return the instruction data block to the backfilling module via the bus.

[0073] It should be noted that, due to the data transmission requirements of the bus protocol, the target acquisition request can be generated by the backfilling module based on information such as address missing information and bus protocol requirements. The bus protocol requirements also include the number of bursts of returned data, which indicates how many bus-width data entries need to be returned to the backfilling module starting from a certain address.

[0074] In some implementations, the backfilling module is further configured to, when the acquired instruction data block corresponds to the address missing information, set the acquisition flag corresponding to the address missing information to be available, so as to provide the first target instruction to the instruction fetch pipeline and send instruction data to the temporary storage module; wherein, the acquisition flag is used to indicate that the instruction fetch pipeline can acquire the first target instruction from the instruction data block.

[0075] The instruction data block contains a request for information, which may be an identifier corresponding to the missing address information.

[0076] In some cases, multiple misses may occur in the pipeline. The backfilling module can typically handle multiple misses simultaneously by sending multiple fetch requests via the bus. Consequently, the instruction data blocks fetched by the backfilling module may belong to different fetch requests. Therefore, when providing a target instruction to the instruction fetch pipeline, it is necessary to first determine whether the current instruction data block corresponds to the current address missing information of the instruction fetch pipeline. This determines whether the instruction data block is the same instruction data block that the instruction fetch pipeline is currently waiting for, i.e., whether the instruction data block is what the instruction fetch pipeline currently needs.

[0077] Specifically, the backfilling module can send the identifier corresponding to the missing address information onto the bus along with the target fetch request. After the external memory responds to the target fetch request, it can return the identifier as fetch request information along with the instruction data block to the backfilling module. After fetching the instruction data block returned from the bus, the backfilling module can store it in the backfill buffer register. The backfilling module maintains fetch identifiers corresponding to multiple missing address information. Based on the fetch request information, the backfilling module can determine which missing address in the fetch pipeline the instruction data block corresponds to, then set the fetch identifier corresponding to that missing address to fetchable, and store the instruction data block in the backfill buffer register. The fetch pipeline checks the data in the backfill buffer register, comparing the fetch identifiers corresponding to each missing address with the current first target instruction address of the fetch pipeline. If the fetch flag corresponding to the instruction address that matches the current first target instruction address of the instruction fetch pipeline is available, and the instruction address corresponding to the data in the backfill buffer register matches the current first target instruction address of the instruction fetch pipeline, the instruction fetch pipeline can fetch the first target instruction corresponding to the first target instruction address from the backfill buffer register.

[0078] Furthermore, when the backfilling module sends instruction data to the temporary storage module, it first needs to determine which address in the instruction fetch pipeline the acquired instruction data block corresponds to, in order to determine whether the instruction data block is currently needed by the instruction fetch pipeline. If the instruction data block is needed by the instruction fetch pipeline, the backfilling module can send the instruction data included in the instruction data block to the temporary storage module, so that the instruction fetch pipeline can directly retrieve the required second target instruction from the temporary storage module later.

[0079] Furthermore, according to the instruction cache mechanism, when a fetch pipeline miss occurs, the backfilling module needs to request an instruction data block the size of a cache line from external memory. The cache line is the smallest storage unit of the instruction cache module. Since the cache line size is usually larger than the bus width, the instruction data block needs to be divided into several instruction data segments of a predetermined size and returned via the bus in stages. The backfilling module retrieves one instruction data segment returned from the bus at a time. Each segment of instruction data corresponds to a fetch request, allowing the backfilling module to determine which address in the fetch pipeline each instruction data segment corresponds to based on the fetch request information. The module then sets the fetch flag corresponding to that address to be fetchable, enabling the fetch pipeline to determine whether the instruction data in the backfill buffer register is currently needed by the fetch pipeline based on the fetch flags corresponding to each instruction address. In some embodiments, the predetermined size can be the bus width. The backfilling module can send all of the fetched instruction data to the temporary storage module, or it can send only a portion of the fetched instruction data to the temporary storage module.

[0080] In some embodiments, the instruction fetch pipeline can directly fetch the target instruction from the fill buffer register using a bypass method. Specifically, the instruction fetch pipeline can check each cycle whether the instruction data block in the fill buffer register is the one currently needed, and based on the fetch flags corresponding to each instruction address maintained by the fill processing module and the current target instruction address of the instruction fetch pipeline, it can directly fetch the corresponding target instruction using the bypass method, store it in the instruction buffer, and send it to the subsequent pipeline.

[0081] In other embodiments, the backfilling module may determine whether the instruction data block in the backfill buffer register is currently needed by the instruction fetch pipeline, and provide the corresponding target instruction directly to the instruction fetch pipeline through the bypass method based on the fetch identifier corresponding to each instruction address maintained by the backfilling module and the current target instruction address of the instruction fetch pipeline.

[0082] In some implementations, the backfilling module is also used to send instruction data to the temporary storage module when the instruction address corresponding to the instruction data corresponds to the instruction address of the second target instruction.

[0083] It is understandable that if the fetch request information corresponding to the instruction data block obtained by the backfilling module corresponds to the address missing information of the instruction fetch pipeline, then the instruction data block is the instruction data block currently being waited for by the instruction fetch pipeline. Therefore, the backfilling module can determine that the instruction data included in the instruction data block is in the same instruction data block as the instruction data block currently being waited for by the instruction fetch pipeline.

[0084] In some cases, to conserve hardware resources, the available space in the temporary storage module is limited. Therefore, when using the temporary storage module to store instruction data, it's advisable to first determine whether the instruction in the instruction data is the target instruction to be fetched by the instruction fetch pipeline. If the instruction in the instruction data is the target instruction to be fetched by the instruction fetch pipeline, then the instruction data is stored in the temporary storage module.

[0085] Specifically, the backfilling module can determine whether the address of the remaining instruction data matches the address of the second target instruction subsequently fetched by the instruction fetch pipeline, if the first target instruction in the data stored in the backfill buffer register has already been fetched by the instruction fetch pipeline. This determines whether the remaining instruction data includes the second target instruction that the instruction fetch pipeline needs to fetch later. If the address of the remaining instruction matches the address of the second target instruction subsequently fetched by the instruction fetch pipeline, the backfilling module can send the remaining instruction data to the temporary storage module.

[0086] In some embodiments, the instruction data block obtained by the backfilling module is instruction data of a predetermined size obtained by dividing an instruction data block corresponding to a cache line size of the target fetch request. For example, the cache line size is 64 bytes, the bus width is 128 bits, and the backfill buffer register size is 128 bits. Based on the bus width, the instruction data block requested by the backfilling module is divided into four 128-bit instruction data blocks: instruction data 1, instruction data 2, instruction data 3, and instruction data 4. These are returned to the backfilling module in four separate passes by the bus, with each instruction fetched by the fetch pipeline fetching 64 bits of data. Assuming that instruction data 1 is returned by the bus in cycle t, the backfilling module can obtain it and store it in the backfill buffer register. If the instruction data block to which instruction data 1 belongs is the same instruction data block as the instruction data block currently being waited for by the fetch pipeline, and assuming that instruction data 1 includes the instruction corresponding to instruction address addr1 and the instruction corresponding to instruction address addr1+8, then... The instruction fetch pipeline retrieves the first target instruction (the first 64 bits of instruction data 1) from the fill buffer register based on the first target instruction address addr1. The fill processing module then determines whether this matches the second target instruction address addr2 in the next cycle of the instruction fetch pipeline, based on the instruction address addr1+8. Understandably, in the case of sequential instruction fetch, the second target instruction address addr2 matches the instruction address addr1+8. Therefore, the last 64 bits of instruction data 1 represent the target instruction to be fetched by the instruction fetch pipeline, and the fill processing module can send these 64 bits to the temporary storage module.

[0087] For example, if the instruction data block to which instruction data 1 belongs is the same instruction data block as the instruction data block currently being waited for by the instruction fetch pipeline, assuming that instruction data 1 includes instructions corresponding to instruction addresses addr1-8 and instructions corresponding to instruction address addr1. The instruction fetch pipeline retrieves the corresponding first target instruction from the backfill buffer register based on the first target instruction address addr1, i.e., the last 64 bits of instruction data 1. Then, the backfill processing module can determine whether it matches the second target instruction address addr2 in the next cycle of the instruction fetch pipeline based on instruction addresses addr1-8. It can be understood that in the case of sequential instruction fetch, the second target instruction address addr2 matches the instruction address addr1+8. Therefore, the first 64 bits of instruction data 1 are not the target instruction to be fetched by the instruction fetch pipeline, and the backfill processing module does not need to send this 64 bits of data to the temporary storage module.

[0088] In some embodiments, the instruction data corresponds to first identification information, which is the sorting identifier of the instruction data in the instruction data block.

[0089] The temporary storage module is also used to provide a second target instruction to the instruction fetch pipeline according to the first identifier information corresponding to the instruction data, provided that the second identifier information is valid; wherein, the second identifier information being valid indicates that the instruction data is available.

[0090] The first identification information can be used to indicate the arrangement position of instruction data within its instruction data block. The second identification information can be used to indicate that the corresponding instruction data in the temporary storage module is in the instruction data block currently being waited for by the instruction fetch pipeline, from which the instruction fetch pipeline can obtain the required target instruction.

[0091] Understandably, instruction data blocks are typically divided into several instruction data segments of a predetermined size and returned multiple times via the bus. Therefore, each instruction data segment has a first identifier indicating its position within the block after which it belongs. The instruction fetch pipeline can compare the second target instruction address and the fetch identifier corresponding to the missing address information to determine which instruction data segment within the instruction data block the fetch pipeline is waiting for. Therefore, the temporary storage module can provide the second target instruction to the instruction fetch pipeline based on the first identifier corresponding to the instruction data.

[0092] Specifically, when the external memory returns instruction data via the bus, it includes the corresponding first identification information and fetch request information. If the backfilling module determines, based on the fetch request information, that the instruction data block to which the instruction data belongs is the same instruction data block currently being waited for by the instruction fetch pipeline, it can send the instruction data and its corresponding first identification information to the temporary storage module. The temporary storage module stores the instruction data sent by the backfilling module and sets the corresponding second identification information to valid, indicating that the instruction fetch pipeline can retrieve the required target instruction from the instruction data stored in the temporary storage module. First, the instruction fetch pipeline can compare the address of the second target instruction with the fetch identifier corresponding to the missing address information to determine which instruction data block the second target instruction is located in, i.e., to determine the sorting identifier of the instruction data currently needed by the instruction fetch pipeline, provided that the corresponding fetch identifier is available. Second, the instruction fetch pipeline can check the second identifier information corresponding to the instruction data in the temporary storage module. If the second identifier information is valid, it determines whether the first identifier information corresponding to the instruction data matches the previously determined sorting identifier, thereby determining whether the required second target instruction can be obtained from the instruction data. If the first identifier information matches the previously determined sorting identifier, the instruction fetch pipeline can further obtain the corresponding second target instruction from the instruction data based on the address of the second target instruction. Thus, the temporary storage module can provide the second target instruction to the instruction fetch pipeline.

[0093] Understandably, the instruction fetch pipeline can check the fetch flag corresponding to the missing address information in the backfill processing module, and determine whether it is necessary to fetch the required target instruction from the temporary storage module based on the fetch flag and the data stored in the backfill buffer register.

[0094] In some embodiments, the instruction fetch pipeline can directly fetch the target instruction from the fill buffer register and temporary storage module using a bypass method. For example, the cache line size is 64 bytes, the bus width is 128 bits, the fill buffer register size is 128 bits, the instruction fetch pipeline fetches 64 bits of data per instruction, and the cache line-sized instruction data block B1 is divided into four 128-bit instruction data blocks according to the bus width: instruction data 1, instruction data 2, instruction data 3, and instruction data 4. The process of the instruction fetch pipeline fetching the target instruction may include:

[0095] The t-cycle is the read cycle of the instruction fetch pipeline, which accesses the instruction cache module based on the current instruction address 32'h20.

[0096] In cycle t+1, the fetch pipeline reads data from the instruction cache module. When the fetch pipeline determines that the current instruction address 32'h20 is not found in the instruction cache module based on the read data, it generates address missing information based on the missing instruction address 32'h20, the request to read data from external memory, memory attributes, etc., and sends it to the backfill processing module.

[0097] In cycle t+2, the backfilling module generates a corresponding target acquisition request based on the address missing information and sends the target acquisition request to the external memory via the bus to request the acquisition of a 64-byte instruction data block B1, and begins to wait for the external memory to return the instruction data to the backfilling module via the bus.

[0098] During cycle T, the external memory returns the first 128 bits of instruction data 1 from instruction data block B1, along with fetch request information and first identifier information corresponding to instruction data 1. The backfilling module fetches instruction data 1 and stores it in the backfill buffer register. Based on the fetch request information of instruction data 1, it determines whether instruction data 1 corresponds to address missing information 1. If the backfilling module determines that instruction data 1 corresponds to address missing information 1, it can determine that instruction data 1 is currently needed by the instruction fetch pipeline. Based on the first identifier information corresponding to instruction data 1, it determines that instruction data 1 is the first 128 bits of data in instruction data block B1. Then, the backfilling module can set the first of the four fetch identifiers for instruction data corresponding to address missing information 1 to fetchable.

[0099] In cycle T+1, 1) the fetch pipeline checks instruction data 1 in the fill buffer register. Based on the fetch flag corresponding to address missing information 1, it determines that part of the data in the currently waiting instruction data block has been returned. If the instruction address corresponding to instruction data 1 matches the current target instruction address 32'h20 of the fetch pipeline, the target instruction is directly fetched from the fill buffer register using the bypass method based on the target instruction address 32'h20 and stored in the instruction buffer; 2) the fill processing module obtains access to the instruction cache module and fills instruction data 1 in the fill buffer register into the instruction cache module; 3) the fill processing module sends instruction data 1 and its corresponding first flag information to the temporary storage module for storage, as the source of the target instruction for the fetch pipeline in the next cycle; the temporary storage module stores instruction data 1 and its corresponding first flag information and sets the second flag information corresponding to instruction data 1 to valid; 4) since the fill processing module can release the fill buffer register, it can receive instruction data 2 returned from the bus and store it in the fill buffer register.

[0100] In cycle T+2, 1) the current instruction address of the fetch pipeline is (32'h20)+8. The fetch pipeline checks instruction data 1 in the temporary storage module. If the second identifier of instruction data 1 is valid, it directly retrieves the corresponding target instruction from the temporary storage module using the bypass method based on the first identifier of instruction data 1 and the target instruction address (32'h20)+8, and stores it in the instruction buffer; 2) At this time, the backfill processing module still has access to the instruction cache module and backfills instruction data 2 from the backfill buffer register to the instruction cache module; 3) The backfill processing module sends a copy of instruction data 2 and its corresponding first identifier to the temporary storage module for storage, as the source of the target instruction for the fetch pipeline in the next cycle; the temporary storage module stores instruction data 2 and its corresponding first identifier, and sets the second identifier of instruction data 2 to valid; 4) Since the backfill processing module can release the backfill buffer register, it can receive instruction data 3 returned from the bus and store it in the backfill buffer register;

[0101] In subsequent cycles, the above steps are repeated: 1) The subsequent instruction fetch pipeline checks instruction data 2 in the temporary storage module. If the second identifier of instruction data 2 is valid, the target instruction is directly retrieved from the temporary storage module using the bypass method based on the first identifier corresponding to instruction data 2 and the target instruction address (32'h20)+16, and stored in the instruction buffer; 2) The backfill processing module still obtains access to the instruction cache module and backfills instruction data 3 in the backfill buffer register to the instruction cache module; 3) The backfill processing module sends a copy of instruction data 3 and its corresponding first identifier to the temporary storage module for storage, as the source of the target instruction for the instruction fetch pipeline in the next cycle; the temporary storage module stores instruction data 3 and its corresponding first identifier and sets the second identifier corresponding to instruction data 3 to valid; 4) Since the backfill processing module can release the backfill buffer register, it can receive instruction data 4 returned from the bus and store it in the backfill buffer register until all instruction data returned from the bus has been backfilled to the instruction cache module. In this way, the backfill processing module can backfill one instruction data returned on the bus in each cycle, without wasting any bus cycles or introducing additional pipeline pauses.

[0102] In other embodiments, the backfilling module and the temporary storage module may bypass the instruction data to the instruction fetch pipeline using a bypass method.

[0103] It should be noted that the instruction data obtained by dividing instruction data blocks of the same cache line size may not be returned in order. Furthermore, since the backfilling module may send multiple target retrieval requests at the same time, and each target retrieval request corresponds to the return of an instruction data block of the same cache line size, the return order of each instruction data may be uncertain.

[0104] In some implementations, the instruction data includes several instructions. The temporary storage module is further configured to, when storing instruction data, set the second identification information corresponding to the instruction data to valid, and when all the instructions included in the instruction data are provided to the instruction fetch pipeline, set the second identification information corresponding to the instruction data to invalid; wherein, the second identification information being valid indicates that the instruction data is available.

[0105] Specifically, the temporary storage module stores the instruction data sent by the backfill processing module and sets the second identifier information corresponding to the instruction data to valid, indicating that the instruction fetch pipeline can obtain the required target instruction from the instruction data stored in the temporary storage module. When all the instructions included in the instruction data stored in the temporary storage module have been fetched by the instruction fetch pipeline, and no new instruction data is stored to overwrite the instruction data, the temporary storage module can set the second identifier information corresponding to the instruction data to invalid.

[0106] In some embodiments, the second identification information can be represented by 1 to indicate validity and 0 to indicate invalidity. The temporary storage module can adopt a two-layer structure to store data that has been backfilled into the instruction cache module by the backfill processing module in the last two iterations. For example, the cache line size is 64 bytes, the bus width is 128 bits, the backfill buffer register size is 128 bits, and an instruction data block of one cache line size is divided into four 128-bit instruction data blocks according to the bus width. (See reference...) Figure 3 As shown, each layer of the temporary storage module contains a 1-bit valid flag, a 2-bit flag, and a 128-bit data. The valid flag corresponds to the second identification information in this specification, indicating that the instruction data in the data bits is available, i.e., it can be fetched by the instruction fetch pipeline. The flag corresponds to the first identification information in this specification, indicating which 128-bit position of the instruction data in its instruction data block it is. The data bits are used to store instruction data.

[0107] For example, the backfilling module sends a 128-bit instruction data 1 to the temporary storage module. The temporary storage module can store instruction data 1 in the first-level structure and set the valid flag in the first-level structure to 1, indicating that if the instruction data block to which the instruction data in this layer belongs is the same instruction data block as the instruction data block currently being waited for by the instruction fetch pipeline, the instruction fetch pipeline can obtain the required target instruction from the instruction data in this layer. The instruction fetch pipeline needs to fetch 2 instructions each time according to the target instruction address, and the size of 1 instruction is 32 bits. Assuming that the instruction fetch pipeline obtains the first 64 bits of instruction data 1 from the first-level structure of the temporary storage module according to the target instruction address 32'h20 in the first cycle, and obtains the last 64 bits of instruction data 1 from the first-level structure of the temporary storage module according to the target instruction address (32'h20)+8 in the second cycle, at this time, all the instructions in instruction data 1 in the first-level structure of the temporary storage module have been obtained by the instruction fetch pipeline. Suppose that in the second cycle, the backfill processing module sends a 128-bit instruction data 2 to the temporary storage module. The temporary storage module can store instruction data 2 in the second-level structure and set the valid flag in the second-level structure to 1. Since no new instruction data is stored in the first-level structure, the temporary storage module can set the valid flag corresponding to instruction data 1 in the first-level structure to 0.

[0108] It should be noted that the structure of the temporary storage module can be set according to actual needs. Generally, the size of the temporary storage module should not be less than the data size of each instruction fetched by the instruction fetch pipeline.

[0109] For example, the cache line size is 64 bytes, the bus width is 128 bits, the backfill buffer register size is 128 bits, the instruction fetch pipeline fetches 64 bits of data per instruction, and the temporary storage module can store 64 bits of instruction data. The instruction data block B1, the size of the cache line, is divided into four 128-bit instruction data blocks according to the bus width: Instruction Data 1, Instruction Data 2, Instruction Data 3, and Instruction Data 4. The process of the instruction fetch pipeline fetching the target instruction may include:

[0110] The t-cycle is the read cycle of the instruction fetch pipeline, which accesses the instruction cache module based on the current instruction address 32'h20.

[0111] In cycle t+1, the fetch pipeline reads data from the instruction cache module. When the fetch pipeline determines that the current instruction address 32'h20 is not found in the instruction cache module, the fetch pipeline generates address missing information based on the missing instruction address 32'h20, the request to read data from external memory, memory attributes, and other information, and sends it to the backfill processing module.

[0112] In cycle t+2, the backfilling module generates a corresponding target acquisition request based on the address missing information and sends the target acquisition request to the external memory via the bus to request a 64-byte instruction data block B1, and then waits for the external memory to return the instruction data to the backfilling module via the bus.

[0113] During cycle T, the external memory returns the first 128 bits of instruction data 1 from instruction data block B1 via the bus, along with fetch request information and first identifier information corresponding to instruction data 1. The backfilling module retrieves instruction data 1 and stores it in the backfill buffer register. Based on the fetch request information of instruction data 1, it determines whether instruction data 1 corresponds to address missing information 1. If the backfilling module determines that instruction data 1 corresponds to address missing information 1, it can determine that instruction data 1 is currently needed by the instruction fetch pipeline. Based on the first identifier information corresponding to instruction data 1, it determines that instruction data 1 is the first 128 bits of data in instruction data block B1. Then, the backfilling module can set the first fetch identifier corresponding to address missing information 1 to fetchable.

[0114] In cycle T+1, 1) the fetch pipeline checks instruction data 1 in the fill buffer register, determines that part of the data in the currently waiting instruction data block B1 has been returned, and, based on the fetch flag corresponding to address missing information 1, and if the instruction address corresponding to instruction data 1 matches the current target instruction address 32'h20 in the fetch pipeline, directly retrieves the target instruction from the fill buffer register using the bypass method and stores it in the instruction buffer; 2) the fill processing module obtains access to the instruction cache module and fills instruction data 1 from the fill buffer register into the instruction cache module; 3) the fill processing module... If the instruction address corresponding to the remaining part of instruction data 1 (instruction data 1') is determined to be the target instruction address of the next cycle of the instruction fetch pipeline, instruction data 1' and its corresponding first identification information are sent to the temporary storage module for storage as the source of the target instruction for the next cycle of the instruction fetch pipeline; the temporary storage module stores instruction data 1' and its corresponding first identification information and sets the second identification information corresponding to instruction data 1' to valid; 4) Since the backfill processing module can release the backfill buffer register, it can receive instruction data 2 returned from the bus and store it in the backfill buffer register, and set the second acquisition flag corresponding to the address missing information 1 to acquire;

[0115] In cycle T+2, 1) the current instruction address of the instruction fetch pipeline is (32'h20)+8. The instruction fetch pipeline simultaneously checks the data in the backfill buffer register and the temporary storage module, and determines that the target instruction needs to be fetched from the temporary storage module. If the second identifier information corresponding to instruction data 1' is valid, based on the first identifier information corresponding to instruction data 1' in the temporary storage module and the target instruction address (32'h20)+8, the corresponding target instruction is directly fetched from the temporary storage module using the bypass method and stored in the instruction buffer.

[0116] In subsequent cycles, the above steps are repeated. In cycle T+3, 1) the current instruction address of the fetch pipeline is (32'h20)+16. The fetch pipeline checks the instruction data 2 in the fill buffer register. Based on the fetch flag corresponding to the address missing information 1, and if the instruction address corresponding to instruction data 2 matches the current target instruction address (32'h20)+16 of the fetch pipeline, the target instruction is directly fetched from the fill buffer register using the bypass method according to the target instruction address (32'h20)+16 and stored in the instruction buffer; 2) the fill processing module obtains access to the instruction cache module and fills the instruction data 2 in the fill buffer register back into the instruction cache module; 3) fill... The processing module determines that the instruction address corresponding to the remaining part of instruction data 2 (instruction data 2') is the target instruction address of the next cycle of the instruction fetch pipeline. It sends a copy of instruction data 2' and its corresponding first identification information to the temporary storage module for storage, which serves as the source of the target instruction for the next cycle of the instruction fetch pipeline. The temporary storage module stores instruction data 2' and its corresponding first identification information and sets the second identification information corresponding to instruction data 2' to valid. 4) Since the backfill processing module can release the backfill buffer register, it can receive instruction data 3 returned from the bus and store it in the backfill buffer register.

[0117] In cycle T+4, 1) the current instruction address of the instruction fetch pipeline is (32'h20)+24. The instruction fetch pipeline simultaneously checks the data in the backfill buffer register and the temporary storage module. It determines that the target instruction needs to be fetched from the temporary storage module. If the second identifier corresponding to instruction data 2' is valid, based on the first identifier corresponding to instruction data 2' in the temporary storage module and the target instruction address (32'h20)+24, it directly fetches the corresponding target instruction from the temporary storage module using a bypass method and stores it in the instruction buffer. Subsequent cycles repeat the above steps until all instruction data returned from the bus has been backfilled into the instruction cache module. The specific steps are not detailed here.

[0118] In some embodiments, the second identification information may be in the form of a signal to indicate whether the corresponding instruction data in the temporary storage module is available.

[0119] In some implementations, the backfilling module is also used to obtain access to the instruction cache module when the available space of the temporary storage module is not less than a preset data size, so as to provide the first target instruction to the instruction fetch pipeline and send the instruction data included in the instruction data block to the temporary storage module.

[0120] The preset data size is the size of the instruction data sent by the backfilling processing module to the temporary storage module each time.

[0121] In some cases, the instruction data stored in the temporary storage module may not be fully retrieved by the instruction fetch pipeline after several cycles. In such situations, the temporary storage module cannot release available space to receive and store new instruction data sent by the backfilling module. If the backfilling module still has access to the instruction cache module for backfilling, the new instruction data may be lost, preventing subsequent instruction fetches from obtaining the corresponding target instruction, thus causing pipeline stalls. Therefore, the availability of space in the temporary storage module can be used to determine whether to transfer access permissions from the instruction cache module to the backfilling module.

[0122] Specifically, after the backfilling module receives the instruction data block returned from the bus, it can request access to the instruction cache module. The instruction cache module can then determine the available space size of the temporary storage module and whether it is not less than the preset data size. If the available space of the temporary storage module is not less than the preset data size, the instruction cache module can grant access to the backfilling module, enabling it to provide the target instruction to the instruction fetch pipeline and send instruction data to the temporary storage module.

[0123] Understandably, according to the instruction cache mechanism, the backfilling module sends a target fetch request to the external memory to retrieve an instruction data block the size of a cache line. Since the cache line size is typically larger than the bus width, the instruction data block needs to be divided into several instruction data blocks of a predetermined size and returned multiple times via the bus. The backfilling module can only retrieve one instruction data block returned on the bus at a time. Because the predetermined size is usually the bus width, in some embodiments, the preset data size can be the bus width.

[0124] For example, the cache line size is 64 bytes, the bus width is 128 bits, the backfill buffer register size is 128 bits, and the data size fetched per instruction in the instruction fetch pipeline is 64 bits. The instruction data block of the cache line size is divided into four 128-bit instruction data blocks according to the bus width: Instruction Data 1, Instruction Data 2, Instruction Data 3, and Instruction Data 4. (Continue to refer to...) Figure 3As shown, the temporary storage module adopts a single-layer structure to store the data that the backfilling module recently backfilled into the instruction cache module. The temporary storage module stores 128 bits of instruction data 1. Assume that in the first cycle, the instruction fetch pipeline fetches the first 64 bits of instruction data 1 from the temporary storage module based on the target instruction address `addr`, and the remaining 64 bits are not fetched by the pipeline in the next four cycles. At this time, the backfilling module fetches 128 bits of instruction data block 3 and stores it in the backfill buffer register. The backfilling module then requests backfilling from the instruction cache module. Based on the available space in the temporary storage module, the instruction cache module determines that it does not have enough space to store instruction data block 3 that the backfilling module is about to backfill into the instruction cache module; therefore, the instruction cache module rejects the backfilling module's request. Suppose that in the sixth cycle, the instruction fetch pipeline retrieves the last 64 bits of instruction data 1 from the temporary storage module based on the target instruction address addr+8. At this point, the temporary storage module can invalidate the corresponding second identifier information to free up sufficient available space. The instruction cache module can then grant access rights to the backfilling module, allowing it to backfill instruction data block 3 and send a copy to the temporary storage module for storage. Therefore, while waiting for the temporary storage module to release space, there will be some pause in backfilling or bus occupancy, but this saves temporary storage module resources and incurs no additional losses when there are no other requests or data on the bus.

[0125] In other embodiments, the preset data size can be the data size fetched by the instruction fetch pipeline each time.

[0126] In the above implementation, by combining the available space of the temporary storage module, it is determined whether to transfer the access rights of the instruction cache module to the backfilling processing module, so as to ensure the consistency between the data stored in the temporary storage module and the data backfilled into the instruction cache module by the backfilling processing module.

[0127] In some implementations, the backfilling processing module has a permission priority, which is used to obtain access permission according to the permission priority when the time when the backfilling processing module requests access permission from the instruction cache module meets a preset time threshold condition.

[0128] In some cases, after a miss occurs in the instruction fetch pipeline, subsequent misses or pauses may not occur again due to pipeline flushing. Because the instruction fetch pipeline has a higher access priority to the instruction cache module than the fill-in module, the instruction fetch pipeline can continuously access the instruction cache module. However, since the fill-in module cannot access the instruction cache module to complete the fill-in operation, it cannot receive new data returned from the bus, resulting in the bus being continuously occupied. Therefore, the fill-in module needs to have priority access to ensure that it can obtain access to the instruction cache module within a certain timeframe.

[0129] Specifically, after the backfilling processing module receives the instruction data block returned from the bus, it can request access to the instruction cache module. Understandably, if the backfilling processing module does not obtain access after its request, it will request access from the instruction cache module every cycle until it does. If the backfilling processing module continuously requests access for a preset time threshold, its access rights will be forcibly transferred from the instruction cache module to the backfilling processing module based on its priority.

[0130] In some embodiments, the preset time threshold may be 16 cycles.

[0131] It should be noted that the instruction data block in the embodiments of this specification can be the instruction data obtained by dividing the instruction data block as described above. The preset time threshold can be set according to actual needs, and this specification does not impose specific limitations.

[0132] In the above implementation, if a miss occurs in the instruction fetch pipeline and no further misses or pauses occur in the subsequent instruction fetch pipeline, after the backfilling module continuously requests access to the instruction cache module for a certain period of time, the access rights of the instruction cache module are forcibly transferred to the backfilling module according to the permission priority of the backfilling module. This ensures that the bus can be released within a certain period of time, reducing the occupation of the bus.

[0133] In some implementations, the backfilling module is also used to write instruction data blocks to the instruction cache module when it has obtained access to the instruction cache module.

[0134] Specifically, after the backfill processing module obtains the instruction data block, it can store it in the backfill buffer register and request access to the instruction cache module. After obtaining access to the instruction cache module, the backfill processing module can perform a backfill operation to write the instruction data block in the backfill buffer register to the instruction cache module and send a copy of the instruction data included in the instruction data block to the temporary storage module for storage.

[0135] In some implementations, a temporary storage module is used to store instruction data sent by the backfilling module in order to provide a second target instruction to the instruction fetching pipeline, when the backfilling module has permission to write data to the instruction cache module and the instruction fetching pipeline does not have permission to read data from the instruction cache module.

[0136] Specifically, when the backfilling module obtains permission to write data to the instruction cache module to backfill the instruction data block to the instruction cache module, and the instruction fetch pipeline does not obtain permission to read data from the instruction cache module to read the required instructions from the instruction cache module, the temporary storage module stores the instruction data sent by the backfilling module so that the instruction fetch pipeline can obtain the required target instructions from the temporary storage module.

[0137] It should be noted that the instruction data block in the above embodiments can be instruction data of a predetermined size obtained by dividing the instruction data block as described above. The instruction data sent from the backfilling processing module to the temporary storage module can be all of the aforementioned instruction data of the predetermined size, or it can be a part of the aforementioned instruction data of the predetermined size.

[0138] This specification provides an instruction storage method applied to an instruction storage system, which includes a temporary storage module connected to a backfilling module. The backfilling module is connected to an instruction cache module and is used to acquire an instruction data block including the first target instruction when the instruction fetch pipeline fails to retrieve the first target instruction from the instruction cache module; to provide the first target instruction to the instruction fetch pipeline when the instruction fetch pipeline does not have access to the instruction cache module; and to send the instruction data included in the instruction data block to the temporary storage module. The instruction storage method includes: when the backfilling module has access to the instruction cache module, storing the instruction data sent by the backfilling module in the temporary storage module, so that the temporary storage module provides a second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

[0139] It should be noted that for the description of the temporary storage module and the backfilling module in the above embodiments, please refer to the description of the temporary storage module and the backfilling module in the embodiments of the instruction storage system in this specification, and will not be repeated here.

[0140] This specification provides an instruction storage device applied to an instruction storage system. The instruction storage system includes a temporary storage module; the temporary storage module is connected to a backfilling module; wherein the backfilling module is connected to an instruction cache module and is used to acquire an instruction data block including the first target instruction when the instruction fetch pipeline does not acquire the first target instruction from the instruction cache module; and to provide the first target instruction to the instruction fetch pipeline and send the instruction data including the instruction data block to the temporary storage module when the instruction fetch pipeline does not have access to the instruction cache module. (Reference) Figure 4 As shown, the instruction storage device 400 includes a data block storage module 410.

[0141] The data storage module 410 is used to store the instruction data sent by the backfilling processing module in the temporary storage module when the backfilling processing module obtains access to the instruction cache module, so that the temporary storage module provides the second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

[0142] For specific limitations regarding the instruction storage device, please refer to the limitations on the instruction storage method above, which will not be repeated here. Each module in the aforementioned instruction storage device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0143] This specification also provides a computer device, see embodiments thereof. Figure 5 As shown, the computer device 500 includes a memory 510, a processor 520, and a computer program 530 stored in the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 530, it implements the aforementioned instruction storage method.

[0144] This specification also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned instruction storage method.

[0145] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0146] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0147] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0148] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0149] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0150] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An instruction storage system, characterized in that, The instruction storage system includes a temporary storage module; the temporary storage module is connected to the backfilling module; wherein, the backfilling module is connected to the instruction cache module, and is used to acquire an instruction data block including the first target instruction when the instruction fetch pipeline does not acquire the first target instruction from the instruction cache module; and to provide the first target instruction to the instruction fetch pipeline and send the instruction data included in the instruction data block to the temporary storage module when the instruction fetch pipeline does not have access to the instruction cache module. The temporary storage module is used to store the instruction data sent by the backfill processing module when the backfill processing module obtains access permission to the instruction cache module, so as to provide a second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

2. The system according to claim 1, characterized in that, The backfilling module is further configured to receive address missing information provided by the instruction fetch pipeline, and send a corresponding target acquisition request to the external memory according to the address missing information, so as to acquire the instruction data block from the external memory; wherein, the address missing information is generated by the instruction fetch pipeline based on the instruction address of the first target instruction when it fails to acquire the first target instruction from the instruction cache module.

3. The system according to claim 2, characterized in that, The backfilling processing module is further configured to, when the acquired instruction data block corresponds to the address missing information, set the acquisition identifier corresponding to the address missing information to be available, so as to provide the first target instruction to the instruction fetch pipeline and send the instruction data to the temporary storage module; wherein, the acquisition identifier is used to indicate that the instruction fetch pipeline can acquire the first target instruction from the instruction data block.

4. The system according to claim 3, characterized in that, The backfilling processing module is further configured to send the instruction data to the temporary storage module when the instruction address corresponding to the instruction data corresponds to the instruction address of the second target instruction.

5. The system according to claim 3, characterized in that, The instruction data corresponds to first identification information, which is the sorting identifier of the instruction data in the instruction data block. The temporary storage module is further configured to provide the second target instruction to the instruction fetch pipeline according to the first identifier information corresponding to the instruction data, provided that the second identifier information is valid; wherein, the second identifier information being valid indicates that the instruction data is available.

6. The system according to claim 1, characterized in that, The instruction data includes several instructions; The temporary storage module is further configured to, when storing the instruction data, set the second identification information corresponding to the instruction data to be valid, and when all of the plurality of instructions included in the instruction data are provided to the instruction fetch pipeline, set the second identification information corresponding to the instruction data to be invalid; wherein, the second identification information being valid indicates that the instruction data is available.

7. The system according to claim 1, characterized in that, The backfilling module is further configured to obtain access to the instruction cache module when the available space of the temporary storage module is not less than a preset data size, so as to provide the first target instruction to the instruction fetch pipeline and send the instruction data included in the instruction data block to the temporary storage module.

8. The system according to claim 1, characterized in that, The backfilling processing module has a permission priority, which is used to obtain the access permission according to the permission priority when the time when the backfilling processing module requests the access permission of the instruction cache module meets a preset time threshold condition.

9. The system according to claim 1, characterized in that, The backfilling processing module is further configured to write the instruction data block to the instruction cache module when it has obtained access rights to the instruction cache module.

10. The system according to any one of claims 1 to 9, characterized in that, The temporary storage module is used to store the instruction data sent by the backfill processing module, so as to provide the second target instruction to the instruction fetch pipeline, when the backfill processing module obtains permission to write data to the instruction cache module and the instruction fetch pipeline does not obtain permission to read data from the instruction cache module.

11. An instruction storage method, characterized in that, An instruction storage system is applied, the instruction storage system including a temporary storage module; the temporary storage module is connected to a backfilling module; wherein, the backfilling module is connected to an instruction cache module, and is used to acquire an instruction data block including the first target instruction when the instruction fetch pipeline does not acquire the first target instruction from the instruction cache module; and to provide the first target instruction to the instruction fetch pipeline when the instruction fetch pipeline does not have access to the instruction cache module, and to send the instruction data included in the instruction data block to the temporary storage module; the method includes: When the backfill processing module obtains access to the instruction cache module, it stores the instruction data sent by the backfill processing module in the temporary storage module, so that the temporary storage module provides a second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

12. An instruction storage device, characterized in that, An instruction storage system is applied, the instruction storage system including a temporary storage module; the temporary storage module is connected to a backfilling module; wherein, the backfilling module is connected to an instruction cache module, and is used to acquire an instruction data block including the first target instruction when the instruction fetch pipeline does not acquire the first target instruction from the instruction cache module; to provide the first target instruction to the instruction fetch pipeline when the instruction fetch pipeline does not have access to the instruction cache module, and to send the instruction data included in the instruction data block to the temporary storage module; the apparatus includes: The data storage module is used to store the instruction data sent by the backfilling processing module in the temporary storage module when the backfilling processing module obtains access to the instruction cache module, so that the temporary storage module provides a second target instruction to the instruction fetch pipeline; wherein the instruction address of the second target instruction is in the same instruction address space as the instruction address of the first target instruction.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 11.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 11.

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