System and method for detecting intra-chip communication errors in a reconfigurable hardware system

Abstract

A system and method for error detection on an address channel is disclosed. The method includes generating a token, applying the token to a request at a source, and generating a first result. The request is sent to a destination along with the first result through the address channel. It is determined at the destination whether an error associated with the request has occurred. Determining whether an error has occurred includes: receiving a received request corresponding to the request through the address channel; receiving the first result along with the received request; applying the token to the received request and generating a second result; comparing the first result to the second result; and sending a signal in response to the comparison.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 63 / 278,396, filed on November 11, 2021, entitled “SECURITY AND RELIABILITY EXTENSION FOR INTRA-CHIP COMMUNICATION PROTOCOL DEPLOYED ON MULTI-TASK / TENANT RECONFIGURABLE HARDWARE SYSTEM,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more aspects according to embodiments of the present disclosure relate to error detection, and more particularly, to detecting intra-chip communication errors in a multi-tasking / multi-tenant reconfigurable hardware system. Background Art

[0004] A multi-tasking / multi-tenant (collectively referred to as multi-tenant) field programmable gate array (FPGA) can support multiple applications from the same user, or multiple users can deploy their applications to coexist in one FPGA chip. Multi-tenant FPGAs are a promising architecture for deployment in data centers and / or clouds to drive hardware acceleration.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0006] Embodiments of the present disclosure are directed to a method for error detection on an address channel. The method includes generating a token, applying the token to a request at a source, and generating a first result. The request is sent to a destination through an address channel together with the first result. It is determined at the destination whether an error associated with the request has occurred. Determining whether an error has occurred includes: receiving a received request corresponding to the request through the address channel; receiving the first result together with the received request; applying the token to the received request and generating a second result; comparing the first result with the second result; and sending a signal in response to the comparison.

[0007] According to one embodiment, the token is a preset token stored at the source and the destination.

[0008] According to one embodiment, the request is one of a request to read data or a request to write data, wherein the request includes an address for reading or writing data, and the method further comprises: in response to the request, transmitting data through a data channel, wherein the data channel is different from an address channel.

[0009] According to one embodiment, applying the token to the request includes performing an XOR operation between the token and the request, and applying the token to the received request includes performing an XOR operation between the token and the received request.

[0010] According to one embodiment, the received request is identical to the request and the signal indicates that there are no errors associated with the request, wherein in response to the signal the source sends a second request over the address channel.

[0011] According to one embodiment, wherein the received request is different than the request and the signal indicates an error associated with the request, wherein in response to the signal the source resends the request over the address channel.

[0012] According to one embodiment, the source and the destination are interfaces of logic blocks of the multi-tenant reconfigurable hardware system.

[0013] According to one embodiment, the multi-tenant reconfigurable hardware system is a multi-tenant field programmable gate array.

[0014] An embodiment of the present disclosure is also directed to a method for performing error detection on a data channel, comprising: generating a first check bit and a second check bit; sending first data having the first check bit and second data having the second check bit to a destination via the data channel; determining at the destination whether an error associated with the first data and the second data has occurred, wherein determining whether an error has occurred comprises: performing a check based on the first check bit and the second check bit; and sending a signal in response to the check.

[0015] According to one embodiment, the first check bit is complementary to the second check bit.

[0016] According to one embodiment, performing the check includes performing an XOR operation between the first check bit and the second check bit and generating a value of 1, wherein the signal indicates that there are no errors associated with the first data and the second data.

[0017] According to one embodiment, in response to the check signal, the source sends third data through the data channel.

[0018] According to one embodiment, performing the check includes performing an XOR operation between the first check bit and the second check bit and producing a value of 0, wherein the signal indicates an error associated with the first data and the second data.

[0019] According to one embodiment, in response to the signal, the source resends the first data and the second data.

[0020] According to one embodiment, the first data and the second data are transmitted in a burst mode in a single transaction.

[0021] According to one embodiment, the method further comprises: receiving, by the destination, a request associated with the first data and the second data through an address channel, wherein the address channel is different from the data channel.

[0022] According to one embodiment, the source and the destination are interfaces of logic blocks of a multi-tenant field programmable gate array.

[0023] According to one embodiment, the method further includes: transmitting the first data and the second data through a first line; adding a propagation delay to a second line different from the first line; and transmitting the first check bit and the second check bit through the second line.

[0024] Embodiments of the present disclosure are also directed to a reconfigurable hardware system, comprising: a processing chip including a plurality of logic blocks for running a first application and a second application; and a communication link for providing communication between the plurality of logic blocks. The processing chip is configured to: generate a token; apply the token to a request at a source and generate a first result; send the request together with the first result to a destination through an address channel of the communication link; at the destination, determine whether an error associated with the request has occurred, wherein when determining whether an error has occurred, the processing chip is further configured to: receive a received request corresponding to the request through the address channel; receive the first result together with the received request; apply the token to the received request and generate a second result; compare the first result with the second result; and send a signal in response to the comparison.

[0025] The embodiment of the present disclosure is also directed to a reconfigurable hardware system, which includes: a processing chip, including a plurality of logic blocks for running a first application and a second application; and a communication link for providing communication between the plurality of logic blocks. The processing chip is configured to: generate a first check bit and a second check bit; send first data with the first check bit and second data with the second check bit to a destination through a data channel of the communication link; at the destination, determine whether an error associated with the first data and the second data has occurred, wherein when determining whether an error has occurred, the processing chip is also configured to: perform a check based on the first check bit and the second check bit; and send a signal in response to the check.

[0026] These and other features, aspects and advantages of the embodiments of the present disclosure will be more fully understood when considered with respect to the following detailed description, appended claims and accompanying drawings.Of course, the actual scope of the invention is defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Non-limiting and non-exhaustive embodiments of the present embodiments are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0028] Figure 1 is a block diagram of a multi-tenant reconfigurable hardware system according to one embodiment;

[0029] Figure 2 is a conceptual block diagram of a field programmable gate array (FPGA) according to one embodiment;

[0030] Figure 3 According to one embodiment, Figure 2 A block diagram of an exemplary communication channel for intra-chip communication between logic blocks of an FPGA;

[0031] Figure 4A-4B is a flow chart of a handshake process according to one embodiment, the handshake process including error checking for a read address channel and a write address channel;

[0032] Figure 5 is a flow chart of an error detection method participated in by a receiver according to one embodiment, the error detection method being used to detect errors in requests received via a read address channel and a write address channel;

[0033] Figure 6 is a flow chart of a handshake process according to one embodiment, the handshake process including error checking for a read data channel and a write data channel; and

[0034] Figure 7 is a flow chart of an error detection method by a source for detecting data transmission errors on a read data channel and a write data channel according to one embodiment. DETAILED DESCRIPTION

[0035] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements. However, the present disclosure may be embodied in various forms and should not be construed as being limited to the embodiments shown herein. More specifically, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are unnecessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals represent the same elements, and therefore, their descriptions may not be repeated. In addition, in the drawings, for clarity, the relative sizes of elements, layers and regions may be exaggerated and / or simplified.

[0036] Field programmable arrays (FPGAs) can be used to accelerate computing and data management tasks in a variety of application areas. As the demand for hardware acceleration increases, multi-tenant FPGAs can be considered. For example, in a cloud setting, multi-tenant FPGAs can be useful for co-locating workloads of different tenants and improving FPGA utilization.

[0037] In general, an FPGA chip includes various logic blocks / modules that communicate with each other using an intra-chip communication protocol. One such protocol is the Advanced Microcontroller Bus Architecture (AMBA) Advanced Extensible Interface (AXI) protocol. The popularity of the AMBA AXI protocol can be attributed to its ability to provide high-frequency, high-bandwidth, and high-speed data communications between modules. However, a disadvantage of intra-chip communication protocols such as AMBAAXI is that it is generally used for single-tenant FPGAs. In addition, the protocol supports intra-chip connections of FPGA modules, which are approximately in the sub-micron range. Therefore, it may not be necessary to ensure the security and reliability of communications, because any erroneous transmissions can be resolved by retransmitting the data.

[0038] However, for multi-tenant reconfigurable hardware systems (such as FPGAs), security and reliability measures are expected. In a multi-tenant FPGA, multiple tasks or tenants can coexist on one FPGA chip. Different tenants can flexibly program and run their own applications while sharing certain hardware resources.

[0039] The power distribution network / system (PDN / S) may typically function as a single shared power supply that drives the FPGA. One problem with shared power supplies is that power side channels (such as, for example, intra-chip power contention between different circuits / applications on the FPGA) may cause voltage fluctuations. In a multi-tenant setting, aggressive FPGA usage by an application of one tenant may cause a power supply voltage drop. The power supply voltage drop may be caused by malicious co-tenants to inject faults into the device (e.g., a fault injection attack) to access, for example, privileged information. It would be desirable to extend the intra-chip communication protocol to provide error detection to detect, for example, a fault injection attack.

[0040] Figure 1 1 is a block diagram of a multi-tenant reconfigurable hardware system according to one embodiment. The system includes a reconfigurable processing device 100, such as, for example, an FPGA. Hereinafter, the reconfigurable processing device will be referred to simply as FPGA 100. However, embodiments of the present disclosure are not limited thereto and may be extended to other processing devices whose logic may be reconfigured and reused, for example, at runtime to support any workload that a user may desire.

[0041] FPGA 100 can be coupled to external off-chip memory, such as dynamic random access memory (DRAM) 102 and non-volatile memory (NVM) / storage device 104. Storage device 104 can be, for example, a solid-state drive (SSD). FPGA 100 can also be coupled to a power system 112. Power system 112 can be configured to supply power to the entire FPGA.

[0042] In one embodiment, FPGA 100 can be deployed in a data center and / or cloud. FPGA 100 can serve multiple users / tenants 106a, 106b (collectively referred to as 106), allowing multiple users / tenants 106 to deploy software applications 108a, 108b (collectively referred to as 108) to coexist on the same FPGA. Application 108 can be, for example, a data processing application, a graphics processing application, a machine learning application, etc. Tenant 106 can access FPGA 100 through a data communication network (e.g., the Internet) 110 as an independent node or connected to a host.

[0043] Due to the co-tenancy of the FPGA, the application 108 of a particular tenant 106 may be vulnerable to attack (e.g., by another tenant). An attacker may gain unauthorized access to the application 108 of a particular tenant by launching, for example, a fault injection attack. The fault injection attack launched by the attacker may exploit the shared power system 112. For example, a co-tenant of FPGA 100 (e.g., tenant 106a) may cause a voltage drop in the power supplied to the FPGA by the power system 112 through aggressive FPGA usage. The voltage drop may make other co-tenants (e.g., tenant 106b) vulnerable to attacks by the tenant that caused the voltage drop.

[0044] Figure 2 1 is a more detailed conceptual block diagram of an FPGA 100 according to one embodiment. The FPGA includes one or more logic blocks / modules 200a-200e (collectively referred to as 200), which include circuits for running the application 108 of the tenant 106. One or more blocks 200 are also referred to as intellectual property (IP) cores / blocks, and can be reusable multiple logics that form the building blocks of the FPGA. The logic blocks can communicate with each other through data communication links 202a-202c (collectively referred to as 202). The communication on the links 202a-202c can follow an intra-chip communication protocol, such as AMBA AXI. Although AMBA AXI is used as an example, the embodiments of the present disclosure are not limited thereto and can be extended to other intra-chip communication protocols that will be understood by those skilled in the art.

[0045] In one embodiment, the logic block can be accessed by tenants 106 to run their corresponding applications 108. In one example, tenant A 106a runs application 108a ( Figure 1), tenant B 106b runs application 108b ( Figure 1 ). Module 1 200a may be a time division multiplexing module configured to schedule time for both tenant A 106a and tenant B 106b to separately and independently process their data for applications 108a and 108b. Module 2 200b and module 3 200c may store data from tenant A 106a and run application 108a. Module 4 200d and module 5 200e may store data from tenant B 106b and run application 108b. An attack on a tenant may be launched, for example, via link 202a and / or link 202b.

[0046] In one embodiment, off-chip memory (eg, DRAM 102 and NVM 104) is partitioned between tenants 106 for storing data for the tenants. One or more logic blocks 200 can access data from the off-chip memory when running applications 108.

[0047] Figure 3 is a block diagram of an exemplary communication channel for intra-chip communication between logic blocks 200 according to one embodiment. Communication over the communication channel may follow the protocol promulgated by the AMBA AXI protocol.

[0048] In one embodiment, five separate communication channels are used for intra-chip communication: read address 300; write address 302; read data 304; write data 306; and write response 308. The communication channels can be similar to those disclosed in Arm Ltd., "Introduction to AMBA AXI4", Issue 01, 2020 (the contents of which are incorporated herein by reference). Using separate address channels and data channels for read and write transfers can help maximize the bandwidth of the interface. For example, a read sequence can occur simultaneously with a write sequence.

[0049] In one embodiment, channels 300-308 are established between a manager 310 and a subordinate 312. The manager 310 and the subordinate 312 may be communication interfaces for communication between logic blocks 200 (e.g., IP block 0 320a and IP block 1 320b). In order to communicate using one of the channels, a handshake process may be performed first using a "ready" signal and a "valid" signal. For example, when participating in a handshake in a read address channel 300, a channel source (e.g., a manager 310) may provide a valid signal through the channel, and a channel sink (e.g., a subordinate 312) may provide a ready signal through the same channel. After both the valid signal and the ready signal are activated, a transmission of a request with an address to be read may occur on the address channel 300. It should be understood that the roles of the manager 310 and the subordinate 312 as a source or sink may vary depending on the data stream being transmitted. For example, for read address channel 300, write address channel 302, and write data channel 306, master 310 is the source and subordinate is the sink 312, while for read data channel 304, subordinate 312 is the source and master 310 is the sink.

[0050] During the handshake process, the prior art intra-communication protocol may not participate in error checking. Although this is acceptable for a single-tenant FPGA, error detection is desired for a multi-tenant FPGA. Therefore, in one embodiment, the handshake process in the read address channel 300, the write address channel 302, the read data channel 304, and the write data channel 306 is enhanced with an error detection mechanism.

[0051] Figure 4A-4B is a flow chart of an enhanced handshaking process with error detection for the read address channel 300 and the write address channel 302 according to one embodiment. Figure 4A It is a handshake process for the supervisor 310, which plays the role of the source of the request.

[0052] At block 400, the supervisor 310 asserts a read address valid signal (ARVALID) or a write address valid signal (AWVALID) to indicate that a valid request is available. The request may include, for example, the address, source identifier, burst length, and / or size of the requested data. In one embodiment, the request is generated by a data buffer or a finite state machine.

[0053] At block 402, the master 310 (source) sends a request to the subordinate 312 (sink) on either the read address channel 300 or the write address channel 302, depending on whether data is to be read or written.

[0054] At block 404, the supervisor 310 determines whether an error associated with the request has occurred. In this regard, the supervisor 310 may check a response signal from the subordinate 312. If the response signal is a signal indicating no error (e.g., an ARREADY signal or an AWREADY signal), at block 406, the source sends the next request.

[0055] However, if the response signal from the receiver is a signal indicating an error, the source sends a command at block 408 to resend the request and increments a global error counter at block 410. In one embodiment, the global counter stores the sequential number of errors encountered by the FPGA during intra-chip communication using the communication channels 300-306. The global counter can help identify attacks (e.g., fault injection attacks) even if the frequency of the attacks is low. For example, in a carefully designed attack, an adversary may launch an attack at a lower frequency that is designed to avoid FPGA overload protection (e.g., shutdown) but does not stop data transmission within the channel. When a threshold number of errors due to such an attack is detected, a notification can be sent to an administrator, and / or the FPGA 100 can be disabled.

[0056] Figure 4B is a handshake process for a subordinate 312 (receiver) according to one embodiment. In response to detecting that the ARVALID signal or the AWVALID signal is asserted at block 450, the subordinate 312 receives a request from the master 310 (source) on the read address channel 300 or the write address channel 302 at block 452, depending on whether data is to be read or written.

[0057] At block 454, the subordinate 312 determines whether an error associated with the request has occurred. In this regard, the subordinate 312 can apply an error detection mechanism that uses a shared key / token to check the integrity of the received request. If an error is detected, a response signal is sent at block 456 indicating an error and / or requesting that the request be repeated. The subordinate 312 can then wait for the request to be resent. In one embodiment, in response to detecting an error, a global counter is increased by the subordinate 312 rather than the supervisor 310. In such an embodiment, block 410 is performed by the subordinate 312 rather than the supervisor 310.

[0058] If it is determined at block 454 that no error occurred in the received request, then at block 458 the subordinate sends a signal (eg, an ARREADY signal or an AWREADY signal) indicating that there was no error.

[0059] Figure 5Flowchart of an error detection method participated in by a receiver 480 (e.g., subordinate 312) according to one embodiment, the error detection method is used to detect errors in requests sent by a source 482 (e.g., supervisor 310) through a read address channel 300 and a write address channel 302. In one embodiment, a shared token 500 is generated and pre-stored in each logic block 200. For example, the token can be stored during the configuration of FPGA100. In one embodiment, different tokens can be generated depending on the type of bitstream, and an appropriate token can be selected for error detection based on the type of bitstream involved in the current transaction. For example, a read request can call a different token than a write request. The size of the token can be the same as the request, or a portion of the size of the request.

[0060] Source 482 may apply token (T) 500 to generated request (R) 502 to generate source check result (C) 504. In one embodiment, supervisor 310 performs an XOR operation between token 500 and request 502 to calculate source check result 504 as follows: The source inspection result 504 may be packaged with the request 502 and sent to the subordinate 312 (eg, the receiver 480 ) via the read address channel 300 or the write address channel 302 .

[0061] The receiver 480 receives the received request (R') 506 and the received check value (C') 508. The subordinate 312 performs an XOR operation between the shared token 500 and the received request (R') 506 to calculate the subordinate check result (C"). The received check value (C') 508 is compared with the subordinate check result C" to determine whether they are equal. If the answer is yes, as determined in block 510, the received request (R') 506 is considered to be equal to the sent request (R) 502. Therefore, no error is detected in the sent request, and the subordinate 312 sends an ARREADY signal or an AWREADY signal to prompt the source 482 to send the next request 512.

[0062] If the answer is no, an error is detected and the subordinate 312 sends an error signal to prompt the master 312 (e.g., source 482) to resend the request 514. In this way, the subordinate 312 waits to receive a non-error request before sending an ARREADY signal or an AWREADY signal that completes the handshake process on the address channel 300, 302.

[0063] Figure 6is a flow chart of an enhanced handshaking process according to one embodiment that includes error checking for read data channel 304 and write data channel 306. In response to a successful handshake on either read address channel 300 or write address channel, handshaking on data channels 304, 306 may be invoked.

[0064] At block 600, the source asserts a read valid signal (RVALID) or a write valid (WVALID) signal, which is used to indicate that valid data is available to the source. In one embodiment, subordinates 312 act as the source of data transfer in response to a read request, and the master 310 acts as the sink of the read data. For a write request, the master 310 may be the source of the data to be written, and the subordinates 312 may be the sink.

[0065] In one embodiment, the data to be transferred includes multiple data items based on a single address identified in a read request or a write request transmitted through the read address channel 300 or the write address channel 302. Multiple data items can be transferred in a burst mode in a single transaction. Data items transferred in a burst mode can be referred to as a beat.

[0066] At block 602 , a source sends a data item (beat) via a read data channel 304 or a write data channel 306 , and a receiver receives the sent data item at block 604 .

[0067] Until the last data item associated with the burst is identified, the transmission and reception of the data items in the burst occurs. In this regard, at block 606, the source determines whether the last data has been identified. If the answer is no, the next data item is transmitted and received.

[0068] If the answer is yes, then at block 608, the source determines whether an error is detected for the transmitted data. In this regard, the source can check the response signal from the receiver. If the response signal is a signal indicating no error (e.g., an RREADY signal or a WREADY signal), then at block 610, the source sends the next data burst.

[0069] However, if the response signal from the receiver is a signal indicating an error, the source sends a command at block 612 and the data burst is resent to the destination. In one embodiment, at block 614, the source also increases a burst repetition counter. In one embodiment, the burst repetition counter stores the sequential number (running number) of burst repetitions for a single data transaction. The burst repetition counter can help identify high-frequency attacks (e.g., fault injection attacks) in which an adversary blocks progress in the transmission of a data burst. When a threshold number of burst repetitions is reached due to such an attack, a notification can be sent to an administrator, and / or the FPGA 100 can be disabled. In one embodiment, a successful data transmission before the threshold number is reached resets the burst repetition counter.

[0070] Figure 7 7 is a flow chart of an error detection method by a source 700 for detecting data transmission errors on a read data channel 304 and a write data channel 306 according to one embodiment. In one embodiment, the source 700 stores data items to be transmitted in a burst buffer 702. The data items may be identified based on a read data request or a write data request transmitted via the read address channel 300 or the write address channel 302.

[0071] In one embodiment, source 700 adds parity bits (also called check bits) 704 to each beat of data and sends the padded beats to receiver 706. In one embodiment, the parity bits are selected so that two consecutive parity bits to be added to two consecutive beats of data are complementary to each other (e.g., 01 or 10).

[0072] Source 700 may send data items in burst buffer 702 to receiver 706 via data channels 304, 306. In one embodiment, parity bits are transmitted separately via parity check line 708. Receiver 706 may initiate a parity check function when the last data in a burst is received.

[0073] In one embodiment, the parity check function performs an XOR operation between two consecutive parity bits 710a-710c, and further applies an AND operation to the result of the XOR operation to output a final check result as follows:

[0074]

[0075] Where N is the burst length and is an even number.

[0076] If the value of the check result is 1, as determined in block 712 , no error is detected and the receiver 706 sends an AREADY signal or a WREADY signal to prompt the source 700 to send the next burst 714 .

[0077] If the value of the check result is 0, an error is detected and the receiver 706 sends an error signal to prompt the source 700 to resend 716 the data burst. In this way, the receiver 706 waits for error-free data transmission of the data burst before sending an RREADY signal or a WREADY signal to complete the handshake process on the data channel 304, 306.

[0078] In one embodiment, FPGA100 includes measures for minimizing the possibility of false negative check results. When the data transmitted by data channels 304, 306 is damaged but the parity bit is not damaged, false negatives may occur, causing the check result to take a value of 1, which indicates no error. In order to minimize the possibility of false negatives, the load of parity check line 708 is increased, making parity check line 708 more sensitive to attacks (e.g., fault injection attacks) than data channels 304, 306. In one embodiment, the load of parity check line 708 is increased by connecting the parity check line to a carry chain (e.g., CARRY4) that increases the propagation delay of the parity bit transmission.

[0079] Those skilled in the art will recognize that the system and method for detecting intra-chip communication errors as described herein provides advantages over prior art intra-chip communication protocols by allowing error detection in communications, data recall, and sending alerts for perceived fault injection attacks. Error detection is low cost and does not require additional complex hardware design to resolve the faults.

[0080] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the inventive concept. In addition, unless explicitly stated, the embodiments described herein are not mutually exclusive. The aspects of the embodiments described herein can be combined in some embodiments.

[0081] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, rather than terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art.

[0082] As used herein, the singular form "one" is also intended to include the plural form, unless the context clearly indicates otherwise. It will also be understood that the terms "include" and / or "comprise" when used in this specification, indicate the existence of the stated features, wholes, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. When after the element list, statements such as "at least one of" modify the entire element list without modifying the individual elements of the list. In addition, when describing the embodiments of the present invention, the use of "can" refers to "one or more embodiments of the present disclosure". In addition, the term "exemplary" is intended to refer to an example or example. As used herein, the terms "use", "use of ... " and "used" can be considered to be synonymous with the terms "utilize", "utilize ... " and "utilize" respectively.

[0083] It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or there may be one or more intervening elements or layers. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0084] Although exemplary embodiments of systems and methods for detecting intra-chip communication errors have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that systems and methods for detecting intra-chip communication errors constructed according to the principles of the present disclosure may be embodied in ways other than those specifically described herein. The present disclosure is further defined in the appended claims and their equivalents.

Claims

1. A method for error detection, comprising: Generate a token; applying the token to the request at the source and generating a first result, wherein applying the token to the request comprises comparing the request to the token at the source; sending the request together with the first result to the destination through the address channel; Determining at the destination whether an error associated with the request has occurred, wherein determining whether an error has occurred comprises: receiving, via an address channel, a received request corresponding to the request; receiving the first result together with the received request; applying the token to the received request and generating a second result, wherein applying the token to the received request comprises comparing the received request to the token at the destination; comparing the first result to the second result; and A signal is sent in response to a comparison of the first result and the second result.

2. The method of claim 1, wherein the token is a preset token stored at the source and the destination.

3. The method according to claim 1, wherein the request is one of a request to read data or a request to write data, wherein the request includes an address for reading or writing data, the method further comprising: In response to the request, data is transmitted over a data channel, wherein the data channel is distinct from the address channel.

4. The method of claim 1, wherein applying the token to the request comprises performing an XOR operation between the token and the request, and applying the token to the received request comprises performing an XOR operation between the token and the received request.

5. The method of claim 1, wherein the received request is identical to the request and the signal indicates that there are no errors associated with the request, wherein in response to the signal the source sends a second request over the address channel.

6. The method of claim 1, wherein the received request is different than the request and the signal indicates an error associated with the request, wherein in response to the signal, the source resends the request over an address channel.

7. The method of claim 1, wherein the source and the destination are interfaces of logic blocks of the multi-tenant reconfigurable hardware system.

8. The method of claim 7, wherein the multi-tenant reconfigurable hardware system is a multi-tenant field programmable gate array.

9. The method of claim 3, wherein based on the signal having a first value, error detection is performed on the data channel, and wherein based on the signal having a second value, a property of a processing device is changed.

10. The method according to claim 9, further comprising: A second signal is generated based on performing error detection on the data channel, wherein a property of the processing device is changed based on the second signal having a third value.

11. A reconfigurable hardware system, comprising: A processing chip, comprising a plurality of logic blocks for running a first application and a second application; a communication link for providing communication between the plurality of logic blocks, The processing chip is configured as follows: Generate a token; applying a token to a request at a source and generating a first result, wherein in a processing chip configured to apply the token to the request, the processing chip is configured to compare the request to the token at the source; sending the request and the first result to a destination via an address channel of the communication link; At the destination, determining whether an error associated with the request has occurred, wherein when determining whether the error has occurred, the processing chip is further configured to: receiving, via an address channel, a received request corresponding to the request; receiving the first result together with the received request; applying the token to the received request and generating a second result, wherein in a processing chip configured to apply the token to the received request, the processing chip is configured to compare the received request to the token at the destination; comparing the first result to the second result; as well as A signal is sent in response to a comparison of the first result and the second result.

12. The system of claim 11, wherein the token is a preset token stored at the source and the destination.

13. The system according to claim 11, wherein the request is one of a request to read data or a request to write data, wherein the request includes an address for reading or writing data, and the processing chip is further configured to: In response to the request, data is transmitted over a data channel, wherein the data channel is distinct from the address channel.

14. A system according to claim 11, wherein when the token is applied to the request, the processing chip is also configured to perform an XOR operation between the token and the request, and wherein when the token is applied to the received request, the processing chip is also configured to perform an XOR operation between the token and the received request.

15. The system of claim 11, wherein the received request is identical to the request and the signal indicates that there are no errors associated with the request, wherein in response to the signal the source is configured to send a second request over the address channel.

16. The system of claim 11, wherein the received request is different than the request and the signal indicates an error associated with the request, wherein in response to the signal the source is configured to resend the request over the address channel.

17. The system of claim 11, wherein the source and the destination are interfaces of logic blocks of the multi-tenant reconfigurable hardware system.

18. The system of claim 17, wherein the multi-tenant reconfigurable hardware system is a multi-tenant field programmable gate array.

19. The system of claim 13, wherein based on the signal having a first value, the processing chip is configured to perform error detection on the data channel, and wherein based on the signal having a second value, the processing chip is configured to change a property of a processing device.

20. The system according to claim 19, wherein the processing chip is further configured to: Based on performing error detection on the data channel, a second signal is generated, wherein based on the second signal having a third value, a property of the processing device is changed.

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