A modeling method of a DRAM storage system performance model, a terminal and a medium

Abstract

The application discloses a modeling method of a DRAM storage system performance model, and the method comprises the following steps: building a minimum access system; constructing a memory access scene for simulation, calculating the utilization rate under the memory access scene, and generating a utilization rate lookup table; modeling the utilization rate in the lookup table to perform function fitting, calculating function coefficients, and obtaining a relationship between the utilization rate and the memory access independent variable; changing the memory access independent variable under the memory access scene, re-simulating to obtain a new utilization rate, modeling the new utilization rate to perform function fitting, obtaining a new relationship between the utilization rate and the memory access independent variable, repeatedly performing function fitting to obtain utilization rate functions of multiple independent variables, predicting a real memory access scene, calculating multiple predicted utilization rates by using the utilization rate functions, taking the minimum utilization rate as a predicted read or write utilization rate; and obtaining a predicted performance value under the memory access scene by dividing the theoretical performance by the predicted read or write utilization rate. The modeling method is simple, fast, accurate, and highly adaptable.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a modeling method of a DRAM storage system performance model, a terminal and a medium. BACKGROUND

[0002] In the development process of a chip, for the purpose of developing software in advance, exploring performance, etc., the chip is modeled in advance through a software means to realize a virtual prototype of hardware, also known as a simulator. A model completely simulating the functions of the chip hardware is called a functional model, and a model that can simulate the running time of the chip is called a performance model. For performance simulation, it is mainly divided into on-chip performance simulation and off-chip performance simulation. The off-chip performance simulation mainly corresponds to the memory access performance of a DRAM storage system.

[0003] The common practice of the simulator for the estimation method of the memory access performance of the DRAM is to assume a utilization rate, and the estimated memory access time is obtained by dividing the data amount of the memory access by the bandwidth and the utilization rate. Another estimation method of the memory access performance is to make a detailed modeling of the DRAM, including the behaviors of the DRAM controller and the DRAM grain. The method of estimating the memory access time by the bandwidth and the utilization rate is relatively rough, and the actual different memory access behaviors correspond to very different DRAM utilization rates. The performance evaluation obtained by the method of assuming the utilization rate may be very different from the actual performance, and has little reference value. The method of making a detailed modeling of the DRAM grain and its controller can obtain a relatively accurate performance simulation, but requires very strong professional ability and huge workload, and different generations of DRAM and its controllers have different parameters, such as DDR3, DDR4, LPDDR4, GDDR4, etc. It takes a large team to spend a lot of time to complete such modeling. SUMMARY

[0004] In view of the defects in the prior art, the modeling method of the DRAM storage system performance model, the terminal and the medium provided by the embodiments of the present application are simple, fast and accurate, and have strong adaptability.

[0005] In a first aspect, the present application provides a modeling method of a DRAM storage system performance model, comprising:

[0006] S1: building a minimum access system containing memory access logic, a bus, a DRAM controller and a phy / grain model;

[0007] S2: generating values of the modified memory access transaction generation logic and the control bus interface signal to construct a memory access scene for simulation, wherein the factors affecting the memory access performance in the memory access scene are memory access independent variables, and the memory access scene is a read-only scene;

[0008] S3: calculate the first utilization rate in the read-only scenario, generate a first utilization rate lookup table, model the first utilization rate, perform function fitting, calculate the first function coefficient, and obtain the relationship between the first utilization rate and the memory independent variable;

[0009] S4: change the memory independent variable in the read-only scenario, re-simulate to obtain a second utilization rate, generate a second utilization rate lookup table, model the second utilization rate, perform function fitting, calculate the second function coefficient, and obtain the relationship between the second utilization rate and the memory independent variable;

[0010] S5: repeat step S4 to obtain utilization rate functions of multiple independent variables;

[0011] S6: when predicting a real memory scenario, calculate multiple predicted utilization rates by using the utilization rate functions of the multiple independent variables, compare the obtained multiple predicted utilization rates, and take the smallest utilization rate as a predicted read utilization rate;

[0012] S7: obtain a predicted performance value in the read-only scenario according to a theoretical performance divided by the predicted read utilization rate.

[0013] In a second aspect, an embodiment of the present application provides a modeling method of a DRAM storage system performance model, which comprises:

[0014] S1: build a minimum access system comprising memory access logic, a bus, a DRAM controller, and a phy / particle model;

[0015] S2: simulate according to modified memory transaction generation logic and control bus interface signal values to construct a memory scenario, wherein factors affecting memory performance in the memory scenario are memory independent variables, and the memory scenario is a read-only scenario;

[0016] S3: calculate a third utilization rate in the write-only scenario, generate a third utilization rate lookup table, model the third utilization rate, perform function fitting, calculate a third function coefficient, and obtain the relationship between the third utilization rate and the memory independent variable;

[0017] S4: change the memory independent variable in the write-only scenario, re-simulate to obtain a fourth utilization rate, generate a fourth utilization rate lookup table, model the fourth utilization rate, perform function fitting, calculate a fourth function coefficient, and obtain the relationship between the fourth utilization rate and the memory independent variable;

[0018] S5: repeat step S4 to obtain utilization rate functions of multiple independent variables;

[0019] S6: when predicting a real memory scenario, calculate multiple predicted utilization rates by using the utilization rate functions of the multiple independent variables, compare the obtained multiple predicted utilization rates, and take the smallest utilization rate as a predicted write utilization rate;

[0020] S7: obtain the predicted performance value in the write-only scenario according to the theoretical performance divided by the predicted write utilization.

[0021] In a third aspect, the embodiment of the present application provides a modeling method of a DRAM storage system performance model, which comprises: building a minimum access system comprising a memory access logic, a bus, a DRAM controller and a phy / grain model;

[0022] According to the modified memory access transaction, a numerical value of a control bus interface signal is generated to construct a simulation memory access scenario, wherein a factor affecting the memory access performance in the simulation memory access scenario is a memory access independent variable, and the simulation memory access scenario is a read-write scenario.

[0023] The predicted read utilization is calculated according to the method described in the above embodiment.

[0024] The predicted write utilization is calculated according to the method described in the above embodiment.

[0025] According to the predicted read utilization and the predicted write utilization, a multi-variable function is fitted to obtain a multi-variable function coefficient, and a relationship between the predicted read utilization, the predicted write utilization and the actual read-write utilization is obtained.

[0026] The predicted read-write utilization is calculated according to the relationship between the predicted read utilization, the predicted write utilization and the actual read-write utilization.

[0027] According to the theoretical performance divided by the predicted read-write utilization, a predicted performance value in the read-write scenario is obtained.

[0028] In a fourth aspect, the embodiment of the present application provides an intelligent terminal, which comprises a processor, an input device, an output device and a memory, wherein the processor, the input device, the output device and the memory are connected to each other, the memory is used for storing a computer program, the computer program comprises program instructions, and the processor is configured to invoke the program instructions to execute the method described in the above embodiment.

[0029] In a fifth aspect, the embodiment of the present application provides a computer readable storage medium, which stores a computer program, wherein the computer program comprises program instructions, and the program instructions make a processor execute the method described in the above embodiment when the processor executes the program instructions.

[0030] The present application has the following beneficial effects:

[0031] The embodiment of the present application provides a modeling method of a DRAM storage system performance model, utilization is obtained by simulation according to different memory access scenes, a detailed lookup table is formed, and then utilization formula is obtained by modeling. The estimated utilization is obtained by the utilization formula according to the memory access behavior during simulation of the simulator, and then performance data is obtained. The utilization of the memory access scene is used for inductive modeling, the accuracy problem of the assumed utilization is overcome, and the complex behavior of the DRAM controller and the timing parameter of the DRAM particle do not need to be modeled, so that the modeling method is simple, fast and accurate, and has strong adaptability. The method is not only suitable for modeling of the DRAM storage system, but also can be extended to performance modeling of different types of storage systems.

[0032] The embodiment of the present application provides a kind of intelligent terminal and computer readable storage medium, with the same inventive concept as the modeling method of the general DRAM storage system performance model described above, with the same beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.

[0034] Figure 1 A flow chart of a modeling method of a DRAM storage system performance model provided by the first embodiment of the present application is shown;

[0035] Figure 2 A structure diagram of a minimum memory access system of AXI4 bus protocol is shown;

[0036] Figure 3 A structure diagram of a smart terminal provided by another embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0038] It should be understood that the terms "comprises" and "comprising," when used in this specification and accompanying claims, indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0039] It should also be understood that the terms used in the specification of the application herein are used for the purpose of describing particular embodiments only and are not intended to limit the application. As used in the specification and the appended claims of the application, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0040] It should further be understood that the term "and / or" used in the specification of the application and the appended claims means one or more of the associated listed items as well as all possible combinations of the items and includes the combinations.

[0041] As used in the specification and the appended claims of the application, the term "if' can be interpreted as meaning "when" or "once" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if detected [the described condition or event]" can be interpreted to mean "once determined" or "in response to a determination" or "once detected [the described condition or event]" or "in response to detecting [the described condition or event]" depending on the context.

[0042] It should be noted that unless otherwise specified, technical terms or scientific terms used in the present application should be understood as their common meanings to those skilled in the art to which the present application belongs.

[0043] As Figure 1 shown, a flow chart of a modeling method of a DRAM storage system performance model provided by a first embodiment of the application is shown, which includes simulation and modeling steps, and the specific method includes the following steps:

[0044] S1: build a minimum access system containing access logic, bus, DRAM controller and phy / granular model;

[0045] S2: according to the modified access transaction, generate the numerical value of the logic and control bus interface signal to construct the access scene, the factors affecting the access performance in the access scene are the access independent variables, and the access scene is a read-only scene;

[0046] S3: calculate the first utilization rate under the read-only scene, sort and generate the first utilization rate lookup table, model the first utilization rate, do function fitting, calculate the first function coefficient, and obtain the relationship between the first utilization rate and the access independent variable;

[0047] S4: changing the memory access independent variable in the read-only scenario, re-simulating to obtain a second utilization rate, organizing to generate a second utilization rate lookup table, modeling the second utilization rate to perform function fitting, calculating a second function coefficient, and obtaining a relationship between the second utilization rate and the memory access independent variable;

[0048] S5: repeating step S4 to obtain utilization rate functions of multiple independent variables;

[0049] S6: in the prediction of a real memory access scenario, utilizing the utilization rate functions of the multiple independent variables to calculate multiple predicted utilization rates, comparing the obtained multiple predicted utilization rates, and taking the smallest utilization rate as a predicted read utilization rate;

[0050] S7: obtaining a predicted performance value in the read-only scenario according to the theoretical performance divided by the predicted read utilization rate.

[0051] The simulation process is as follows:

[0052] 1. Building a minimum access system including memory access logic, a bus, a DRAM controller, and a phy / particle model.

[0053] The DRAM controller and the phy / particle model need to be a simulatable chip IP, which is usually purchased from a third-party IP vendor, such as a DDR4 controller / phy. The memory transaction generation logic needs to be written by oneself through a hardware description language such as Verilog, and its interface can be connected to the input of the DRAM controller using a bus protocol such as AXI4. As shown in FIG. 1, a structure diagram of a minimum memory system is shown by taking the AXI4 bus protocol as an example. Figure 2

[0054] In general, a piece of hardware logic is implemented to control the bus interface signals, which are connected to the DRAM controller via the bus interface. The DRAM controller reads and writes the DRAM particles and returns the response after receiving the bus request. This is a minimum memory system, and the waveform is obtained by simulating the EDA simulation tool. The time from the request sent by the bus interface to the end of the response in the waveform is the performance of the memory access. Taking the AXI4 protocol read transaction as an example, the time difference between the first valid ar_valid and the last valid rvalid signal is the performance of the memory access behavior.

[0055] 2. Constructing different memory access scenarios, considering variables such as memory access direction, memory access starting address, burst length, and memory access address jump.

[0056] Different memory access scenarios need to modify the memory transaction generation logic to control the values of the bus interface signals. Taking the AXI4 protocol read transaction as an example, the values of the bus interface signals are controlled by modifying the memory transaction generation logic. Figure 2 ​For example, the AXI4 protocol, ar_valid is read DRAM, aw_valid is write DRAM, ar_addr / aw_addr is the first address of memory access, ar_len / aw_len is the burst length of read / write, that is, the number of read / write shots in one access; When sending multiple read / write requests in succession, ar_len is fixed at 0, and then ar_addr / aw_addr is regularly incremented to control the jump of memory access address. At the same time, reading and writing DRAM will pull up both ar_valid and aw_valid during simulation.

[0057] For example: the minimum memory access system is built, the clock is 1GHz, the bus width is 128bit, and the scene is to continuously read 16KB data from DRAM. The memory access logic configuration interface signal can be controlled: pull up the ar channel related interface signal, assign ar_len=15, that is, the burst length is 16(ar_len+1), the first time ar_valid is pulled up ar_addr=0x0, and then ar_addr is incremented by 16x128 / 8=256 every time ar_valid is pulled up. After the EDA tool simulation is completed, the memory access time is obtained.

[0058] 3、The utilization rate of DRAM is divided into three categories according to the memory access direction: read-only scenario, write-only scenario, and read-write scenario. During simulation, control a single variable and simulate a large number of times to obtain the memory access time, i.e., memory access performance.

[0059] 1) Fix the memory access direction, burst length, and memory access address jump distance, and change the memory access starting address for simulation. Changing the starting address means controlling the value of ar_addr / aw_addr sent by the bus interface for the first time.

[0060] 2) Fix the memory access direction, starting address, and memory access address jump distance, and change the burst length for simulation. Changing the burst length means controlling the value of ar_len / aw_len of the bus interface.

[0061] 3) Fix the memory access direction, starting address, and burst length, and change the address jump distance for simulation. Changing the address jump distance means controlling the increment of ar_addr / aw_addr when ar_valid / aw_valid is continuously sent.

[0062] 4) Change the memory access direction and repeat steps 1) to 3). Changing the memory access direction means pulling up ar_valid or aw_valid.

[0063] 4、Calculate the utilization rate of the above simulation scenarios and classify and organize them.

[0064] Utilization rate = ideal performance / actual performance, actual performance = ideal performance / utilization rate.

[0065] For example, at 1GHz, the bus interface is 128bit, and 16KB data is transmitted, and the ideal performance is 1024ns. If the actual simulation result is 1500ns, the utilization is 1024 / 1500 = 0.68.

[0066] The utilization of the above different scenarios is sorted as follows in Table 1:

[0067] Table 1

[0068]

[0069] The modeling process is as follows:

[0070] 1. Model the read utilization to obtain a read utilization formula.

[0071] Observing the utilization of the read DRAM scenario, generally, certain regularity is presented, such as when the address jumps, the overall utilization is very low, and the larger the jump, the lower the utilization; the larger the burst length, the higher the utilization; when the address offset is a multiple of 0x40, the utilization is relatively high, and in other cases, the utilization is about the same.

[0072] Summarizing these regularities, a segmented method is used to fit the read utilization. In this embodiment, in order to simplify the calculation process, a quadratic function is used for fitting. Assuming that the first address offset is the dominant factor, such as the first address offset is x1, the utilization is y1, and the formula is y1 = a1*x1 2 +b1*x1+c1, the coefficients a1, b1, and c1 are solved to obtain the formula between the utilization and the first address offset. Similarly, the formula between the utilization and the burst length is y2 = a2*x2 2 +b2*x2+c2, and the formula between the utilization and the address jump is y3 = a3*x3 2 +b3*x3+c3.

[0073] Then, for a new read DRAM scenario, the new read DRAM scenario is changed with another memory variable, the address offset, the burst length, and the address jump are solved, and then the utilization is substituted into the above three formulas to obtain y4, y5, and y6, and the minimum value of the three values is taken as the predicted utilization. Finally, the predicted performance value is obtained by dividing the theoretical performance by the predicted utilization.

[0074] 2. Model the write utilization to obtain a write utilization formula.

[0075] The specific modeling method is consistent with the modeling method of the read utilization, and is not described here.

[0076] 3. Model the read-write utilization to obtain a read-write utilization formula.

[0077] In the scenario of reading and writing DRAM simultaneously, it is difficult to directly summarize a formula of predicted utilization rate due to too many variables, so in the embodiment, read utilization rate in the read DRAM scenario and write utilization rate in the write DRAM scenario are analyzed, and then curve fitting is performed according to the simulation results, with the variables being read utilization rate and write utilization rate, and the target being utilization rate of reading and writing simultaneously.

[0078] Specific method: predicted read utilization rate and predicted write utilization rate are respectively obtained by using the read utilization rate formula in the read DRAM scenario and the write utilization rate formula in the write DRAM scenario, and table 2 is formed:

[0079] Table 2

[0080]

[0081]

[0082] Taking predicted read utilization rate as x, predicted write utilization rate as y, and actual read and write utilization rate as z, the equation z=a0*x+a1*x*y+a2*y+a3*x+a4*y+a5 is used for fitting, and coefficients a0-a5 are obtained, that is, a read and write utilization rate formula in the scenario of reading and writing DRAM simultaneously is obtained. 2 2

[0083] After that, for a new read and write DRAM scenario, predicted read utilization rate and predicted write utilization rate are first obtained, and then substituted into the read and write utilization rate formula to obtain predicted read and write utilization rate, and finally the predicted performance in the read and write scenario is obtained by dividing the theoretical performance by the predicted read and write utilization rate.

[0084] The embodiment of the application determines the utilization rate of different memory access behaviors of DRAM by a simulation method, obtains memory access utilization rates in different scenarios, constructs a detailed lookup table, and then models the lookup table to obtain utilization rate formulas in different scenarios. The estimated utilization rate is obtained by using the utilization rate formula according to the memory access behavior during simulation of the simulator, and then performance data is obtained, which can overcome the accuracy problem of the assumed utilization rate, so that the accuracy of the method is high.

[0085] ​​According to the common characteristics of DRAM access, factors affecting DRAM access performance include access direction, access first address, access burst length, access address jump distance, access delay, and DRAM self-refresh time. Among them, the access delay and the DRAM self-refresh time are invariants and are not controlled. In simulation, different access directions, access first addresses, burst lengths, and access address jump distances are used as independent variables to simulate the utilization. Each simulation needs to control a single variable to obtain the utilization. Then, the utilization under different access behaviors obtained by simulation is used to model the read utilization, the write utilization, and the read-write utilization, to obtain the utilization formula under three access directions. When simulating the access behavior, the simulator can calculate the utilization according to the access behavior, and then obtain the time consumed by the current access behavior through the data volume, bandwidth, utilization, and access delay, to obtain the approximate performance result.

[0086] In the embodiment, the main access independent variables in the simulation process are different access directions, access first addresses, burst lengths, and access address jump distances. The independent variables can be simplified or increased according to the specific access behavior characteristics of the chip, for example, if the access path of the chip is only read or write, and there is no read-write access behavior, the read-only and write-only simulation can be performed separately. If the access is always continuous address access, and there is no address jump, the utilization simulation of the access jump can be removed.

[0087] After sufficient utilization data is obtained by simulation, the modeling method of read utilization or write utilization can also be flexible and variable, for example, a polynomial function can be directly established with multiple independent variables as input, the coefficients are obtained after fitting, and the utilization formula of multiple variables is obtained. The utilization can also be predicted by a decision tree, which first determines which independent variable is the dominant factor of performance, and then only substitutes the utilization formula of the independent variable.

[0088] The modeling method of the DRAM storage system performance model provided in the embodiment simulates the utilization of different access behaviors under different access scenarios to obtain a detailed utilization lookup table, and uses the utilization to summarize and model, which can overcome the accuracy problem of the assumed utilization, and does not need to model the complex behavior of the DRAM controller and the timing parameters of the DRAM particles. It is a simple, fast, and accurate modeling method with strong adaptability. It is not only suitable for modeling of DRAM storage systems, but also can be extended to performance modeling of different types of storage systems.

[0089] As Figure 3As shown in FIG. 1, a structural schematic diagram of an intelligent terminal according to another embodiment of the present application is shown, which includes a processor, an input device, an output device and a memory, the processor, the input device, the output device and the memory are connected with each other, the memory is configured to store a computer program, the computer program includes program instructions, and the processor is configured to invoke the program instructions to execute the method described in the above embodiment.

[0090] It should be understood that, in the embodiments of the present application, the processor can be a central processing unit (CPU), and the processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0091] The input device can include a touchpad, a fingerprint acquisition sensor (used to acquire fingerprint information and direction information of a fingerprint of a user), a microphone, etc., and the output device can include a display (LCD, etc.), a speaker, etc.

[0092] The memory can include a read-only memory and a random access memory, and provide the processor with instructions and data. A portion of the memory can also include a non-volatile random access memory. For example, the memory can also store device type information.

[0093] In specific implementations, the processor, the input device and the output device described in the embodiments of the present application can execute the implementation manners described in the method embodiments provided by the embodiments of the present application, and can also execute the implementation manners of the system embodiments described in the embodiments of the present application, which will not be described here.

[0094] The present application also provides an embodiment of a computer readable storage medium, the computer storage medium stores a computer program, the computer program includes program instructions, and the program instructions, when executed by a processor, cause the processor to execute the method described in the above embodiment.

[0095] The computer readable storage medium can be an internal storage unit of the terminal, such as a hard disk or a memory of the terminal. The computer readable storage medium can also be an external storage device of the terminal, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal. Further, the computer readable storage medium can include both the internal storage unit and the external storage device of the terminal. The computer readable storage medium is used to store the computer program and other programs and data required by the terminal. The computer readable storage medium can also be used to temporarily store data that has been output or will be output.

[0096] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0097] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the terminal and the units described above can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0098] In several embodiments provided in the present application, it should be understood that the disclosed terminal and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can also be electrical, mechanical or other forms of connection.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the description of the present application.

Claims

1. A method for modeling a DRAM storage system performance model, characterized in that: include: S1: Build a minimum access system including memory access logic, bus, DRAM controller and phy particle model; S2: constructing a memory access scenario for simulation based on the modified memory access transaction generation logic and the control bus interface signal value, wherein the factors affecting the memory access performance in the memory access scenario are memory access independent variables, and the memory access scenario is a read-only scenario; S3: Calculate a first utilization rate in a read-only scenario, organize and generate a first utilization rate lookup table, model the first utilization rate and perform function fitting, calculate a first function coefficient, and obtain a relationship between the first utilization rate and memory access independent variables; the memory access independent variables include memory access direction, memory access first address, burst length, and memory access address jump distance; S4: In the read-only scenario, change the memory access variable, re-simulate to obtain a second utilization rate, organize and generate a second utilization rate lookup table, model the second utilization rate and perform function fitting, calculate the second function coefficient, and obtain a relationship between the second utilization rate and the memory access variable; S5: Repeat step S4 to obtain utilization functions of multiple different memory access variables; S6: when predicting an actual memory access scenario, using the utilization functions of the multiple different memory access independent variables to calculate multiple predicted utilizations, comparing the multiple predicted utilizations, and taking the smallest utilization as the predicted read utilization; S7: Divide the theoretical performance by the predicted read utilization to obtain the predicted performance value in the read-only scenario.

2. The method according to claim 1, wherein The specific method of modeling the first utilization rate, fitting the function, calculating the first function coefficient, and obtaining the relationship between the first utilization rate and the memory access independent variable includes: Find out the changing pattern of the first utilization rate and the memory access independent variable; The first utilization rate and the memory access independent variable are fitted using a quadratic function to obtain a coefficient of the quadratic function and a relationship between the first utilization rate and the memory access independent variable.

3. The method according to claim 1, wherein The specific method of modeling the first utilization rate, fitting the function, calculating the first function coefficient, and obtaining the relationship between the first utilization rate and the memory access independent variable includes: Find out the changing pattern of the first utilization rate and the memory access independent variable; The first utilization rate and the memory access independent variable are fitted using a polynomial function to obtain coefficients of the polynomial function and obtain a relationship between the first utilization rate and the memory access independent variable.

4. A method for modeling a DRAM storage system performance model, characterized in that: include: S1: Build a minimum access system including memory access logic, bus, DRAM controller and phy particle model; S2: constructing a memory access scenario for simulation based on the modified memory access transaction generation logic and the control bus interface signal value, wherein the factors affecting the memory access performance in the memory access scenario are memory access independent variables, and the memory access scenario is a read-only scenario; S3: Calculate the third utilization rate in the write-only scenario, organize and generate a third utilization rate lookup table, model the third utilization rate and perform function fitting, calculate the third function coefficient, and obtain a relationship between the third utilization rate and memory access independent variables; the memory access independent variables include memory access direction, memory access first address, burst length, and memory access address jump distance; S4: In the write-only scenario, change the memory access independent variable, re-simulate to obtain the fourth utilization, organize and generate a fourth utilization lookup table, model the fourth utilization and perform function fitting, calculate the fourth function coefficient, and obtain a relationship between the fourth utilization and the memory access independent variable; S5: Repeat step S4 to obtain utilization functions of multiple different memory access variables; S6: When predicting an actual memory access scenario, calculate multiple predicted utilizations using the utilization functions of the multiple different memory access independent variables, compare the multiple predicted utilizations, and use the smallest utilization as the predicted write utilization; S7: Divide the theoretical performance by the predicted write utilization to obtain the predicted performance value in the write-only scenario.

5. The method according to claim 4, wherein The specific method of modeling the third utilization rate, fitting the function, calculating the third function coefficient, and obtaining the relationship between the third utilization rate and the memory access independent variable includes: Find out the changing pattern of the third utilization rate and the memory access independent variable; The third utilization rate and the memory access independent variable are fitted using a quadratic function to obtain the coefficient of the quadratic function and obtain a relationship between the third utilization rate and the memory access independent variable.

6. The method according to claim 4, wherein: The specific method of modeling the third utilization rate, performing function fitting, calculating the third function coefficient, and obtaining the relationship between the third utilization rate and the memory access independent variable includes: Find out the changing pattern of the third utilization rate and the memory access independent variable; The third utilization rate and the memory access independent variable are fitted using a polynomial function to obtain coefficients of the polynomial function and obtain a relationship between the third utilization rate and the memory access independent variable.

7. A method for modeling a DRAM storage system performance model, characterized in that: include: Build a minimum access system including memory access logic, bus, DRAM controller and phy particle model; Modifying the memory access transaction generation logic and the value of the control bus interface signal to construct a memory access scenario simulation, wherein the factors affecting the memory access performance in the memory access scenario are memory access independent variables, and the memory access scenario is a simultaneous read and write scenario; Calculating a predicted read utilization rate according to the method according to any one of claims 1 to 3; Calculating a predicted write utilization rate according to the method according to any one of claims 4 to 6; Fitting the predicted read utilization and the predicted write utilization using a multi-independent variable function to obtain coefficients of the multi-independent variable function, and obtaining a relationship between the predicted read utilization, the predicted write utilization, and the actual read and write utilization; Calculate the predicted read and write utilization rate based on the relationship between the predicted read utilization rate, the predicted write utilization rate, and the actual read and write utilization rate; Divide the theoretical performance by the predicted read and write utilization to obtain the predicted performance value in the simultaneous read and write scenario.

8. An intelligent terminal comprising a processor, an input device, an output device, and a memory, wherein the processor, the input device, the output device, and the memory are interconnected, the memory is used to store a computer program, and the computer program includes program instructions, characterized in that: The processor is configured to call the program instructions and execute the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the processor is caused to perform the method according to any one of claims 1 to 7.

Images