Write buffer extension for a storage interface controller

Abstract

This application relates to write buffer extension for a storage interface controller. Devices and methods are presented in which a buffer can be used to temporarily store data from an application while a memory device is in an inactive power mode. This can allow the memory device to remain in a dormant state. The buffer can be located on a host device such that the power mode of the memory device can not affect the buffer. In this way, data can be stored in the buffer without waking up the memory device. If the memory device is in an active power mode, data that has been temporarily stored in the buffer can be sent to the memory device for storage. During a read operation, if requested data is stored in the buffer, the requested data can be used instead of data in the memory device.

Description

[0001] CROSS REFERENCE

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 807,838 to AMBULA et al., filed June 20, 2022, entitled “WRITE BUFFER EXTENSIONS FOR STORAGE INTERFACE CONTROLLERS,” and U.S. Provisional Patent Application No. 63 / 277,354 to AMBULA et al., filed November 9, 2021, entitled “WRITE BUFFER EXTENSIONS FOR STORAGE INTERFACE CONTROLLERS,” each of which is assigned to the assignee hereof and each of which is expressly incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The technical field relates to write buffer extensions for storage interface controllers. BACKGROUND

[0004] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross point memory (3D cross point), or non-volatile (NV) RAM (NVRAM) devices, among others. A memory device can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power source. SUMMARY

[0005] A method is described. The method can include receiving, by a storage interface controller of a host device, data to be written to a storage device; storing, by the storage interface controller, the data to a write buffer of the storage interface controller based at least in part on a power mode of the storage device; retrieving, by the storage interface controller, the data from the write buffer based at least in part on a change to the power mode of the storage device; and sending, by the storage interface controller, the data to the storage device.

[0006] An apparatus is described. The apparatus can include a write buffer and a storage interface controller coupled with the write buffer. The storage interface controller can be to receive data to be written to a storage device; store the data to the write buffer based on a power mode of the storage device; retrieve the data from the write buffer based at least in part on a change to the power mode; and send the data to the storage device.

[0007] An apparatus is described. The apparatus can include a write buffer and a storage interface controller coupled with the write buffer. The storage interface controller can be to receive a plurality of data sets to be written to a storage device; and determine a power mode of the storage device upon receiving each data set of the plurality of data sets. Based on the determined power mode of the storage device being a sleep mode, the storage interface controller can be to store a respective data set in the write buffer; and refrain from waking up the storage device. Based on the determined power mode of the storage device being an active mode, the storage interface controller can be to retrieve data buffered at the write buffer; send the data to the storage device; and send the respective data set to the storage device. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 An example of a system to support write buffer extension for a storage interface controller is shown in accordance with examples disclosed herein.

[0009] Figure 2 An example of a system to support write buffer extension for a storage interface controller is shown in accordance with examples disclosed herein.

[0010] Figure 3 An example of a power mode state diagram to support write buffer extension for a storage interface controller is shown in accordance with examples disclosed herein.

[0011] Figures 4A-4C An example of a set of write data operations to support write buffer extension for a storage interface controller is shown in accordance with examples disclosed herein.

[0012] Figures 5A-5B An example of a set of read data operations to support write buffer extension for a storage interface controller is shown in accordance with examples disclosed herein.

[0013] Figure 6 A block diagram of a memory device to support write buffer extension for a storage interface controller is shown in accordance with examples disclosed herein.

[0014] Figure 7 and 8A flow diagram is shown illustrating a method of supporting a write buffer extension for a storage interface controller in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0015] Many devices use non-volatile memory to store system or application data, and often place the non-volatile memory in a hibernation state when the non-volatile memory is not in use to conserve power. For example, a cell phone can place its non-volatile memory in a hibernation state when no memory accesses have occurred for a certain amount of time (e.g., a few milliseconds), or when the user is not using the cell phone at night. Memory that has been placed in a hibernation state is in an inactive power mode in which memory accesses cannot be made. Once memory is placed in a hibernation state, it must be awakened (e.g., placed in an active power mode) before data on it can be accessed. Some applications need to periodically access data stored on memory, even when the memory is in a hibernation state. For example, an application can periodically store a status or log to memory every minute or so. However, because memory accesses are periodic, between each memory access, the memory can be placed in a hibernation state. Thus, each time the application needs to make a memory access, the memory must be awakened, which can consume additional power. Thus, it can be ironic that placing memory in a hibernation state can waste power if the memory must be frequently awakened for periodic accesses.

[0016] A device and method are presented in which a buffer can be used to temporarily store data from an application when a non-volatile memory device is in a sleep state (in an inactive power mode). This can allow the memory device to remain in a sleep state, so that power is not wasted when it is awakened. The buffer can be located on a host device, so that the power mode of the memory device does not affect the buffer. In this way, data can be stored in the buffer without awakening the non-volatile memory device. Later, when the non-volatile memory device is in an awake state (in an active power mode), the data temporarily stored in the buffer can be sent to the non-volatile memory device for storage. During read operations, if the requested data is stored in the buffer, it can be used instead of data in the non-volatile memory device.

[0017] The features of the present disclosure are first described in the context of the system and device described with reference to Figure 1 and 2 The features of the present disclosure are further described in the context of the state diagrams and sets of operations described with reference to Figures 3-5B and the device diagrams and flow diagrams involving the use of a write buffer extension for a storage interface controller described with reference to Figures 6-8 These and other features of the present disclosure are further illustrated and described in the context of the device diagrams and flow diagrams involving the use of a write buffer extension for a storage interface controller described with reference to

[0018] Figure 1 An example of a system 100 that supports write buffer extension for a storage interface controller is shown in accordance with examples disclosed herein. The system 100 includes a host system 105 coupled with a memory system 110.

[0019] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-Line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0020] The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0021] The system 100 can include a host system 105, which can be coupled with a memory system 110. In some examples, this coupling can include an interface with a host system controller 106, which can be an example of a controller or control component configured to cause the host system 105 to perform various operations in accordance with examples described herein. The host system 105 can include one or more devices, and in some cases can include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 can include an application configured to communicate with the memory system 110 or a device therein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 can use the memory system 110, for example, to write data to the memory system 110 and to read data from the memory system 110. Although Figure 1 One memory system 110 is shown, but the host system 105 can be coupled with any number of memory systems 110.

[0022] The host system 105 can be coupled with the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-enabled DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in, or otherwise supported between, a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 can be coupled with the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled with the memory system controller 115).

[0023] The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 Two memory devices 130-a and 130-b are shown in the example of FIG. 1, but the memory system 110 can include any number of memory devices 130. Moreover, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 can include the same or different types of memory cells.

[0024] The memory system controller 115 can be coupled with and in communication with the host system 105 (e.g., via a physical host interface) and can be an instance of a controller or control component configured to cause the memory system 110 to perform various operations in accordance with the examples described herein. The memory system controller 115 can also be coupled with and in communication with the memory devices 130 to perform operations at the memory devices 130 that can be generally referred to as access operations, such as reading data, writing data, erasing data, or updating data, among other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with the one or more memory devices 130 to execute such commands (e.g., at memory arrays within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effectuate the desired access to the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0025] The memory system controller 115 can be configured for other operations associated with the memory devices 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 130.

[0026] The memory system controller 115 can include hardware, such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware can include circuitry with specialized (e.g., hard-coded) logic to perform operations attributed to the memory system controller 115 herein. The memory system controller 115 can be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 can also include a local memory 120. In some cases, the local memory 120 can include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 can additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, for example, in connection with the functions attributed herein to the memory system controller 115.

[0028] The memory devices 130 can include one or more arrays of non-volatile memory cells. For example, the memory devices 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), resistive memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory devices 130 can include one or more arrays of volatile memory cells. For example, the memory devices 130 can include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some examples, the memory devices 130 can include (e.g., on the same die or within the same package) a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 can operate in conjunction with the memory system controller 115, or can perform one or more functions attributed herein to the memory system controller 115. For example, as shown, the memory device 130-a can include a local controller 135-a, and the memory device 130-b can include a local controller 135-b. Figure 1

[0030] ​In some cases, the memory device 130 can be or include a NAND device (e.g., a NAND flash device). The memory device 130 can be or include a memory die 160. For example, in some cases, the memory device 130 can be a package that includes one or more dies 160. In some examples, a die 160 can be a piece of electronic-grade semiconductor (e.g., a silicon die cut from a silicon wafer) that is cut from a wafer. Each die 160 can include one or more planes 165, and each plane 165 can include a set of respective blocks 170, where each block 170 can include a set of respective pages 175, and each page 175 can include a set of memory cells.

[0031] In some cases, the NAND memory device 130 can include memory cells that are configured to each store one bit of information, which can be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 can include memory cells that are configured to each store multiple bits of information, which can be referred to as multi-level cells (MLCs) if configured to each store two bits of information, triple-level cells (TLCs) if configured to each store three bits of information, quad-level cells (QLCs) if configured to each store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density relative to SLC memory cells, but in some cases, can involve narrower read or write margins or greater complexity for supporting circuitry.

[0032] In some cases, a plane 165 can refer to a group of blocks 170, and in some cases, parallel operations can occur within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170, so long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 can be referred to as physical blocks, and a virtual block 180 can refer to a group of blocks 170 within which parallel operations can occur. For example, parallel operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d can collectively be referred to as a virtual block 180. In some cases, a virtual block can include blocks 170 from different memory devices 130 (e.g., include blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block can have the same block address within their respective planes 165 (e.g., block 170-a can be “block 0” of plane 165-a, block 170-b can be “block 0” of plane 165-b, etc.). In some cases, parallel operations in different planes 165 can be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., in relation to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, a block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., be coupled with) and memory cells in the same string can share a common digit line (which can alternatively be referred to as a bit line) (e.g., be coupled with).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page granularity level), but can be erased at a second granularity level (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be programmed or read independently (e.g., simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be erased independently (e.g., simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Thus, for example, in some cases, a used page 175 can not be updated until the entire block 170 that includes the page 175 has been erased.

[0035] The system 100 can include any number of non-transitory computer- readable media that support write buffer extension for a storage interface controller. For example, the host system 105, the memory system controller 115, or the memory device 130 can include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, such instructions, if executed by the host system 105 (e.g., by the host system controller 106), the memory system controller 115, or the memory device 130 (e.g., by the local controller 135), can cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more of the relevant functions described herein.

[0036] Figure 2 An example of a system 200 that supports write buffer extension for a storage interface controller in accordance with examples disclosed herein is shown. The system 200 can be an example of the system 100 described with reference to Figure 1 or aspects thereof. The system 200 can include a memory device 210 configured to store data received from a host device 205 or send data to the host device 205 when requested by the host device 205 using an access command (e.g., a read command or a write command). The system 200 can implement various aspects of the system 100 described with reference to Figure 1 For example, the host device 205 can be an example of the host system 105 and the memory device 210 can be an example of the memory system 110 or the memory device 130.

[0037] The memory device 210 can be a non-volatile memory device and can include one or more memories 250 described with reference to Figure 1 For example, the memory device 210 can include NAND memory, PCM, self-selecting memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM. The memory 250 can be or include one or more memory dies.

[0038] Memory device 210 can additionally include a storage controller 245 configured to control the direct transfer of data to and from memory device 210, e.g., for storing data, retrieving data, and determining memory locations at which data is stored and from which data is retrieved. Storage controller 245 can be configured to receive data access requests (e.g., read and write requests) from host device 205 via host device interface 235; store data to and retrieve data from memory 250 (e.g., a NAND die) based on the requests; and send data to and receive data from host device 205 via host device interface 235. Memory device 210 can be in an active power mode, in which the memory device is capable of receiving and processing access commands (e.g., read and write commands) from host device 205, and an inactive power mode, in which the memory device is not capable of processing access commands until it is transitioned to the active power mode. As discussed with respect to Figure 3 the active and inactive power modes can each include various states. Memory device 210 can transition from the active power mode to the inactive power mode based on a command received from host device 205 via host device interface 235, or based on one or more timers expiring in the absence of receiving an access command. Storage controller 245 can affect the mode change accordingly, as discussed with respect to the states of Figure 3 For example, storage controller 245 can power up or power down various components of memory device 210, including host device interface 235, portions of storage controller 245, voltage sources, or memory 250.

[0039] The host device 205 can include a host CPU / controller 215 configured to execute host applications. The applications can use data that can be stored at the memory device 210. To access the memory device 210, a storage interface controller 220 can be used. The applications can invoke (e.g., call) one or more software routines of a device driver 218 associated with the storage interface controller 220 (e.g., using an application layer or a service layer) to store or obtain data corresponding to a virtual address space. Based on the invoked software routines of the associated device driver 218, the storage interface controller 220 can be configured to perform read and write commands at a lower communication layer by communicating with the memory device 210 via a memory device interface 230. The memory device interface 230 can be coupled with a host device interface 235 of the memory device 210 and configured to transfer requests and data, as well as other control signals (e.g., state change commands) therebetween. The storage interface controller 220 can access the memory device 210 according to a logical address space that is the same as or different from the virtual address space. For example, the storage interface controller 220 can translate one or more virtual address spaces used by the applications to a logical address space of the memory device 210.

[0040] In some examples, the storage interface controller 220 can control power modes and states of the memory device 210, as discussed in Figure 3

[0041] The host device 205 can further include a buffer 225 coupled with the storage interface controller 220. The storage interface controller 220 can be configured to store and obtain data at a lower communication layer using the buffer 225 in certain situations where the memory device can be in a sleep state. Because the buffer 225 can be on the host device 205, the buffer 225 can be available to the storage interface controller 220 even if the memory device 210 can be in a sleep state. In some examples, the buffer 225 can be physically separate from the storage interface controller 220. In some examples, the buffer 225 can be located on or otherwise incorporated into the storage interface controller 220. In some examples, the buffer 225 can be in a portion of memory (e.g., volatile memory) on the host device 205, but held in a separate region (e.g., that can be specifically allocated for use by the storage interface controller 220). The applications and host CPU / controller 215 can also use memory on the host device 205, but can not directly access the buffer 225. The buffer 225 can also be referred to herein as a write buffer.

[0042] ​To store data received from an application of the host CPU / controller 215 (e.g., when invoked by a device driver), the storage interface controller 220 can send the application data and associated virtual addresses to the memory device 210 (e.g., via a write command) if the memory device is in a wake state (e.g., in an active power mode). If the memory device 210 is in a sleep state (e.g., in an inactive power mode), the storage interface controller 220 can store the application data in the buffer 225. If the buffer 225 is full (e.g., there is not enough space available to store the data), the storage interface controller 220 can first wake up the memory device (e.g., place the memory device in an active state) and then send the data and logical addresses of the data to the memory device. The storage interface controller 220 can also send (e.g., move or transfer) the application data to the memory device 210 (e.g., via a write command) along with the data and associated logical addresses that have been stored in the buffer 225. In some examples, the buffer data and logical addresses can be automatically sent to the memory device whenever the memory device 210 becomes awake.

[0043] To retrieve application data of the host CPU / controller 215 (e.g., when invoked by a device driver), the storage interface controller 220 can determine whether to obtain the requested data from the buffer 225 (e.g., if the data is stored therein) or from the memory device 210 (e.g., via a read command), waking up the memory device first if the memory device 210 is in a sleep state.

[0044] Figure 3 An example of a power mode state diagram 300 to support write buffer extension for a storage interface controller is shown in accordance with examples disclosed herein. The power mode state diagram 300 can apply to the memory device 210, which can be the memory device described with reference to Figure 2 The memory device 210 of Figure 2 will be used for purposes of this discussion, but any type of memory device can be used. In some examples, the power mode state diagram 300 can illustrate an example set of power states associated with a memory device to support write buffer extension for a storage interface controller. For example, the power mode state diagram 300 depicts power states of a memory device during operation of a host device. In some examples, the storage controller 245 controls the power states of the memory device.

[0045] The memory device can be in either an "awake state" or a "sleep state," as shown in the power mode state diagram 300. The active state 310 and the idle state 315 can correspond to the memory device being in the awake state. The hibernate state 320, the power down state 325, and the deep power down state 330 can correspond to the memory device being in the sleep state. The more or less power states can alternatively correspond to the memory device being in the awake state or the sleep state. When the memory device is awake, it can be considered to be in an active power mode. That is, if the memory device is in the active state 310 or the idle state 315, the memory device can be considered to be in the awake state and in the active power mode. If the memory device is in the sleep state, it can be considered to be in an inactive power mode. That is, if the memory device is in the hibernate state 320, the power down state 325, or the deep power down state 330, the memory device can be considered to be in the sleep state and in the inactive power mode. Waking up the memory device means placing the memory device in one of the power states corresponding to the active power mode. Placing the memory device in the hibernate state means placing the memory device in one of the power states corresponding to the inactive power mode.

[0046] The memory device can be commanded into any power state by the host device (e.g., by the storage interface controller 220 of the host device 205). In some cases, the host device can send a change state command to the storage controller 245 (e.g., via the memory device interface 230 and the host device interface 235) along with an indication of the state to enter. For example, the storage interface controller 220 can send a change state command to the memory device with a state indicator (Ind) of "1," "2," "3," or "4." The storage controller 245 can receive the command and transition the memory device to the active state 310, the hibernate state 320, the power down state 325, or the deep power down state 330, respectively.

[0047] If the memory device is in the awake state, three memory device components (e.g., the memory 250, the storage controller 245, and the host device interface 235) can be powered on. As such, the memory device can be ready to read or write to the memory when a request is received from the host device (e.g., from the storage interface controller 220).

[0048] In the active state 310, the memory device can process read or write commands received from a host device (e.g., from the memory controller 245). In the idle state 315, the memory device may not process read or write commands from the host device, but may be ready to receive such requests. In some cases, the memory device may automatically move between the idle state 315 and the active state 310 depending on whether a read command or a write command is being processed. Upon initial power-on 305, the memory device may wake up in either the active state 310 or the idle state 315. In some cases, if the memory device is in continuous use, the memory device may generally remain awake (e.g., in the active state 310 or the idle state 315).

[0049] In some examples, the host device can (e.g., via memory device interface 230 and host device interface 235) place the memory device in a sleep state during times when the memory device is rarely or not in use. In some examples, the expiration of a timer can be used to place the memory device in a sleep state. For example, if no command is received within a certain amount of time, the timer can expire, causing the memory to be automatically placed in a sleep state. While in the sleep state, power to one or more of the three memory device components (e.g., memory 250, memory controller 245, or host device interface 235) can be removed or reduced (e.g., by memory controller 245) to conserve power.

[0050] In the dormant state 320, power to the memory of the memory device can be removed or reduced, while the memory controller and the host device interface can continue to be powered. When the memory device is in the dormant state 320, the memory controller can determine when a request to change state is received from the host device and can affect the change accordingly. For example, to wake up the memory device (e.g., to transition the memory device to the active state 310), the memory controller can power on the memory of the memory device. While the memory is powered on, the memory controller can process information received from the host device via the host device interface. If the memory device subsequently receives a read or write command, the memory controller can access the memory.

[0051] In the powered down state 325, power to both the storage controller (e.g., at least a portion of the storage controller) and the memory can be removed or reduced, while the host device interface can continue to be powered. While the memory device is in the powered down state 325, the storage controller can determine when a request to change state is received from the host device (e.g., via the host device interface) and can affect the change accordingly. For example, to wake up the memory device (e.g., transition the memory device to the active state 310), the storage controller can power up the memory or any portion of the storage controller that was powered down. Once the storage controller is powered up, it can process information received from the host device via the host device interface. If the memory device subsequently receives a read or write command, the storage controller can access the memory.

[0052] In the deep powered down state 330, power to the storage controller, the memory, and the host device interface can be removed or reduced. Without power, the host device interface can not forward a request to change state to the storage controller when the request is received from the host device. Thus, the storage controller can not affect a change in state (e.g., the host device interface can not power up components of the memory device) while in the deep powered down state 330. Thus, the memory device can not wake up directly from the deep powered down state 330 (e.g., transition directly to the active state 310); to wake up the memory device from the deep powered down state 330 (e.g., transition the memory device back to the active state 310), a typical power cycle of the memory device can be performed.

[0053] In some examples, the power states of the power mode state diagram 300 can correspond to UFS power mode states. For example, the hibernate state 320, the powered down state 325, and the deep powered down state 330 can correspond to a UFS hibernate state, a UFS powered down state, and a UFS deep hibernate state, respectively.

[0054] Figures 4A-4C An example is shown that supports a set of write data operations for a write buffer extension for a storage interface controller in accordance with examples disclosed herein. Process flows 401, 402, and 403 can be performed by the host device 205 and the memory device 210, which can be the host device and memory device referenced with respect to FIGS. 1-3. Figure 2Respective examples of the host device and memory device are described. Operations associated with the application 406, the storage interface controller 407, and the buffer 408 can be performed at the host device 205 by the host CPU / controller 215, the storage interface controller 220, and the buffer 225, respectively. In some examples, the process flows 401, 402, and 403 can illustrate example sequences of operations performed to support write buffer extension for a storage interface controller. For example, the process flows 401, 402, and 403 depict operations to write data associated with a write command to a buffer at the host or to a memory device depending on whether the memory device is in an awake state or a sleep state.

[0055] Using the process flows 401, 402, and 403, a software routine to store data can be invoked by an application of the host CPU / controller and can be handled by the storage interface controller such that application data can be sent to a buffer for temporary storage if the memory device is in a sleep state or to the memory device if the memory device is in an awake state or the buffer is full (e.g., there is not enough available space to store the data). If the memory device is in a sleep state, the memory device can be first awakened. Data that has been stored in the buffer can be transferred to the memory device along with the application data.

[0056] The operations described in each of the process flows 401, 402, and 403 can be performed earlier or later in the process; can be omitted, replaced, or supplemented; or can be combined with another operation in the process. Additionally, additional operations not included in the process flows 401, 402, and 403 can be included as described herein.

[0057] Turning to the process flow 401, at block 405, a software routine to store data can be invoked by an application 406 executing on the host device. In some examples, the software routine can be a call to a device driver of the storage interface controller 407.

[0058] At arrow 410, the application data and associated virtual addresses can be made available to the storage interface controller 407 by or in response to the invoked routine (e.g., using an application layer or a service layer). In some examples, the virtual addresses can correspond to logical addresses of the application data. Alternatively, the storage interface controller 407 can perform address translation from one or more virtual address spaces used by the application to a logical address space of the memory device 210.

[0059] At block 415, when the application invokes the software routine, the storage interface controller 407 can determine that the memory device 210 is in an inactive power mode (e.g., as described with respect to FIG. 2). In some examples, the storage interface controller 407 can determine that the memory device 210 is in an inactive power mode based on a signal from the memory device 210 or based on a lack of a signal from the memory device 210. Figure 3sleep state 320, powered-off state 325, or deep powered-off state 330). In some cases, to determine the power mode of the memory device 210, the storage interface controller 407 can query the memory device 210 via the interface circuit (e.g., the memory device interface 230 and the host device interface 235). Alternatively, the storage interface controller 407 can maintain an indicator of the current power mode of the memory device 210.

[0060] At arrow 425, upon determining that the memory device 210 is in an inactive power mode, the storage interface controller 407 can store the application data received from the application program in the buffer 408. The application data can be temporarily stored in the buffer 408 until the data can be moved (e.g., written) to the memory device 210 when the memory device 210 is in an active power mode, as discussed with reference to process flow 402 and 403. The associated virtual (or logical) addresses can also be stored in the buffer 408. In some instances, the associated virtual or logical addresses can be stored in the buffer 408 with the application data. Alternatively, the associated virtual or logical addresses can be stored in a table that points to the location in the buffer where the application data is stored. In some cases, the storage interface controller 407 can notify the device driver that the invoked routine has completed. Accordingly, the application program 406 can continue in accordance with the successful operation of the device driver associated with the storage interface controller 407 by the invoked routine.

[0061] In some cases, as shown in block 420, the storage interface controller 407 can first determine whether the buffer 408 is full (e.g., does not have enough available space to store the application data) before deciding whether to temporarily store the data in the buffer 408, and if the buffer 408 is not full, the data can be temporarily stored in the buffer 408 (process flow 402 describes operations that can be performed in the case that the buffer 408 is full). In some cases, the storage interface controller 407 can determine whether the buffer 408 is full based on a threshold. In some cases, the storage interface controller 407 can determine that the buffer 408 is not full by determining that the buffer 408 has enough space for the application data. In some cases, the storage interface controller 407 can determine that the buffer 408 is not full by determining that the amount of data stored in the buffer 408 does not satisfy (e.g., is less than) a threshold.

[0062] Turning to process flow 402, at block 430, while obtaining application data from the application 406 (as discussed in process flow 401 at arrow 410) and determining that the memory device 210 is in the inactive power mode (as discussed in process flow 401 at block 415), the storage interface controller 407 can determine that the buffer 408 is full. In some cases, the storage interface controller 407 can determine that the buffer 408 is full by determining that the buffer 408 does not have enough space for the application data. In some cases, the storage interface controller 407 can determine whether the buffer 408 is full based on a threshold. In some cases, the storage interface controller 407 can determine that the buffer 408 is full by determining that an amount of data stored in the buffer 408 satisfies (e.g., is greater than or equal to) the threshold.

[0063] At arrow 435, upon determining that the buffer 408 is full, the storage interface controller 407 can wake up the memory device 210 by placing the memory device 210 in the active power mode. In some cases, the storage interface controller 407 can send a wake-up signal (e.g., a request to change to the active state 310, as discussed with respect to FIG. 3) to the memory device 210 (e.g., via the memory device interface 230 and the host device interface 235) to move the memory device 210 to the active power mode (e.g., to the active state 310). This can cause the memory device 210 to wake up and move to the active power mode. In some examples, in response to the wake-up signal, if the memory device 210 is in the wake-up state and in the active power mode, the memory device 210 can send an indicator to the storage interface controller 407. In some cases, the storage interface controller 407 can receive the indicator via the memory device interface 230. Figure 3

[0064] At arrow 445, after waking up the memory device 210 (placing the memory device in the active power mode), the storage interface controller 407 can send (e.g., via a write command) the application data and the associated logical address to the memory device 210 to store the application data. In some cases, the write command can be sent to the memory device 210 via the interface circuit (e.g., the memory device interface 230 and the host device interface 235). The memory device can map the logical address to a physical address in the memory of the memory device 210 and store the data at the physical address.

[0065] ​At arrows 450 and 455, the storage interface controller 407 can retrieve the data that has been temporarily stored in the buffer 408 and send the buffer data to the memory device 210 for storage (e.g., via one or more write commands). In some cases, the one or more write commands can be sent to the memory device 210 along with the buffer data and associated virtual (e.g., logical) addresses via the interface circuitry (e.g., the memory device interface 230 and the host device interface 235). The memory device 210 can map the logical addresses to physical addresses in the memory of the memory device 210 and store the buffer data at the physical addresses. In some cases, the storage interface controller 407 can retrieve the data from the buffer 408 and send the buffer data to the memory device 210. In some cases, the data can be sent directly from the buffer 408 to the memory device 210, bypassing the storage interface controller 407. The buffer data can be sent to the memory device 210 before or after the application data. In some cases, if the buffer data is sent to the memory device 210 after the application data, the storage interface controller 407 can remove the buffer data associated with the same logical addresses as the application data (e.g., not sent to the memory device). In this way, older buffer data can not overwrite newer application data that has just been stored in the memory device 210.

[0066] At arrow 460, after the buffer data and the application data have been sent to the memory device 210, the storage interface controller 407 can optionally place the memory device 210 in a hibernated state. In some cases, the storage interface controller 407 can send a hibernate signal to the memory device 210 (e.g., via the memory device interface 230 and the host device interface 235) to move the memory device 210 to an inactive power mode (e.g., the hibernated state 320, the powered-off state 325, or the deep powered-off state 330, as discussed with respect to FIG. 3). In some cases, the storage interface controller 407 can command the memory device 210 to move to the power state that the memory device 210 was in prior to the storage interface controller 407 waking the memory device 210. Alternatively, the storage interface controller 407 can refrain from placing the memory device 210 in a hibernated state (e.g., allowing the memory device to remain awake in an active power mode). Figure 3

[0067] At optional block 465, the data in the buffer 408 that was sent to the memory device 210 for storage can be cleared. Otherwise, the buffer data can remain in the buffer 408, but can be overwritten by new data as new data is subsequently written to the buffer 408.

[0068] ​Turning to process flow 403, at block 470, when application data is obtained from the application 406 (as discussed at arrow 410 in process flow 401), the storage interface controller 407 can determine that the memory device 210 is in an active power mode (e.g., in a wake state under active state 310 or idle state 315) rather than an inactive power mode. In some cases, to determine the power mode of the memory device 210, the storage interface controller 407 can query the memory device 210 via the interface circuitry (e.g., the memory device interface 230 and the host device interface 235).

[0069] At arrow 475, upon determining that the memory device 210 is in an active power mode, the storage interface controller 407 can send the application data to the memory device 210 (e.g., via a write command). The write command can include the application data and an associated logical address. In some cases, the write command can be sent to the memory device 210 via the interface circuitry. The memory device 210 can map the logical address to a physical address in the memory of the memory device 210 and store the data at the physical address.

[0070] At arrows 480 and 485, the storage interface controller 407 can retrieve the data that has been temporarily stored in the buffer 408 and send the buffer data to the memory device 210 for storage in a similar manner as discussed at arrows 450 and 455. The buffer data can be sent to the memory device 210 before or after the application data, as discussed at arrows 450 and 455.

[0071] At optional block 490, the data in the buffer 408 that was sent to the memory device for storage can be cleared. Alternatively, the buffer data can remain in the buffer 408, but can be overwritten by new data as new data is subsequently written to the buffer 408.

[0072] Figures 5A-5B An example is shown that supports a set of read data operations for a write buffer extension of a storage interface controller in accordance with examples disclosed herein. Process flows 501 and 502 can be performed by the host device 205 and the memory device 210, which can be the host device 205 and the memory device 210 referenced with respect to FIGS. 1-4. Figure 2Respective examples of the host device and memory device are described. Operations associated with the application 506, the storage interface controller 507, and the buffer 508 can be performed at the host device 205 by the host CPU / controller 215, the storage interface controller 220, and the buffer 225, respectively. In some examples, process flows 501 and 502 can illustrate example sequences of operations performed to support a write buffer extension for a storage interface controller. For example, process flows 501 and 502 depict operations to read data associated with a read command from either the buffer at the host or the memory device, depending on whether the memory device is in an awake state or a sleep state.

[0073] Using process flows 501 and 502, a software routine to obtain data can be invoked by an application of the host CPU / controller, and can be handled by the storage interface controller, such that the requested data can be obtained from the buffer (if stored therein) or from the memory device. If the requested data is not in the buffer, the memory device can first be awakened if it is in a sleep state prior to obtaining data from the memory device.

[0074] The operations described in each of process flows 501 and 502 can be performed earlier or later in the process; can be omitted, replaced, or supplemented; or can be combined with another operation in the process. Additionally, additional operations not included in process flows 501 and 502 can be included as described herein.

[0075] Turning to process flow 501, at block 505, a software routine to obtain data can be invoked by the application 506 executing on the host device. In some examples, the software routine can be a call to a device driver of the storage interface controller 220.

[0076] At arrow 510, virtual addresses associated with the application data can be made available to the storage interface controller 507 by or in response to the invoked routine (e.g., using an application layer or a service layer). In some examples, the virtual addresses can correspond to logical addresses of the memory device 210, or the storage interface controller 507 can translate the virtual addresses to logical addresses.

[0077] At block 515, when the application 506 calls the software routine, the storage interface controller 507 can determine that the requested data is stored in the buffer 508. In some examples, the storage interface controller 507 can determine that the requested data is stored in the buffer 508 by determining that data associated with the virtual (or logical) address of the read routine is stored in the buffer 508. In some examples, the associated virtual address or logical address can be stored with the data in the buffer 508. Alternatively, the associated virtual address or logical address can be stored in a separate table (e.g., in the buffer 508) that points to the location in the buffer 508 where the data is stored.

[0078] At arrow 520, upon determining that the requested data is temporarily stored in the buffer 508, the storage interface controller 507 may obtain the requested data from the buffer 508. In some examples, the storage interface controller 507 may obtain the requested data by obtaining data associated with a virtual (or logical) address associated with the requested data from the buffer 508.

[0079] At arrow 525, storage interface controller 507 may make the obtained data available to application 506. In some examples, storage interface controller 507 may make the requested data available to application 506 using an application layer or a service layer (eg, via a device driver).

[0080] Turning to process flow 502, at block 530, upon obtaining the virtual address from application 506 (as discussed at arrow 510 in process flow 501), storage interface controller 507 may determine that the requested data is not temporarily stored in buffer 508. In some examples, storage interface controller 507 may determine that the requested data is not stored in buffer 508 by determining that a virtual (or logical) address associated with a read routine is not stored in buffer 508.

[0081] At block 535, upon determining that the requested data is not temporarily stored in the buffer 508, the storage interface controller 507 may determine whether the memory device 210 is in an active power mode (e.g., in the active state 310 or the idle state 315) or in an inactive power mode (e.g., the sleep state 320, the power-off state 325, or the deep power-off state 330). In some cases, to determine the power mode of the memory device 210, the storage interface controller 507 may query the memory device 210 via interface circuitry (e.g., the memory device interface 230 and the host device interface 235).

[0082] At arrow 540, if the storage interface controller 507 determined at block 535 that the memory device 210 is in the inactive power mode, the storage interface controller 507 can wake up the memory device 210 in a similar manner as discussed at arrow 435 of process flow 402 to place the memory device 210 in the active power mode. Alternatively, if the storage interface controller 507 determined at block 535 that the memory device 210 is in the active power mode (e.g., in the awake state under the active state 310 or the idle state 315), the storage interface controller 507 can skip this operation. That is, if the memory device 210 is already awake, the storage interface controller 507 can refrain from waking up the memory device 210.

[0083] At arrow 550, once the memory device 210 is awake (in the active power mode), the storage interface controller 507 can obtain the requested data from the memory device 210. In some examples, the storage interface controller 507 can obtain the requested data by sending a read command to the memory device 210 and then receiving the data from the memory device 210. The read command can include a logical address associated with the requested data.

[0084] At arrow 555, the storage interface controller 507 can make the obtained data available to the application 506. In some examples, the storage interface controller 507 can use an application layer or a service layer (e.g., via a device driver) to make the requested data available to the application 506.

[0085] At arrow 560, after the storage interface controller 507 has obtained the requested data from the memory device 210, the storage interface controller 507 can optionally place the memory device 210 back to sleep (to the inactive power mode), as discussed at arrow 460 of Figure 4B Alternatively, the storage interface controller 507 can refrain from placing the memory device 210 to the sleep state.

[0086] Process flows 501 and 502 can include further operations not shown therein. For example, after the memory device 210 has been woken up to the active power mode, the data that has been temporarily stored in the buffer 508 can be sent to the memory device 210 for storage. After the requested data has been made available to the application 506 at 555, the storage interface controller 507 can retrieve the data that has been temporarily stored in the buffer 508 and send the buffer data to the memory device 210 for storage in a similar manner as discussed at arrows 450 and 455 of Figure 4B

[0087] ​In some examples, the buffer 508 can not be addressable according to the virtual or logical addresses of the data. (For example, there can not be a cache or content addressable memory capability that can be queried by the associated address.) In these cases, to determine whether the data is in the buffer, it can be necessary to look at every address of the buffer, which can be relatively slow. However, if the memory device 210 has been woken up, the data stored in the buffer 508 can have been moved to the memory device 210, so it can not be necessary to look at the buffer. Thus, if the memory device 210 is in the wake-up state, the storage interface controller 507 can obtain data from the memory device 210 more quickly without first determining whether the data is in the buffer 508. This can speed up the obtaining of data from the memory device 210.

[0088] Thus, in some examples, after obtaining the virtual address, the storage interface controller 507 can bypass looking at the buffer 508 (block 515 or block 530) and first determine the power mode of the memory device 210 (block 535). If the determined power mode is the active power mode, the storage interface controller 507 can obtain the data from the memory device 210 (arrows 545 and 550). If the determined power mode is the inactive power mode, the storage interface controller 507 can then look at the buffer 508. If the requested data is stored in the buffer 508 (block 515), the storage interface controller 507 can obtain the data from the buffer 508 (arrow 520). If the requested data is not stored in the buffer 508 (block 530), the storage interface controller 507 can wake up the memory device 210 (arrow 540) and obtain the data from the memory device 210 (arrows 545 and 550).

[0089] Figure 6 A block diagram 600 of a memory device 620 that supports write buffer extension for a storage interface controller in accordance with examples as disclosed herein is shown. The memory device 620 can be an example of aspects of the memory devices described with reference to Figure 1 FIGS. 1 through 5. The memory device 620, or various components thereof, can be an example of means for performing various aspects of write buffer extension for a storage interface controller as described herein. For example, the memory device 620 can include a host application I / O component 625, a write buffer manager 630, a stored data manager 635, a power mode manager 640, or any combination thereof. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0090] The host application I / O component 625 can be configured as or otherwise support means for receiving, by a storage interface controller of a host device, data to be written to a storage device. The write buffer manager 630 can be configured as or otherwise support means for storing, by the storage interface controller, the data to a write buffer of the storage interface controller based at least in part on a power mode of the storage device. The write buffer manager 630 can be configured as or otherwise support means for retrieving, by the storage interface controller, the data from the write buffer based at least in part on a change to the power mode of the storage device. The store data manager 635 can be configured as or otherwise support means for sending, by the storage interface controller, the data to the storage device.

[0091] In some examples, the power mode manager 640 can be configured as or otherwise support means for determining, by the storage interface controller, whether the power mode of the storage device is an inactive power mode upon receiving the data. In some examples, the write buffer manager 630 can be configured as or otherwise support means for storing, by the storage interface controller, the data to the write buffer based at least in part on determining that the power mode of the storage device is the inactive power mode. In some examples, the power mode manager 640 can be configured as or otherwise support means for refraining from waking the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode.

[0092] In some examples, to support moving the data from the write buffer to the storage device, the power mode manager 640 can be configured as or otherwise support means for determining, by the storage interface controller, whether the power mode of the storage device has changed to an active power mode. In some examples, to support moving the data from the write buffer to the storage device, the store data manager 635 can be configured as or otherwise support means for moving, by the storage interface controller, the data from the write buffer to the storage device based at least in part on determining that the power mode of the storage device has changed to the active power mode.

[0093] In some examples, storing the data to the write buffer can be further based at least in part on an amount of additional data stored in the write buffer.

[0094] In some examples, the write buffer manager 630 can be configured as or otherwise support means for determining, by the storage interface controller, whether an amount of data stored in the write buffer satisfies a threshold when additional data to be written to the storage device is received. In some examples, the power mode manager 640 can be configured as or otherwise support means for determining, by the storage interface controller, whether a power mode of the storage device is an inactive power mode. In some examples, the power mode manager 640 can be configured as or otherwise support means for waking up the storage device, by the storage interface controller, based at least in part on determining that the power mode of the storage device is the inactive power mode and determining that the amount of data stored in the write buffer satisfies the threshold, where moving the data from the write buffer to the storage device is performed after waking up the storage device. In some examples, the power mode manager 640 can be configured as or otherwise support means for commanding the storage device to return to the inactive power mode after moving the data from the write buffer to the storage device.

[0095] In some examples, the host application I / O component 625 can be configured as or otherwise support means for receiving, at the storage interface controller, a request from an application of the host device to read data associated with an address of the storage device. In some examples, the write buffer manager 630 can be configured as or otherwise support means for determining, by the storage interface controller, whether the data associated with the address is stored in the write buffer. In some examples, the write buffer manager 630 can be configured as or otherwise support means for retrieving, by the storage interface controller, the data associated with the address from the write buffer based at least in part on determining that the data associated with the address is stored in the write buffer. In some examples, the host application I / O component 625 can be configured as or otherwise support means for sending, by the storage interface controller, the data associated with the address to the application of the host device.

[0096] In some examples, the host application I / O component 625 can be configured as or otherwise support means for receiving, at the storage interface controller from an application of the host device, a request to read data associated with an address of the storage device. In some examples, the write buffer manager 630 can be configured as or otherwise support means for determining, by the storage interface controller, that the data associated with the address is not stored in the write buffer. In some examples, the storage data manager 635 can be configured as or otherwise support means for retrieving, by the storage interface controller from the storage device, the data associated with the address. In some examples, the host application I / O component 625 can be configured as or otherwise support means for sending, by the storage interface controller, the data associated with the address to the application of the host device.

[0097] In some examples, the power mode manager 640 can be configured as or otherwise support means for determining, by the storage interface controller, whether a power mode of the storage device is an inactive power mode. In some examples, the power mode manager 640 can be configured as or otherwise support means for waking, by the storage interface controller, the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode, where retrieving the data associated with the address from the storage device is performed after waking the storage device. In some examples, the power mode manager 640 can be configured as or otherwise support means for commanding, after retrieving the data associated with the address from the storage device, the storage device to return to the inactive power mode.

[0098] The host application I / O component 625 can be configured as or otherwise support means for receiving, by a storage interface controller of a host device, a plurality of data sets to be written to a storage device, the host device including a write buffer associated with the storage interface controller. The power mode manager 640 can be configured as or otherwise support means for determining, upon receipt by the storage interface controller of each data set of the plurality of data sets, a power mode of the storage device. The write buffer manager 630 can be configured as or otherwise support means for storing, by the storage interface controller, a respective data set in the write buffer associated with the storage interface controller based on the determined power mode of the storage device being an inactive power mode. The power mode manager 640 can be configured as or otherwise support means for refraining, by the storage interface controller, from waking up the storage device based on the determined power mode of the storage device being the inactive power mode. The write buffer manager 630 can be configured as or otherwise support means for retrieving, by the storage interface controller, data buffered at the write buffer based on the determined power mode of the storage device being an active power mode. The stored data manager 635 can be configured as or otherwise support means for sending, by the storage interface controller, the buffered data to the storage device based on the determined power mode of the storage device being the active power mode. The stored data manager 635 can be configured as or otherwise support means for sending, by the storage interface controller, a respective data set to the storage device based on the determined power mode of the storage device being the active power mode.

[0099] In some examples, the respective data set can include the first data set. In some examples, the host application I / O component 625 can be configured as or otherwise support means for receiving a second data set to be written to the storage device, the second data set not including the plurality of data sets. In some examples, the power mode manager 640 can be configured as or otherwise support means for determining a power mode of the storage device based at least in part on receiving the second data set. In some examples, the power mode manager 640 can be configured as or otherwise support means for waking up the storage device based on the determined power mode of the storage device being an inactive power mode and an amount of data stored in the write buffer exceeding a threshold. In some examples, the write buffer manager 630 can be configured as or otherwise support means for retrieving the first data set from the write buffer based on the determined power mode of the storage device being an inactive power mode and the amount of data stored in the write buffer exceeding the threshold. In some examples, the stored data manager 635 can be configured as or otherwise support means for sending the first data set to the storage device based on the determined power mode of the storage device being an inactive power mode and the amount of data stored in the write buffer exceeding the threshold. In some examples, the stored data manager 635 can be configured as or otherwise support means for sending the second data set to the storage device based on the determined power mode of the storage device being an inactive power mode and the amount of data stored in the write buffer exceeding the threshold. In some examples, the power mode manager 640 can be configured as or otherwise support means for returning the storage device to a hibernation state based on the determined power mode of the storage device being an inactive power mode and the amount of data stored in the write buffer exceeding the threshold.

[0100] In some examples, the host application I / O component 625 can be configured as or otherwise support means for receiving a request to read a data set associated with an address of the storage device. In some examples, the write buffer manager 630 can be configured as or otherwise support means for determining that the data set associated with the address is not stored in the write buffer. In some examples, the stored data manager 635 can be configured as or otherwise support means for retrieving the data set associated with the address from the storage device. In some examples, the host application I / O component 625 can be configured as or otherwise support means for sending the retrieved data set to the host device.

[0101] In some examples, the power mode manager 640 can be configured as or otherwise support means for determining whether a power mode of the storage device is an inactive power mode upon receiving the request to read the set of data. In some examples, the power mode manager 640 can be configured as or otherwise support means for waking up the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode, where retrieving the data associated with the address from the storage device is performed after waking up the storage device. In some examples, the power mode manager 640 can be configured as or otherwise support means for commanding the storage device to return to the inactive power mode after retrieving the data associated with the address from the storage device.

[0102] Figure 7 A flow diagram is shown illustrating a method 700 to support write buffer extension for a storage interface controller in accordance with examples as disclosed herein. The operations of method 700 can be implemented by a memory device or its components as described herein. For example, the operations of method 700 can be performed by a memory device as described with reference to FIGS. 1-6B in accordance with examples as disclosed herein. Figures 1 to 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0103] At 705, the method can include receiving, by a storage interface controller of a host device, data to be written to a storage device. The operations of 705 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 705 can be performed by a host application I / O component 625 as described with reference to FIGS. 1-6B in accordance with examples as disclosed herein. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0104] At 710, the method can include storing, by the storage interface controller, the data to a write buffer of the storage interface controller based at least in part on a power mode of the storage device. The operations of 710 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 710 can be performed by a write buffer manager 630 as described with reference to FIGS. 1-6B in accordance with examples as disclosed herein. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0105] At 715, the method can include retrieving, by the storage interface controller, the data from the write buffer based at least in part on a change to the power mode of the storage device. The operations of 715 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 715 can be performed by a write buffer manager 630 as described with reference to FIGS. 1-6B in accordance with examples as disclosed herein. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0106] At 720, the method can include sending, by the storage interface controller, the data to the storage device. The operations of 720 can be performed according to the examples disclosed herein. In some examples, aspects of the operations of 720 can be performed by a storage interface controller as described with reference to FIG. 5. Figure 6 The storage data manager 635 described is executed.

[0107] In some examples, the apparatuses described herein can perform one or more methods, such as method 700. The apparatuses can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, by a storage interface controller of a host device, data to be written to a storage device; storing, by the storage interface controller, the data to a write buffer of the storage interface controller based at least in part on a power mode of the storage device; retrieving, by the storage interface controller, the data from the write buffer based at least in part on a change to the power mode of the storage device; and sending, by the storage interface controller, the data to the storage device.

[0108] In some examples of the method 700 and apparatuses described herein, storing the data to the write buffer can include determining, by the storage interface controller, whether the power mode of the storage device is an inactive power mode when the data is received; storing, by the storage interface controller, the data to the write buffer based at least in part on determining that the power mode of the storage device is the inactive power mode; and refraining from waking the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode.

[0109] In some examples of the method 700 and apparatuses described herein, moving the data from the write buffer to the storage device can include determining, by the storage interface controller, whether the power mode of the storage device has changed to an active power mode; and moving, by the storage interface controller, the data from the write buffer to the storage device based at least in part on determining that the power mode of the storage device has changed to the active power mode.

[0110] In some examples of the method 700 and apparatuses described herein, storing the data to the write buffer can also be based at least in part on an amount of additional data stored in the write buffer.

[0111] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for determining, by the storage interface controller, whether an amount of data stored in the write buffer satisfies a threshold when additional data is received to be written to the storage device; determining, by the storage interface controller, whether a power mode of the storage device is an inactive power mode; waking up the storage device, by the storage interface controller, based at least in part on determining that the power mode of the storage device is the inactive power mode and determining that the amount of data stored in the write buffer satisfies the threshold, wherein moving the data from the write buffer to the storage device is performed after waking up the storage device; and commanding the storage device to return to the inactive power mode after moving the data from the write buffer to the storage device.

[0112] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving, at the storage interface controller, a request from an application of the host device to read data associated with an address of the storage device; determining, by the storage interface controller, whether the data associated with the address is stored in the write buffer; retrieving, by the storage interface controller, the data associated with the address from the write buffer based at least in part on determining that the data associated with the address is stored in the write buffer; and sending, by the storage interface controller, the data associated with the address to the application of the host device.

[0113] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving, at the storage interface controller, a request from an application of the host device to read data associated with an address of the storage device; determining, by the storage interface controller, that the data associated with the address is not stored in the write buffer; retrieving, by the storage interface controller, the data associated with the address from the storage device; and sending, by the storage interface controller, the data associated with the address to the application of the host device.

[0114] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for determining, by the storage interface controller, whether a power mode of the storage device is an inactive power mode; waking up the storage device, by the storage interface controller, based at least in part on determining that the power mode of the storage device is the inactive power mode, wherein retrieving the data associated with the address from the storage device is performed after waking up the storage device; and commanding the storage device to return to the inactive power mode after retrieving the data associated with the address from the storage device.

[0115] Figure 8A flow diagram is shown illustrating a method 800 to support write buffer extension for a storage interface controller in accordance with examples as disclosed herein. The operations of method 800 can be implemented by a memory device or its components as described herein. For example, the operations of method 800 can be performed by a memory device as described with reference to Figures 1 to 6 The memory device described can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform various aspects of the described functions using special-purpose hardware.

[0116] At 805, the method can include receiving, by a storage interface controller of a host device, a plurality of data sets to be written to a storage device, the host device including a write buffer associated with the storage interface controller. The operations of 805 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 805 can be performed by a host application I / O component 625 as described with reference to Figure 6 The host application I / O component 625 described.

[0117] At 810, upon receiving each data set of the plurality of data sets, the method can move to 815. The operations of 810 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 810 can be performed by a host application I / O component 625 as described with reference to Figure 6 The host application I / O component 625 described.

[0118] At 815, the method can include determining, by the storage interface controller, a power mode of the storage device upon receiving each data set of the plurality of data sets. The operations of 815 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 815 can be performed by a power mode manager 640 as described with reference to Figure 6 The power mode manager 640 described.

[0119] Based on the determined power mode of the storage device being an inactive power mode, the method can move to 820 or 825. Based on the determined power mode of the storage device being an active power mode, the method can include 830, 835, and / or 840.

[0120] At 820, the method can include storing, by the storage interface controller, the respective data set in a write buffer of the storage interface controller. The operations of 820 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 820 can be performed by a write buffer manager 630 as described with reference to Figure 6 The write buffer manager 630 described.

[0121] At 825, the method can include refraining, by the storage interface controller, from waking up the storage device. The operations of 825 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 825 can be performed by a write buffer manager 630 as described with reference to Figure 6The described power mode manager 640 performs.

[0122] At 830, the method can include retrieving, by the storage interface controller, data buffered at the write buffer. The operations of 830 can be performed according to the examples disclosed herein. In some examples, aspects of the operations of 830 can be performed by a write buffer manager 630 as described with reference to FIG. 6. Figure 6 The described write buffer manager 630 performs.

[0123] At 835, the method can include sending, by the storage interface controller, the buffered data to the storage device. The operations of 835 can be performed according to the examples disclosed herein. In some examples, aspects of the operations of 835 can be performed by a storage data manager 635 as described with reference to FIG. 6. Figure 6 The described storage data manager 635 performs.

[0124] At 840, the method can include sending, by the storage interface controller, the respective data set to the storage device. The operations of 840 can be performed according to the examples disclosed herein. In some examples, aspects of the operations of 840 can be performed by a storage data manager 635 as described with reference to FIG. 6. Figure 6 The described storage data manager 635 performs.

[0125] In some examples, the apparatuses described herein can perform one or more methods, such as method 800. The apparatuses can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, by a storage interface controller of a host device, a plurality of data sets to be written to a storage device, the host device including a write buffer associated with the storage interface controller, and determining, by the storage interface controller, a power mode of the storage device upon receipt of each data set of the plurality of data sets. The apparatuses described herein can further include operations, features, circuitry, logic, means, or instructions for storing, by the storage interface controller, the respective data set in the write buffer of the storage interface controller based on the determined power mode of the storage device being an inactive power mode, avoiding, by the storage interface controller, waking up the storage device. The apparatuses described herein can further include operations, features, circuitry, logic, means, or instructions for retrieving, by the storage interface controller, data buffered at the write buffer based on the determined power mode of the storage device being an active power mode, sending, by the storage interface controller, the buffered data to the storage device, and sending, by the storage interface controller, the respective data set to the storage device.

[0126] The method 800 and some examples of the devices described herein can further include operations, features, circuitry, logic, means, or instructions for receiving a second set of data to be written to the storage device, the second set of data not comprising the plurality of sets of data, and determining a power mode of the storage device based at least in part on receiving the second set of data. The devices described herein can further include operations, features, circuitry, logic, means, or instructions for waking up the storage device based on the determined power mode of the storage device being an inactive power mode and an amount of data stored in the write buffer exceeding a threshold, retrieving the first set of data from the write buffer, sending the first set of data to the storage device, sending the second set of data to the storage device, and returning the storage device to a hibernation state.

[0127] The method 800 and some examples of the devices described herein can further include operations, features, circuitry, logic, means, or instructions for receiving a request to read a set of data associated with an address of the storage device, determining that the set of data associated with the address is not stored in the write buffer, retrieving the set of data associated with the address from the storage device, and sending the retrieved set of data to the host device.

[0128] The method 800 and some examples of the devices described herein can further include operations, features, circuitry, logic, means, or instructions for determining whether a power mode of the storage device is an inactive power mode upon receiving a request to read a set of data, waking up the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode, wherein retrieving the set of data associated with the address from the storage device is performed after waking up the storage device, and commanding the storage device to return to the inactive power mode after retrieving the set of data associated with the address from the storage device.

[0129] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more methods can be combined.

[0130] An apparatus is described. The apparatus can include a write buffer and a storage interface controller coupled with the write buffer. The storage interface controller can be used to receive data to be written to a storage device, store the data to the write buffer based at least in part on a power mode of the storage device, retrieve the data from the write buffer based at least in part on a change to the power mode of the storage device, and send the data to the storage device.

[0131] In some examples of the device, to store data to the write buffer, the storage interface controller can be further to: determine, upon receiving the data, whether the power mode of the storage device is the inactive power mode; store the data to the write buffer based at least in part on determining that the power mode of the storage device is the inactive power mode; and refrain from waking the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode.

[0132] In some examples of the device, to retrieve data from the write buffer, the storage interface controller can be further to determine whether the power mode of the storage device has changed to the active power mode; and retrieve the data from the write buffer to send to the storage device based at least in part on determining that the power mode of the storage device has changed to the active power mode.

[0133] In some examples of the device, the storage interface controller can be further to determine, upon receiving additional data to write to the storage device, whether an amount of data stored in the write buffer satisfies a threshold; determine whether the power mode of the storage device is the inactive power mode; wake the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode and determining that the amount of data stored in the write buffer satisfies the threshold, wherein sending the data from the write buffer to the storage device is performed after waking the storage device; and command the storage device to return to the inactive power mode after moving the data from the write buffer to the storage device.

[0134] In some examples of the device, the storage interface controller can be further to receive, from an application of the device, a request to read data associated with an address of the storage device; determine whether the data associated with the address is stored in the write buffer; retrieve the data associated with the address from the write buffer based at least in part on determining that the data associated with the address is stored in the write buffer; and send the data associated with the address to the application.

[0135] In some examples of the device, the storage interface controller can include a Universal Flash Storage (UFS) controller. In some examples of the device, the storage device can be physically separate from the storage interface controller. In some examples of the device, the write buffer can be located on the storage interface controller.

[0136] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0137] The terms“in electronic communication,”“in conductive contact,”“connected,” and“coupled” can refer to a relationship between components in which an electrical current flows between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of a signal between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) can be open or closed at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of a signal between connected components can be interrupted for a period of time, e.g., using one or more intervening components such as switches or transistors.

[0138] The term“coupled” refers to the condition of components moving from an open relationship between the components, in which a signal cannot currently be communicated between the components through a conductive path, to a closed relationship between the components, in which a signal can be communicated between the components through a conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows a signal to flow between the other components via a conductive path that previously did not permit the flow of a signal.

[0139] The terms“if,”“when,”“based on,” or“based at least in part on” can be used interchangeably. In some examples, the terms“if,”“when,”“based on,” or“based at least in part on” can be used interchangeably to describe a conditional relationship between two or more events, a conditional process, or a conditional portion of a process.

[0140] The term“in response to” can refer to a condition or action that occurs at least partially (if not entirely) as a result of a prior condition or action. For example, a first condition or action can occur, and as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intervening conditions or actions after the first condition or action), a second condition or action can occur at least partially.

[0141] Additionally, the term "directly responsive to" or "directly responsive" can refer to a condition or action occurring as a direct result of a prior condition or action. In some examples, a first condition or action can occur, and a second condition or action can occur directly as a result of the prior condition or action occurring, independent of whether other conditions or actions occur. In some examples, a first condition or action can occur, and a second condition or action can occur directly as a result of the prior condition or action occurring, such that no other intervening conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intervening steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on," "based at least in part on," or "responsive to" some other step, action, event, or condition can additionally or alternatively (e.g., in alternative examples) be performed "directly responsive to" or "directly in response to" such other condition or action.

[0142] The description set forth herein describes example configurations and does not represent all examples that can be practiced under the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" or "superior." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0143] In the drawings, like reference numerals can be used to denote like components throughout the several views. Additionally, various components of the same type can be distinguished from each other by following the convention of using a leading capital letter to designate the hundreds place for the reference numeral of the component. For example, the drawing figures can include a first component 102 and a second component 202. It is to be understood that such distinctions are merely exemplary as components of the same type can or can not be distinguished in this fashion. In addition, if only the first reference numeral is used in the specification, the description is applicable to any one of the similar components having the same first reference numeral irrespective of the second reference numeral.

[0144] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0145] The various illustrative blocks and components described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein, for example. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0146] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a referring to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both conditions A and B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” is intended to be similarly interpreted as the phrase “based, at least in part, on.”

[0147] Computer-readable media includes both non-transitory computer-readable storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0148] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: receiving, by a storage interface controller of a host device, data to be written to a storage device; storing, by the storage interface controller, the data to a write buffer of the storage interface controller based at least in part on a power mode of the storage device; retrieving, by the storage interface controller, the data from the write buffer based at least in part on a change to the power mode of the storage device; and sending, by the storage interface controller, the data to the storage device.

2. The method of claim 1, wherein storing the data to the write buffer comprises: determining, by the storage interface controller upon receiving the data, whether the power mode of the storage device is an inactive power mode; storing, by the storage interface controller, the data to the write buffer based at least in part on determining that the power mode of the storage device is the inactive power mode; and avoiding, based at least in part on determining that the power mode of the storage device is the inactive power mode, waking up the storage device.

3. The method of claim 1, wherein moving the data from the write buffer to the storage device comprises: determining, by the storage interface controller, whether the power mode of the storage device has changed to an active power mode; and moving, by the storage interface controller, the data from the write buffer to the storage device based at least in part on determining that the power mode of the storage device has changed to the active power mode.

4. The method of claim 1, wherein storing the data to the write buffer is further based at least in part on an amount of additional data stored in the write buffer.

5. The method of claim 1, further comprising: determining, by the storage interface controller upon receiving additional data to be written to the storage device, whether an amount of data stored in the write buffer satisfies a threshold; determining, by the storage interface controller, whether the power mode of the storage device is an inactive power mode; waking up, by the storage interface controller, the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode and determining that the amount of data stored in the write buffer satisfies the threshold, wherein moving the data from the write buffer to the storage device is performed after waking up the storage device; and commanding, after moving the data from the write buffer to the storage device, the storage device to return to the inactive power mode.

6. The method of claim 1, further comprising: receiving, at the storage interface controller from an application of the host device, a request to read data associated with an address of the storage device; determining, by the storage interface controller, whether the data associated with the address is stored in the write buffer; retrieving, by the storage interface controller, the data associated with the address from the write buffer based at least in part on determining that the data associated with the address is stored in the write buffer; and sending, by the storage interface controller, the data associated with the address to the application program of the host device.

7. The method of claim 1, further comprising: receiving, at the storage interface controller, a request from an application program of the host device to read data associated with an address of the storage device; determining, by the storage interface controller, that data associated with the address is not stored in the write buffer; retrieving, by the storage interface controller, the data associated with the address from the storage device; and sending, by the storage interface controller, the data associated with the address to the application program of the host device.

8. The method of claim 7, further comprising: determining, by the storage interface controller, whether the power mode of the storage device is an inactive power mode; waking up the storage device, by the storage interface controller, based at least in part on determining that the power mode of the storage device is the inactive power mode, wherein retrieving the data associated with the address from the storage device is performed after waking up the storage device; and after retrieving the data associated with the address from the storage device, commanding the storage device to return to the inactive power mode.

9. An apparatus comprising: a write buffer; and a storage interface controller coupled with the write buffer and operable to: receive data to be written to a storage device; store the data to the write buffer based at least in part on a power mode of the storage device; retrieve the data from the write buffer based at least in part on a change to the power mode of the storage device; and send the data to the storage device.

10. The apparatus of claim 9, wherein storing the data to the write buffer comprises the storage interface controller being further operable to: determine, upon receiving the data, whether the power mode of the storage device is an inactive power mode; store the data to the write buffer based at least in part on determining that the power mode of the storage device is the inactive power mode; and avoid waking up the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode.

11. The apparatus of claim 9, wherein retrieving the data from the write buffer comprises the storage interface controller being further operable to: determine whether the power mode of the storage device has changed to an active power mode; and move the data from the write buffer to the storage device based at least in part on determining that the power mode of the storage device has changed to the active power mode. ​ ​ 12. The device of claim 9, wherein the storage interface controller is further operable to: determine whether an amount of data stored in the write buffer satisfies a threshold upon receiving additional data to be written to the storage device; determine whether the power mode of the storage device is an inactive power mode; wake up the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode and determining that the amount of data stored in the write buffer satisfies the threshold, wherein moving the data from the write buffer to the storage device is performed after waking up the storage device; and after moving the data from the write buffer to the storage device, command the storage device to return to the inactive power mode.

13. The device of claim 9, wherein the storage interface controller is further operable to: receive a request from an application program of the device to read data associated with an address of the storage device; determine whether data associated with the address is stored in the write buffer; retrieve the data associated with the address from the write buffer based at least in part on determining that the data associated with the address is stored in the write buffer; and send the data associated with the address to the application program.

14. The device of claim 9, wherein the storage interface controller comprises a Universal Flash Storage (UFS) controller.

15. The device of claim 9, wherein the storage device is physically separate from the storage interface controller.

16. The device of claim 9, wherein the write buffer is located on the storage interface controller.

17. A device comprising: a write buffer; and a storage interface controller coupled with the write buffer and operable to: receive a plurality of data sets to be written to a storage device; and upon receiving each data set of the plurality of data sets: determine a power mode of the storage device; based on the determined power mode of the storage device being an inactive power mode: store the respective data set in the write buffer; and avoid waking up the storage device; and based on the determined power mode of the storage device being an active power mode: retrieve data buffered at the write buffer; send the data to the storage device; and send the respective data set to the storage device.

18. The device of claim 17, wherein the respective data set comprises a first data set, and wherein the storage interface controller is further operable to: receive a second data set to be written to the storage device, the second data set not comprising the plurality of data sets; determine the power mode of the storage device based at least in part on receiving the second data set; and based on the determined power mode of the storage device being the inactive power mode and an amount of data stored in the write buffer exceeding a threshold: wake up the storage device; retrieve the first data set from the write buffer; ​ ​ ​ ​ ​ ​ sending the first data set to the storage device; sending the second data set to the storage device; and returning the storage device to a sleep state.

19. The apparatus of claim 17, wherein the storage interface controller is further operable to: receive a request to read a data set associated with an address of the storage device; determine that the data set associated with the address is not stored in the write buffer; retrieve the data set associated with the address from the storage device; and send the retrieved data set to a host device.

20. The apparatus of claim 19, wherein the storage interface controller is further operable to: determine whether the power mode of the storage device is the inactive power mode upon receiving the request to read the data set; wake up the storage device based at least in part on determining that the power mode of the storage device is the inactive power mode, wherein retrieving the data set associated with the address from the storage device is performed after waking up the storage device; and command the storage device to return to the inactive power mode after retrieving the data set associated with the address from the storage device.

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