A signal transmission circuit and a computing device

Abstract

The embodiment of the application discloses a signal transmission circuit and a computing device, and the signal transmission circuit comprises a first circuit board, a union bus (UBC) connector and a power supply connector; a power supply interface of the first circuit board is connected with a first end of the power supply connector, and a peripheral component interconnect express (PCIe) interface of the first circuit board is connected with a first end of the UBC connector; a second end of the power supply connector is used for being connected with a first PCIe device through a PCIe connector, so as to supply power for the first PCIe device; and a second end of the UBC connector is used for being connected with the first PCIe device through the PCIe connector, so as to transmit a PCIe signal to the first PCIe device. According to the embodiment of the application, the UBC connector and the power supply connector are adopted, so that the wiring difficulty of a mainboard can be reduced, and hardware resources can be saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a signal transmission circuit and a computing device. BACKGROUND

[0002] With the progress of computer technology, the functions and performances of servers are constantly improved and perfected, and the servers play an increasingly important role in the fields of cloud computing, data center, big data, etc. In order to meet the growing demand for data processing, the computing performance of processing chips such as central processing units (CPUs) in servers is also getting higher and higher, and in order to fully exert the computing capacity of the processing chips such as CPUs, the bandwidth requirement for data transmission is also getting higher and higher. Accordingly, the data transmission protocol (standard) also develops accordingly, and the peripheral component interconnect express (PCIe) technology has developed from PCIe 1.0 version to PCIe 5.0 version (5th generation PCIe technology).

[0003] In order to transmit PCIe high-speed signals, a double density union bus connector (UBCDD) connector can be used to realize the transmission through the printed circuit board (PCB) wiring to the PCIe connector. In this way, a plurality of UBCDD connectors need to be arranged on the mainboard of the server, and the UBCDD connector occupies a large area of the server mainboard, which will have a great impact on the wiring, resulting in difficult wiring. SUMMARY

[0004] Embodiments of the present application disclose a signal transmission circuit and a computing device, which can reduce the difficulty of mainboard wiring, save hardware resources, and can expand application scenarios.

[0005] The first aspect discloses a signal transmission circuit, which comprises a first circuit board, a union bus (UBC) connector and a power connector. The power interface of the first circuit board is connected with the first end of the power connector, and the peripheral component interconnect express (PCIe) interface of the first circuit board is connected with the first end of the UBC connector. The second end of the power connector is used to connect with a first PCIe device through a PCIe connector to supply power for the first PCIe device. The second end of the UBC connector is used to connect with the first PCIe device through the PCIe connector to transmit PCIe signals to the first PCIe device.

[0006] In the embodiments of the present application, the first PCIe device can be connected by using the UBC connector and the power connector to the PCIe connector. Compared with the UBCDD connector, the UBC connector and the power connector occupy a smaller area of the mainboard of the computing device, and thus the wiring difficulty of the mainboard can be reduced. Meanwhile, the UBC connector can support X8 transmission at most, and thus in a scenario where X16 transmission is not needed (for example, in a scenario where the PCIe connector is connected to an X8 network card), the UBCDD connector is replaced by the UBC high-speed connector and the power connector, so that hardware resources can be saved. In addition, the UBC connector has more application scenarios and higher flexibility than the UBCDD connector.

[0007] As a possible implementation, the second end of the UBC connector is further configured to connect the second PCIe device.

[0008] In the embodiments of the present application, the second end of the UBC connector can also be connected to the second PCIe device, and the first PCIe device can be connected without the PCIe connector, so that the flexibility of application can be improved.

[0009] As a possible implementation, the first circuit board further includes a power module and a controller, the power module is configured to transmit a first power to the power connector, and the controller is configured to transmit a PCIe signal to the UBC connector; the power connector is configured to output the first power to the PCIe connector, and the UBC connector is configured to output the PCIe signal to the PCIe connector; and the PCIe connector is configured to output the first power and the PCIe signal to the first PCIe device.

[0010] In the embodiments of the present application, the power signal can be transmitted through the power connector, and the PCIe signal can be transmitted through the UBC connector. The power connector and the UBC connector can be flexibly arranged on different boards of the computing device.

[0011] As a possible implementation, the UBC connector and the power connector are arranged on the first circuit board and / or the second circuit board; when the UBC connector and the power connector are arranged on the first circuit board, a power interface of the first circuit board is connected to the first end of the power connector through a cable or printed circuit board (PCB) wiring, and a PCIe interface of the first circuit board is connected to the first end of the UBC connector through a cable or printed circuit board (PCB) wiring; when the UBC connector and the power connector are arranged on the second circuit board, the power interface of the first circuit board and the first end of the power connector, and the PCIe interface of the first circuit board and the first end of the UBC connector are all connected through a cable.

[0012] In the embodiments of the present application, the PCIe interface of the first circuit board and the first end of the UBC connector can be connected through a cable, and the UBC connector and the PCIe connector can also be connected through a cable, so that the transmission loss of the PCIe signal can be reduced.

[0013] As a possible implementation, the PCIe interface of the first circuit board and the first end of the UBC connector are connected through a first cable, and / or the second end of the UBC connector and the first end of the PCIe connector are connected through a second cable.

[0014] As a possible implementation, when the UBC connector is arranged on the first circuit board, the PCIe interface of the first circuit board and the first end of the UBC connector are connected through internal wiring on the first circuit board.

[0015] As a possible implementation, the second end of the power connector and the first end of the PCIe connector are connected through a third cable.

[0016] As a possible implementation, the first end of the PCIe connector includes at least one first pin and at least one second pin, the at least one first pin is welded to one end of the second cable, the other end of the second cable forms a first plug, and the first plug is used for plugging with the second end of the UBC connector; the at least one second pin is welded to one end of the third cable, and the other end of the third cable forms a second plug, and the second plug is used for plugging with the second end of the power connector.

[0017] In the embodiments of the present application, the pins of the PCIe connector for transmitting PCIe signals can be welded to one end of the second cable, the other end of the second cable can form a first plug, the pins of the PCIe connector for transmitting power signals can be welded to one end of the third cable, and the other end of the third cable can form a second plug, so that when the first PCIe device needs to be connected to the computing device, the first plug and the second plug can be flexibly plugged into the second end of the UBC connector and the second end of the power connector, respectively, and the first PCIe device can be flexibly inserted into the slot of the PCIe connector.

[0018] As a possible implementation, the first end of the UBC connector and the first end of the power connector are welded on the first circuit board.

[0019] As a possible implementation, the PCIe connector is fixedly arranged on the first circuit board or the second circuit board.

[0020] As a possible implementation, the first PCIe device is a network card, a redundant array of independent disks card, or a graphics card.

[0021] As a possible implementation, the second PCIe device is an Open Compute Project card or a hard disk adapter.

[0022] The second aspect discloses a computing device, which comprises a first circuit board and a second circuit board, the first circuit board is provided with a power module, a controller, a power connector and a union bus (UBC) connector, and the second circuit board is provided with a peripheral component interconnect express (PCIe) connector and a PCIe device; the power module is connected with a first end of the power connector through a cable or printed circuit board (PCB) wiring, the controller is connected with a first end of the UBC connector through a cable or PCB wiring, a second end of the UBC connector is connected with a first end of the PCIe connector through a second cable, a second end of the power connector is connected with the first end of the PCIe connector through a third cable, and a second end of the PCIe connector is connected with the PCIe device.

[0023] As a possible implementation, the first end of the PCIe connector comprises at least one first pin and at least one second pin, the at least one first pin is welded with one end of the second cable, the other end of the second cable forms a first plug, and the first plug is used for plugging with the second end of the UBC connector; the at least one second pin is welded with one end of the third cable, the other end of the third cable forms a second plug, and the second plug is used for plugging with the second end of the power connector.

[0024] The third aspect discloses a computing device, which can comprise the signal transmission circuit provided in the first aspect and any possible implementation of the first aspect.

[0025] It should be understood that the implementation and beneficial effects of the above aspects or any possible implementation of the present application can be mutually referred to. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1 is a structural schematic diagram of a computing device disclosed by the embodiments of the present application;

[0028] Figure 2 is a size schematic diagram of a UBCDD connector disclosed by the embodiments of the present application;

[0029] Figure 3 is a structural schematic diagram of another computing device disclosed by the embodiments of the present application;

[0030] Figure 4 is a structural schematic diagram of still another computing device disclosed by the embodiments of the present application;

[0031] Figure 5A is a connection schematic diagram of a 2Pin power connector disclosed by the embodiments of the present application;

[0032] Figure 5B is a connection schematic diagram of a 4Pin power connector disclosed by the embodiments of the present application;

[0033] Figure 6 is a structural schematic diagram of still another computing device disclosed by the embodiments of the present application;

[0034] Figure 7 is a connection schematic diagram of a controller (CPU) and a PCIe exchange chip disclosed by the embodiments of the present application;

[0035] Figure 8 is a size schematic diagram of a UBC connector disclosed by the embodiments of the present application;

[0036] Figure 9 is a size schematic diagram of a 2pin power connector disclosed by the embodiments of the present application;

[0037] Figure 10 is a structural schematic diagram of still another computing device disclosed by the embodiments of the present application;

[0038] Figure 11 is a connection schematic diagram of a cable and a PCIe connector disclosed by the embodiments of the present application;

[0039] Figure 12 is a structural schematic diagram of still another computing device disclosed by the embodiments of the present application;

[0040] Figure 13 is a structural schematic diagram of still another computing device disclosed by the embodiments of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application disclose a signal transmission circuit and a computing device, which can reduce the wiring difficulty of a mainboard, save hardware resources, and can expand application scenarios. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0042] In order to better understand the embodiments of the present application, the related technologies of the embodiments of the present application will be described first.

[0043] With the progress of computer technology, the functions and performances of servers are constantly improved and perfected, and servers also play an increasingly important role in the fields of cloud computing, data center, big data, etc. Moreover, in order to meet the growing demand for data processing, the computing performance of processing chips such as central processing units (CPUs) in servers is also getting higher and higher, and in order to fully exert the computing capacity of the processing chips such as CPUs, the bandwidth requirement for data transmission is also getting higher and higher. Correspondingly, the data transmission protocol (standard) also develops accordingly, and the peripheral component interconnect express (PCIe) technology has developed from PCIe 1.0 version to PCIe 5.0 version (5th generation PCIe technology). At present, the data link speed of PCIe 5.0 can reach 32 giga transmission per second (GT / s), which is twice that of PCIe 4.0, and has downward compatibility.

[0044] PCIe is a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and the connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. In order to meet the transmission needs of different devices (including low-speed devices and high-speed devices), PCIe data transmission includes different specifications such as X1, X4, X8, X16. X1 represents 1 Lane (channel), which can transmit 1 pair of differential signals. Similarly, X2 represents 2 Lanes, which can transmit 2 pairs of differential signals, X8 represents 8 Lanes, which can transmit 8 pairs of differential signals, and X16 represents 16 Lanes, which can transmit 16 pairs of differential signals. Among them, the more the number of Lanes, the faster the data transmission rate. For example, X1 under PCIe 5.0 standard can reach 4 gigabytes per second (GB / s), X4 can reach 16 GB / s, X8 can reach 32 GB / s, and X16 can reach 64 GB / s. The actual data transmission rate is also related to the encoding scheme used.

[0045] Currently, for transmitting PCIe 5.0 signals, a union bus connector double density (UBCDD) connector (high-speed connector) is used to realize the transmission through a cable to a PCIe connector. In this way, a plurality of UBCDD connectors are usually arranged on the motherboard of the server so that there are enough connectors for expansion, such as external network cards, graphics cards, redundant array of independent disks (RAID) cards, graphics processing unit (GPU) cards and other PCIe devices.

[0046] Specifically, please refer to Figure 1 , Figure 1 is a structural schematic diagram of a computing device disclosed in an embodiment of the present application. As shown in Figure 1 , the computing device 100 can include a circuit board 101, a UBCDD connector 102, a PCIe connector 103, a PCIe device 104, and a controller 105. The controller 105 on the circuit board 101 can be connected to the UBCDD connector 102 through printed circuit board (PCB) traces, and the UBCDD connector 102 can be connected to the PCIe connector 103 through a cable. The PCIe connector 103 can include a slot, and the PCIe device 104 can be inserted into the slot of the PCIe connector 103. The circuit board 101 can be a motherboard, and the controller 105 can be a CPU.

[0047] The circuit board 101 can further include a power module. The power module and the controller 105 can transmit power and high-speed signals (PCIe signals) to the UBCDD connector 102 through PCB traces, respectively. The UBCDD connector 102 can transmit the power and the high-speed signals to the PCIe connector 103 through a cable, and the PCIe connector 103 can transmit the power and the high-speed signals to the PCIe device 104. In this way, the required power (such as 12V power) can be provided to the PCIe device 104 so that the PCIe device 104 can work normally. Moreover, the high-speed signals can be transmitted through the UBCDD connector 102, the PCIe connector 103, and the PCB traces. However, since the transmission rate of PCIe 5.0 is relatively high, the loss of transmission through the PCB traces is also relatively large. The PCIe device 104 can be a network card, a GPU card, etc.

[0048] In addition, the UBCDD connector is bulky and occupies a large area of the motherboard of the server. Therefore, the area available for wiring is relatively small, which can greatly affect the wiring and cause difficulty in wiring. For example, please refer toFigure 2 , Figure 2 is a size diagram of a UBCDD connector disclosed in an embodiment of the present application. As shown in Figure 2 , the length and width of the UBCDD connector are 36 millimeters (mm) and 12.5 mm respectively, so that one UBCDD connector needs to occupy an area of 36 mm*12.5 mm of the mainboard.

[0049] Further, the UBCDD connector supports X16 transmission, while in actual scenarios, X16 transmission can not be used, and X8, X4 can be used for transmission, which will cause waste of hardware resources. For example, in the structure shown in Figure 1 , the PCIe connector 103 can connect with an X8 network card, so that the PCIe connector 103 end can use X8 (8 differential pairs) for transmission, and the maximum support of X16 of the UBCDD connector 102 cannot be fully utilized, thereby causing waste of resources.

[0050] To solve the above problem, in an embodiment of the present application, a union bus (UBC) connector (high-speed connector) + power connector to PCIe connector mode can be used to connect network cards, RAID cards and the like. Since the UBC connector and the power connector occupy a smaller area of the mainboard of the computing device, the wiring difficulty of the mainboard can be reduced. At the same time, the UBC connector can support X8 transmission at most, so that in scenarios where X16 transmission is not needed (such as the scenario where the PCIe connector connects with an X8 network card), the UBCDD connector is changed to a UBC high-speed connector + power connector, which can save hardware resources. Moreover, the UBC connector has more application scenarios and higher flexibility than the UBCDD connector. In addition, the UBC connector and the PCIe connector can use a cable to transmit PCIe signals, so that transmission loss can be reduced.

[0051] Next, the configuration of the computing device and the related connector provided in the present application will be illustrated by way of example in combination with Figures 3-13 .

[0052] Please refer to Figure 3 , Figure 3 is a structure diagram of another computing device disclosed in an embodiment of the present application. As shown in Figure 3As shown, the computing device 200 can include a first circuit board 201, a power connector 202, a UBC connector 203, a PCIe connector 204, a first PCIe device 205, a power module 206, a controller 207, and a second circuit board 208. The PCIe connector 204 can be a PCIe direct plug connector, and the first PCIe device 205 can be a network card, a RAID card, etc. The first circuit board 201 can be a motherboard of the computing device. In some embodiments, the computing device 200 can be a heterogeneous server, a rack server, a cabinet server, a high-density server, etc.

[0053] The power connector 202 and the UBC connector 203 can be disposed on the first circuit board 201, and the power module 206 and the controller 207 can also be disposed on the first circuit board 201. The power module 206 and the power connector 202 can be connected through PCB lines or cables inside the first circuit board 201 to transmit signals, and the controller 207 and the UBC connector 203 can also be connected through PCB lines or cables inside the first circuit board 201 to transmit signals. Specifically, the output end of the power module 206 can be connected to the first end of the power connector 202 through a power interface, and the output end of the controller 207 can be connected to the first end of the UBC connector 203 through a PCIe interface of the first circuit board. The power interface can be disposed on the first circuit board, which can be a pin or a connector of the power module. The PCIe interface can be a PCIe pin of the controller or a connector connected to the PCIe pin of the controller. The output end of the power module 206 is connected to the first end of the power connector 202, and the output end of the controller 207 is connected to the first end of the UBC connector 203, so as to transmit power (first power) to the power connector 202 and high-speed signals to the UBC connector 203. The PCIe connector 204 can be disposed on the second circuit board 208, and the second end of the power connector 202 and the second end of the UBC connector 203 can be connected to the first end of the PCIe connector 204 to output power and high-speed signals to the PCIe connector 204. Specifically, the second end of the power connector 202 and the second end of the UBC connector 203 can be connected to the first end of the PCIe connector 204 through cables, respectively. The second end of the PCIe connector 204 can be connected to the first PCIe device 205. For example, the first PCIe device 205 can be inserted into a slot of the PCIe connector 204 through its own gold finger, so as to realize the electrical connection between the first PCIe device 205 and the PCIe connector 204, so that the power module 206 and the controller 207 on the first circuit board 201 output power and high-speed signals to the first PCIe device 205. The first circuit board 201 can be a motherboard or other circuit board provided with a processor / controller, and the second circuit board 208 can be a switching board, a backplane, or a riser card of the computing device.

[0054] In some embodiments, the power connector 202 and the UBC connector 203 can also be arranged on the second circuit board 208 (not shown in the figure). Figure 3

[0055] It should be noted that the controller 207 can be a processor (such as a CPU), a complex programmable logic device (CPLD), or the like, which is not limited herein.

[0056] Optionally, the first circuit board 201 and the power connector 202 can be connected through a cable, and the power connector 202 can output power (such as 12V or 5V direct current) through the cable. In some embodiments, the first circuit board 201 can further include a power inlet connector, which can be connected to an output interface of a power module (such as an output interface of a power supply unit (PSU) of a server) through a cable, so as to receive 12V direct current output by the power module after conversion. The first circuit board 201 can directly relay the 12V direct current output by the power module to the power connector 202, or the first circuit board 201 can relay the 12V direct current output by the power module after conversion, such as converting the 12V direct current to 5V direct current through a direct current / direct current (DC / DC) module and then relaying the 5V direct current to the power connector 202. Correspondingly, the power output interface (such as a 12V or 5V power output interface) on the first circuit board 201 can be connected to the first end of the power connector 202 through a cable.

[0057] For example, Figure 4 ​As shown, the computing device 200 can also include a PSU 209 and a power inlet connector 210. The power inlet connector 210 can also be disposed on the first circuit board 201. The first end (input end) of the PSU 209 can receive a 220V AC or 380V AC input, and the PSU 209 can convert the 220V AC or 380V AC to 48V DC or 12V DC output through the second end (output end) of the PSU 209. The second end of the PSU 209 can be connected to the first end of the power inlet connector 210 through a cable, and the second end of the power inlet connector 210 can be connected to the first end of the power connector 202 through PCB wiring inside the first circuit board 201, or through a cable, so as to supply power to the first PCIe device 205. In some embodiments, other circuit units can also be disposed on the first circuit board 201, through which the power output by the PSU 209 can be converted. For example, a step-down module 211 can also be disposed on the first circuit board 201, and the first end of the step-down module 211 can be connected to the second end of the power inlet connector 210 through PCB wiring inside the first circuit board 201, or through a cable. The second end of the step-down module 211 can be connected to the first end of the power connector 202 through PCB wiring inside the first circuit board 201, or through a cable, so as to supply power to the first PCIe device 205.

[0058] In some embodiments, the PSU 209 can be disposed on a fifth circuit board, which can be a power backplane.

[0059] In some embodiments, the power connector 202 can be a 2-pin power connector or a 4-pin power connector, and accordingly, the power connector 202 can be connected to a 2-pin power output interface on the first circuit board 201 through two cables, or connected to a 4-pin power output interface on the first circuit board 201 through four cables. Similarly, the power connector can also be connected to the first end of the PCIe connector 204 through two cables or four cables. For example, Figure 5A As shown, when the power connector 202 is a 2-pin power connector, the first end of the power connector 202 can be connected to the second end of the power module 206 through two cables, and the second end of the power connector 202 can also be connected to the first end of the PCIe connector through two cables. For example, Figure 5B As shown, when the power connector 202 is a 4-pin power connector, the first end of the power connector 202 can be connected to the second end of the power module 206 through four cables, and the second end of the power connector 202 can also be connected to the first end of the PCIe connector through four cables.

[0060] It should be noted that the power module 206 in the above embodiments can be a power module 206 as shown in FIG. 1, can also include the power inlet connector 210, and can further include the PSU 209, the power inlet connector 210, and the step-down module 211. The above components can be connected by a cable or by internal PCB wiring. Figure 4

[0061] The controller 207 on the first circuit board 201 and the UBC connector 203 can also be connected by a cable (i.e., a first cable), and the high-speed signal (e.g., a PCIe signal) can be output to the UBC connector 203 through the cable. It should be understood that the PCIe signal can be used for communication between the controller 207 on the first circuit board and a PCIe device (e.g., a GPU card, a network card, a RAID card, etc.). Therefore, the pin on the first end of the UBC connector 203 for transmitting the PCIe signal can be connected to the corresponding pin (PCIe interface) on the first circuit board for transmitting the PCIe signal output by the controller 207 through a cable, and the controller 207 can output the high-speed signal to the UBC connector 203 through the cable. It should be understood that other chips or chipsets can also be included on the first circuit board, and these chips or chipsets can also output the PCIe signal to the UBC connector 203 through the cable.

[0062] In some real-time modes, the connection between the power module 206 and the power connector 202, and the connection between the controller 207 and the UBC connector 203 can also be connected by internal PCB wiring of the first circuit board 201. In some embodiments, the PCIe link can be expanded by a switch chip to provide more PCIe ports for connecting PCIe devices. Accordingly, the pin on the first end of the UBC connector 203 for transmitting the PCIe signal can be connected to the corresponding pin on the switch chip for transmitting the PCIe signal through a cable or by internal PCB wiring of the first circuit board 201. It should be understood that the number of cables required for transmission varies for different PCIe signals such as X4, X8, etc. For example, the number of cables required for transmitting an X8 PCIe signal can be twice the number of cables required for transmitting an X4 PCIe signal.

[0063] It should be understood that the PCIe switch chip can be disposed on a switch board, as shown in FIG. 2. Figure 6 ​As shown, in one possible implementation, the computing device 200 may include a third circuit board 212, on which a UBC connector 213, a PCIe switching chip 214, a UBC connector 215, and a UBCDD connector 216 may be disposed. The first end of the UBC connector 213 can be connected to the second end of the UBC connector 203 via a cable. The second end of the UBC connector 213 can be connected to the first end (input end) of the PCIe switching chip 214 via PCB traces within the third circuit board 212 or via a cable to transmit PCIe signals. The second end (output end) of the PCIe switching chip 214 can be connected to the first end of the UBC connector 215 via PCB traces within the third circuit board 212 or via a cable. The second end of the PCIe switching chip 214 can also be connected to the UBCDD connector 216 via PCB traces within the third circuit board 212 or via a cable. The second end of the UBC connector 215 can be connected to the first end of the PCIe connector 204 via a cable to transmit PCIe signals. It should be understood that the UBC connector 216 can also be used to connect PCIe devices via a PCIe connector. Figure 6 The text is not indicated.

[0064] It should be noted that, Figure 6 The signal transmission circuit shown is merely illustrative and does not constitute a limitation thereof. In other embodiments of this application, the number of UBC connectors and UBCDD connectors connected to the PCIe chip can be flexibly configured according to actual needs. For example, Figure 6 The UBCDD connector 216 shown can also be configured as a UBC connector.

[0065] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating the connection between a controller (CPU) and a PCIe switching chip according to an embodiment of this application. Figure 7 As shown, when the controller 207 is a CPU, the CPU 207 may include multiple root ports (RPs). Figure 7 Taking two RPs (RP0 and RP1) as an example, RP0 can be connected to an endpoint device (EP) or a bridge device (…). Figure 7 (Not shown in the image), RP1 can be connected to the upstream port (UP) of the PCIe switching chip 214 (switch). The PCIe switching chip 214 can include m+1 downstream ports (DP), which can be labeled DP_0, DP_1, ..., DP_m respectively. Each downstream port can connect to one endpoint device.Figure 7 The endpoint devices shown are labeled EP_0, EP_1, ..., EP_m. For example, the root port RP1 connecting to the upstream port UP can occupy bus X, and the link between RP1 and UP can occupy bus N. In this case, the connection from the upstream port to m+1 downstream ports inside the PCIe switching chip 214 can occupy bus N+1, and the connection between each downstream port and its corresponding endpoint device can occupy bus N+2, bus N+3, ..., bus N+2+m, respectively.

[0066] like Figure 3 As shown, the power connector 202 and the PCIe connector 204 can be connected via a cable (i.e., a third cable) to achieve an electrical connection, allowing the PCIe connector 204 to transmit power signals (such as 12V or 5V DC). In some embodiments, the power connector 202 can be a 2-pin power connector or a 4-pin power connector, and correspondingly, the power pins of the power connector 202 and the PCIe connector 204 can be connected via two or four cables.

[0067] UBC connector 203 and PCIe connector 204 can be connected by a cable (i.e., a second cable) to achieve electrical connection with PCIe connector 204, so that PCIe connector 204 can also be used to transmit high-speed signals.

[0068] PCIe connector 204 may include a slot, primarily for connecting PCIe devices. A first PCIe device 205 can be inserted into the slot of PCIe connector 204. In this way, PCIe connector 204 can output power and PCIe signals to the first PCIe device 205, enabling the network card / RAID card 20 to function properly. It should be understood that PCIe signal transmission can be bidirectional; the first PCIe device 205 can also output PCIe signals to the first circuit board 201 (the CPU on the first circuit board 201). It should also be understood that PCIe connector 204 can include various specifications such as X4 and X8. Different specifications of PCIe connectors can have different numbers of pins, allowing for the transmission of different PCIe signals (X4, X8, etc.) and supporting different PCIe devices.

[0069] It should be understood that, generally, computing device 200 can be equipped with multiple UBC connectors, multiple power connectors, and multiple PCIe connectors to connect more PCIe devices such as network cards and RAID cards, thus expanding the functionality of computing device 200. Since UBC connectors and power connectors occupy less board space than UCDD connectors, wiring complexity can be reduced. For example, please refer to... Figure 8 andFigure 9 Figure 8 is a size diagram of a UBC connector disclosed by an embodiment of the present application, Figure 9 is a size diagram of a 2pin power connector disclosed by an embodiment of the present application. As shown in Figure 8 , the length and width of the UBC connector are about 25.2mm and 11mm, as shown in Figure 9 , the length of the 2pin power connector is about 11.6mm, and the width of the pin is about 3.0mm, and since only the pin of the power connector contacts the board, the actual board area occupied by the power connector can be less than 11.6mm*3.0mm. As can be seen, Figure 8 , the total board area occupied by the UBC connector shown in Figure 9 and the 2pin power connector shown in Figure 2 is less than that of the UBCDD connector shown in

[0070] Further, the cost of the UBCDD connector is higher than that of the UBC connector+power connector, and therefore, using the UBC connector+power connector to convert into a PCIE connector can reduce the overall cost of the computing device. Moreover, the reduction of the board area can save the PCB area, and therefore, the overall cost of the computing device can be further reduced.

[0071] It should be noted that when the UBCDD connector is replaced by the UBC high-speed connector+power connector, a small number of UBCDD connectors can be arranged on the first circuit board 201 so as to support the X16 PCIe device.

[0072] It should be noted that Figure 3 the computing device 200 shown in is only illustrative and does not constitute a limitation. In other embodiments of the present application, Figure 3 the computing device 200 shown in can include more or fewer devices or modules than shown, and is not limited to only including the first circuit board 201, the power connector 202, the UBC connector 203, the PCIe connector 204, the first PCIe device 205, etc. shown in Figure 3 . For example, the computing device 200 can further include one or more memories (such as hard disks), one or more fans, etc. For another example, the PCIe connector 204, the first PCIe device 205, etc. can not belong to the computing device 200.

[0073] In an embodiment of the present application, the UBC connector 203 can further include a power pin in addition to the pin for transmitting the PCIe signal, for transmitting power. Please refer to Figure 10 Figure 10 is a structure diagram of another computing device disclosed by an embodiment of the present application. Figure 10 in which​​Figure 3 The parts that are the same as those in the previous text will not be repeated here.

[0074] like Figure 10 As shown, in one possible implementation, a power module a 217 and a power module b 218 can be disposed on the first circuit board 201. The first ends of power modules a 217 and b 218 can receive different power signals, such as power module a 217 receiving a 12V power signal and power module b 218 receiving a 5V power signal. The second end of power module a 217 can be connected to the first end of power connector 202 via PCB traces or cables inside the first circuit board 201, and the second end of power module b 218 can also be connected to the first end of UBC connector 203 via PCB traces or cables inside the first circuit board 201 to transmit power signals. Power connector 202 and UBC connector 203 can transfer power signals to PCIe connector 204, which can then transmit power signals to the first PCIe device 205. The power signal between UBC connector 203 and PCIe connector 204 can be transmitted via cables.

[0075] It should be noted that power module a 217 and power module b 218 can be as follows: Figure 4 The power inlet connector 210 may also include the power inlet connector 210 and the step-down module 211, and may also include the PSU 209, the power inlet connector 210 and the step-down module 211. The above components can be connected by cables or by internal traces on the PCB.

[0076] In some embodiments, the power output from the first circuit board 201 to the power connector 202 and the UBC connector 203 may be different. In one possible implementation, the power output from the first circuit board 201 to the power connector 202 and the UBC connector 203 may be DC power of different voltages. For example, the power output from the first circuit board 201 to the power connector 202 may be 12V DC, and the power output from the first circuit board 201 to the UBC connector 203 may be 3.3V DC. Thus, the power supplied by the PCIe connector to the first PCIe device 205 may include 12V DC and 3.3V DC, respectively provided to the power pins of different first PCIe devices 205. In some embodiments, the different voltage power signals transmitted by the power connector 202 and the UBC connector 203 can power different PCIe devices.

[0077] It should be understood that the UBC connector 203 generally transmits a relatively small amount of power, which may not meet the rated power requirements of the first PCIe device 205. Therefore, Figure 3The purpose of the power connector 202 is mainly to meet the rated power requirement of the first PCIe device 205. In actual application scenarios, the power connector 202 can be flexibly arranged at a suitable position, not limited to beside the UBC connector 203, or even not limited to the first circuit board 201, which can improve the flexibility of the layout.

[0078] It should be noted that in a possible implementation, the first end of the power connector 202 and the first end of the UBC connector 203 can be welded on the first circuit board 201 (such as a mainboard) in advance. Moreover, the pin of the power connector 202 and the power interface (pin) on the first circuit board 201 can be connected together through a cable, and the pin of the UBC connector 203 and the PCIe interface on the first circuit board 201 can be connected together through a cable. The power connector 202 can also reserve a female power connector outside, and the UBC connector 203 can also reserve a female UBC connector outside.

[0079] The first end pin of the PCIe connector 204 can be welded with one end of the second cable and the third cable, and the other end of the cable (i.e. the second cable) for transmitting PCIe signals and the cable (i.e. the second cable) for transmitting part of the power signals can be packaged into a male UBC connector (i.e. the first plug), and the other end of the cable (i.e. the third cable) for transmitting power can be packaged into a male power connector (i.e. the second plug). In this way, when an external PCIe device is needed, the male power connector of the PCIe connector 204 can be plugged with the female power connector of the power connector 202, and the male UBC connector of the PCIe connector 204 can be plugged with the female UBC connector of the UBC connector 203. Meanwhile, the PCIe connector 204 can also reserve an interface (slot) for connecting a PCIe device (such as a network card, a RAID card, etc.).

[0080] For example, Figure 11As shown, the second cable includes ends A2 and B2, and the third cable includes ends A1 and B1. Ends B2 of the second cable and B1 of the third cable can be soldered to the first end of the PCIe connector 204. End A2 of the second cable can be encapsulated as a first plug, and end A1 of the third cable can be encapsulated as a second plug. The first PCIe device 205 can be inserted into the slot of the PCIe connector 204 via its own gold fingers. It should be understood that in some embodiments, the first plug can be a male connector, in which case the corresponding connection end (such as the second end of the UBC connector 203 described above) can be a female connector. In other embodiments, the first plug can also be a female connector, in which case the corresponding connection end (such as the second end of the UBC connector 203 described above) can be a male connector. Similarly, the second plug can also be either a male or female connector.

[0081] It should be understood that the aforementioned first cable, second cable and third cable may include multiple conductors.

[0082] In one possible implementation, the PCIe connector 204 can be fixed inside the computing device 200 by screws, such as on the first circuit board 201, the second circuit board 208, or other boards of the computing device 200. It should be understood that the PCIe connector 204 can also be fixed inside the computing device 200 by other means (such as mounting recesses), which are not limited here.

[0083] It should be understood that UBC connectors have more application scenarios and greater flexibility compared to UBCCDD connectors. For example, UBC connectors can connect to Open Compute Project (OCP) cards, M.2 adapter boards, etc., while UBCCDD connectors cannot. Furthermore, because the female power connector of power connector 202 and the male power connector of PCIe connector 204 can be flexibly plugged in and out, as can the female UBC connector of UBC connector 203 and the male UBC connector of PCIe connector 204, UBC connector 203 can be flexibly used in practical applications. For example, if it is necessary to connect PCIe devices such as network cards or RAID cards, UBC connector 203 can be connected to the PCIe connector, and then the network card, RAID card, etc., can be connected through the PCIe connector. Moreover, the PCIe connector can be fixed to the circuit board of the computing device (such as the first circuit board 201 or the second circuit board 208 mentioned above) with screws. The circuit board of the computing device can also be fixed to the computing device with screws. For example, if you need to connect an OCP card, M.2 adapter board (hard drive adapter board), etc., you can directly connect the UBC connector 203 to the OCP card, M.2 adapter board, etc. via cable.

[0084] Please see Figure 12, Figure 12 This is a schematic diagram of the structure of another computing device disclosed in the embodiments of this application. Figure 12 As shown, in this scenario, the second end of UBC connector 203 can be connected to the first end of UBC connector 221 via a cable, and the second end of power connector 202 can be connected to the first end of power connector 220 via a cable. Power connector 220 and UBC connector 221 can be disposed on a fourth circuit board 222, which can also be provided with a 4C+ connector 223 and an OCP card 224 (second PCIe device). The second end of power connector 220 can be connected to the first end of 4C+ connector 223 via PCB traces or cables inside the fourth circuit board 222, and the second end of UBC connector 221 can also be connected to the first end of 4C+ connector 223 via PCB traces or cables inside the fourth circuit board 222. OCP card 224 can be connected to the second end of 4C+ connector 223; for example, OCP card 224 can be inserted into the slot of 4C+ connector 223 via its own gold fingers. It should be understood that in some embodiments, 4C+ connector 223 can also be replaced by a 4C connector and a 4C+ connector. The OCP NIC (Network Interface Card) 3.0 specification defines two sizes of OCP cards: large form factor (LFF) and small form factor (SFF). SFF network cards can have a 4C+ interface, while LFF network cards can have both 4C and 4C+ interfaces. The fourth circuit board 222 can be the backplane of the computing device.

[0085] In some embodiments, a Retimer card 219 may also be provided on the first circuit board 201 of the computing device. The Retimer card 219 primarily functions as a signal relay in the computing device, providing signal equalization and enhancement. When the signal transmission distance between the computing device and the PCIe device is long, the Retimer card 219 can assist in signal transmission. Specifically, the output terminal of the controller 207 and the first terminal of the Retimer card 219 can be connected via PCB traces or cables within the first circuit board 201, thereby transmitting high-speed signals to the Retimer card 219. The second terminal of the Retimer card 219 and the first terminal of the UBC connector 203 can be connected via PCB traces or cables within the first circuit board 201, thereby transmitting high-speed signals to the UBC connector 203.

[0086] As can be seen, by using a UBC connector + power connector to PCIe connector, the UBC connector 203 can be used flexibly according to different scenarios. For example, if more hard drives are needed for the computing device, the UBC connector 203 can be connected to an M.2 adapter board, which can connect to one or more M.2 solid-state drives (SSDs), thus expanding the storage capacity of the computing device 200. Figure 13 As shown, the second end of UBC connector 203 can be connected to the first end of UBC connector 226 via a cable, and the second end of power connector 202 can be connected to the first end of power connector 225 via a cable. Power connector 225 and UBC connector 226 can be mounted on M.2 adapter board 227. M.2 adapter board 227 can be used to connect one or more M.2 hard drives (second PCIe devices). Specifically, M.2 adapter board 227 can also be provided with one or more M.2 connectors (such as...). Figure 13 The M.2 connectors a 228 and b 229 are shown. The second end of the power connector 225 can be connected to the first end of the M.2 connectors a 228 and b 229 via PCB traces or cables inside the M.2 adapter board 227. Similarly, the second end of the UBC connector 226 can be connected to the first end of the M.2 connectors a 228 and b 229 via PCB traces or cables inside the M.2 adapter board 227. The M.2 hard drive a 230 can be connected to the second end of the M.2 connector a 228, and the M.2 hard drive b 231 can be connected to the second end of the M.2 connector b 229. For example, the M.2 hard drive a 230 can be inserted into the slot of the M.2 connector a 228 via its own gold fingers, and the M.2 hard drive b 231 can be inserted into the slot of the M.2 connector b 229 via its own gold fingers.

[0087] It can be understood that, since the UBCDD connector is relatively large, the UBCDD connector is generally arranged on a mainboard with a large space. Since the UBC connector and the power connector are relatively small, the UBC connector and the power connector can be flexibly arranged according to actual conditions, and can be arranged on other board cards, such as a switching board, a power backboard, and the like. Specifically, in some embodiments, the UBC connector 203 and the power connector 202 can be arranged on the same board card. For example, the UBC connector 203 and the power connector 202 can be both arranged on the first circuit board 201 of the computing device 200. For another example, the UBC connector 203 and the power connector 202 can be both arranged on a switching board (i.e., a board card on which a switching chip is arranged) of the computing device 200. In other embodiments, the UBC connector 203 and the power connector 202 can be arranged on different board cards. For example, the UBC connector 203 can be arranged on the first circuit board 201 of the computing device 200, and the power connector 202 can be arranged on a power backboard of the computing device 200. For another example, the UBC connector 203 can be arranged on a switching board of the computing device 200, and the power connector 202 can be arranged on a power backboard of the computing device 200.

[0088] Different computing device models can include different hardware devices. For example, assume that there are model A and model B, model A includes a RAID card and does not include an OCP card, and model B includes an OCP card and does not include a RAID card. Therefore, for a mainboard including only a UBCDD connector, it can be impossible to adapt to both models. However, if the UBCDD connector on the mainboard is replaced with a UBC connector + a power connector, it can be adapted to both models. For model A, the UBC connector can be connected to the OCP card through the 4C+ connector, which can be referred to the description of the 4C+ connector described above. For model B, the UBC connector and the power connector can be connected to a PCIe connector, and then the PCIe connector can be connected to the RAID card, and the PCIe connector can be fixed on a circuit board of the computing device, such as the first circuit board 201 or the second circuit board 208 described above. It should be understood that, by using the UBC connector + the power connector to convert the PCIe connector, the UBC connector can be shared in different models, so that the development of the mainboard can be reduced, and the development cycle of the computing device can be shortened. Figure 12

[0089] It should be noted that, Figure 6 and Figure 7 The computing device 200 shown in FIGS. 1-3 is only illustrative and does not constitute a limitation.

[0090] ​In the above implementation manner, by adopting the UBC connector + power connector to PCIe connector mode, the PCB area can be saved, and the wiring difficulty is reduced. Moreover, by adopting the UBC connector, the application scenarios can be expanded, and the flexibility of the application is improved. In addition, in the embodiment of the application, the high-speed signal (PCIe signal) is transmitted through the cable, so that the loss can be reduced, and the signal quality is improved.

[0091] It should be noted that the related information (i.e., the same information or similar information) and the related description in the above different embodiments can be mutually referred to.

[0092] It should be understood that the "connection" in the present application can be understood as direct connection (i.e., electrical connection); or can be understood as indirect connection, that is, connection through other devices, elements, modules, apparatuses, etc.

[0093] The technical terms used in the embodiments of the present application are only used for describing the specific embodiments and are not intended to limit the present application. In this document, the singular forms "a", "an" and "the" are used to include both the plural forms, unless the context clearly indicates otherwise. Further, the use of "include" and / or "contain" in the specification means that the features, integers, steps, operations, elements, and / or components exist, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, and / or components.

[0094] It should also be understood that in the embodiments of the present application, "at least one", "one or more" means one, two or more than two. The term "and / or", used to describe the association relationship of the associated objects, means that there can be three relationships; for example, A and / or B, which means that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents a "or" relationship between the associated objects before and after it.

[0095] In the present specification, the reference to "one embodiment" or "some embodiments" and the like means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Therefore, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in other some embodiments" and the like appearing in different places in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized.

[0096] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements (if any) described herein are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present application has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the application to the precise form disclosed.

[0097] The above detailed description has been given for the purposes of illustration and description, and not for the purposes of limiting the application as far as it is not limited by the appended claims.

Claims

1. A signal transmission circuit, characterized in that, Includes the first circuit board, the Union Bus UBC connector, and the power connector; The power interface of the first circuit board is connected to the first end of the power connector, and the PCIe interface of the first circuit board is connected to the first end of the UBC connector; the second end of the power connector is used to connect to the first PCIe device through the PCIe connector to supply power to the first PCIe device. The second end of the UBC connector is used to connect to the first PCIe device through the PCIe connector in order to transmit PCIe signals to the first PCIe device; The UBC connector and the power connector are mounted on the second circuit board; the power interface of the first circuit board and the first end of the power connector, as well as the PCIe interface of the first circuit board and the first end of the UBC connector, are connected by cables.

2. The signal transmission circuit according to claim 1, characterized in that, The first circuit board also includes a power module and a controller. The power module is used to transmit a first power supply to the power connector, and the controller is used to transmit PCIe signals to the UBC connector. The power connector is used to output the first power to the PCIe connector, and the UBC connector is used to output the PCIe signal to the PCIe connector; The PCIe connector is used to output the first power supply and the PCIe signal to the first PCIe device.

3. The signal transmission circuit according to claim 1, characterized in that, The second end of the UBC connector is connected to the first end of the PCIe connector via a second cable, and the second end of the power connector is connected to the first end of the PCIe connector via a third cable.

4. The signal transmission circuit according to claim 3, characterized in that, The first end of the PCIe connector includes at least one first pin and at least one second pin. The at least one first pin is soldered to one end of the second cable, and the other end of the second cable forms a first plug. The first plug is used to connect to the second end of the UBC connector. The at least one second pin is soldered to one end of the third cable, and the other end of the third cable forms a second plug. The second plug is used to connect to the second end of the power connector.

5. The signal transmission circuit according to any one of claims 1-4, characterized in that, The PCIe connector is fixedly mounted on the second circuit board.

6. The signal transmission circuit according to any one of claims 1-4, characterized in that, The first PCIe device is a network card, a redundant RAID card, or a graphics card.

7. A computing device, characterized in that, The computing device includes the signal transmission circuit as described in any one of claims 1-6.

8. A signal transmission circuit, characterized in that, It includes a first circuit board, a first unified bus UBC connector, a first power connector, a second UBC connector, a second power connector, and a first connector; the second UBC connector, the second power connector, and the first connector are all disposed on a fourth circuit board; The power interface of the first circuit board is connected to the first end of the first power connector, and the PCIe interface of the first circuit board is connected to the first end of the first UBC connector. The second end of the first power connector is connected to the first end of the second power connector via a cable. The second end of the second power connector is connected to the first end of the first connector via a printed circuit board (PCB) trace or cable on the fourth circuit board. The second end of the first connector is connected to the second PCIe device to supply power to the second PCIe device. The second end of the first UBC connector is connected to the first end of the second UBC connector via a cable. The second end of the second UBC connector is connected to the first end of the first connector via a printed circuit board (PCB) trace or cable on the fourth circuit board. The second end of the first connector is connected to the second PCIe device. The first connector is a 4C+ connector or an M.2 connector.

9. The signal transmission circuit according to claim 8, characterized in that, When the first connector is a 4C+ connector, the second PCIe device is an Open Compute Project card; when the first connector is a 4C+ connector and is an M.2 connector, the second PCIe device is an M.2 hard drive.

10. A computing device, characterized in that, The computing device includes the signal transmission circuit as described in claim 8 or 9.

11. A signal transmission circuit, characterized in that, Includes the first circuit board, the Union Bus UBC connector, and the power connector; The power interface of the first circuit board is connected to the first end of the power connector, and the PCIe interface of the first circuit board is connected to the first end of the UBC connector; the second end of the power connector is used to connect to the first PCIe device through the PCIe connector to supply power to the first PCIe device. The second end of the UBC connector is used to connect to the first PCIe device through the PCIe connector in order to transmit PCIe signals to the first PCIe device; The first end of the UBC connector is soldered to the first end of the power connector on the first circuit board.

12. A computing device, characterized in that, The computing device includes the signal transmission circuit as described in claim 11.

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