Memristor-based in-memory logic circuit, in-memory logic computing system and application

Abstract

The application discloses an in-memory logic circuit based on a memistor, an in-memory logic computing system and application, and belongs to the technical field of integrated circuits.The in-memory logic circuit comprises a first storage unit and a second storage unit which are connected in parallel, and a sensitive amplifier for generating a logic operation result; the two storage units comprise a memistor and a MOS gating tube which are connected in series; the resistance value state of the two memristors is used to represent a first group of logic input signals, and the potential signal applied to the gate of the two MOS gating tubes is used to represent a second group of logic input signals. The application further provides an in-memory logic computing system and application. The in-memory logic circuit has a simple structure and can realize non-destructive logic computation. When the in-memory logic circuit is applied to an in-memory logic computing system, the reliability influence of device aging on the memristor computing system caused by frequent erasing and writing of the memristor can be avoided, the compatibility of the logic computing unit and the memristor array is improved, and the programmable performance of the logic operation unit can be ensured.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and more specifically, relates to an in-memory logic circuit, an in-memory logic computing system, and its application based on memristors. Background Technology

[0002] In-memory computing, as a computing processing method for emerging edge applications such as target recognition, autonomous driving, artificial intelligence, big data, and 5G, has attracted widespread attention due to its potential to overcome the memory wall and power wall bottlenecks in traditional von Neumann systems. Memristor-based non-volatile logic computing is one of the promising technical routes for realizing this architecture. Memristors utilize resistance as a physical state variable, and under pulse voltage operation, they can switch between two stable resistance states: a high resistance state (RHRS) and a low resistance state (RLRS). The high resistance state corresponds to logic "0", and the low resistance state corresponds to logic "1".

[0003] Currently, memristor-based logic computation methods are mainly divided into two categories: state logic circuits and CMOS hybrid logic circuits. State logic circuits represent the logic inputs and outputs using the high and low resistance states of the memristor. Logical operations are achieved by changing the resistance state of the memristor through an applied bias voltage. This mainly includes implied logic circuits and memristor-assisted logic (MAGIC) circuits. CMOS hybrid logic circuits based on memristors represent the logic inputs and outputs using the high and low levels of CMOS auxiliary circuits or auxiliary MOSFETs. Logic computation is achieved by configuring the voltage division ratio of the high and low resistance states of the memristor in the hybrid logic circuit.

[0004] However, the computation process of memristor-based state logic circuits requires repeated programming of the memristors, affecting device lifespan and reliability, and computational efficiency decreases significantly with increasing logic cascading. MAGIC logic circuits require memristor series and parallel designs for different logic gates, increasing design complexity; IMPLY logic circuits require additional auxiliary resistors, and the logic output overwrites input data, failing to meet the requirement of protecting input weights in neural network applications. CMOS hybrid logic circuits based on memristors disrupt the original structure of the memristor array, making large-scale integration impossible; furthermore, these logic circuits have a single logic function, implementing only one logic operation within a single circuit, leading to complex applications. Summary of the Invention

[0005] To address the shortcomings and improvement needs of existing technologies, this invention provides an in-memory logic circuit, an in-memory logic computing system, and its application based on memristors. The purpose is to design a simple logic operation circuit compatible with memristor arrays, capable of non-destructive logic computing. Furthermore, its application in large-scale integrated circuits can reduce the overhead of peripheral auxiliary computing components, improve the reliability of memristor in-memory computing systems, and reduce complexity.

[0006] To achieve the above objectives, according to a first aspect of the present invention, a memristor-based in-memory logic circuit is provided, comprising:

[0007] The first and second memory cells are connected in parallel, along with a sensitive amplifier;

[0008] The first memory cell includes a first memristor and a first MOS transistor connected in series, and the second memory cell includes a second memristor and a second MOS transistor connected in series.

[0009] One end of the first memristor and one end of the second memristor are grounded; the parallel terminals of the first MOS gate and the second MOS gate are connected to the first input terminal of the sensitive amplifier, the second input terminal of the sensitive amplifier is connected to the reference signal, and the positive and negative output potential signals of the sensitive amplifier are the results of logic operations;

[0010] The resistance values ​​of the first memristor and the second memristor represent the first set of logic input signals, and the potential signals applied to the gates of the first MOS transistor and the second MOS transistor represent the second set of logic input signals.

[0011] Furthermore,

[0012] Let the first input signal A represent the resistance state Din1(A) of the first memristor, and the inverted signal of the first input signal A. As the resistance state of the second memristor

[0013] Let the second input signal B represent the potential signal Din2′(B) applied to the gate of the second MOS gate, and let the inverted signal of the second input signal B be... As the potential signal applied to the gate of the first MOS gate

[0014] The sensitive amplifier generates XOR and XOR NOT logic operation results.

[0015] Furthermore,

[0016] The first input signal A represents the resistance state Din1(A) of the first memristor, and the resistance state of the second memristor is set to the low resistance state Din1′(1);

[0017] Let the second input signal B represent the potential signal Din2′(B) applied to the gate of the second MOS gate, and let the inverted signal of the second input signal B be... As the potential signal applied to the gate of the first MOS gate

[0018] The sensitive amplifier generates OR and NOR logic operation results.

[0019] Furthermore,

[0020] Let the first input signal A represent the resistance state Din1(A) of the first memristor, and the inverted signal of the first input signal A. As the resistance state of the second memristor

[0021] The second input signal B represents the potential signal Din2′(B) applied to the gate of the second MOS gate, and the potential signal applied to the gate terminal WL0 of the first MOS gate is set to a high level Din2(1);

[0022] The sensitive amplifier generates OR and NOR logic operation results.

[0023] Furthermore,

[0024] The first input signal A represents the resistance state Din1′(A) of the second memristor, and the resistance state of the first memristor is set to the high resistance state Din1(0);

[0025] Let the second input signal B represent the potential signal Din2′(B) applied to the gate of the second MOS gate, and let the inverted signal of the second input signal B be... As the potential signal applied to the gate of the first MOS gate ;

[0026] The sensitive amplifier generates AND and NAND logic operation results.

[0027] Furthermore,

[0028] Let the first input signal A represent the resistance state Din1(A) of the first memristor, and the inverted signal of the first input signal A. As the resistance state of the second memristor

[0029] The second input signal B represents the potential signal Din2(B) applied to the gate of the first MOS gate, and the potential signal applied to the gate of the second MOS gate is set to a low level Din2′(0);

[0030] The sensitive amplifier generates AND and NAND logic operation results.

[0031] According to a second aspect of the present invention, a memristor-based in-memory logic computing system is provided, comprising at least one in-memory logic circuit as described in any one of the first aspects.

[0032] Furthermore, it also includes: word line decoder and driver circuit, source line decoder gating and driver circuit, bit line decoder gating and driver circuit, and controller;

[0033] The memristor-based computing units form an array structure. One end of the memristor-based computing units in the same column is connected to the bit line decoding gating and driving circuit via a bit line, and the other end is connected to the source line decoding gating and driving circuit via a source line, and is connected to the first input terminal of the sensitive amplifier via the source line decoding gating and driving circuit. The memristor-based computing units in the same row are connected to the word line decoder and driving circuit via word lines. The memristor-based computing units are the first and second memory units connected in parallel.

[0034] The controller controls the word line decoder and driver circuit, the source line decoder gating and driver circuit, and the bit line decoder gating and driver circuit, respectively.

[0035] Furthermore, the array structure formed between the memristor-in-memristor storage units is a two-transistor two-memristor array structure, or a two-group one-transistor one-memristor parallel array structure.

[0036] According to a third aspect of the present invention, a neural network in-memory computing hardware accelerator is provided for protecting weight data in the neural network, including the in-memory logic computing system described in any of the second aspects.

[0037] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0038] (1) The present invention designs a new memory logic circuit based on memristors by using two sets of parallel memory cells (each set of memory cells includes a memristor and a gating transistor connected in series) and a sensitive amplifier. The memory logic circuit has a simple structure.

[0039] During calculation, the resistance states of two memristors represent the first set of input signals, and the potential signals of the gates of two select transistors represent the second set of input signals. During the logic calculation, the resistance states of the two memristors do not change, enabling non-destructive logic calculation and facilitating large-scale integration.

[0040] (2) Furthermore, the in-memory logic circuit designed in this invention has programmable logic functions, can realize different logic operations, and can be applied to complex logic operation systems; at the same time, by changing the resistance state of the two memristors and the potential signal of the gate of the two select transistors, the logic calculations of "XOR / XOR NOT", "OR / OR NOT" and "AND / NAND" are realized, which makes it easy to realize different logic functions in the same circuit structure, and does not require changing the series and parallel relationship of the memristors, thus reducing the complexity of design and application; at the same time, it avoids the impact of device aging caused by frequent erasure and writing of memristors on the reliability of the memristor in-memory computing system.

[0041] (3) Further, based on the in-memory logic circuit designed in this invention, an in-memory logic computing system based on memristors is provided. This in-memory logic computing system does not require the introduction of additional auxiliary computing components other than the peripheral circuits necessary for the memory array. It can reduce the overhead of peripheral auxiliary computing components, improve the reliability of the computing system, and enhance the compatibility between the in-memory logic circuit and the memristor array structure. Moreover, the structure of the computing system is relatively simple.

[0042] (4) Preferably, the memristor-based in-memory logic computing system of the present invention can be a logic computing unit with two transistors and two memristors and a memristor array structure, or it can be two sets of parallel structures with one transistor and one memristor. The array structure formed is flexible and easy to use.

[0043] (5) Further, the in-memory logic computing system provided by the present invention is applied to a neural network, and the input weights are represented as the resistance states of the memristors in the memristor array. During the network computing process, since the resistance states of the memristors do not change, the non-destructive requirement of the neural network weight data is met.

[0044] In summary, the memristor-based in-memory logic circuit of this invention is a pass-transistor-memristor logic (PTM logic), which has a simple structure and can realize non-destructive logic calculation. When applied to in-memory logic computing systems, it can avoid the impact of device aging caused by frequent memristor erasure and writing on the reliability of memristor computing systems. While improving the compatibility between logic computing units and memristor arrays, it can also ensure the programmable performance of logic operation units. Attached Figure Description

[0045] Figure 1(a) shows the in-memory logic circuit provided by the present invention; Figure 1(b) shows a schematic diagram of the corresponding input signal settings.

[0046] Figure 2(a) is a schematic diagram of the logic circuit in the memristor provided in Embodiment 1 of the present invention to implement the logic "XOR / XOR NOT" operation; Figure 2(b) is the corresponding truth table.

[0047] Figure 3(a) is a schematic diagram of the memristor in-memory logic circuit implementing the first logic "OR / OR NOT" operation provided in Embodiment 2 of the present invention; Figure 3(b) is the corresponding truth table.

[0048] Figure 4(a) is a schematic diagram of the memristor in-memory logic circuit provided in Embodiment 3 of the present invention implementing the second logic "OR / OR NOT" operation; Figure 4(b) is the corresponding truth table.

[0049] Figure 5(a) is a schematic diagram of the memristor in-memory logic circuit provided in Embodiment 4 of the present invention implementing the first logic "AND / NAND" operation; Figure 5(b) is the corresponding truth table.

[0050] Figure 6(a) is a schematic diagram of the memristor in-memory logic circuit provided in Embodiment 5 of the present invention implementing the second type of logic "AND / NAND" operation; Figure 6(b) is the corresponding truth table.

[0051] Figure 7 This is a schematic diagram of the in-memory logic computing system structure based on a memristor array (2T2R) provided in Embodiment 6 of the present invention.

[0052] Figure 8 This is a schematic diagram of the non-destructive parallel operation of the memristor in-memory logic circuit provided in Embodiment 6 of the present invention, taking the "XOR / XOR NOT" operation of the input vector and weight vector in a neural network as an example.

[0053] In all the accompanying drawings, the same reference numerals are used to denote the same elements and structures, wherein:

[0054] 1 is the first memory cell, 11 is the first memristor, 12 is the first MOS transistor, 2 is the second memory cell, 21 is the second memristor, 22 is the second MOS transistor, and 3 is the sensitive amplifier. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0056] In this invention, the terms "first," "second," etc., used in the invention and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0057] As shown in Figure 1(a), the memory logic circuit based on memristors of the present invention mainly includes: a first memory cell 1 and a second memory cell 2 connected in parallel, and a CMOS sensitive amplifier 3 for generating logic operation results; wherein, the first memory cell 1 includes a first memristor 11 and a first MOS selector 12 connected in series, and the second memory cell 2 includes a second memristor 21 and a second MOS selector 22 connected in series; one end BL0 of the first memristor 11 is grounded, and the other end is connected in series with the first MOS selector 12; one end BL1 of the second memristor 21 is grounded, and the other end is connected in series with the second MOS selector 22; the parallel terminal SL0 of the first MOS selector 12 and the second MOS selector 22 is connected to the first input terminal of the sensitive amplifier 3; the second input terminal of the sensitive amplifier 3 is connected to a reference signal; the signal received by the first input terminal of the sensitive amplifier 3 is compared with the amplitude of the reference signal at the second input terminal; and the positive and negative output potential signals of the sensitive amplifier 3 are the logic operation results.

[0058] Specifically, when the signal amplitude received at the first input terminal of the sensitive amplifier is greater than the reference signal amplitude at the second input terminal of the sensitive amplifier, the non-inverting output terminal of the sensitive amplifier outputs a high-potential signal and the inverting output terminal outputs a low-potential signal; when the signal amplitude received at the first input terminal of the sensitive amplifier is less than the reference signal amplitude at the second input terminal of the sensitive amplifier, the non-inverting output terminal of the sensitive amplifier outputs a low-potential signal and the inverting output terminal outputs a high-potential signal.

[0059] The memory logic circuit based on memristors of the present invention includes two sets of logic input signals, as shown in Figure 1(b). The first set of logic input signals (Din1, Din1′) is represented by the resistance values ​​of the first memristor 11 and the second memristor 21. When the first memristor or the second memristor is in a high resistance state, it represents logic "0", and when it is in a low resistance state, it represents logic "1". The second set of logic input signals (Din2, Din2′) is represented by the potential signals of the gates of the first MOS transistor 12 and the second MOS transistor 22. When the potential signal of the gate terminal WL0 of the first MOS transistor 12 or the potential signal of the gate terminal WL1 of the second MOS transistor 22 is high, it represents logic "1", and when it is low, it represents logic "0".

[0060] The first or second memristor in this invention includes a resistive random access memory (RRAM), a phase change memory (PRAM), or a magnetic random access memory (MRAM) with two ends.

[0061] Refer to Figure 1(a) and Figure 1(b), and combine with Figure 2(a). Figures 2(b)-6(a) Figure 6(b) provides a detailed description of the memristor in-memory logic calculation circuit provided by the present invention.

[0062] Example 1

[0063] As shown in Figures 2(a) and 2(b), based on the memristor-based in-memory logic circuit described above, the method for implementing the logic operation as "XOR / XOR NOT" is as follows:

[0064] Let the first input signal A represent the resistance state Din1(A) of the first memristor 11, and the inverted signal of the first input signal A. As the resistance state of the second memristor 21

[0065] Let the second input signal B be represented as the potential signal Din2′(B) applied to the gate terminal WL1 of the second MOS selector 22, and the inverted signal of the second input signal B. The potential signal applied to the gate terminal WL0 of the first MOS select transistor 12

[0066] The signal received at the first input terminal of the sensitive amplifier 3 is compared with the amplitude of the reference signal at the second input terminal, generating a logic output potential signal with inverted "XOR" and "XOR NOT" signals. This represents the result of the XOR operation on the output of the sensitive amplifier 3. This represents the result of the "XOR NOT" logical operation.

[0067] Example 2

[0068] As shown in Figures 3(a) and 3(b), based on the memristor-based in-memory logic circuit described above, the method for implementing the first "OR / OR NOT" logic operation is as follows:

[0069] The first input signal A is represented as the resistance state Din1(A) of the first memristor 11, and the resistance state of the second memristor 21 is set to the low resistance state Din1′(1);

[0070] Let the second input signal B be represented as the potential signal Din2′(B) applied to the gate terminal WL1 of the second MOS selector 22, and the inverted signal of the second input signal B. The potential signal applied to the gate terminal WL0 of the first MOS select transistor 12

[0071] The signal received at the first input terminal of the sensitive amplifier 3 is compared with the amplitude of the reference signal at the second input terminal, generating a logic output potential signal with inverted OR and NOR operations. Here, Dout(A+B) represents the result of the OR logic operation output by the sensitive amplifier 3. It represents the result of the "OR NOT" logical operation.

[0072] Example 3

[0073] As shown in Figures 4(a) and 4(b), based on the memristor-based in-memory logic circuit described above, the method for implementing the second "OR / OR NOT" logic operation is as follows:

[0074] Let the first input signal A represent the resistance state Din1(A) of the first memristor 11, and the inverted signal of the first input signal A. As the resistance state of the second memristor 21

[0075] The second input signal B is represented as the potential signal Din2′(B) applied to the gate terminal WL1 of the second MOS gate 22, and the potential signal applied to the gate terminal WL0 of the first MOS gate 12 is set to a high level Din2(1).

[0076] The signal received at the first input terminal of the sensitive amplifier 3 is compared with the amplitude of the reference signal at the second input terminal, generating a logic output potential signal with inverted OR and NOR operations. Here, Dout(A+B) represents the result of the OR logic operation output by the sensitive amplifier 3. It represents the result of the "OR NOT" logical operation.

[0077] Example 4

[0078] As shown in Figures 5(a) and 5(b), based on the memristor-based in-memory logic circuit described above, the method for implementing the first type of "AND / NAND" logic operation is as follows:

[0079] The first input signal A is used to represent the resistance state Din1′(A) of the second memristor 21, and the resistance state of the first memristor 11 is set to the high resistance state Din1(0);

[0080] Let the second input signal B be represented as the potential signal Din2′(B) applied to the gate terminal WL1 of the second MOS selector 22, and the inverted signal of the second input signal B. The potential signal applied to the gate terminal WL0 of the first MOS select transistor 12

[0081] The signal received at the first input terminal of the sensitive amplifier 3 is compared with the amplitude of the reference signal at the second input terminal, generating a logic output potential signal with inverted AND and NAND operations. Here, Dout(A·B) represents the result of the AND logic operation output by the sensitive amplifier 3. This represents the result of a "NAND" logical operation.

[0082] Example 5

[0083] As shown in Figures 6(a) and 6(b), based on the memristor-based in-memory logic circuit described above, the method for implementing the second type of AND / NAND logic operation is as follows:

[0084] Let the first input signal A represent the resistance state Din1(A) of the first memristor 11, and the inverted signal of the first input signal A. As the resistance state of the second memristor 21

[0085] The second input signal B is represented as the potential signal Din2(B) applied to the gate terminal WL0 of the first MOS gate 12, and the potential signal applied to the gate terminal WL1 of the second MOS gate 22 is set to a low level Din2′(0).

[0086] The signal received at the first input terminal of the sensitive amplifier 3 is compared with the amplitude of the reference signal at the second input terminal, generating a logic output potential signal with inverted AND and NAND operations. Here, Dout(A·B) represents the result of the AND logic operation output by the sensitive amplifier 3. This represents the result of a "NAND" logical operation.

[0087] Wherein, when the first input signal A makes Din1(A) or Din1′(A) a low-impedance state, it represents a logic input "1"; when the first input signal A makes Din1(A) or Din1′(A) a high-impedance state, it represents a logic input "0". The resistance states are opposite; when the second input signal B makes Din2(B) or Din2′(B) high, it represents logic input "1"; when the second input signal B makes Din2(B) or Din2′(B) low, it represents logic input "0". Din2′(B) and The potential signal is opposite.

[0088] Example 6

[0089] like Figure 7 As shown, based on the above-mentioned memristor-based in-memory logic circuit, the present invention also provides a memristor-based in-memory logic computing system, which mainly includes: at least one memristor in-memory computing unit (RRAM CIM Cell), a sensitive amplifier (SA), a word line (WL) decoder and driving circuit, a source line (SL) decoder gating and driving circuit, a bit line (BL) decoder gating and driving circuit, and an in-memory logic computing system controller;

[0090] The memristor-based computing units form an array structure. One end of the memristor-based computing units in the same column is connected to the source line (SL) decoding and driving circuit through the source line, and is also connected to the first input terminal of the sensitive amplifier 3 through the source line (SL) decoding and driving circuit. The other end of the memristor-based computing units in the same column is connected to the bit line (BL) decoding and driving circuit through the bit line. The memristor-based computing units in the same row are connected to the word line decoder and driving circuit through the word line. The memristor-based computing units are the first storage unit 1 and the second storage unit 2 connected in parallel.

[0091] The in-memory logic computing system controller controls the word line decoder and driver circuit, the source line (SL) decoder gating and driver circuit, and the bit line (BL) decoder gating and driver circuit.

[0092] The memristor's internal computing unit can be a logic computing unit of two transistors and two memristors (2T2R) and a memristor array structure, or it can be a parallel structure of two sets of one transistor and one memristor (1T1R), or other forms of memristor array structure.

[0093] Specifically, such as Figure 8 As shown, taking the XOR / XOR NOT operation between the input vector and the weight vector in a neural network convolution calculation application as an example, this invention illustrates that the memristor-based in-memory logic calculation system can realize parallel XOR / XOR NOT operations on weights that are compatible with memristor arrays.

[0094] The positive and negative combinations of different weight vectors in a neural network can be represented as the resistance states of memristors in a memristor array (refer to...). Figure 8 w1, (etc.), the combination of positive and negative input vectors is represented as a word line in the memristor array (refer to...). Figure 8 Potential signals of WL0, WL1, etc. (refer to) Figure 8 in1, ). In-memory logic units located on the same word line can perform XOR and XOR NOT logic operations in parallel, via the source lines in the memristor array (see reference). Figure 8 SL0, SL k The sensitive amplifier (SA) on the (etc.) generates a logic operation output potential signal (refer to) Figure 8 middle (etc.), and protect the weight vector data (see Figure 8 w1, The memristor's resistance remains unchanged during calculations, meaning there is no need for frequent erasure and rewriting, resulting in high reliability.

[0095] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memristor-based in-memory logic circuit, characterized by, The application relates to a logic operation circuit. The first storage unit (1) and the second storage unit (2) are connected in parallel, and a sensitive amplifier (3) is arranged between the first storage unit (1) and the second storage unit (2); The first storage unit (1) comprises a first memristor (11) and a first MOS gating tube (12) connected in series, and the second storage unit (2) comprises a second memristor (21) and a second MOS gating tube (22) connected in series; One end of the first memristor (11) and the second memristor (21) is grounded; the parallel ends of the first MOS gating tube (12) and the second MOS gating tube (22) are connected with the first input end of the sensitive amplifier (3), the second input end of the sensitive amplifier (3) is connected with a reference signal, and the positive and negative phase output potential signals of the sensitive amplifier (3) are logic operation results; The resistance state of the first memristor (11) and the second memristor (21) represents a first group of logic input signals, and the potential signal applied to the gate of the first MOS gating tube (12) and the second MOS gating tube (22) represents a second group of logic input signals; with a first input signal representing a resistance state of the first memristor (11) , a first input signal an inverted signal of the first input signal as a resistance state of the second memristor (21) ; with a second input signal a potential signal applied to the gate of the second MOS gate (22) , second input signal an inverted signal of the second input signal as a potential signal applied to the gate of the first MOS gate (12) ; The sensitive amplifier (3) generates "XOR" and "XOR NOT" logic operation results.

2. A memristor-based in-memory logic circuit, comprising: The application relates to a logic operation circuit. The first storage unit (1) and the second storage unit (2) are connected in parallel, and a sensitive amplifier (3) is arranged between the first storage unit (1) and the second storage unit (2); The first storage unit (1) comprises a first memristor (11) and a first MOS gating tube (12) connected in series, and the second storage unit (2) comprises a second memristor (21) and a second MOS gating tube (22) connected in series; One end of the first memristor (11) and the second memristor (21) is grounded; the parallel ends of the first MOS gating tube (12) and the second MOS gating tube (22) are connected with the first input end of the sensitive amplifier (3), the second input end of the sensitive amplifier (3) is connected with a reference signal, and the positive and negative phase output potential signals of the sensitive amplifier (3) are logic operation results; The resistance state of the first memristor (11) and the second memristor (21) represents a first group of logic input signals, and the potential signal applied to the gate of the first MOS gating tube (12) and the second MOS gating tube (22) represents a second group of logic input signals; with a first input signal representing a resistance state of the first memristor (11) , the resistance state of the second memristor (21) being set to a low resistance state ; with a second input signal a potential signal applied to the gate of the second MOS gate (22) , second input signal an inverted signal of the second input signal as a potential signal applied to the gate of the first MOS gate (12) ; The sensitive amplifier (3) generates "OR" and "OR NOT" logic operation results.

3. A memristor-based in-memory logic circuit, comprising: The application relates to a logic operation circuit. The first storage unit (1) and the second storage unit (2) are connected in parallel, and a sensitive amplifier (3) is arranged between the first storage unit (1) and the second storage unit (2); The first storage unit (1) comprises a first memristor (11) and a first MOS gating tube (12) connected in series, and the second storage unit (2) comprises a second memristor (21) and a second MOS gating tube (22) connected in series; One end of the first memristor (11) and the second memristor (21) is grounded; the parallel ends of the first MOS gating tube (12) and the second MOS gating tube (22) are connected with the first input end of the sensitive amplifier (3), the second input end of the sensitive amplifier (3) is connected with a reference signal, and the positive and negative phase output potential signals of the sensitive amplifier (3) are logic operation results; The resistance state of the first memristor (11) and the second memristor (21) represents a first group of logic input signals, and the potential signal applied to the gate of the first MOS gating tube (12) and the second MOS gating tube (22) represents a second group of logic input signals; The sensitive amplifier (3) generates "OR" and "OR NOT" logic operation results. The resistance state of the first and second memristors (11, 21) represents a first set of logic input signals, and the potential signal applied to the gates of the first and second MOS pass-gates (12, 22) represents a second set of logic input signals. with a first input signal representing a resistance state of the first memristor (11) , a first input signal an inverted signal of the first input signal as a resistance state of the second memristor (21) ; with a second input signal a potential signal applied to the gate terminal of the second MOS gate (22) is represented by Vg2 a potential signal applied to the gate terminal WL0 of the first MOS gate (12) is set to high level ; The sensitive amplifier (3) generates "and" and "and not" logic operation results.

4. A memristor-based in-memory logic circuit, comprising: It comprises: a first storage unit (1) and a second storage unit (2) connected in parallel with each other, and a sensitive amplifier (3); The first storage unit (1) comprises a first memristor (11) and a first MOS pass-gate (12) connected in series, and the second storage unit (2) comprises a second memristor (21) and a second MOS pass-gate (22) connected in series; One end of the first and second memristors (11, 21) is grounded; the parallel ends of the first and second MOS pass-gates (12, 22) are connected to the first input end of the sensitive amplifier (3), the second input end of the sensitive amplifier (3) is connected to a reference signal, and the positive and negative phase output potential signals of the sensitive amplifier (3) are logic operation results; The resistance state of the first and second memristors (11, 21) represents a first set of logic input signals, and the potential signal applied to the gates of the first and second MOS pass-gates (12, 22) represents a second set of logic input signals. with a first input signal representing a resistance state of the second memristor (21) , the resistance state of the first memristor (11) is set to a high resistance state ; with a second input signal a potential signal applied to the gate of the second MOS gate (22) , second input signal an inverted signal of the second input signal as a potential signal applied to the gate of the first MOS gate (12) ; The sensitive amplifier (3) generates "and" and "and not" logic operation results.

5. A memristor-based in-memory logic circuit, comprising: It comprises: a first storage unit (1) and a second storage unit (2) connected in parallel with each other, and a sensitive amplifier (3); The first storage unit (1) comprises a first memristor (11) and a first MOS pass-gate (12) connected in series, and the second storage unit (2) comprises a second memristor (21) and a second MOS pass-gate (22) connected in series; One end of the first and second memristors (11, 21) is grounded; the parallel ends of the first and second MOS pass-gates (12, 22) are connected to the first input end of the sensitive amplifier (3), the second input end of the sensitive amplifier (3) is connected to a reference signal, and the positive and negative phase output potential signals of the sensitive amplifier (3) are logic operation results; The resistance state of the first and second memristors (11, 21) represents a first set of logic input signals, and the potential signal applied to the gates of the first and second MOS pass-gates (12, 22) represents a second set of logic input signals. with a first input signal representing a resistance state of the first memristor (11) , a first input signal an inverted signal of the first input signal as a resistance state of the second memristor (21) ; with a second input signal a potential signal applied to the gate of the first MOS gate (12) is represented by a potential signal applied to the gate of the second MOS gate (22) is set to low ; The sensitive amplifier (3) generates "and" and "and not" logic operation results.

6. A memristor-based in-memory logic computing system, comprising: It comprises at least one in-memory logic circuit according to any one of claims 1-5.

7. The compute-in-memory system of claim 6, wherein, It further comprises: a word line decoder and driving circuit, a source line decoder and driving circuit, a bit line decoder and driving circuit, and a controller; The array structure is formed between the memristor in-memory computing units, one end of the memristor in-memory computing units in the same column is connected to the bit line decoding gating and driving circuit through the bit line, the other end is connected to the source line decoding gating and driving circuit through the source line, and is connected to the first input end of the sense amplifier (3) through the source line decoding gating and driving circuit; the memristor in-memory computing units in the same row are connected to the word line decoder and driving circuit through the word line; wherein the memristor in-memory computing unit is the first storage unit (1) and the second storage unit (2) which are connected in parallel; The controller controls the word line decoder and driving circuit, the source line decoding gating and driving circuit, and the bit line decoding gating and driving circuit respectively.

8. The compute-in-memory system of claim 7, wherein, The array structure formed between the memristor in-memory computing units is a two-transistor two-memristor array structure, or an array structure of two groups of one-transistor one-memristor connected in parallel.

9. A neural network in-memory computing hardware accelerator for protecting weight data in the neural network, comprising: The in-memory logic computing system of any one of claims 6-8 is included.

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