Memory with dqs pulse control circuitry and associated systems, devices, and methods

Abstract

Disclosed herein are memories having DQS pulse control circuitry, and associated systems, devices, and methods. In one embodiment, a memory device includes a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width that is greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width that is greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse having a fourth width that is equivalent to the third width based at least in part on the third pulse.

Description

Technical Field

[0001] This disclosure relates to memory systems, apparatus, and methods. More specifically, this disclosure relates to a memory having a data strobe (DQS) pulse control circuitry system, and associated systems, apparatus, and methods. Background Technology

[0002] Memory devices are widely used to store information associated with various electronic devices such as computers, wireless communication devices, cameras, digital displays, and so on. Memory devices are often provided as internal semiconductor integrated circuits and / or external removable devices within computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory, including Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), requires an external power supply to maintain its data. In contrast, non-volatile memory retains its stored data even without an external power supply. Non-volatile memory is used in a wide variety of technologies, including flash memory (e.g., NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others. Improvements to memory devices typically include increasing memory cell density, increasing read / write speeds or further reducing operational latency, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. Summary of the Invention

[0003] In one aspect, this disclosure relates to a memory device comprising: an external terminal configured to receive an external timing signal comprising a first pulse having a first pulse width; and a circuit system operatively coupled to the external terminal, wherein the circuit system is configured to: generate a second pulse at least partially based on the first pulse, wherein the second pulse has a second pulse width greater than the width of the first pulse, and output an internal timing signal comprising the second pulse.

[0004] In another aspect, this disclosure relates to a memory system comprising: a memory controller; and a memory device operatively connected to the memory controller, wherein the memory device includes: an external terminal configured to receive an external timing signal from the memory controller, the external timing signal including a first pulse having a first pulse width; and a circuit system operatively coupled to the external terminal, wherein the circuit system is configured to: generate a second pulse at least partially based on the first pulse, wherein the second pulse has a second pulse width greater than the first pulse width, and output an internal timing signal including the second pulse.

[0005] In another aspect, this disclosure relates to a circuit comprising: a set / reset (SR) latch; and a delay element having (a) an input operatively connected to an output of the SR latch and (b) an output operatively connected to a second input of the SR latch, wherein: the circuit is configured to receive an input corresponding to an external timing signal, and the circuit is further configured to output an internal timing signal at least in part based on the external timing signal. Attached Figure Description

[0006] Many aspects of this disclosure can be better understood with reference to the following figures. The components in the figures are not necessarily to scale. In fact, the focus is on clearly illustrating the principles of this disclosure. The figures should not be construed as limiting this disclosure to the specific embodiments depicted, but are for explanation and understanding only.

[0007] Figure 1A A block diagram illustrating a memory system configured according to various embodiments of the technology according to the present invention.

[0008] Figure 1B A block diagram illustrating a memory device configured according to various embodiments of the technology according to the present invention.

[0009] Figure 2A Signal diagram for complementary external DQS signal and external data (DQ) signal.

[0010] Figure 2B This is a signal diagram of the internal DQS signal and the internal DQ signal.

[0011] Figure 3 A schematic diagram of a DQS pulse control circuit system configured for various embodiments of the present invention.

[0012] Figure 4 To illustrate the operation of various embodiments of the technology according to the present invention Figure 3 The flowchart shows the method for the DQS pulse control circuit system.

[0013] Figure 5A and 5B Various embodiments of the present invention Figure 3 Signal diagram of the DQS pulse control circuit system.

[0014] Figure 6 This is a signal diagram of the internal DQS signal and the internal DQ signal according to various embodiments of the present invention.

[0015] Figure 7 A schematic diagram of a system comprising various embodiments of a memory device or system configured according to the technology of the present invention. Detailed Implementation

[0016] As discussed in more detail below, the technology disclosed herein relates to memories having a DQS pulse control circuitry system, and associated systems, apparatus, and methods. In some embodiments, a memory device may include a circuitry operatively coupled to a DQS terminal configured to receive an external DQS signal. In operation, the circuitry may be configured to extend the pulse width of any DQS pulse over the external DQS signal, the pulse width being less than a minimum pulse width. Therefore, the circuitry ensures that any DQS pulse output by the circuitry over an internal DQS signal has a width greater than or equal to the minimum pulse width. Those skilled in the art will understand that this technology may have additional embodiments, and this technology may be described without further reference. Figures 1A to 7 The described embodiments are practiced in several details.

[0017] In the embodiments shown below, memory devices and systems are described primarily in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the invention may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., NAND and / or NOR) storage media.

[0018] A. Overview

[0019] In many memory systems, when the memory controller instructs the memory device to write data to its memory array, the memory controller supplies an external DQS signal to the memory device. The memory controller can supply data to the DQ terminal of the memory device, and the external DQS signal can be used as a clock to gate data into the memory device via the DQ terminal. In other words, the external DQS signal can be used to indicate when the memory device samples data received at the DQ terminal. When the memory device receives the external DQS and DQ signals, the memory device can (a) generate an internal DQS signal at least in part based on the external DQS signal, and (b) latch and register the data received at the DQ terminal at the rising and / or falling edges of the internal DQS signal.

[0020] At the end of data transmission (e.g., after a burst of eight data bits), the memory controller may stop transmitting the external DQS signal. More specifically, the memory controller (a) may hold the DQS signal at a lower duration defined by the DQS write-after-synchronization specification tWPST for a duration (e.g., equivalent to half the period (tCK) of the external DQS signal) during the write-after-synchronization cycle, and (b) may then stop driving the external DQS signal. During the write-after-synchronization cycle, the memory device may finish latching and registering the write data received at the DQ terminal. After the memory controller stops driving the external DQS signal, the last rising edge of the external DQS signal may float or pull to the termination voltage.

[0021] When the external DQS signal floats or pulls to the termination voltage, reflections on the corresponding signal trace (e.g., due to parasitic effects) can cause ringing in the external DQS signal, which can be interpreted by the memory device and registered as a transition in the external DQS signal. In other words, ringing can cause the memory device to register a short-time pulse interference pulse in an internal DQS signal generated at least in part based on the external DQS signal. In response to the short-time pulse interference pulse, the memory device may attempt to latch incorrect or invalid data at the DQ terminal, thereby corrupting the last bit of the data supplied to the DQ terminal by the memory controller and latched by the memory device. Specifically, the last bit of the written data can be corrupted by an amount at least partially corresponding to the width of the short-time pulse interference pulse in the internal DQS signal. Furthermore, a write operation failure may occur when (a) the memory controller fails to maintain the external DQS signal at a low duration for approximately the duration defined by the DQS write-after-synchronization specification tWPST during the write-after-synchronization cycle (e.g., 0.3 tCK or more for a tWPST defined as 0.5 tCK) and (b) ringing in the external DQS signal causes the memory device to register a short-duration pulse wave interference pulse on the internal DQS signal. Alternatively, if the width of the short-duration pulse wave interference pulse in the internal DQS signal is less than approximately 0.5 tCK, the memory device may not have sufficient margin to properly latch the last bit of the data supplied by the memory controller to the DQ terminal of the memory device, thus causing the write operation to fail.

[0022] To address these issues, a memory device configured according to the present invention may include a DQS pulse control circuitry system that (a) receives an external DQS signal (or is at least partially based on an input of an external DQS signal) and (b) outputs an internal DQS signal comprising pulses having a width greater than or equal to a minimum pulse width. Specifically, the external DQS signal received by the memory device may be fed into the DQS pulse control circuitry system. In turn, the DQS pulse control circuitry system may extend or stretch any pulse in the external DQS signal having a width shorter than the minimum pulse width, such that the corresponding pulse in the internal DQS signal output from the DQS pulse control circuitry system has a width greater than or equal to the minimum pulse width. For example, internal DQS pulses with pulse widths of approximately 0.3tCK to 0.7tCK (e.g., 0.5tCK) are not expected to corrupt internally latched data and / or cause write operations in some memory devices to fail, because these internal DQS pulses have a similar timing margin provided by the DQS pulses during normal write operations. Therefore, in some embodiments, the minimum pulse width can be set to a value between 0.3tCK and 0.7tCK (e.g., 0.5tCK). In these embodiments, the DQS pulse control circuitry can stretch any pulse in the external DQS signal with a width less than the minimum pulse width, such that the corresponding pulses output from the DQS pulse control circuitry in the internal DQS signal each have a width equal to the minimum pulse width. Alternatively, the DQS pulse control circuitry can be configured such that pulses in the external DQS signal with a width greater than or equal to the minimum pulse width pass through the DQS pulse control circuitry unimpeded or unchanged. In other words, the DQS pulse control circuitry ensures that all pulses in the internal DQS signal output from the DQS pulse control circuitry have a width greater than or equal to the minimum pulse width. As a result, when the memory device interprets ringing in the external DQS signal as transitions in the external DQS signal, the width of short-time pulse wave interference pulses in the internal DQS signal is extended or stretched by the DQS pulse control circuitry to the minimum pulse width (assuming the width of the short-time pulse wave interference pulses is initially less than the minimum pulse width). Conversely, short-duration pulse interference pulses in the internal DQS signal output from the DQS pulse control circuitry are unlikely to corrupt previously latched valid data by the memory device and / or are unlikely to induce write operation failures due to insufficient timing margin. Alternatively, when the memory controller does not maintain the external DQS signal at a low level for approximately the duration defined by the DQS write-after-synchronization specification tWPST during the write-after-synchronization cycle, the DQS pulse control circuitry may extend the duration of the corresponding portion of the internal DQS signal held low (e.g., to the minimum pulse width).

[0023] B. Selected embodiments of memory systems and associated apparatus and methods

[0024] Figure 1A A block diagram illustrating a memory system 190 configured according to various embodiments of the invention. In one embodiment, the memory system 190 is a dual in-line memory module (DIMM) having one or more memory devices 100 (e.g., one or more DRAM memory devices). Although Figure 1A While a single memory device 100 is shown, in some embodiments, the memory system 190 may include one or more modules and / or multiple memory devices 100. Well-known components of the memory system 190 have been described... Figure 1A The details are omitted and not described in detail below to avoid unnecessarily obscuring aspects of the invention.

[0025] One or more memory devices 100 of the memory system 190 may be connected to an electronic device or component thereof capable of temporarily or permanently storing information using the memory. For example, Figure 1A The memory device 100 is operatively connected to the host device 108. The host device 108 may be a computing device, such as a desktop or portable computer, server, handheld device (e.g., mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., central processing unit, coprocessor, dedicated memory controller, etc.). The host device 108 may be a networking device (e.g., switch, router, etc.); a recorder of digital images, audio, and / or video; a vehicle; an electrical appliance; a toy; or any of several other products. In one embodiment, the host device 108 may be directly connected to the memory device 100 (e.g., via a communication bus (not shown) with signal traces). Alternatively or concurrently, the host device 108 may be indirectly connected to the memory device 100 (e.g., via a networking connection or through an intermediate device, such as through the memory controller 101 and / or via the communication bus 117 with signal traces).

[0026] The memory device 100 of the memory system 190 is operatively connected to the memory controller 101 via a command / address (CMD / ADDR) bus 118, a data strobe (DQS) bus 119, and a data (DQ) bus 120. (The following text is about...) Figure 1BIn more detail, the CMD / ADDR bus 118, DQS bus 119, and DQ bus 120 can be used by the memory controller 101 to transmit commands, memory addresses, and / or data to the memory device 100. In response, the memory device 100 can execute commands received from the memory controller 101. For example, in the case of receiving a write command from the memory controller 101 via the CMD / ADDR bus 118, the memory device 100 (a) can receive data from the memory controller 101 via the data DQ bus 120 according to the DQS signal received via the DQS bus 119, and (b) can write data corresponding to the memory address received from the memory controller 101 to the memory cell via the CMD / ADDR bus 118. As another example, when a read command is received from the memory controller 101 via the CMD / ADDR bus 118, the memory device 100 may (a) retrieve data from the memory cell corresponding to the memory address received from the memory controller 101 via the CMD / ADDR bus 118 and (b) output data to the memory controller 101 via the data DQ bus 120 according to the DQS signal transmitted via the DQS bus 119.

[0027] Figure 1B Configured for various embodiments of the present invention. Figure 1A A block diagram of a memory device 100. As shown, the memory device 100 may employ multiple external terminals. The external terminals may include those operatively connected to a CMD / ADDR bus 118. Figure 1A The external terminals may further include a chip select terminal for receiving the chip select signal CS, a clock terminal for receiving clock signals CK and CKF, and data terminals DQ, DQS, DBI, and DMI (e.g., operably connected to...). Figure 1AThe memory device 100 may include DQS bus 119 and / or DQ bus 120 and / or power supply terminals VDD, VSS, and VDDQ. The memory device 100 may additionally or alternatively include data clock terminals for receiving data clock signals WCK and WCKF, and / or read data strobe terminals RDQS. For example, in embodiments where the memory device 100 is a Double Data Rate (DDR) memory device or a Low Power DDR4 (LPDDR4) memory device, the memory device 100 may include clock terminals CK and CKF for receiving differential clock signals and a bidirectional data strobe terminal DQS for transmitting and / or receiving differential data strobe signals DQS_t and DQS_c. As another example, in an embodiment where the memory device 100 is a graphics DDR (GDDR) or LPDDR5 memory device, the memory device 100 may include clock terminals CK and CKF for receiving data clock signals, data clock terminals for receiving data clock signals WCK and WCKF, and a one-way read data strobe terminal RDQS (e.g., replacing the data strobe DQS terminal).

[0028] A power potential V can be supplied to the power supply terminals of the memory device 100. DD and V SS These power supply potentials V DD and V SS It can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can be based on the power supply potential V. DD and V SS This generates various internal potentials V PP V OD V ARY V PERI Wait a minute. Internal potential V PP It can be used in the line decoder 140, with an internal potential V. OD and V ARY It can be used in the sensing amplifier included in the memory array 150 of the memory device 100, and the internal potential V PERI It can be used in many other circuit blocks.

[0029] It can also supply a power potential V to the power terminals. DDQ The power supply potential V can be... DDQ Together with the power supply potential V SS Together, they are supplied to the input / output (I / O) circuit 160. In an embodiment of the present invention, the power supply potential V DDQ It can be related to the power supply potential V DD The same potential. In another embodiment of the invention, the power supply potential V... DDQ It can be related to the power supply potential V DD Different potentials. However, the potential V of a dedicated power supply.DDQ It can be used in I / O circuit 160 to prevent power supply noise generated by I / O circuit 160 from propagating to other circuit blocks.

[0030] External clock signals and / or complementary external clock signals can be supplied to clock terminals, data clock terminals, and / or additional clock terminals. External clock signals CK, CKF, WCK, and / or WCKF can be supplied to clock input circuit 133. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. Complementary clock signals can simultaneously have relative clock levels and transitions between relative clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0031] In embodiments where the memory device 100 includes both a clock terminal and a data clock terminal, the clock signals CK and CKF received at the clock terminal may have the same or different frequencies as the data clock signals WCK and WCKF received at the data clock terminal. For example, depending on the operating mode of the memory device 100, the data clock signals WCK and WCKF may have frequencies that are respectively larger than the frequencies of the clock signals CK and CKF (e.g., twice as large, four times as large, etc.). More specifically, the data clock signals WCK and WCKF may have frequencies that are respectively twice as large as the frequencies of the clock signals CK and CKF when the memory device 100 operates in a low-power operating mode (a), and may have frequencies that are respectively four times as large as the frequencies of the clock signals CK and CKF when the memory device 100 operates in a high-speed or high-data-transfer operating mode (b). In these and other embodiments, a data strobe signal output via the read data strobe terminal RDQS may be generated using or at least partially based on the data clock signals WCK and WCKF. In embodiments where the memory device 100 does not include a data clock terminal, a data strobe signal output and / or received via the DQS terminal may be generated using or at least partially based on clock signals CK and CKF.

[0032] An input buffer included in clock input circuit 133 can receive an external clock signal. For example, when enabled by a CKE signal from command decoder 115, the input buffer can receive CK and CKF signals and / or WCK and WCKF signals. Clock input circuit 133 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can provide various phase and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from command decoder 115. For example, internal clock circuit 130 may include a clock path that receives the internal clock signal ICLK and provides various clock signals (not shown) to command decoder 115. Figure 1B (Not shown in the image). Internal clock circuitry 130 can further provide input / output (I / O) clock signals. The I / O clock signals can be supplied to I / O circuitry 160 and can be used as timing signals to, for example, determine the timing of input / output (I / O) clock signals via DQ bus 119. Figure 1A The data transmitted is output timing and / or input timing and / or transmitted via command insertion terminal CI via command insertion signal trace 120. Figure 1A The conditions / commands for transmission. Multiple clock frequencies can be provided for the I / O clock signal to enable different data rates for outputting data from and inputting data to the memory device 100. A higher clock frequency may be desirable when high memory speed is required. A lower clock frequency may be desirable when lower power consumption and / or a looser timing margin are required. An internal clock signal ICLK can also be supplied to the timing generator 135, thus generating various internal clock signals that can be used by the command decoder 115, column decoder 145, I / O circuitry 160, and / or other components of the memory device 100.

[0033] Memory device 100 may include an array of memory cells, such as memory array 150. The memory cells of memory array 150 may be arranged in multiple memory regions, and each memory region may include multiple word lines (WLs), multiple bit lines (BLs), and multiple memory cells arranged at the intersections of word lines and bit lines. In some embodiments, a memory region may be one or more memory groups or another arrangement of memory cells (e.g., half a memory group, a subarray within a memory group, etc.). In these and other embodiments, the memory regions of memory array 150 may be arranged in one or more groups (e.g., one or more groups of memory groups). The memory cells in memory array 150 may include any of several different memory medium types, including capacitor, magnetoresistive, ferroelectric, phase-change, etc. The selection of word lines WLs may be performed by row decoder 140, and the selection of bit lines BLs may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for a corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which may then be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG), which may act as a switch. The memory array 150 may also include board lines and corresponding circuitry for managing its operation.

[0034] Address signals and group address signals can be supplied from outside the memory device 100 to the command and address terminals. The address signals and group address signals supplied to the address terminals can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive the address signals and supply the decoded row address signal (XADD) to the row decoder 140, and the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive the group address signal (BADD) and supply the group address signal to both the row decoder 140 and the column decoder 145.

[0035] Command signals CMD, address signals ADDR, and chip select signals CS can be supplied to command and address terminals (e.g., from memory controller 101 and / or host device 108). Command signals can represent various memory commands (e.g., access commands, which may include read and write commands). The select signal CS can be used to select memory device 100 to respond to commands and addresses supplied to the command and address terminals. When an active CS signal is supplied to memory device 100, commands and addresses can be decoded, and memory operations can be performed. Command signals CMD can be provided as internal command signals ICMD to command decoder 115 via command / address input circuitry 105. Command decoder 115 may include circuitry for decoding internal command signals ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. Internal command signals may also include output and input activation commands, such as timing commands (not shown) to command decoder 115. Command decoder 115 may further include one or more registers 128 that track various counts or values, such as the number of times a memory region (e.g., a memory row) has been activated.

[0036] When a read command is issued and the read command is supplied to the row address and column address in a timely manner, read data can be read from the memory cell specified by the row address and column address in the memory array 150. The read command can be received by the command decoder 115, which can provide internal commands to the I / O circuit 160 so that read data can be output from the data terminals DQ, DBI, and DMI via the read / write (RW) amplifier 155 and the I / O circuit 160 according to the read data strobe timing signal output from the memory device 100 via the DQS or RDQS terminals. As a specific example, the memory device 100 can transmit the read data strobe timing signal to the memory controller 101 via the DQ terminal of the memory device 100 (a) Figure 1A (b) The read data is transferred to the memory controller 101. The read data strobe timing signal can be used as a clock to strobe the read data to the memory controller 101. In other words, the read data strobe timing signal can be used to indicate when the memory controller 101 samples the read data received from the memory device 100.

[0037] In some embodiments, this may be achieved, for example, in the mode register ( Figure 1B(Not shown) Read data is provided within a time limit defined by read delay information RL, which is programmable in memory device 100. The read delay information RL can be defined according to the clock cycle of the CK clock signal. For example, the read delay information RL can be the number of clock cycles of the CK signal after the memory device 100 receives a read command when providing the associated read data.

[0038] When a write command is issued and commands are supplied to the row and column addresses in a timely manner, write data can be supplied to the data terminals DQ, DBI, and DMI according to the DQS, WCK, and / or WCKF clock signals. The write command can be received by a command decoder 115, which can provide internal commands to I / O circuitry 160 so that write data can be received by the data receiver in I / O circuitry 160 and supplied to memory array 150 via I / O circuitry 160 and RW amplifier 155. Write data can be written to the memory cells specified by the row and column addresses. In some embodiments, write data can be supplied to the data terminals at a time defined by write latency (WL) information. The write latency (WL) information is programmable in memory device 100, for example, programmed in a mode register (…). Figure 1B (Not shown in the text). The write delay WL information can be defined based on the clock cycles of the CK clock signal. For example, the write delay information WL can be the number of clock cycles of the CK signal after the write command is received by the memory device 100 when the associated write data is received.

[0039] As a specific instance of a write operation, memory controller 101 ( Figure 1A The memory controller 101 can (a) supply an external DQS signal (e.g., a differential write data strobe (WDQS) signal including DQS_t and DQS_c) to the DQS terminal of the memory device 100, and (b) write data to the DQ terminal of the memory device 100. The external DQS signal can be used as a clock to strobe write data into the memory device 100 via the DQ terminal. In other words, the external DQS signal can be used to indicate when the memory device 100 samples write data received at the DQ terminal of the memory device 100. In some embodiments, when the memory controller 101 ( Figure 1AWhen initiating a write operation, the memory controller 101 may begin a bi-state switching of the external DQS signal during the write preamble cycle to notify the memory device 100 that the memory controller 101 will soon begin transmitting write data to the DQ terminal of the memory device 100. After the preamble cycle, the memory controller 101 may supply write data to the DQ terminal of the memory device 100 according to the external DQS signal. Conversely, the memory device 100 may latch and register the write data received at the DQ terminal at the rising and / or falling edges of the internal DQS signal generated at least in part based on the external DQS signal.

[0040] At the end of data transmission (e.g., after a burst of eight data bits), the memory controller 101 may stop transmitting the external DQS signal. More specifically, the memory controller 101 (a) may maintain the external DQS signal at half (or another fraction or multiple) of the period (tCK) of the lower sustained external DQS signal during the post-write synchronization period according to the DQS write-after-synchronization specification tWPST, and (b) may then stop driving the external DQS signal. During the post-write synchronization period, the memory device 100 may terminate latching and registering the write data received at the DQ terminal. After the memory controller 101 stops driving the external DQS signal, the last rising edge of the external DQS signal may float or pull to the termination voltage.

[0041] As discussed above, the DQS bus 119 ( Figure 1A Reflections on the signal (e.g., due to parasitic effects) can cause ringing in the external DQS signal. When ringing causes the external DQS signal to exceed the midpoint or another value of the reference voltage and then drop below the midpoint or another value, the memory device 100 can interpret the ringing and register it as a transition in the external DQS signal. For example, Figure 2A The signal diagram 280 shows the complementary external DQS signals DQS_t and DQS_c, as well as the corresponding external DQ signals. Figure 2B Signal diagram 285 shows the internal DQS and internal DQ signals. It is at least partially based on... Figure 2A The complementary external DQS signals DQS_t and DQS_c are generated. Figure 2A The internal DQS signal (e.g., without using the DQS pulse control circuitry system of the present invention described in more detail below). See also... Figure 2A and 2B Memory controller 101 ( Figure 1A The eight-bit burst of data d0 to d7 is transmitted based on the transitions of the complementary external DQS signals DQS_t and DQS_c. Figure 2A Conversely, memory device 100 ( Figure 1A and 1BThe eight bits d0 to d7 of the write data are latched and registered on the corresponding rising and / or falling edges of the internal DQS signal. Figure 2B At the end of the eight-bit burst, the memory controller 101 holds the external DQS signal DQS_t low (and / or the external DQS signal DQS_c high) for a certain duration during the post-write synchronization cycle (according to the post-write synchronization specification tWPST). Then, the memory controller 101 stops driving the complementary external DQS signals DQS_t and DQS_c, and the external DQS_t signal floats and / or is pulled up toward the termination voltage.

[0042] At this time, DQS bus 119 ( Figure 1A Reflection on the signal can trigger ringing on one or both of the external DQS signals DQS_t and / or DQS_c 283 ( Figure 2A The memory device 100 can interpret the ringing as a transition of external DQS signals DQS_t and / or DQS_c (e.g., from low to high and then from high to low, and / or vice versa). Figure 2B As shown, ringing can cause the memory device 100 to register a short-time pulse interference pulse 287 in the internal DQS signal. In response, the memory device 100 may attempt to latch incorrect or invalid data at the DQ terminal (e.g., at the rising and / or falling edges of the short-time pulse interference pulse 287), thereby corrupting the last bit d7 of the write data latched by the memory device (e.g., corrupting an amount at least partially corresponding to the width of the short-time pulse interference pulse 287 in the internal DQS signal). Alternatively or additionally, because the width of the short-time pulse interference pulse 287 is less than approximately 0.5tCK, the memory device 100 may not have sufficient margin to properly latch corrupted data. As a result, the short-time pulse interference pulse 287 may cause the write operation to fail. Write operation failure can also occur when (a) the memory controller 101 does not keep the external DQS signal DQS_t at a low level for an approximate duration defined by the DQS write-after synchronization specification tWPST (e.g., 0.5tCK or about 330 ps) during the write-after synchronization period (e.g., 0.3tCK or greater, or about 200 ps or greater) and (b) the memory device 100 registers a short-duration pulse wave interference pulse on the internal DQS signal.

[0043] To address these issues, a memory device configured according to the present invention (e.g., Figure 1B The memory device 100 may include a DQS pulse control circuit system 165. Figure 1BSpecifically, the external DQS signal received by the memory device 100 at the DQS terminal can be fed into the input buffer 161 and / or into the DQS pulse control circuitry system 165 of the I / O circuitry 160. In turn, the DQS pulse control circuitry system 165 can generate an internal DQS signal based at least in part on the external DQS signal. As discussed in more detail below, the DQS pulse control circuitry system 165 can extend or stretch any pulse in the external DQS signal that has a width shorter than the minimum pulse width, such that the corresponding pulse in the internal DQS signal output from the DQS pulse control circuitry system 165 has a width greater than or equal to the minimum pulse width. For example, internal DQS pulses with pulse widths of approximately 0.3tCK to 0.7tCK (e.g., 0.5tCK) are not expected to corrupt internally latched data or cause write operations to fail because these internal DQS pulses have a similar timing margin provided by the DQS pulses during normal write operations. Therefore, in some embodiments, the minimum pulse width can be set to a value between 0.3tCK and 0.7tCK (e.g., 0.5tCK). In these embodiments, the DQS pulse control circuitry 165 can stretch any pulse in the external DQS signal with a width less than the minimum pulse width, such that the corresponding pulses output from the DQS pulse control circuitry 165 in the internal DQS signal each have a width equal to the minimum pulse width. Alternatively, the DQS pulse control circuitry 165 can be configured such that pulses in the external DQS signal with a width greater than or equal to the minimum pulse width pass through the DQS pulse control circuitry 165 unimpeded or unchanged. In other words, the DQS pulse control circuitry 165 can ensure that all pulses in the internal DQS signal output from the DQS pulse control circuitry 165 have a width greater than or equal to the minimum pulse width, thereby reducing the possibility that valid data latched by the memory device 100 is corrupted and / or write operations fail due to insufficient timing margin. Alternatively, when the memory controller does not hold the external DQS signal at a low duration during the post-write synchronization cycle for approximately the duration defined by the DQS post-write synchronization specification tWPST (e.g., when the memory controller holds the external DQS signal at a low duration of 0.3tCK or less, or about 200 ps or less), the DQS pulse control circuitry system may extend the duration of the corresponding portion of the internal DQS signal held at a low duration (e.g., extending to the minimum pulse width, such as 0.5tCK or about 330 ps).

[0044] Despite Figure 1BThe diagram shows a portion of the I / O circuitry system 160, but in other embodiments, the DQS pulse control circuitry system 165 may be located at other locations within the memory device 100. For example, in embodiments where the memory device 100 uses data clock signals WCK and WCKF as write data strobe signals, the DQS pulse control circuitry system 165 may be located within the clock input circuitry 133, the timing generator 135, and / or the internal clock circuitry 130 to control pulses registered on internal signals generated at least in part based on the data clock signals WCK and / or WCKF.

[0045] Figure 3 A schematic diagram of a DQS pulse control circuit system 365 (“circuit system 365”) configured for various embodiments of the present invention. In some embodiments, the circuit system 365 may be... Figure 1B The DQS pulse control circuit system 365 or other DQS pulse control circuit systems of the present invention. As shown, circuit system 365 includes a first inverter 321, a set / reset (SR) latch 322, a delay element 323, a second inverter 324, and an amplifier 328. The SR latch 322 includes two NAND logic gates 326 (in... Figure 3 Individually identified as the first NAND logic gate 326a and the second NAND logic gate 326b. In other embodiments, the SR latch 322 may include other logic gates (e.g., NOR logic gates) and / or other circuit elements. Using an SR latch composed of logic gates can reduce or minimize (a) process, voltage, and temperature (PVT) variations and / or (b) power consumption. The delay element 323 of the circuit system 365 may include inverters, logic gates, and / or other suitable metallized or circuit elements for delaying the signal arrival at the inputs of the second inverter 324 and / or the second NAND logic gate 326b, as discussed in more detail below.

[0046] Circuitry 365 is configured such that an input is provided to the first inverter 321. In some embodiments, the input may be, for example, an external DQS signal received from a memory controller at a DQS terminal of a corresponding memory device. In other embodiments, the external DQS signal received at the DQS terminal may be fed into an input buffer (not shown) electrically connected to the first inverter 321, such that the input of circuitry 365 is at least partially based on the output of the input buffer of the external DQS signal fed into the input buffer.

[0047] Conversely, the first inverter 321 inverts the state of the input signal and feeds the inverted input signal to the input of the first NAND logic gate 326a of the SR latch 322. As discussed in more detail below, the second input of the first NAND logic gate 326a is fed as the output Qb of the second NAND logic gate 326b of the SR latch 322. The output Q of the first NAND logic gate 326a is (a) fed as an input to the second NAND logic gate 326b, (b) fed as an input to the delay element 323 and (after delay) fed to the second inverter 324, and (c) fed as an input to the amplifier 328 so that it is amplified and used as the output of the circuit system 365. The output of the circuit system 365 is also referred to herein as the internal DQS signal, which has an internal DQS pulse corresponding to the external DQS pulse fed into the circuit 365 on the external DQS signal.

[0048] As discussed above, delay element 323 is configured to delay the arrival of the output Q of the first NAND logic gate 326a at the second inverter 324 and / or the second NAND logic gate 326b. In some embodiments, the delay applied (e.g., injected) by delay element 323 may be fixed (e.g., at manufacturing) or reprogrammable (e.g., changeable). In these and other embodiments, the delay applied by delay element 323 may be set to a value between 0.3tCk and 0.7tCk (e.g., 0.5tCK), as discussed in more detail below. Continuing this example, when a portion of the output Q is provided to delay element 323, the delay element may delay the arrival of a portion of the output Q at the second inverter 324 and / or the second NAND logic gate 326b by approximately 0.5tCK. Conversely, the second inverter 324 is configured to invert the output Q and feed the inverted output Q (hereinafter referred to as the "signal Q bar") as an input to the second NAND logic gate 326b of the SR latch 322. In some embodiments, the delay element 323 may be electrically positioned between the second inverter 324 and the second NAND logic gate 326b such that the second inverter 324 inverts the output Q to the signal Q bar and the delay element 323 delays the arrival of the signal Q bar at the second NAND logic gate 326b.

[0049] The second NAND logic gate 326b is further configured to receive a reset signal as an input. As discussed in more detail below, the reset signal can be asserted upon power-up of the circuit system 365 and / or the corresponding memory device. In these and other embodiments, the reset signal may remain unasserted after being asserted upon power-up (e.g., until the next instance of power-up of the circuit system 365 and / or the memory device).

[0050] Figure 4To illustrate the operation of various embodiments of the technology according to the present invention Figure 3 The flowchart of method 430 of the DQS pulse control circuit system 365 is shown. Method 430 is shown as a set of steps or blocks 431 to 436. All or a subset of one or more of blocks 431 to 436 may be derived by, for example... Figure 1A The memory system 190 and other memory system components or devices may perform this function. For example, all or a subset of one or more of blocks 431 to 436 may be performed by (i) memory devices (e.g., memory system 190). Figure 1A and 1B (i) memory device 100), (ii) memory controller (e.g., Figure 1A (iii) memory controller 101) and / or host device (e.g., Figure 1A The host device 108) performs the execution. For clarity and understanding, references are repeated below. Figure 3 , 5A Let's discuss method 430 in detail with 5B. Figure 5A and 5B Various embodiments of the present invention are respectively Figure 3 The signal diagrams for the DQS pulse control circuit system are shown in Figures 550 and 560.

[0051] Method 430 is achieved by setting the circuit system 365 ( Figure 3 The delay element 323 () Figure 3 The delay applied begins at block 431. As discussed above, the delay can be set during manufacturing. For example, delay element 323 may include inverters, logic gates, and / or other suitable metallized or circuit elements that apply a fixed amount of delay. Continuing this example, the delay applied by delay element 323 can be fixed during the assembly of circuit system 365 by specific elements in delay element 323 of circuit system 365 that have a fixed delay. In other embodiments, the delay applied by delay element 323 may be programmable or reprogrammable. For example, the elements of delay element 323 may be adjusted (e.g., activated, deactivated, and / or changed) for example using a fuse array (not shown) corresponding to a memory device, such that the delay applied by delay element 323 of circuit system 365 can be adjusted. As discussed in more detail below, the delay applied by delay element 323 may correspond to the minimum pulse width output by circuit system 365. In some embodiments, the delay may be set to a value between 0.3tCk and 0.7tCk (e.g., 0.5tCK). In some embodiments, a delay significantly less than 0.5tCK can induce write operation failure in the corresponding memory device because there is insufficient timing margin to latch the written data. In these and other embodiments, a delay significantly greater than 0.5tCK can also induce write operation failure by interfering with the timing margin of the next latch of the written data at the next transition of the DQS signal.

[0052] At box 432, method 430 asserts to SR latch 322 of circuit system 365 ( Figure 3 The second NAND logic gate 326b ( Figure 3 The process continues upon input of a reset signal in the circuit system 365. In some embodiments, the reset signal can be asserted when the circuit system 365 and / or the corresponding memory device are powered on. In these and other embodiments, the reset signal can be asserted by transitioning the reset signal (a) from a high state to a low state or (b) from a low state to a high state. Reference Figure 5A and 5B The reset signal is asserted by temporarily transitioning it from a high state to a low state at time t0. Asserting the reset signal causes the output Qb of the second NAND logic gate 326b to be high, regardless of its state before time t0. Conversely, assuming the DQS signal is not high (e.g., not driven and / or currently low), then the output Q of the first NAND logic gate 326a is caused to be low, regardless of its state before time t0. Therefore, similarly, the output of circuit system 365 (e.g., the internal DQS signal) is caused to be low, regardless of its state before time t0. The reset signal is then not asserted at time t1. Figure 5A and 5B As shown by arrow 551, the width of the reset signal pulse can be longer or shorter than... Figure 5A and 5B The width is shown in the figure. In some embodiments, the reset signal should not be asserted at time t3.

[0053] exist Figure 5A and 5B The time t2 causes the signal Q bar to go high (e.g., the opposite state of output Q at time t0), regardless of its state before time t2. The time elapsed between time t0 and time t2 corresponds to the time it takes for output Q to reach the second inverter 324 of circuit system 365. Figure 3 ) and / or the second NAND logic gate 326b ( Figure 3 Previously, it was delayed by element 323 ( Figure 3 The delay is applied to the output. Therefore, by time t2, the circuit system 365 has reached the reset state, where (a) the output Q and the output of the circuit system 365 are low and (b) the signal Q bar, the output Qb and / or the reset signal are high.

[0054] In method 430 ( Figure 4 At block 433, method 430 continues by receiving a pulse of an external DQS signal. In some embodiments, the external DQS signal may include... Figure 2AThe DQS signal DQS_t and / or the DQS signal DQS_c. Figures 3 to 5B For clarity and understanding, the DQS pulse hereafter refers to the temporary transition of the DQS signal from a low state to a high state. However, in other embodiments of the present invention, the DQS pulse may additionally or alternatively refer to the temporary transition of the DQS signal from a high state to a low state.

[0055] Refer again Figure 5A and 5B When the DQS signal transitions from a low state to a high state, the circuit system 365 ( Figure 3 The DQS pulse is received at time t3. When the DQS signal transitions to a high state, the SR latch 322 ( Figure 3 )'s first NAND logic gate 326a ( Figure 3 The output Q of SR latch 322 transitions to a high state. Conversely, the second NAND logic gate 326b of SR latch 322... Figure 3 The output Qb transitions to a low state.

[0056] In method 430 ( Figure 4 At box 434, method 430 determines whether the width of the DQS pulse received at box 433 is less than that of the delay element 323 of circuit system 365. Figure 3 The method continues with the applied delay. If the width of the DQS pulse is less than the delay applied by the delay element 323, then method 430 proceeds to block 435 to output an internal DQS pulse corresponding to the DQS pulse received at block 433 but with a width equal to the minimum pulse width. Figure 5A Signal diagram 550 corresponds to the DQS pulse received at block 433 of method 430 being smaller than that caused by delay element 323 of circuit system 365. Figure 3 In the case of an applied delay, if the width of the DQS pulse received at block 433 is greater than or equal to the delay applied by delay element 323, then method 430 proceeds to block 436 to output an internal DQS pulse with a width equal to the width of the DQS pulse received at block 433. Figure 5B Signal diagram 560 corresponds to a scenario in which the DQS pulse received at block 433 of method 430 is greater than or equal to the delay applied by delay element 323 of circuit system 365.

[0057] refer to Figure 5A The delay element 323 of the circuit system 365 ( Figure 3The applied delay is represented as the difference between time t3 and time t5. As shown, the DQS pulse received at time t3 terminates at time t4, meaning the DQS pulse has a width less than the delay applied by the delay element 323 of the circuit system 365. In this case, the output Q (and therefore the output of the circuit system 365) remains high even after the DQS signal transitions to a low state at t4. Specifically, the output Q remains high until the output Q passes through the delay element 323, by the second inverter 324 of the circuit system ( Figure 3 The process reverses and reaches the second NAND logic gate 326b at time t5. Figure 3 More specifically, the signal Q bar transitions to a low state after a delay, and is then used to transition the output Qb of the second NAND logic gate 326b to a high state. When the output Qb transitions to a high state, the output Q transitions to a low state. Thus, the circuit system 365 outputs an internal DQS pulse on the internal DQS signal, which has a width corresponding to the delay applied by the delay element 323, also referred to as the minimum pulse width. At time t7 (corresponding to time t5 plus the delay applied by the delay element 323), the signal Q bar transitions to a high state and the circuit system 365 returns to the reset state discussed above with respect to block 432. In some embodiments, method 430 ( Figure 4 It can return to box 433 and wait to receive the next external DQS pulse at box 433.

[0058] refer to Figure 5B The delay element 323 of the circuit system 365 ( Figure 3 The applied delay is represented as the difference between time t3 and time t5. As shown, the DQS pulse received at time t3 terminates at time t6, which means that the DQS pulse has a width greater than or equal to the delay applied by the delay element 323 of the circuit system 365. In this case, the output Q (and therefore the output of the circuit system 365) even at time t5 when the signal Q bar transitions to a low state and the second NAND logic gate 326b ( Figure 3 After the output Qb of the circuit transitions to a high state, it remains high. Specifically, as long as the DQS signal remains high, the output Q will remain high. Therefore, circuit system 365 outputs an internal DQS pulse on the internal DQS signal, the internal DQS signal having a width corresponding to the width of the external DQS pulse on the DQS signal. At time t8 (corresponding to time t6 plus the delay applied by delay element 323), the signal Q bar transitions to a high state and circuit system 365 returns to the reset state discussed above with respect to block 432. In some embodiments, method 430 ( Figure 4 It can return to box 433 and wait to receive the next external DQS pulse at box 433.

[0059] Although boxes 431 to 436 of method 430 are discussed and shown in a specific order, Figure 4 The method 430 shown is not so limited. In other embodiments, method 430 may be performed in a different order. In these and other embodiments, any of blocks 431 to 436 of method 430 may be performed before, during, and / or after any of the other blocks 431 to 436 of method 430. Furthermore, those skilled in the art will recognize that the method 430 shown can be modified while remaining within these and other embodiments of the present invention. For example, in some embodiments, methods may be omitted and / or repeated. Figure 4 One or more blocks 431 to 436 of the method 430 shown.

[0060] Embodiments of the present invention that include a DQS pulse control circuit system can therefore provide several advantages, such as guaranteeing a minimum internal DQS pulse width. Conversely, embodiments of the present invention can guarantee a minimum timing margin for latching data and thereby reduce the likelihood of write operation failures.

[0061] Figure 6 Signal diagram 685 illustrates the internal DQS signal and internal DQ signal according to various embodiments of the present invention. Signal diagram 685 shows several advantages provided by embodiments of the present invention. For example, similar to... Figure 2B The internal DQS signal is at least partially based on Figure 2A The complementary external DQS signals DQS_t and DQS_c are generated. Figure 6 The internal DQS signal. However, with Figure 2B Compared to the internal DQS signal, Figure 6 The internal DQS signal is generated using the DQS pulse control circuit system of this invention.

[0062] Will Figure 6 Signal diagram 685 and Figure 2B Compare the signal diagram 285. Figure 6 The width of the short-time pulse wave interference pulse 687 in the internal DQS signal is greater than Figure 2B The width of the short-time pulse wave interference pulse 287 in the internal DQS signal. As a result, the corresponding memory device has a longer time to latch the last bit d7 of the written data. Therefore, the signal used to generate Figure 6The internal DQS signal's DQS pulse control circuitry system (a) reduces the likelihood that the last bit d7 of the written data will be damaged by a short-time pulse wave interference pulse 687 and / or by a memory controller that fails to keep the corresponding external DQS signal low for at least 0.5 tCK according to the Post-Write Synchronization Specification tWPST and / or (b) reduces the likelihood of write operation failures. In some embodiments, the width of the short-time pulse wave interference pulse 687 may correspond to a minimum pulse width (e.g., 0.5 tCK) and / or may conform to the Post-Write Synchronization Specification tWPST, as discussed above.

[0063] The above references Figures 1A to 6 Any of the aforementioned memory systems, devices, and / or methods can be incorporated into any of numerous larger and / or more complex systems, a representative example of which is... Figure 7 The system 790 is schematically shown in the diagram. System 790 may include a semiconductor device assembly 700, a power supply 792, a driver 794, a processor 796, and / or other subsystems and components 798. The semiconductor device assembly 700 may include components generally consistent with those described above. Figures 1A to 6 The described memory system, apparatus, and / or method are characterized by similar features. The resulting system 790 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 790 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 790 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 790 may also include remote devices and any of a wide variety of computer-readable media.

[0064] C. in conclusion

[0065] The above detailed description of embodiments of this technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. As those skilled in the art will recognize, although specific embodiments and examples of this technology have been described above for illustrative purposes, various equivalent modifications can be made within the scope of the technology. For example, while steps are presented and / or discussed in a given order, alternative embodiments may perform the steps in a different order. Furthermore, the various embodiments described herein may be combined to provide other embodiments.

[0066] Based on the foregoing, it should be understood that specific embodiments of the technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, unless the word “or” is explicitly limited to referring only to a single item exclusive to other items in a list referring to two or more items, the use of “or” in this list may be understood to include: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, as used herein, the phrase “and / or” in phrases such as “A and / or B” means only A, only B, and both A and B. Moreover, the terms “comprising,” “including,” “having,” and “with” are used throughout to mean at least one or more of the described features, such that no larger number of identical features and / or other features of additional types are excluded.

[0067] Based on the foregoing, it should also be understood that various modifications can be made without departing from the present technology. For example, the various components of the present technology may be further divided into sub-components, or the various components and functions of the present technology may be combined and / or integrated. Furthermore, although advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also present these advantages, and not all embodiments are required to present these advantages to fall within the scope of the present technology. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A memory device comprising: An external data strobe DQS terminal is configured to receive an external DQS timing signal comprising (i) a first pulse having a first pulse width less than the minimum pulse width and (ii) a second pulse having a second pulse width greater than or equal to the minimum pulse width. as well as A circuit system operatively coupled to the external DQS terminal to receive the external DQS timing signal, wherein the circuit system is configured to: A third pulse is generated at least in part based on the first pulse, wherein the third pulse has a third pulse width equal to the minimum pulse width and greater than the first pulse width. A fourth pulse is generated at least in part based on the second pulse, wherein the fourth pulse has a fourth pulse width equal to the width of the second pulse, and The output includes an internal DQS timing signal containing the third pulse and the fourth pulse.

2. The memory device of claim 1, wherein the circuitry includes a delay element, the minimum pulse width is at least partially based on a delay applied by the delay element to a signal transmitted within the circuitry, and the third pulse width corresponds at least partially to the delay applied by the delay element.

3. The memory device of claim 1, wherein the minimum pulse width is equal to half the period of the external DQS timing signal.

4. The memory device of claim 1, wherein the circuit system comprises: Set / reset SR latch; and A delay element that is operatively coupled to the output of the SR latch.

5. The memory device of claim 4, wherein the circuit system further comprises: A first inverter having an output operably coupled to a first input of the SR latch; and A second inverter, wherein the second inverter is operatively coupled to the delay element, includes an input operatively coupled to the output of the SR latch, and includes an output operatively coupled to a second input of the SR latch.

6. The memory device of claim 5, wherein the SR latch further includes a third input operatively coupled to a reset signal.

7. The memory device of claim 1, wherein the first pulse corresponds to ringing on the external DQS timing signal.

8. The memory device of claim 1, further comprising an input buffer having an input operatively coupled to the external DQS terminal and an output operatively coupled to the input of the circuit system.

9. The memory device of claim 1, further comprising a data DQ terminal configured to receive write data.

10. The memory device of claim 9, wherein the memory device is configured to sample the write data received at the DQ terminal based at least in part on timing defined by the internal DQS timing signal output from the circuit system.

11. A memory system comprising: Memory controller; as well as A memory device operatively connected to the memory controller, wherein the memory device comprises: An external data strobe DQS terminal is configured to receive an external DQS timing signal from the memory controller, the external DQS timing signal comprising (i) a first pulse having a first pulse width and (ii) a second pulse having a second pulse width greater than the first pulse width; as well as A circuit system operatively coupled to the external DQS terminal, wherein the circuit system is configured to: A third pulse is generated at least in part based on the first pulse, wherein the third pulse has a third pulse width that is greater than the width of the first pulse and equal to the minimum pulse width, and A fourth pulse is generated at least in part based on the second pulse, wherein the fourth pulse has a fourth pulse width equal to the width of the second pulse and greater than or equal to the minimum pulse width. The output includes an internal DQS timing signal containing the third pulse and the fourth pulse.

12. The memory system according to claim 11, wherein: The memory device further includes a data DQ terminal configured to receive a DQ signal from the memory controller containing write data; and The memory device is configured to sample the write data received at the DQ terminal based at least in part on timing defined by the internal DQS timing signal output from the circuit system.

13. The memory system according to claim 11, wherein: The memory controller is configured to stop driving the external DQS timing signal to the external DQS terminal after a post-write synchronization cycle that ends data transfer on the memory device; and After the memory controller stops driving the external DQS timing signal, the first pulse corresponds to ringing on the external DQS timing signal.

14. A circuit comprising: An inverter having an input and an output, wherein the input is coupled to a data strobe DQS terminal of a memory device; A set / reset SR latch having a first input coupled to the output of the inverter such that the SR latch receives an inverted DQS signal at the first input, the inverted DQS signal corresponding to an external DQS signal received at the data strobe DQS terminal of the memory device; as well as A delay element having (a) an input operably connected to the output of the SR latch and (b) an output operably connected to a second input of the SR latch, wherein the delay applied by the delay element to the signal output from the output of the SR latch corresponds to a minimum pulse width, and The circuit described therein is configured to: The first pulse, which has a pulse width less than the minimum pulse width, contained in the external DQS signal, is extended into a corresponding second pulse with a pulse width equal to the minimum pulse width. The external DQS signal is supplied with a third pulse having a pulse width greater than or equal to the minimum pulse width. The output includes the corresponding second pulse and the third pulse of the internal DQS signal.

15. The circuit of claim 14, wherein the input of the inverter is coupled to the DQS terminal such that the inverter is configured to receive the external DQS signal at the input of the inverter.

16. The circuit of claim 14, further comprising another inverter having (a) an output operably connected to the second input of the SR latch or the input of the delay element, and (b) an input operably connected to the output of the SR latch or the output of the delay element.

17. The circuit of claim 14, wherein the delay element comprises an inverter or a logic gate.

18. The circuit of claim 14, wherein the SR latch comprises a NAND logic gate.

19. The circuit of claim 14, further comprising an amplifier having an input operably connected to the output of the SR latch and configured to output the internal DQS signal.

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