Integrated Chip and Its Manufacturing Method

Abstract

The manufacturing method of the integrated chip provided by the present invention includes: providing a substrate including an NMOS region and a PMOS region, a stacked layer including at least two spacer layers and a first semiconductor layer located between two adjacent spacer layers is formed on the upper surface of the substrate; removing a partial thickness of the stacked layer on the PMOS region to form a groove, and forming a second semiconductor layer to fill the groove; forming a first mask structure on the NMOS region and a second mask structure on the PMOS region, the cross-sectional width of the first mask structure is greater than the cross-sectional width of the second mask structure; etching downward and stopping at the upper surface of the substrate, forming a first stack structure on the NMOS region and a second stack structure on the PMOS region; removing the spacer layers in the first and second stack structures, retaining the first semiconductor layer as a nanosheet channel, and retaining the second semiconductor layer as a fin channel. In this way, channels with different shapes can be formed in the NMOS region and the PMOS region, which helps to improve the performance of NMOS transistors and PMOS transistors simultaneously. The present invention also provides an integrated chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to an integrated chip and a manufacturing method thereof. Background Art

[0002] Figure 1 It is a schematic diagram of the crystal plane and crystal orientation of a wafer. As Figure 1 shown, the commonly used crystal planes / crystal orientations of existing 12-inch production wafers are (100) / <110>, and the (100) crystal plane is parallel to the upper surface of the wafer. An integrated chip usually includes an N-type metal oxide semiconductor field effect transistor (abbreviated as NMOS transistor) and a P-type metal oxide semiconductor field effect transistor (abbreviated as PMOS transistor) fabricated on the wafer.

[0003] In the prior art, the channel cross-sectional structures of NMOS transistors and PMOS transistors are generally the same, and the crystal planes / crystal orientations of the channels are also the same. Based on Figure 1 the wafer, the crystal plane and crystal orientation of the top surface of the fin channel of a fin field-effect transistor (FinFET) are (100) and <110> respectively, and the crystal plane and crystal orientation of the side wall of the fin channel are (110) and <110> respectively. According to the simulation test of TCAD, the place where the channel carrier concentration is the largest is near the channel surface. Moreover, it is found that the channel surface characteristics of the (100) crystal plane / <110> crystal orientation are beneficial to the carrier migration of NMOS transistors, while the channel surface characteristics of the (110) crystal plane / <110> crystal orientation are beneficial to the carrier migration of PMOS transistors. Therefore, the top of the fin channel is beneficial to the carrier migration of NMOS transistors, and the side wall of the fin channel is beneficial to the carrier migration of PMOS transistors.

[0004] However, as CMOS transistors develop towards smaller-sized FinFETs, the area of the top of the fin channel needs to be continuously reduced, thereby limiting the number of carrier migrations of NMOS transistors and making it difficult to improve the performance of NMOS transistors. Summary of the Invention

[0005] The present invention provides an integrated chip and a manufacturing method thereof, which can simultaneously improve the channel carrier mobility of NMOS and PMOS.

[0006] To achieve the above object, on the one hand, the present invention provides a manufacturing method of an integrated chip. The manufacturing method includes:

[0007] Providing a substrate, the substrate includes an NMOS region and a PMOS region located on the side of the NMOS region, and a stacked layer covering the upper surface of the substrate is formed on the substrate. The stacked layer includes at least two spacer layers and a first semiconductor layer located between two adjacent spacer layers;

[0008] Etch the stacked layer and stop at the spacer layer closest to the substrate in the stacked layer to remove a partial thickness of the stacked layer on the PMOS region to form a groove;

[0009] Form a second semiconductor layer, and the second semiconductor layer fills the groove;

[0010] Form a first mask structure on the NMOS region and a second mask structure on the PMOS region. Both the first mask structure and the second mask structure extend along a first direction parallel to the upper surface of the substrate. In a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, the cross-sectional width of the first mask structure is greater than the cross-sectional width of the second mask structure;

[0011] Using the first mask structure and the second mask structure as masks, etch the stacked layer and the second semiconductor layer downward and stop at the upper surface of the substrate to form a first stack structure on the NMOS region and a second stack structure on the PMOS region;

[0012] Remove the spacer layer in the first stack structure and the second stack structure, retain the first semiconductor layer as a nanosheet channel, and retain the second semiconductor layer as a fin channel.

[0013] Optionally, the method of forming the first mask structure on the NMOS region and the second mask structure on the PMOS region includes:

[0014] Form a plurality of core molds on the substrate. There is a first pitch between two adjacent core molds on the NMOS region, and there is a second pitch greater than the first pitch between two adjacent core molds on the PMOS region;

[0015] Form a sidewall material layer covering the upper surface of the substrate. The sidewall material layer fills the gap between two adjacent core molds on the NMOS region and does not fill the gap between two adjacent core molds on the PMOS region;

[0016] Etch the sidewall material layer to form a first sidewall on the NMOS region and a second sidewall on the PMOS region. The first sidewall fills the gap between two adjacent core molds on the NMOS region, and there is a gap between two second sidewalls between two adjacent core molds on the PMOS region;

[0017] Remove the core molds, use the first sidewall as the first mask structure, and use the second sidewall as the second mask structure.

[0018] Optionally, the method of forming the plurality of core molds on the substrate includes:

[0019] Forming a hard mask layer and a core mold material layer on the substrate in sequence, wherein both the hard mask layer and the core mold material layer cover the stacked layer and the second semiconductor layer;

[0020] Patterning the core mold material layer to form the plurality of core molds.

[0021] Optionally, after forming the first stack structure and the second stack structure and before removing the spacer layer in the first stack structure and the second stack structure, the manufacturing method includes:

[0022] Forming dummy gates covering the middle parts of the first stack structure and the second stack structure, and exposing the ends of the first stack structure and the second stack structure;

[0023] Etching and removing the exposed ends of the first stack structure and the second stack structure; and

[0024] Forming source-drain regions at both ends of the first stack structure and the second stack structure.

[0025] Optionally, both the stacked layer and the second semiconductor layer are formed by an epitaxial growth process.

[0026] Optionally, the crystal plane and crystal orientation of the upper surface of the substrate are (100) and <110> respectively; the crystal plane and crystal orientation of the upper surface of the nanosheet channel are (100) and <110> respectively; the crystal plane and crystal orientation of the sidewall of the fin channel are (110) and <110> respectively.

[0027] Optionally, the thicknesses of both the spacer layer and the first semiconductor layer are 10 nanometers to 20 nanometers.

[0028] On the other hand, the present invention provides an integrated chip. The integrated chip includes:

[0029] A substrate, the substrate includes an NMOS region and a PMOS region located on the side of the NMOS region;

[0030] A nanosheet channel, disposed on the NMOS region and parallel to the upper surface of the substrate;

[0031] A fin channel, vertically disposed on the PMOS region;

[0032] A plurality of source-drain regions, respectively connected and disposed at the ends of the nanosheet channel and the fin channel;

[0033] Among them, both the nanosheet channel and the fin channel extend along a first direction parallel to the upper surface of the substrate. In a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, the cross-sectional width of the nanosheet channel is greater than the top surface cross-sectional width of the fin channel.

[0034] Optionally, the crystal plane and crystal orientation of the upper surface of the substrate are (100) and <110> respectively; the crystal plane and crystal orientation of the upper surface of the nanosheet channel are (100) and <110> respectively; the crystal plane and crystal orientation of the sidewall of the fin channel are (110) and <110> respectively.

[0035] Optionally, two or more nanosheet channels are provided on the NMOS region. The two or more nanosheet channels are stacked in sequence in the thickness direction of the substrate, and there is a spacing greater than zero between two adjacent nanosheet channels.

[0036] In the manufacturing method of the integrated chip of the present invention, first, a stacked layer is formed on the substrate; then, a part of the thickness of the stacked layer on the PMOS region of the substrate is removed to form a groove, and a second semiconductor layer is formed to fill the groove; then, a first mask structure is formed on the NMOS region of the substrate and a second mask structure is formed on the PMOS region. Both the first mask structure and the second mask structure extend along a first direction parallel to the upper surface of the substrate. In a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, the cross-sectional width of the first mask structure is greater than the cross-sectional width of the second mask structure; then, the stacked layer and the second semiconductor layer are etched to form a first stacked structure on the NMOS region and a second stacked structure on the PMOS region; then, the spacer layers in the first stacked structure and the second stacked structure are removed, and the first semiconductor layer of the first stacked structure is retained as the nanosheet channel, and the second semiconductor layer of the second stacked structure is retained as the fin channel. The formed nanosheet channel is parallel to the upper surface of the substrate, and the cross-sectional width is greater than the top surface cross-sectional width of the fin channel, which can increase the area of the horizontal surface of the channel (parallel to the upper surface of the substrate), and is helpful for improving the channel carrier mobility of the NMOS transistor; the sidewall of the formed fin channel (such as perpendicular to the upper surface of the substrate) has a relatively large area, which is helpful for improving the channel carrier mobility of the PMOS transistor. That is to say, by using the manufacturing method of the integrated chip of the present invention, nanosheet channels and fin channels with different shapes can be formed in the NMOS region and the PMOS region respectively, which can solve the problem that the carrier mobilities of the NMOS transistor and the PMOS transistor cannot be taken into account simultaneously due to a single channel shape, and is helpful for improving the performance of the NMOS transistor and the PMOS transistor at the same time.

[0037] In the integrated chip of the present invention, a nanosheet channel is provided on the NMOS region and a fin channel is provided on the PMOS region, which can solve the problem that the carrier mobilities of the NMOS transistor and the PMOS transistor cannot be taken into account simultaneously due to a single channel shape, and helps to improve the performance of the NMOS transistor and the PMOS transistor simultaneously. Brief Description of the Drawings

[0038] Figure 1 It is a schematic diagram of the crystal plane and crystal orientation of a wafer.

[0039] Figure 2 It is a schematic diagram of the structure of a fin channel.

[0040] Figure 3 It is a schematic flowchart of the manufacturing method of the integrated chip according to an embodiment of the present invention.

[0041] Figures 4 to 20 It is a schematic diagram of the process of manufacturing an integrated chip by using the manufacturing method of the integrated chip according to an embodiment of the present invention.

[0042] Description of the reference numerals: 100 - substrate; 101 - stacked layer; 101a - spacer layer; 101b - first semiconductor layer 101b; 101b' - nanosheet channel; 102 - liner oxide layer; 103 - groove; 104 - second semiconductor layer; 104' - fin channel; 105 - silicon nitride layer; 106 - silicon oxide layer; 107 - core mold material layer; 107a - core mold; 108 - sidewall material layer; 108a - first sidewall; 108b - second sidewall; 109 - first stack structure; 110 - second stack structure; 111 - N-type source / drain region; 112 - P-type source / drain region; 113 - depression. Detailed Embodiments

[0043] The integrated chip and its manufacturing method proposed by the present invention will be further described in detail below with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] With the development of semiconductor technology, CMOS transistors tend to develop towards smaller-sized fin field-effect transistors (FinFETs). Figure 2 Shows the structure of a fin channel. Refer to Figure 2, the crystal plane and crystal orientation of the top surface of the fin-type channel are (100) / <110> respectively, and the crystal plane and crystal orientation of the side wall of the fin-type channel are (110) / <110> respectively. It has been found through research that the channel surface characteristics of the (100) crystal plane / <110> crystal orientation are beneficial to the carrier migration of NMOS transistors, while the channel surface characteristics of the (110) crystal plane / <110> crystal orientation are beneficial to the carrier migration of PMOS transistors. Therefore, the top of the fin-type channel is beneficial to the carrier migration of NMOS transistors, and the side wall of the fin-type channel is beneficial to the carrier migration of PMOS transistors.

[0045] However, as the size of the fin field-effect transistor shrinks, the area of the top of the fin-type channel needs to be continuously reduced, which in turn limits the number of carriers migrating in the NMOS transistor, making it difficult to improve the performance of the NMOS transistor.

[0046] For this reason, this embodiment provides a method for manufacturing an integrated chip. Figure 3 The flowchart of the method for manufacturing an integrated chip according to an embodiment of the present invention is shown. As Figure 3 shown, the method for manufacturing the integrated chip includes:

[0047] S1, providing a substrate, the substrate includes an NMOS region and a PMOS region located on the side of the NMOS region, a stacked layer covering the upper surface of the substrate is formed on the substrate, and the stacked layer includes at least two spacer layers and a first semiconductor layer located between two adjacent spacer layers;

[0048] S2, etching the stacked layer and stopping in the spacer layer closest to the substrate in the stacked layer to remove a part of the thickness of the stacked layer on the PMOS region to form a groove;

[0049] S3, forming a second semiconductor layer, and the second semiconductor layer fills the groove;

[0050] S4, forming a first mask structure on the NMOS region and a second mask structure on the PMOS region, both the first mask structure and the second mask structure extend along a first direction parallel to the upper surface of the substrate, and in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, the cross-sectional width of the first mask structure is greater than the cross-sectional width of the second mask structure;

[0051] S5, using the first mask structure and the second mask structure as masks, etching the stacked layer and the second semiconductor layer downward and stopping at the upper surface of the substrate to form a first stack structure on the NMOS region and a second stack structure on the PMOS region;

[0052] S6. Remove the spacer layers in the first stack structure and the second stack structure, retain the first semiconductor layer as the nanosheet channel, and retain the second semiconductor layer as the fin channel.

[0053] Figures 4 to 20 FIG. is a schematic process diagram of manufacturing an integrated chip using the method for manufacturing an integrated chip according to an embodiment of the present invention. Among them, Figures 4 to 12 、 Figure 14 、 Figure 16 and Figure 20 are schematic cross-sectional diagrams during the manufacturing process of the integrated chip, Figure 13 、 Figure 15 、 Figures 17 to 19 are schematic plan views during the manufacturing process of the integrated chip. The following will describe the method for manufacturing the integrated chip of this embodiment in conjunction with Figures 3 to 20 as follows.

[0054] As Figure 4 shown, the provided substrate 100 includes an NMOS region 100a and a PMOS region 100b located on the side of the NMOS region. The NMOS region 100a can be used to form an NMOS transistor, and the PMOS region 100b can be used to form a PMOS transistor. The NMOS region 100a and the PMOS region 100b can be isolated by an isolation structure (not shown in the figure).

[0055] The substrate 100 can be a silicon wafer and can be a P-type wafer. However, it is not limited thereto. The substrate 100 can be a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI), or a germanium-on-insulator (GOI), etc. Certain doping particles can also be implanted into the substrate 100 according to design requirements to change electrical parameters.

[0056] In this embodiment, the crystal plane and crystal orientation of the upper surface of the substrate 100 can be (100) and <110> respectively. The size of the substrate 100 can be 8 inches or 12 inches, etc.

[0057] As Figure 5As shown, a stacked layer 101 covering the upper surface of the substrate 100 is formed on the substrate 100. The stacked layer 101 includes at least two spacer layers 101a and a first semiconductor layer 101b located between two adjacent spacer layers 101a. Or rather, the stacked layer 101 includes spacer layers 101a and first semiconductor layers 101b alternately arranged from bottom to top. The top layer of the stacked layer 101 can be a spacer layer 101a, and the bottom layer of the stacked layer 101 can also be a spacer layer 101a. In this way, the first semiconductor layer 101b under the top spacer layer 101a can be protected, which helps to ensure the performance of the nanosheet channels fabricated using the first semiconductor layer 101b.

[0058] As an example, as Figure 5 shown, the stacked layer 101 includes four spacer layers 101a and three first semiconductor layers 101b respectively interspersed between the spacer layers 101a. However, it is not limited thereto. In other embodiments, the stacked layer 101 can include two, three, or more than five spacer layers 101a, and can include two or more first semiconductor layers 101b.

[0059] In this embodiment, the thicknesses of both the spacer layer 101a and the first semiconductor layer 101b can be 10 nanometers to 20 nanometers. However, it is not limited thereto. The thicknesses of the spacer layer 101a and the first semiconductor layer 101b can be adjusted according to actual situations. It should be noted that the thickness of the spacer layer 101a can be set according to the set spacing between two adjacent nanosheet channels. That is to say, the thickness of the spacer layer 101a determines the spacing between two adjacent nanosheet channels formed subsequently.

[0060] In this embodiment, the materials of the spacer layer 101a and the first semiconductor layer 101b are different. For example, the material of the spacer layer 101a can include germanium or silicon germanium, and the material of the first semiconductor layer 101b can include silicon. In some embodiments, both the spacer layer 101a and the first semiconductor layer 101b can be fabricated by epitaxial growth processes.

[0061] As Figure 6 shown, a pad oxide layer 102 (Pad Oxide) can be formed on the substrate 100, and the pad oxide layer 102 covers the upper surface of the stacked layer 101. The material of the pad oxide layer 102 can include at least one of silicon oxide and silicon nitride. The thickness of the pad oxide layer 102 can be 30 angstroms to 80 angstroms. However, it is not limited thereto. The thickness of the pad oxide layer 102 can be adjusted as needed.

[0062] Next, as Figure 7As shown, etch the stacked layer 101 downward and stop at the spacer layer 101a closest to the substrate 100 in the stacked layer 101 to remove a partial thickness of the stacked layer 101 on the PMOS region 100b to form a groove 103. Specifically, a patterned first photoresist layer (not shown in the figure) may be formed on the pad oxide layer 102; using the first photoresist layer as a mask, etch the pad oxide layer 102 and the stacked layer 101 downward and stop at the spacer layer 101a closest to the substrate 100 in the stacked layer 101 to remove a partial thickness of the stacked layer 101 on the PMOS region 100b and form a groove 103.

[0063] As Figure 8 shown, a second semiconductor layer 104 is formed, and the second semiconductor layer 104 fills the groove 103. The method of forming the second semiconductor layer 104 may include: forming the second semiconductor layer 104 on the substrate 100 by an epitaxial growth process, and the second semiconductor layer 104 covers the upper surface of the substrate 100 and fills the groove 103 on the PMOS region 100b; performing a chemical mechanical polishing process (CMP) to remove the portion of the second semiconductor layer 104 above the stacked layer 101 and remove the pad oxide layer 102, such that the upper surface of the second semiconductor layer 104 is flush with the upper surface of the stacked layer 101 (specifically, it may refer to that the height difference between the upper surface of the stacked layer 101 and the upper surface of the second semiconductor layer 104 is within a set error range). However, it is not limited thereto, and the pad oxide layer 102 and the portion of the second semiconductor layer 104 above the stacked layer 101 may be removed by combining a chemical mechanical polishing process and a wet etching process.

[0064] After forming the second semiconductor layer 104, step S4 is performed to form a first mask structure on the NMOS region 100a and a second mask structure on the PMOS region 100b. Both the first mask structure and the second mask structure extend along a first direction parallel to the upper surface of the substrate 100. In a second direction parallel to the upper surface of the substrate 100 and perpendicular to the first direction, the cross-sectional width of the first mask structure is greater than the cross-sectional width of the second mask structure.

[0065] The method of forming the first mask structure on the NMOS region 100a and the second mask structure on the PMOS region 100b may include sub-steps S41 to S44.

[0066] Sub-step S41: Form a plurality of mandrels on the substrate 100. There is a first pitch between two adjacent mandrels on the NMOS region 100a, and there is a second pitch greater than the first pitch between two adjacent mandrels on the PMOS region 100b.

[0067] Specifically, the method of forming the plurality of core molds on the substrate 100 may include: as Figure 9 shown, a hard mask layer and a core mold material layer 107 are sequentially formed on the substrate 100, and both the hard mask layer and the core mold material layer 107 cover the stacked layer 101 and the second semiconductor layer 104; as Figure 10 shown, the core mold material layer 107 is patterned to form a plurality of core molds 107a. Among them, there may be a first pitch (d1) between two adjacent core molds 107a in the NMOS region 100a, and a second pitch (d2) greater than the first pitch (d1) between two adjacent core molds in the PMOS region 101b. The hard mask layer may include a silicon nitride layer 105 and a silicon oxide layer 106 sequentially formed on the substrate 100. However, it is not limited thereto, and the hard mask layer may further include an anti-reflection layer, etc. The material of the core mold material layer 107 may include an amorphous silicon layer (A-Si).

[0068] Sub-step S42: as Figure 11 shown, a sidewall material layer 108 covering the upper surface of the substrate 100 is formed. The sidewall material layer 108 fills the gap between two adjacent core molds 107a in the NMOS region 100a, and does not fill the gap between two adjacent core molds in the PMOS region 100b. That is, after the sidewall material layer 108 is formed, there is still a depression 113 between two adjacent core molds 107a in the PMOS region 100b.

[0069] To ensure that the sidewall material layer 108 can fill the gap between two adjacent core molds 107a in the NMOS region 100a, the first pitch (d1) between two adjacent core molds 107a in the NMOS region 100a may be less than twice the thickness of the sidewall material layer 108, or rather, the thickness of the sidewall material layer 108 is at least greater than half of the first pitch (d1).

[0070] Sub-step S43: as Figure 12 shown, the sidewall material layer 108 is etched to form a first sidewall 108a on the NMOS region 100a and a second sidewall 108b on the PMOS region 100b. The first sidewall 108a fills the gap between two adjacent core molds 107a in the NMOS region 100b, and there is a gap between the two second sidewalls 108b between two adjacent core molds 107a in the PMOS region 100b.

[0071] It should be noted that during the process of etching the sidewall material layer 108 to form the first sidewall 108a and the second sidewall 108b, the part of the sidewall material layer 108 higher than the core mold 107a is etched away. Moreover, since after the sidewall material layer 108 is formed, as Figure 11As shown, there is also a depression 113 between two adjacent core patterns 107a on the PMOS region 100b. During the process of etching the sidewall material layer 108, the sidewall material layer 108 at the bottom of the depression 113 can be removed, thereby forming two second sidewalls 108a with gaps between two adjacent core patterns 107a on the PMOS region 100b.

[0072] In this embodiment, an anisotropic etching process can be used to etch the sidewall material layer 108 to form the first sidewall 108a and the second sidewall 108b.

[0073] Figure 13 The planar structure after the first sidewall and the second sidewall are formed on the upper surface of the substrate 100 is shown. Figure 14 For the substrate along Figure 13 The sectional view along line AB.

[0074] After sub-step S43, sub-step S44 is executed. As Figure 13 And Figure 14 shown, the core pattern 107a is removed, with the first sidewall 108a as the first mask structure and the second sidewall 108b as the second mask structure, and the stacked layer 101 and the second semiconductor layer 104 are etched downward. As Figure 13 shown, the first sidewall 108a and the second sidewall 108b can both extend along a first direction parallel to the upper surface of the substrate 100. In a second direction parallel to the upper surface of the substrate 100 and perpendicular to the first direction, the cross-sectional width of the first sidewall 108a is greater than the cross-sectional width of the second sidewall 108b. For example, in the second direction, the cross-sectional width of the first sidewall 108a (i.e., the first mask structure) can be equal to the first pitch (d1); the cross-sectional width of the second sidewall 108b (i.e., the second mask structure) can be determined by the deposition thickness of the sidewall material layer 108.

[0075] Figure 15 The planar schematic diagram of the substrate after the first stack structure and the second stack structure are formed. Figure 16 For Figure 15 The sectional schematic diagram of the substrate shown along line CD. As Figure 15 And Figure 16 shown, after the first sidewall 108a and the second sidewall 108b are formed, using the first sidewall 108a and the second sidewall 108b as masks, the silicon oxide layer 106, the silicon nitride layer 105, the stacked layer, and the second semiconductor layer 104 are etched downward and stopped at the upper surface of the substrate 100. Then, the silicon oxide layer 106 and the silicon nitride layer 106 are removed, and a first stack structure 109 is formed on the NMOS region 100a and a second stack structure 110 is formed on the PMOS region 100b.

[0076] AsFigure 15 and Figure 16 As shown in Figure 16 , the first stack structure 109 includes the remaining stacked layers 101 on the NMOS region 100a, and the second stack structure 110 includes the remaining second semiconductor layer 104 and the spacer layer 101a on the PMOS region 100b. It should be noted that, in this embodiment, as shown in Figure 15 and Figure 16 As shown in Figure 16 , one first stack structure 109 can be formed on one NMOS region 100a, and two second stack structures 110 can be formed on one PMOS region 100b. However, it is not limited thereto. In other embodiments, more than two first stack structures 109 can be formed on one NMOS region 100a, and one second stack structure 110 or more than three second stack structures 110 can be formed on one PMOS region 100b.

[0077] After forming the first stack structure 109 on the NMOS region 100a and the second stack structure 110 on the PMOS region, the manufacturing method may further include: as shown in Figure 17 As shown in Figure 17 , forming a dummy gate 114 covering the middle portions of the first stack structure 109 and the second stack structure 110, and exposing the ends of the first stack structure 109 and the second stack structure 110.

[0078] Specifically, the method of forming the dummy gate 114 may include: First, forming a dummy interface layer (not shown in the figure) covering the upper surface of the substrate on the substrate 100, and the dummy interface layer covers the sidewalls and the top surfaces of the first stack structure 109 and the second stack structure 110; then, forming a dummy gate material layer on the substrate 100, and the dummy gate material layer covers the dummy interface layer; next, forming a patterned second photoresist layer (not shown in the figure) on the dummy gate material layer, using the patterned second photoresist layer as a mask, etching the dummy gate material layer to form a dummy gate 114 covering the middle portions of the first stack structure 109 and the second stack structure 110, and exposing the ends of the first stack structure 109 and the second stack structure 110.

[0079] Among them, the dummy interface layer may include a dielectric material layer, and the material of the dielectric material layer may include, for example, nitrides (such as silicon nitride or silicon oxynitride), carbides (such as silicon carbide), oxides (such as silicon oxide), or some other suitable materials. The material of the dummy gate 114 (or the dummy gate material layer) may include, for example, polysilicon. The dummy interface layer and the dummy gate material layer can be formed by methods such as thermal oxidation process and / or deposition process (such as PVD, CVD, PE-CVD, ALD, etc.).

[0080] After forming the dummy gate 114, as Figure 18 shown, etch away the exposed ends of the first stack structure 109 and the second stack structure 110. Specifically, the second photoresist layer on the dummy gate 114 can be used as a mask, and under the protection of the dummy gate 114, etch away the exposed ends of the first stack structure 109 and the second stack structure 110.

[0081] Next, as Figure 18 shown, source / drain regions are formed at both ends of the first stack structure 109 and the second stack structure 110. As an example, N-type source / drain regions 111 are formed at both ends of the first stack structure 109, and P-type source / drain regions 112 are formed at both ends of the second stack structure 110. The N-type source / drain regions 111 and the P-type source / drain regions 112 do not directly contact each other. The materials of the N-type source / drain regions 111 and the P-type source / drain regions 112 are, for example, doped silicon. The N-type source / drain regions 111 and the P-type source / drain regions 112 can both be formed by an epitaxial growth process.

[0082] Continuing to refer to Figure 18 , in this embodiment, the two P-type source / drain regions 112 correspond to the two second stack structures 110 on the same PMOS region 100b, and the two P-type source / drain regions 112 are respectively connected to both ends of each second stack structure 110. However, it is not limited to this. In other embodiments, the two P-type source / drain regions 112 can be respectively connected to both ends of one second stack structure 110; or, the two P-type source / drain regions 112 can correspond to three or more second stack structures 110 on the same PMOS region 100b, and the two P-type source / drain regions 112 are respectively connected to both ends of each second stack structure 110.

[0083] Figure 20 is Figure 19 a schematic cross-sectional view along the EF line. After source / drain regions are formed at both ends of the first stack structure 109 and the second stack structure 110, as Figure 19 and Figure 20 shown, remove the spacer layer 101a in the first stack structure 109 and the second stack structure 110. The first semiconductor layer 101b in the remaining first stack structure 109 serves as a nano sheet channel 101b', and the second semiconductor layer 104 in the remaining second stack structure 110 serves as a fin channel 104'.

[0084] As Figure 19 and Figure 20As shown, the nanosheet channel 101b' is disposed parallel to the upper surface of the substrate 100, and the fin channel is vertically disposed on the upper surface of the substrate 100. Both the nanosheet channel 101b' and the fin channel 104' extend along a first direction parallel to the upper surface of the substrate 100. In a second direction, the cross-sectional width of the nanosheet channel 101b' is greater than the top surface cross-sectional width of the fin channel 104'. Forming the nanosheet channel 101b' on the NMOS region 100a can increase the area of the horizontal surface (parallel to the upper surface of the substrate) of the channel, that is, can stretch the horizontal surface of the channel, which helps to improve the channel carrier mobility of the NMOS transistor; forming the fin channel 104' on the PMOS region 100b, the sidewall area of the fin channel 104' is relatively large, that is, can stretch the sidewall of the channel, which helps to improve the channel carrier mobility of the PMOS transistor.

[0085] In this embodiment, the crystal plane and crystal direction of the nanosheet channel 101b' parallel to the upper surface of the substrate 100 are (100) and <110> respectively, which helps to improve the channel carrier mobility of the NMOS transistor. And the crystal plane and crystal direction of the sidewall of the fin channel 104' are (110) and <110> respectively, which helps to improve the channel carrier mobility of the PMOS transistor.

[0086] Using the manufacturing method of the integrated chip of the present invention, the nanosheet channel 101b' and the fin channel 104' can be formed in the NMOS region 100a and the PMOS region 100b respectively, which can solve the problem that the carrier mobilities of the NMOS transistor and the PMOS transistor cannot be taken into account simultaneously due to a single channel shape, and helps to improve the performance of the NMOS transistor and the PMOS transistor simultaneously.

[0087] This embodiment also provides an integrated chip, and the integrated chip can be manufactured by using the manufacturing method of the above integrated chip. However, it is not limited thereto, and the integrated chip can also be manufactured by using other methods.

[0088] As Figure 19 and Figure 20As shown, the integrated chip includes a substrate 100, a nanosheet channel 101b', a fin channel 104', and multiple source / drain regions. The substrate includes an NMOS region 100a and a PMOS region 100b located on the side of the NMOS region 100a. The NMOS region 100a can be used to form an NMOS transistor, and the PMOS region 100b can be used to form a PMOS transistor. The nanosheet channel 101b' is disposed on the NMOS region 100a and parallel to the upper surface of the substrate 100. The fin channel 104' is vertically disposed on the PMOS region 100b. Multiple source / drain regions are respectively connected and disposed at the ends of the nanosheet channel 101b' and the fin channel 104'. The multiple source / drain regions can include an N-type source / drain region 111 disposed on the NMOS region 100 and a P-type source / drain region 112 disposed on the PMOS region 100b.

[0089] Wherein, both the nanosheet channel 101b' and the fin channel 104' extend along a first direction parallel to the upper surface of the substrate 100. In a second direction parallel to the upper surface of the substrate 100 and perpendicular to the first direction, the cross-sectional width of the nanosheet channel 101b' is greater than the top surface cross-sectional width of the fin channel 104'.

[0090] In this embodiment, the crystal plane and crystal orientation of the upper surface of the substrate can be (100) and <110> respectively. In order to increase the carrier mobility of the channels of the NMOS transistor and the PMOS transistor, the crystal plane and crystal orientation of the upper surface of the nanosheet channel 101b' can be (100) and <110> respectively, and the crystal plane and crystal orientation of the sidewalls of the fin channel 104' can be (110) and <110> respectively.

[0091] As an example, as Figure 19 and Figure 20 shown, a group of nanosheet channels 101b' is disposed on one NMOS region 100a, and a group of nanosheet channels 101b' corresponds to, for example, a first stack structure 109; two mutually parallel fin channels 104' are disposed on one PMOS region 100b. However, it is not limited thereto. Two or more groups of nanosheet channels 101b' can be disposed on one NMOS region 100a; one fin channel 104' can be formed on one PMOS region 100b, or three or more fin channels 104' can be disposed.

[0092] Referring to Figure 20 , a group of nanosheet channels 101b' can include more than two nanosheet channels 101b'. The more than two nanosheet channels 101b' are stacked in sequence in the thickness direction of the substrate 100, and there is a spacing greater than zero between two adjacent nanosheet channels 101b'. The spacing greater than zero can be determined by, for example, the thickness of the spacer layer 101a.

[0093] In the integrated chip of this embodiment, a nanosheet channel 101b' is provided on the NMOS region 100a, and a fin channel 104' is provided on the PMOS region 100b. The nanosheet channel 101b' can increase the area of the horizontal surface of the channel (parallel to the upper surface of the substrate), and the fin channel 104' can increase the sidewall area of the channel. In this way, the problem that the carrier mobilities of the NMOS transistor and the PMOS transistor cannot be taken into account simultaneously due to a single channel shape can be solved, which helps to improve the performance of both the NMOS transistor and the PMOS transistor.

[0094] It should be noted that the embodiments in this specification are described in a progressive manner. The structures described later mainly focus on the differences from the methods described earlier. For the same and similar parts between each part, reference can be made to each other. For the integrated chip disclosed in the embodiment, since it corresponds to the manufacturing method of the integrated chip disclosed in the embodiment, the description is relatively simple. For related parts, reference can be made to the description in the method part.

[0095] Referring to "embodiment" in this application means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of this application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art will explicitly and implicitly understand that the embodiments described in this application can be combined with other embodiments without conflict.

[0096] Unless otherwise defined, the technical terms or scientific terms involved in this application should have the ordinary meaning understood by those of ordinary skill in the technical field to which this application belongs. The words such as "a", "an", "one kind", "the" and the like involved in this application do not indicate a quantity limitation and can represent a single or plural number. The terms "including", "comprising", "having" and any variations thereof involved in this application are intended to cover non-exclusive inclusion. The orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer" and the like involved in this application is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as a limitation to this application.

[0097] The above description is only a description of the preferred embodiments of the present invention and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical content disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing an integrated chip, characterized in that, Including: Providing a substrate, the substrate including an NMOS region and a PMOS region located on the side of the NMOS region, a stacked layer covering the upper surface of the substrate being formed on the substrate, the stacked layer including at least two spacer layers and a first semiconductor layer located between two adjacent spacer layers; Etching the stacked layer and stopping in the spacer layer closest to the substrate in the stacked layer to remove a partial thickness of the stacked layer on the PMOS region to form a groove; Forming a second semiconductor layer, the second semiconductor layer filling the groove; Forming a first mask structure on the NMOS region and a second mask structure on the PMOS region, both the first mask structure and the second mask structure extending along a first direction parallel to the upper surface of the substrate, and in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, the cross-sectional width of the first mask structure being greater than the cross-sectional width of the second mask structure; Using the first mask structure and the second mask structure as masks, etching the stacked layer and the second semiconductor layer downward and stopping at the upper surface of the substrate to form a first stack structure on the NMOS region and a second stack structure on the PMOS region; Removing the spacer layers in the first stack structure and the second stack structure, retaining the first semiconductor layer as a nanosheet channel, and retaining the second semiconductor layer as a fin channel.

2. The manufacturing method of the integrated chip according to claim 1, wherein The method of forming the first mask structure on the NMOS region and the second mask structure on the PMOS region includes: Forming a plurality of core patterns on the substrate, there being a first pitch between two adjacent core patterns on the NMOS region, and there being a second pitch greater than the first pitch between two adjacent core patterns on the PMOS region; Forming a sidewall material layer covering the upper surface of the substrate, the sidewall material layer filling the gaps between two adjacent core patterns on the NMOS region and not filling the gaps between two adjacent core patterns on the PMOS region; Etching the sidewall material layer to form a first sidewall on the NMOS region and a second sidewall on the PMOS region, the first sidewall filling the gaps between two adjacent core patterns on the NMOS region, and there being a gap between two second sidewalls between two adjacent core patterns on the PMOS region; Removing the core patterns, using the first sidewall as the first mask structure and using the second sidewall as the second mask structure.

3. The manufacturing method according to claim 2, characterized in that, The method of forming the plurality of core patterns on the substrate includes: Sequentially forming a hard mask layer and a core pattern material layer on the substrate, both the hard mask layer and the core pattern material layer covering the stacked layer and the second semiconductor layer; Performing a patterning process on the core pattern material layer to form the plurality of core patterns.

4. The manufacturing method according to claim 1, characterized in that, Before removing the spacer layers in the first stack structure and the second stack structure after forming the first stack structure and the second stack structure, the manufacturing method includes: Form a dummy gate covering the middle part of the first stack structure and the second stack structure, and expose the ends of the first stack structure and the second stack structure; Etch and remove the exposed ends of the first stack structure and the second stack structure; and Form source-drain regions at both ends of the first stack structure and the second stack structure.

5. The manufacturing method according to claim 1, characterized in that, Both the stacked layer and the second semiconductor layer are formed by an epitaxial growth process.

6. The manufacturing method according to claim 1, characterized in that, The crystal plane and crystal orientation of the upper surface of the substrate are (100) and <110> respectively; the crystal plane and crystal orientation of the upper surface of the nanosheet channel are (100) and <110> respectively; the crystal plane and crystal orientation of the sidewall of the fin channel are (110) and <110> respectively.

7. The manufacturing method according to claim 1, characterized in that, The thicknesses of both the spacer layer and the first semiconductor layer are 10 nanometers to 20 nanometers.

8. An integrated chip, characterized in that, Comprising: A substrate, the substrate includes an NMOS region and a PMOS region located on the side of the NMOS region; A nanosheet channel, disposed on the NMOS region and parallel to the upper surface of the substrate; A fin channel, vertically disposed on the PMOS region; Multiple source-drain regions, respectively connected and disposed at the ends of the nanosheet channel and the fin channel; Wherein, both the nanosheet channel and the fin channel extend along a first direction parallel to the upper surface of the substrate, and in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, the cross-sectional width of the nanosheet channel is greater than the top cross-sectional width of the fin channel.

9. The integrated chip according to claim 8, characterized in that, The crystal plane and crystal orientation of the upper surface of the substrate are (100) and <110> respectively; the crystal plane and crystal orientation of the upper surface of the nanosheet channel are (100) and <110> respectively; the crystal plane and crystal orientation of the sidewall of the fin channel are (110) and <110> respectively.

10. The integrated chip according to claim 8, characterized in that, Two or more nanosheet channels are disposed on the NMOS region, the two or more nanosheet channels are stacked in sequence in the thickness direction of the substrate, and there is a spacing greater than zero between adjacent two nanosheet channels.

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