Semiconductor Structure and Method of Manufacturing the Same

Abstract

The present application provides a semiconductor structure and a manufacturing method thereof, relating to the field of semiconductor technology, and is used to solve the technical problem of relatively large bit line loss. The manufacturing method of the semiconductor structure includes: forming a spin-on hard mask layer on a substrate, where multiple spaced active regions are provided in the substrate, and multiple spaced bit lines extending along a first direction are provided on the substrate, and each bit line is electrically connected to at least one active region, and the spin-on hard mask layer fills between the bit lines and covers the bit lines; removing a part of the spin-on hard mask layer to form multiple spaced first channels; forming a first sacrificial layer in the first channels; removing the spin-on hard mask layer between the first sacrificial layers to form second channels; forming a first support layer in the second channels; removing the first sacrificial layer, and extending the first channels between adjacent bit lines to the active regions. The spin-on hard mask layer is used to reduce the loss of bit lines in subsequent etching.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, semiconductor structures are increasingly widely used. Dynamic Random Access Memory (DRAM) has gradually become a commonly used semiconductor storage device in electronic devices. A dynamic random access memory includes a plurality of memory cells, and each memory cell includes a transistor and a capacitor. The capacitor stores data information, and the transistor controls the reading and writing of the data information in the capacitor. Among them, the gate of the transistor is electrically connected to a word line (WL), and the on and off of the transistor are controlled by the voltage on the word line; one of the source and drain of the transistor is electrically connected to a bit line (BL), and the other of the source and drain is electrically connected to the capacitor, and the data information is stored or output through the bit line.

[0003] In related technologies, generally, bit lines arranged at intervals and extending in a first direction are first formed on a substrate, and then a first support layer is formed between adjacent bit lines. The bit lines and the first support layer enclose a filling hole. However, during the process of forming the filling hole, a relatively large amount of the portion of the bit line away from the substrate is lost, affecting the performance of the bit line. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a semiconductor structure and a manufacturing method thereof, which are used to reduce the damage of the bit line and ensure the performance of the bit line.

[0005] A first aspect of an embodiment of this application provides a manufacturing method of a semiconductor structure, which includes: forming a spin-on hard mask layer on a substrate, wherein a plurality of active regions arranged at intervals are provided in the substrate, and a plurality of bit lines arranged at intervals and extending in a first direction are provided on the substrate, each of the bit lines is electrically connected to at least one of the active regions, and the spin-on hard mask layer fills between the bit lines and covers the bit lines; removing a part of the spin-on hard mask layer to form a plurality of first channels arranged at intervals and extending in a second direction; forming a first sacrificial layer in the first channels, and the first sacrificial layer fills the first channels; removing the spin-on hard mask layer between the first sacrificial layers to form second channels; forming a first support layer in the second channels, and the first support layer fills the second channels; removing the first sacrificial layer, and extending the first channels between adjacent bit lines to the active regions.

[0006] The manufacturing method of the semiconductor structure provided by the embodiment of this application has at least the following advantages:

[0007] In the manufacturing method of the semiconductor structure according to the embodiments of the present application, by forming a spin-on hard mask layer filled between the bit lines and covering the bit lines, and taking advantage of the characteristics that the spin-on hard mask layer is difficult to etch, a high selectivity ratio between the spin-on hard mask layer and the bit lines is achieved, thereby reducing the loss of the part of the bit line far from the substrate during subsequent etching and ensuring the performance of the bit line.

[0008] The second aspect of the embodiments of the present application provides a semiconductor structure, which is obtained by the above-mentioned manufacturing method of the semiconductor structure. Therefore, it has at least the advantage of less loss of the bit line. For the specific effects, please refer to the above description and will not be elaborated here. Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0010] Figure 1 It is a flowchart of the manufacturing method of the semiconductor structure according to the embodiments of the present application;

[0011] Figure 2 It is a schematic structural diagram of the substrate and the bit line according to the embodiments of the present application;

[0012] Figure 3 It is a perspective view after forming the photoresist layer according to the embodiments of the present application;

[0013] Figure 4 It is Figure 3 a cross-sectional view taken along line A-A in

[0014] Figure 5 It is a perspective view after forming the first sacrificial layer according to the embodiments of the present application;

[0015] Figure 6 It is Figure 5 a cross-sectional view taken along line B-B in

[0016] Figure 7 It is a perspective view after forming the second channel according to the embodiments of the present application;

[0017] Figure 8 It is a perspective view after forming the first support layer according to the embodiments of the present application;

[0018] Figure 9 It is a perspective view after removing the remaining spin-on hard mask layer according to the embodiments of the present application;

[0019] Figure 10 It is Figure 9Schematic cross-sectional view at C-C;

[0020] Figure 11 Schematic structural view of the contact hole extending into the active region in the embodiment of the present application;

[0021] Figure 12 Schematic structural view after forming the first trench in the embodiment of the present application;

[0022] Figure 13 Schematic structural view after forming the first filling layer in the embodiment of the present application;

[0023] Figure 14 Schematic structural view after exposing the second sacrificial layer in the embodiment of the present application;

[0024] Figure 15 Schematic structural view after forming the first etching groove in the embodiment of the present application;

[0025] Figure 16 Schematic structural view of the first etching groove penetrating through the silicon-containing anti-reflection layer in the embodiment of the present application;

[0026] Figure 17 Schematic structural view after forming the first channel in the embodiment of the present application;

[0027] Figure 18 Schematic structural view after forming the first intermediate groove in the embodiment of the present application;

[0028] Figure 19 Schematic structural view after forming the third sacrificial layer in the embodiment of the present application;

[0029] Figure 20 Schematic structural view after removing a part of the third sacrificial layer in the embodiment of the present application;

[0030] Figure 21 Schematic structural view after forming the first sacrificial layer in the embodiment of the present application;

[0031] Figure 22 Schematic structural view after removing the film layer above the spin-on hard mask layer in the embodiment of the present application;

[0032] Figure 23 Schematic structural view after forming the first conductive layer in the embodiment of the present application;

[0033] Figure 24 Schematic structural view after forming the conductive column in the embodiment of the present application;

[0034] Figure 25 Schematic structural view after forming the first protective layer in the embodiment of the present application.

[0035] Explanation of reference numerals:

[0036] 100 - Substrate; 110 - Substrate; 111 - Active region;

[0037] 112 - Shallow trench isolation; 113 - Word line; 120 - Insulating layer;

[0038] 130 - Barrier layer; 140 - Bit line plug; 150 - Bit line;

[0039] 151 - Second conductive layer; 152 - Second support layer; 153 - Oxide layer;

[0040] 200 - Spin - on hard mask layer; 210 - First channel; 211 - Second trench;

[0041] 212 - Filling hole; 220 - First sacrificial layer; 230 - Second channel;

[0042] 240 - First support layer; 250 - Conductive pillar; 251 - First conductive layer;

[0043] 260 - Protective layer; 300 - Intermediate layer; 400 - Silicon - containing anti - reflection layer;

[0044] 410 - First trench; 420 - Second sacrificial layer; 430 - First filling layer;

[0045] 440 - First etching groove; 500 - First mask layer; 510 - First base layer;

[0046] 520 - First anti - reflection layer; 600 - Second mask layer; 610 - Second base layer;

[0047] 620 - Second anti - reflection layer; 630 - First intermediate groove; 640 - Third sacrificial layer;

[0048] 650 - Second intermediate groove; 700 - Photoresist layer. Detailed implementation manners

[0049] In order to reduce the bit line loss during the fabrication process of the semiconductor structure, an embodiment of the present application provides a method for fabricating a semiconductor structure. By forming a spin - on hard mask layer that fills between the bit lines and covers the bit lines, and using the high selectivity between the spin - on hard mask layer and the bit lines, the loss of the bit lines during subsequent etching is reduced, ensuring the performance of the bit lines.

[0050] To make the above objects, features, and advantages of the embodiments of the present application more apparent and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0051] Referring to Figure 1 , an embodiment of the present application provides a method for manufacturing a semiconductor structure. The manufacturing method at least includes the following steps:

[0052] Step S101: Form a spin-on hard mask layer on a substrate. Among them, a plurality of spaced active regions are provided in the substrate, and a plurality of spaced bit lines extending in a first direction are provided on the substrate. Each bit line is electrically connected to at least one active region, and the spin-on hard mask layer fills between the bit lines and covers the bit lines.

[0053] Referring to Figures 2 to 4 , the filling patterns in the accompanying drawings in the embodiments of the present application are only used to distinguish different structures in the drawings and are not used to represent the materials of the various structures in the drawings. As Figures 2 to 4 shown, the substrate 100 is used to support the film layers formed on the substrate 100, such as the bit line 150 and the spin-on hard mask layer 200.

[0054] As Figures 2 to 4 shown, a plurality of spaced active regions 111 are provided in the substrate 100. Each active region 111 can be defined by shallow trench isolation 112 (Shallow Trench Isolation, abbreviated as STI). Specifically, a part of the substrate 100 is removed by an etching process to a preset depth to form a groove surrounding the plurality of active regions 111, and then an insulating material is deposited in the groove to isolate the active regions 111 from each other. The insulating material can be silicon oxide or silicon nitride, etc.

[0055] Exemplarily, the substrate 100 may include a substrate 110, an insulating layer 120, and a barrier layer 130 that are sequentially stacked. Among them, the substrate 110 may be a semiconductor substrate 110, such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a germanium arsenic substrate, a Silicon On Insulator (SOI) substrate, or a Germanium On Insulator (GOI) substrate, etc. The substrate 110 may be doped or undoped. Exemplarily, the substrate 110 may be an N-type substrate or a P-type substrate.

[0056] The above active region 111 is formed within the substrate 110 and is exposed on the upper surface of the substrate 110. A plurality of word lines 113 spaced apart are also formed within the substrate 110. As Figure 4 shown, the plurality of word lines 113 extend in the second direction, and each word line 113 is insulated from the active region 111. Among them, the word line 113 can be a buried word line (Buried Word Line, abbreviated as BWL), and the active region 111 is inclined with respect to the extending direction of the word line 113 to increase the arrangement density of the active region 111.

[0057] Continuing to refer to Figure 2 and Figure 3 , an insulating layer 120 is formed on the substrate 110 to cover the active region 111 for isolating and protecting the active region 111. The material of the insulating layer 120 can be the same as the insulating material in the shallow trench isolation 112. After depositing the insulating material to form the shallow trench isolation 112, the insulating material is continuously deposited to form the insulating layer 120 to simplify the manufacturing steps of the semiconductor structure.

[0058] A barrier layer 130 is formed on the insulating layer 120, and the barrier layer 130 corresponds to the bit line 150. The material of the barrier layer 130 can be silicon nitride or silicon oxynitride, and can be used as an etch stop layer subsequently to reduce the etching of the insulating layer 120. A plurality of contact holes are formed in the barrier layer 130 and the insulating layer 120, and each contact hole exposes the active region 111. Exemplarily, two contact holes correspond to one active region 111, and each of the two contact holes exposes one end of the active region 111.

[0059] Continuing to refer to Figure 2 and Figure 3 , a plurality of bit lines 150 spaced apart are provided on the substrate 100, and each bit line 150 extends in the first direction, and each bit line 150 is electrically connected to at least one active region 111. Exemplarily, a bit line contact 140 is disposed in the contact hole, and the bit line contact 140 is in contact with the active region 111. The bit line contact 140 can be a plurality of columnar structures filled in the contact hole, or, as Figure 2 shown, the bit line contact 140 can also be a comb-like structure, and each tooth is filled in the contact hole. During the etching and formation process of the bit line contact 140 and the bit line 150, the barrier layer 130 is also etched so that the barrier layer 130 corresponds to the bit line contact 140, that is, the bit line contact 140 located outside the contact hole is disposed on the barrier layer 130. It can be understood that Figure 4 the A-A cross section shown is a plane located between adjacent bit lines, and the barrier layer 130 is not intercepted in this plane.

[0060] Continuing to refer to Figure 2 and Figure 3, in some possible examples, the bit line 150 includes a second conductive layer 151 and a second support layer 152 covering the second conductive layer 151. The second conductive layer 151 extends in a first direction and is in contact with the bit line plug 140, and the electrical connection between the bit line 150 and the active region 111 is realized through the bit line plug 140. As Figure 2 and Figure 3 shown, the second support layer 152 may also cover the substrate 100 between the second conductive layers 151.

[0061] As Figure 2 shown, an oxide layer 153 is further disposed in the second support layer 152 beside the second conductive layer 151. For example, an oxide layer 153 is disposed on each side of the second conductive layer 151, and the oxide layer 153 is not in contact with the second conductive layer 151. Figure 3 The oxide layer 153 is not drawn in

[0062] Among them, as Figure 2 shown, the material of the bit line plug 140 may be poly-silicon, and the second conductive layer 151 may be a metal layer or a metal stack. For example, the second conductive layer 151 includes a titanium nitride layer in contact with the bit line plug 140 and a tungsten layer on the titanium nitride layer. The second support layer 152 may be a nitride layer, such as a silicon nitride layer. Along the direction away from the side wall of the second conductive layer 151, it is nitride, oxide, nitride (Nitride-oxide-Nitride, abbreviated as NON) in sequence.

[0063] Referring to Figure 3 and Figure 4 , the spin-on hardmask layer 200 (Spin on Hardmask, abbreviated as SOH) is filled between the bit lines 150 and covers the bit lines 150. The spin-on hardmask layer 200 may have a large selectivity ratio with the second support layer 152 of the bit line 150, so that during the subsequent etching process of the spin-on hardmask layer 200, the etching loss of the second support layer 152 is small, thereby reducing the loss of the bit line 150 and ensuring the performance of the bit line 150. Exemplarily, the selectivity ratio of the spin-on hardmask layer 200 to the second support layer 152 is greater than or equal to 5.

[0064] Step S102: Remove a part of the spin-on hardmask layer to form a plurality of first channels arranged at intervals and extending in a second direction.

[0065] Dry etching or wet etching is used to remove a part of the spin-on hardmask layer 200 (refer to Figure 4 ), and a plurality of first channels arranged at intervals and extending in a second direction are formed. The second direction has an angle with the first direction. For example, the second direction is perpendicular to the first direction. After the first channels are formed, the spin-on hardmask layer 200 is divided into multiple pieces by the first channels.

[0066] It can be understood that each first channel includes a second trench located above the bit line and extending in the second direction, and a filling hole located between adjacent bit lines and communicating with the second trench. That is, during the formation of the first channel, a second trench is formed in the spin-on hard mask layer 200 above the bit line, and a filling hole is formed in the spin-on hard mask layer 200 between the bit lines. The second trench communicates with the filling hole located below the second trench.

[0067] Step S103: Form a first sacrificial layer in the first channel, and the first sacrificial layer fills the first channel.

[0068] Reference Figure 5 and Figure 6 As shown in FIG. 9 and FIG. 10, a first sacrificial layer 220 is deposited in the first channel, and the first sacrificial layer fills the first channel completely. Exemplarily, the first sacrificial layer 220 is formed by processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). The material of the first sacrificial layer 220 can be an oxide, such as silicon oxide, for easy removal in the subsequent process.

[0069] Step S104: Remove the spin-on hard mask layer between the first sacrificial layers to form a second channel.

[0070] Reference Figure 7 As shown in FIG. 11, after the first sacrificial layer 220 is formed, the spin-on hard mask layer 200 between the first sacrificial layers 220 is etched and removed. It can be understood that the spin-on hard mask layer 200 is removed in two steps. The first step is to remove a part of the spin-on hard mask layer 200 to form the first channel, and the second step is to remove the remaining spin-on hard mask layer 200 to form the second channel 230. The shape of the second channel 230 is substantially the same as that of the first channel.

[0071] Step S105: Form a first support layer in the second channel, and the first support layer fills the second channel.

[0072] Reference Figure 7 and Figure 8 As shown in FIG. 12 and FIG. 13, a first support layer 240 is deposited in the second channel 230, and the first support layer 240 fills the second channel 230 completely. The material of the first support layer 240 can be the same as that of the second support layer 152 of the bit line 150, both of which are insulating materials, such as silicon nitride.

[0073] Step S106: Remove the first sacrificial layer and extend the first channel between adjacent bit lines to the active region.

[0074] Reference Figures 8 to 11 Etch away the first sacrificial layer 220. Exemplarily, the first sacrificial layer 220 is wet-etched using an acidic etchant. The first sacrificial layer 220 has a relatively large selectivity compared to the first support layer 240 to reduce damage to the first support layer 240. After removing the first sacrificial layer 220, the first channel 210 is exposed. As Figure 11 shown, the first channel 210 located between adjacent bit lines 150 also extends to the active region 111 to expose the active region 111 within the first channel 210.

[0075] In a possible embodiment, the substrate 100 includes a substrate 110, an insulating layer 120 disposed on the substrate 110, and a barrier layer 130 disposed on the insulating layer. A plurality of active regions 111 are provided in the substrate 110, and the insulating layer 120 covers the active regions 111. Correspondingly, removing the first sacrificial layer 220 and extending the first channel 210 located between adjacent bit lines 150 to the active region 111 specifically includes:

[0076] Reference Figures 8 to 10 Etch the first sacrificial layer 220 to expose the first channel 210. Each first channel 210 includes a second trench 211 located above the bit line 150 and extending in the second direction, and a filling hole 212 located between adjacent bit lines 150 and communicating with the second trench 211. As Figure 9 and Figure 10 shown, the second support layer 152 extending in the second direction and the first support layer 240 extending in the first direction enclose the above-mentioned filling hole 212.

[0077] Reference Figure 11 , then etch the insulating layer 120 along the filling hole 212 of the first channel 210 to expose the active region 111 in the filling hole 212. As Figure 11 shown, the filling hole 212 penetrates the insulating layer 120 and extends to the active region 111, so that the active region 111 is exposed in the filling hole 212, facilitating electrical connection between the active region 111 and the conductive pillar 250 formed in the filling hole 212. It should be noted that when the second support layer 152 also covers the substrate 100, the filling hole 212 also penetrates the second support layer 152, that is, the filling hole 212 penetrates the second support layer 152 and the insulating layer 120 and extends to the active region 111.

[0078] In summary, in the manufacturing method of the semiconductor structure in the embodiments of the present application, by forming a spin-on hard mask layer 200 filled between the bit lines 150 and covering the bit lines 150, using the relatively high selectivity of the spin-on hard mask layer 200 and the bit lines 150 (reference Figure 2 ), the loss of the part of the bit line 150 far from the substrate 100 during subsequent etching is reduced, ensuring the performance of the bit line 150.

[0079] In some possible examples, referring to Figures 12 to 17 , removing a part of the spin-coated hard mask layer to form a plurality of first channels arranged at intervals and extending in the second direction (step S102) may include the following steps:

[0080] Step S1021: Form an intermediate layer and a silicon-containing anti-reflection layer stacked in sequence on the spin-coated hard mask layer. The silicon-containing anti-reflection layer has a plurality of first trenches arranged at intervals and extending in the second direction.

[0081] Referring to Figure 12 , the intermediate layer 300 can be formed on the spin-coated hard mask layer 200 through a deposition process and cover the spin-coated hard mask layer 200. The silicon-containing anti-reflection layer 400 (SiARC) is formed on the intermediate layer 300 through a deposition process and covers the intermediate layer 300. Of course, the silicon-containing anti-reflection layer 400 can also be formed on the intermediate layer 300 through a spin-coating process. Among them, the material of the intermediate layer 300 can be amorphous carbon (Amorphous Carbon Layer, abbreviated as ACL). The silicon-containing anti-reflection layer 400 has a higher hardness and is not easily collapsed and deformed when etching the first trenches 410 or other structures of the silicon-containing anti-reflection layer 400, and the pattern accuracy formed after etching is also better.

[0082] As Figure 12 shown, a plurality of first trenches 410 are formed in the silicon-containing anti-reflection layer 400 and are arranged at intervals and extend in the second direction. The first trenches 410 can penetrate the silicon-containing anti-reflection layer 400 or not penetrate the silicon-containing anti-reflection layer 400. As Figure 12 shown, the bottom of the first trench 410 is located in the silicon-containing anti-reflection layer 400, that is, the first trench 410 is formed in the upper part of the silicon-containing anti-reflection layer 400 away from the substrate 100, and a first etching groove is formed in the lower part of the silicon-containing anti-reflection layer 400 by using the first trench 410 subsequently. The width of the first etching groove is smaller than the width of the first trench 410, and the density of the first etching groove is greater than the density of the first trench 410, so as to further reduce the feature size of the semiconductor structure and improve the integration degree of the semiconductor structure.

[0083] Step S1022: Form a second sacrificial layer on the side walls of the first trenches. The second sacrificial layer located in the first trenches encloses a third trench.

[0084] Specifically, referring to Figure 12 and 13, a second sacrificial layer 420 is deposited on the sidewalls and the bottom of the first trench 410 and on the silicon-containing anti-reflection layer 400. The second sacrificial layer 420 covers the surface of the silicon-containing anti-reflection layer 400 on the side facing away from the substrate 100, that is, the second sacrificial layer 420 is a whole layer, so as to facilitate the formation of the second sacrificial layer 420. The material of the second sacrificial layer 420 can be silicon oxide.

[0085] Step S1023: Form a first filling layer in the third trench.

[0086] Continue to refer to Figure 12 and Figure 13 , a first filling layer 430 is deposited in the third trench. The material of the first filling layer 430 can be a spin-on hard mask. In some possible examples, as Figure 13 shown, in the third trench and on the second sacrificial layer 420, a first filling layer 430 is deposited. The first filling layer 430 fills the third trench and covers the second sacrificial layer 420.

[0087] Refer to Figure 14 , and then part of the first filling layer 430 and part of the second sacrificial layer 420 are removed to expose the second sacrificial layer 420 on the sidewall of the first trench 410. Specifically, the second sacrificial layer 420 and the first filling layer 430 on the surface of the silicon-containing anti-reflection layer 400 facing away from the substrate 100 are removed to expose the surface of the silicon-containing anti-reflection layer 400 and the second sacrificial layer 420 on the sidewall of the first trench 410. For example, part of the first filling layer 430 and part of the second sacrificial layer 420 are removed by an etching process or a planarization process.

[0088] Step S1024: Remove the second sacrificial layer on the sidewall of the first trench to form a first etching groove.

[0089] Refer to Figure 15 , the second sacrificial layer 420 is etched to form a first etching groove 440. It can be understood that during the process of etching the second sacrificial layer 420, part of the silicon-containing anti-reflection layer 400 and the first filling layer 430 are also etched and removed. The bottom of the first etching groove 440 exposes the silicon-containing anti-reflection layer 400.

[0090] It should be noted that, continuing to refer to Figure 15 , the selectivity ratios of the silicon-containing anti-reflection layer 400 and the first filling layer 430 are different. After the etching is completed, there is a certain height difference between the silicon-containing anti-reflection layer 400 and the first filling layer 430. Exemplarily, the etching rate of the silicon-containing anti-reflection layer 400 is slower than the etching rate of the first filling layer 430. When the second sacrificial layer 420 is etched and removed, in the height direction, that is, in the direction perpendicular to the substrate 10, the height of the silicon-containing anti-reflection layer 400 etched and removed is less, and the height of the first filling layer 430 etched and removed is more. As Figure 15As shown, the surface of the remaining silicon-containing anti-reflection layer 400 facing away from the substrate 110 is higher than the surface of the remaining first filling layer 430 facing away from the substrate 110.

[0091] Step S1025: Etch along the first etching groove to the spin-on hard mask layer to form a first channel.

[0092] Reference Figure 16 and Figure 17 , etch the silicon-containing anti-reflection layer 400, the intermediate layer 300, and the spin-on hard mask layer 200 along the first etching groove 440 to form a first channel 210 in the spin-on hard mask layer 200. In the embodiment of the present application, the silicon-containing anti-reflection layer 400 is used as a transfer layer for the etching pattern to reduce the size of the first etching groove 440, and the extreme ultraviolet (EUV) lithography process is not used in this process, reducing the production cost.

[0093] In some possible embodiments, reference Figure 3 , Figure 4 , Figures 18 to 20 The step of forming a stacked intermediate layer and a silicon-containing anti-reflection layer on the spin-on hard mask layer, where the silicon-containing anti-reflection layer has a plurality of first grooves spaced apart and extending in the second direction includes:

[0094] Step a: Form a first mask layer, a second mask layer, and a photoresist layer stacked in sequence on the silicon-containing anti-reflection layer.

[0095] Reference Figure 3 and Figure 4 , deposit a first mask layer 500 on the silicon-containing anti-reflection layer 400, the first mask layer 500 covering the silicon-containing anti-reflection layer 400, deposit a second mask layer 600 on the first mask layer 500, the second mask layer 600 covering the first mask layer 500, and spin-on coating (Spin on Coating), spray coating (Spray Coating), or brush coating (Brush Coating) etc. on the first mask layer 500 to form a photoresist layer 700.

[0096] Exemplarily, as Figure 3 and Figure 4 shown, the first mask layer 500 includes a first base layer 510 disposed on the silicon-containing anti-reflection layer 400, and a first anti-reflection layer 520 disposed on the first base layer 510; the second mask layer 600 includes a second base layer 610 disposed on the first anti-reflection layer 520, and a second anti-reflection layer 620 disposed on the second base layer 610. That is, the silicon-containing anti-reflection layer 400, the first base layer 510, the first anti-reflection layer 520, the second base layer 610, the second anti-reflection layer 620, and the photoresist layer 700 are stacked in sequence in the direction away from the substrate 100.

[0097] Among them, continuing to refer to Figure 3 and Figure 4 , the photoresist layer 700 is a patterned photoresist (PR) layer, that is, the photoresist layer 700 is formed with a preset pattern through processes such as exposure and development. Part of the second anti-reflection layer 620 is exposed on the photoresist layer 700. The second anti-reflection layer 620 can absorb the light used for exposing the photoresist layer 700, thereby reducing or preventing the light from reflecting on the second anti-reflection layer 620, so as to improve the accuracy of the preset pattern of the photoresist layer 700. The material of the first base layer 510 is the same as that of the second base layer 610, and the materials of the first anti-reflection layer 520 and the second anti-reflection layer 620 are the same, so as to reduce the types of materials used in the manufacturing process of the semiconductor structure. Exemplarily, the materials of the first base layer 510 and the second base layer 610 can be a spin-on hard mask composition, and the materials of the first anti-reflection layer 520 and the second anti-reflection layer 620 can be silicon oxynitride.

[0098] Step b: Using the photoresist layer as a mask, etching the second mask layer, and forming a plurality of first intermediate grooves that are spaced apart and extend along the second direction in the second mask layer.

[0099] Refer to Figure 4 and Figure 18 , using the photoresist layer 700 as a mask, etching the second mask layer 600, removing the part of the second mask layer 600 that is not covered by the photoresist layer 700, and retaining the part of the second mask layer 600 that is covered by the photoresist layer 700. A plurality of first intermediate grooves 630 that are spaced apart and extend along the second direction are formed in the second mask layer 600, and the first intermediate grooves 630 penetrate through the second mask layer 600 to expose the first mask layer 500. With such a setting, the preset pattern in the photoresist layer 700 is transferred to the second mask layer 600, and the first intermediate grooves 630 are formed in the second mask layer 600.

[0100] Step c: Depositing a third sacrificial layer on the sidewalls and the bottom of the first intermediate grooves, and on the second mask layer, and the third sacrificial layer located in the first intermediate grooves encloses a second intermediate groove.

[0101] Refer to Figure 18 and Figure 19 , depositing a third sacrificial layer 640 on the sidewalls and the bottom of the first intermediate grooves 630, and on the second mask layer 600. For example, the third sacrificial layer 640 is formed by an atomic layer deposition process to form a third sacrificial layer 640 with better quality. The material of the third sacrificial layer 640 can be silicon oxide.

[0102] Step d: Removing the third sacrificial layer located on the top of the second mask layer and at the bottom of the second intermediate groove, and retaining the third sacrificial layer on the sidewalls of the first intermediate grooves.

[0103] Reference Figure 20 , the third sacrificial layer 640 located on the top of the second mask layer 600 and the bottom of the second intermediate groove 650 is removed by an etching process, and the third sacrificial layer 640 located on the sidewall of the first intermediate groove 630 is retained. After etching, the second mask layer 600 and the first mask layer 500 are exposed. That is, by deposition and back-etching, the third sacrificial layer 640 located on the sidewall of the first intermediate groove 630 is formed.

[0104] Step e: Using the retained third sacrificial layer as a mask, etch the second mask layer, the first mask layer, and the silicon-containing anti-reflection layer to form a first trench.

[0105] Reference Figure 20 and Figure 12 , etch and remove the second mask layer 600, the first mask layer 500, and the silicon-containing anti-reflection layer 400 located between the third sacrificial layers 640, and form a first trench 410 in the silicon-containing anti-reflection layer 400. After forming the first trench 410, remove other film layers on the silicon-containing anti-reflection layer 400 to expose the silicon-containing anti-reflection layer 400.

[0106] It should be noted that an intermediate layer and a silicon-containing anti-reflection layer are formed in a stacked manner on the spin-coated hard mask layer, and the silicon-containing anti-reflection layer having a plurality of first trenches arranged at intervals and extending in the second direction can also be formed by other methods. In some other possible examples, it includes the following steps:

[0107] Step a': Form a first mask layer, a second mask layer, and a photoresist layer in a stacked manner on the silicon-containing anti-reflection layer.

[0108] Step b': Using the photoresist layer as a mask, etch the second mask layer, and form a plurality of first intermediate grooves arranged at intervals and extending in the second direction in the second mask layer.

[0109] Step c': Deposit a third sacrificial layer on the sidewall and bottom of the first intermediate groove, and on the second mask layer. The third sacrificial layer located in the first intermediate groove encloses a second intermediate groove.

[0110] Step a', step b', and step c' in this example can respectively refer to step a, step b, and step c in the above example, and will not be elaborated here.

[0111] Step d': Form a second filling layer on the second intermediate groove and the third sacrificial layer.

[0112] The second filling layer is formed by a deposition process. The second filling layer fills the second intermediate groove and covers the third sacrificial layer. The material of the third filling layer can be a spin-coated hard mask composition.

[0113] Step e': Remove part of the second filling layer and part of the third sacrificial layer to expose the third sacrificial layer on the sidewall of the first intermediate layer.

[0114] Exemplarily, through a planarization process, remove part of the second filling layer and part of the third sacrificial layer on the surface of the second mask layer facing away from the substrate to expose this surface and the third sacrificial layer on the sidewall of the first intermediate layer.

[0115] Step f': Etch the third sacrificial layer, the first mask layer, and the silicon-containing anti-reflection layer to form a first trench.

[0116] Etch the third sacrificial layer, and the first mask layer and the silicon-containing anti-reflection layer below the third sacrificial layer to form a first trench in the silicon-containing anti-reflection layer. During the etching process, at least part of the film layer above the silicon-containing anti-reflection layer will also be removed. The remaining film layer can be removed separately through an etching process. After removing the remaining film layer, the silicon-containing anti-reflection layer is exposed.

[0117] It should be noted that in different examples where an intermediate layer and a silicon-containing anti-reflection layer are stacked on the spin-coated hard mask layer and the silicon-containing anti-reflection layer has a plurality of first trenches arranged at intervals and extending in the second direction, the patterns of the photoresist layer are different to ensure that the positions of the finally formed first trenches are the same.

[0118] In the embodiments of the present application, a first trench 410 is formed in the silicon-containing anti-reflection layer 400 through a Self-Aligned Double Patterning (SADP) process. The feature size of the formed first trench 410 is reduced and the density is increased. In addition, during the process of forming a first etching groove 440 in the silicon-containing anti-reflection layer 400 subsequently, the self-aligned double patterning process is performed again, so that the feature size of the first etching groove 440 is further reduced and the density is further increased, thereby further improving the integration degree of the subsequently formed semiconductor structure.

[0119] In a possible example of the present application, refer to Figures 12 to 14 , deposit a second sacrificial layer on the sidewall and bottom of the first trench and on the silicon-containing anti-reflection layer. Correspondingly, the step of forming a first filling layer in the third trench includes:

[0120] Refer to Figure 13 , deposit a first filling layer 430 in the third trench and on the second sacrificial layer 420. As shown in Figure 13 , the first filling layer 430 fills the third trench and covers the second sacrificial layer 420, that is, the surface of the first filling layer 430 facing away from the substrate 100 is higher than the surface of the second sacrificial layer 420 facing away from the substrate 100.

[0121] Refer to Figure 14, a part of the first filling layer 430 and a part of the second sacrificial layer 420 are removed to expose the second sacrificial layer 420 located on the sidewall of the first trench 410. As Figure 14 shown, a part of the first filling layer 430 and a part of the second sacrificial layer 420 are removed through a planarization process, and the silicon-containing antireflection layer 400 and the second sacrificial layer 420 are exposed.

[0122] In the embodiment of the present application, after forming the first channel, the step of forming the first sacrificial layer in the first channel includes: depositing the first sacrificial layer 220 in the first etching groove and in the first channel 210. Refer to Figure 21 . The first sacrificial layer 220 fills the first channel 210 and the first etching groove, and can also cover the intermediate layer 300 or the silicon-containing antireflection layer 400. It can be understood that during the process of etching the spin-on hard mask layer 200 to form the first channel 210, a part of the silicon-containing antireflection layer 400 will also be etched away. When the silicon-containing antireflection layer 400 is not completely removed, the first sacrificial layer 220 covers the silicon-containing antireflection layer 400. When the silicon-containing antireflection layer 400 is completely removed, the intermediate layer 300 is exposed, and the first sacrificial layer 220 covers the intermediate layer 300.

[0123] It should be noted that after the step of forming the first sacrificial layer in the first channel, it further includes: removing the intermediate layer, the first sacrificial layer and the silicon-containing antireflection layer located above the spin-on hard mask layer to expose the spin-on hard mask layer. Refer to Figure 22 . Through a planarization process, other film layers located above the spin-on hard mask layer 200 are removed to expose the spin-on hard mask layer 200, which is convenient for subsequent removal of the spin-on hard mask layer 200.

[0124] In some possible examples of the present application, after the step of removing the first sacrificial layer to expose the first channel and the filling hole of the first channel extends to the active region, it further includes: forming a conductive pillar in the filling hole, and the conductive pillar is electrically connected to the active region.

[0125] Refer to Figure 10 、 Figures 23 to 25 . The conductive pillar 250 is in contact with the active region 111 to achieve the electrical connection between the conductive pillar 250 and the active region 111. One conductive pillar 250 is disposed in each filling hole 212, and the conductive pillars 250 are not connected to each other. An active region 111 and a word line 113 are disposed in the substrate 110. The word line 113 is insulated from the active region 111 and is staggered from the conductive pillar 250. Exemplarily, the word line 113 passes through the middle region of the active region 111, and the conductive pillar 250 is electrically connected to the end region of the active region 111.

[0126] Specifically, refer to Figure 11 、 Figure 23 and Figure 24, a conductive column 250 is formed in the filling hole 212. The electrical connection between the conductive column 250 and the active region 111 may include:

[0127] Deposit a first conductive layer 251 in the first channel 210 and on the first support layer 240. The first conductive layer 251 fills the first channel 210 and covers the first support layer 240. The first conductive layer 251 is electrically connected to the active region 111. As Figure 11 and Figure 23 shown, the first conductive layer 251 fills the first channel 210 and covers the first support layer 240. The material of the first conductive layer 251 may be polysilicon.

[0128] After forming the first conductive layer 251, etch the first conductive layer 251, and retain the part of the first conductive layer 251 located in the filling hole 212. The retained first conductive layer 251 forms a plurality of conductive columns 250. As Figure 11 and Figure 24 shown, remove the first conductive layer 251 located above the bit line and the first conductive layer 251 located above the filling hole 212, and retain the first conductive layer 251 located at the bottom of the filling hole 212. The retained first conductive layer 251 is separated into a plurality of conductive layers by the first support layer 240 and the bit line. The conductive columns 250 are spaced apart from each other and are not connected to each other. Specifically, as Figure 24 shown, at least remove the first conductive layer 251 located above the second support layer 152 of the bit line to isolate the first conductive layer 251 into a plurality of conductive layers.

[0129] It should be noted that after the step of forming the conductive column 250 in the filling hole 212 and electrically connecting the conductive column 250 to the active region 111, the method further includes: depositing a protective layer 260 on the conductive column 250, and the protective layer 260 covers the conductive column 250. Referring to Figure 25 , deposit a protective layer 260 on the conductive column 250, and the protective layer 260 covers the surface of the conductive column 250 away from the substrate 100. The material of the protective layer 260 may be a nitride, such as silicon nitride. The thickness of the protective layer 260 is relatively thin. For example, the protective layer 260 can reduce or avoid the oxidation of the conductive column 250 due to exposure to air.

[0130] The embodiment of the present application further provides a semiconductor structure, which is obtained by the above-mentioned manufacturing method of the semiconductor structure. Therefore, it has at least the advantage of less loss of the bit line 150. For the specific effects, refer to the above description and will not be elaborated here.

[0131] In the present specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0132] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, comprising: forming a spin-on hard mask layer on a substrate, wherein a plurality of active regions are disposed at intervals within the substrate, a plurality of bit lines are disposed at intervals on the substrate and extend along a first direction, each of the bit lines is electrically connected to at least one of the active regions, and the spin-on hard mask layer fills between the bit lines and covers the bit lines; removing a part of the spin-on hard mask layer to form a plurality of first channels disposed at intervals and extending along a second direction; forming a first sacrificial layer in the first channels, and the first sacrificial layer fills the first channels; removing the spin-on hard mask layer between the first sacrificial layers to form second channels; forming a first support layer in the second channels, and the first support layer fills the second channels; removing the first sacrificial layer and extending the first channels between adjacent bit lines to the active regions.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the step of removing a part of the spin-on hard mask layer to form a plurality of first channels disposed at intervals and exposing the substrate includes: forming an intermediate layer and a silicon-containing anti-reflection layer stacked in sequence on the spin-on hard mask layer, and the silicon-containing anti-reflection layer has a plurality of first grooves disposed at intervals and extending along the second direction; forming a second sacrificial layer on sidewalls of the first grooves, and the second sacrificial layer located in the first grooves encloses a third groove; forming a first filling layer in the third groove; removing the second sacrificial layer on sidewalls of the first grooves to form first etching grooves; etching along the first etching grooves to the spin-on hard mask layer to form the first channels.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, the bottom of the first grooves is located in the silicon-containing anti-reflection layer.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, the step of forming an intermediate layer and a silicon-containing anti-reflection layer stacked on the spin-on hard mask layer, and the silicon-containing anti-reflection layer has a plurality of first grooves disposed at intervals and extending along the second direction includes: forming a first mask layer, a second mask layer and a photoresist layer stacked in sequence on the silicon-containing anti-reflection layer; using the photoresist layer as a mask to etch the second mask layer, and a plurality of first intermediate grooves disposed at intervals and extending along the second direction are formed in the second mask layer; depositing a third sacrificial layer on sidewalls and the bottom of the first intermediate grooves and on the second mask layer, and the third sacrificial layer located in the first intermediate grooves encloses a second intermediate groove; removing the third sacrificial layer on the top of the second mask layer and at the bottom of the second intermediate groove, and retaining the third sacrificial layer on sidewalls of the first intermediate grooves; using the retained third sacrificial layer as a mask to etch the second mask layer, the first mask layer and the silicon-containing anti-reflection layer to form the first grooves.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The first mask layer includes a first base layer disposed on the silicon-containing anti-reflection layer and a first anti-reflection layer disposed on the first base layer; The second mask layer includes a second base layer disposed on the first anti-reflection layer and a second anti-reflection layer disposed on the second base layer; The material of the first base layer is the same as that of the second base layer, and the materials of the first anti-reflection layer and the second anti-reflection layer are the same.

6. The method for manufacturing a semiconductor structure according to claim 2, wherein, The step of forming a second sacrificial layer on the sidewall of the first trench, and the second sacrificial layer located in the first trench enclosing a third trench includes: Depositing a second sacrificial layer on the sidewall and the bottom of the first trench, and on the silicon-containing anti-reflection layer.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, The step of forming a first filling layer in the third trench includes: Depositing the first filling layer in the third trench and on the second sacrificial layer; Removing a part of the first filling layer and a part of the second sacrificial layer to expose the second sacrificial layer on the sidewall of the first trench.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, The step of forming a first sacrificial layer in the first channel includes: Depositing the first sacrificial layer in the first etching groove and in the first channel.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein, After the step of forming the first sacrificial layer in the first channel, it further includes: Removing the intermediate layer, the first sacrificial layer, and the silicon-containing anti-reflection layer above the spin-on hard mask layer to expose the spin-on hard mask layer.

10. The method for manufacturing a semiconductor structure according to any one of claims 1-9, wherein, The substrate includes a substrate, an insulating layer disposed on the substrate, and a barrier layer disposed on the insulating layer. The active region is disposed in the substrate, and the insulating layer covers the active region; The step of removing the first sacrificial layer and extending the first channel between adjacent bit lines to the active region includes: Etching the first sacrificial layer to expose the first channel. Each first channel includes a second trench located above the bit line and extending in a second direction, and a filling hole located between adjacent bit lines and communicating with the second trench; Etching the insulating layer along the filling hole of the first channel to expose the active region through the filling hole.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein, After the step of removing the first sacrificial layer to expose the first channel and the filling hole of the first channel extending to the active region, it further includes: Forming a conductive pillar in the filling hole, and the conductive pillar is electrically connected to the active region.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein, The step of forming a conductive pillar in the filling hole, and the conductive pillar is electrically connected to the active region includes: Deposit a first conductive layer in the first channel and on the first support layer, where the first conductive layer fills the first channel and covers the first support layer, and the first conductive layer is electrically connected to the active region; Etch the first conductive layer, leaving a portion of the first conductive layer within the filling holes, and the remaining first conductive layer forms a plurality of conductive pillars.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein, A plurality of word lines spaced apart and extending in a second direction are further provided in the substrate, the word lines are insulated from the active region and are offset from the conductive pillars.

14. The method for manufacturing a semiconductor structure according to claim 11, wherein, After the step of forming a conductive pillar in the filling hole, where the conductive pillar is electrically connected to the active region, the method further includes: Deposit a protective layer on the conductive pillar, where the protective layer covers the conductive pillar.

15. The method for manufacturing a semiconductor structure according to any one of claims 1-9, wherein, The bit line includes a second conductive layer and a second support layer covering the second conductive layer. An oxide layer is further provided in the second support layer beside the second conductive layer, and the second support layer is made of the same material as the first support layer; The selectivity ratio of the spin-on hard mask layer to the second support layer is greater than or equal to 5.

16. A semiconductor structure, wherein, The semiconductor structure is obtained by the method for manufacturing a semiconductor structure according to any one of claims 1-15.

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