Method of forming a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure forming method and a semiconductor structure. The semiconductor structure forming method comprises: providing a substrate, the substrate comprising an active array, the active array comprising a plurality of rows of active regions arranged in staggered intervals, each active region comprising a first end, a second end and a middle part, and the first ends and the second ends of the active regions in the same row are arranged alternately along a first direction; and performing a first etching on the middle part of the active region to form a contact hole in the middle part of the active region. In the present disclosure, the first etching is performed on the middle part of the active region to form the contact hole, thereby avoiding damage to the two ends of the active region caused by etching, ensuring the structural integrity of the two ends of the active region, and improving the yield of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a forming method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the increase of the integration of integrated circuits, the size of semiconductor devices is getting smaller and smaller, and the structure size of dynamic random access memory (DRAM) is further reduced, and the structure layout is more compact, which causes many structures of dynamic random access memory to be unable to be directly formed, and multiple masks need to be used to form, resulting in the increase of production cost. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the protection scope of the claims.

[0004] The present disclosure provides a forming method of a semiconductor structure and the semiconductor structure.

[0005] A first aspect of the present disclosure provides a forming method of a semiconductor structure, the forming method comprising:

[0006] providing a substrate, the substrate comprising an active array, the active array comprising a plurality of rows of active regions arranged in an interlaced manner, each of the active regions comprising a first end, a second end and a middle part, the first ends and the second ends of the active regions in the same row being arranged alternately along a first direction;

[0007] performing a first etching on the middle parts of the active regions to form contact holes in the middle parts of the active regions.

[0008] According to some embodiments of the present disclosure, the performing a first etching on the middle parts of the active regions comprises:

[0009] forming a first mask layer above the substrate, a projection of the first mask layer on the substrate covering the first ends or the second ends of the active regions in two adjacent rows, and exposing the middle parts of the active regions; and performing a first etching on the middle parts of the active regions according to the first mask layer.

[0010] According to some embodiments of the present disclosure, a hard mask layer is formed above the substrate, and a first mask layer is formed above the hard mask layer.

[0011] According to some embodiments of the present disclosure, the forming a first mask layer above the hard mask layer comprises:

[0012] forming a first sub-mask above the hard mask layer, forming a second sub-mask on sidewalls of the first sub-mask, the second sub-mask extending along a second direction, a projection of the second sub-mask on the substrate covering the middle part of the active region;

[0013] etching part of the hard mask layer according to the second sub-mask, forming a third sub-mask; filling a fourth sub-mask in the middle of the third sub-mask, removing the third sub-mask, forming a first mask layer.

[0014] According to some embodiments of the present disclosure, the first direction and the second direction intersect at a first included angle, and the first included angle is an obtuse angle.

[0015] According to some embodiments of the present disclosure, the etching the middle part of the active region according to the first mask layer for the first time comprises:

[0016] According to some embodiments of the present disclosure, the etching the middle part of the active region according to the first mask layer for the first time comprises:

[0017] According to some embodiments of the present disclosure, in the first etching, an etching rate of the hard mask layer is less than an etching rate of the middle part of the active region.

[0018] According to some embodiments of the present disclosure, a width of a top of the contact hole is greater than or equal to a width of a bottom of the contact hole.

[0019] According to some embodiments of the present disclosure, in a cross section along the second direction, both sides of the contact hole are isolation structures.

[0020] According to some embodiments of the present disclosure, after forming the contact hole in the middle part of the active region, the method further comprises:

[0021] depositing a first material layer in the contact hole to form a contact structure.

[0022] According to some embodiments of the present disclosure, before forming the hard mask layer above the substrate, the method comprises:

[0023] forming a gate pattern above the substrate, the gate pattern extending along a fourth direction parallel to a top surface of the substrate, the gate pattern being spaced apart along a fifth direction, the fourth direction being perpendicular to the fifth direction;

[0024] forming a plurality of first trenches in the substrate by using the gate pattern as an etching mask;

[0025] forming a plurality of first gate electrodes in the plurality of first trenches.

[0026] According to some embodiments of the present disclosure, after forming the contact hole in the middle part of the active region, further comprising,

[0027] A plurality of bit line structures are formed, the bit line structures extend along a fifth direction, and each of the bit line structures is connected with a plurality of the contact structures.

[0028] According to some embodiments of the present disclosure, the interval between adjacent first mask layers is less than or equal to 1 / 3 of the length of the active region in the first direction.

[0029] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0030] A substrate comprising an active array, the active array comprising a plurality of rows of active regions arranged in an interleaved manner, each of the active regions comprising a first end, a second end and a middle part, the first ends and the second ends of the active regions in the same row being arranged alternately along a first direction;

[0031] A hard mask layer covering a top surface of the substrate;

[0032] A first mask layer covering part of the hard mask layer, the first mask layer comprising a plurality of first mask patterns parallel to each other, the first mask patterns extending in a second direction parallel to the top surface of the substrate and being arranged at a first interval in a third direction, the second direction being perpendicular to the third direction; a projection of the first mask layer on the substrate covers the first end or the second end of the active regions in two adjacent rows, exposing the middle part between the two end parts of the active regions.

[0033] According to some embodiments of the present disclosure, the first direction and the second direction are obliquely intersected at a first included angle, and the first included angle is an obtuse angle.

[0034] According to some embodiments of the present disclosure, the first interval is less than 1 / 3 of the length of the active region in the first direction.

[0035] According to some embodiments of the present disclosure, the semiconductor structure further comprises:

[0036] A plurality of first gate electrodes arranged in the substrate, the first gate electrodes extending along a fourth direction, and the first gate electrodes being arranged at equal intervals in a fifth direction perpendicular to the fourth direction, the fourth direction being obliquely intersected with the first direction;

[0037] The first end of the active region and the second end of the active region are respectively intersected with one of the first gate electrodes.

[0038] The forming method of the semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure form a contact hole by performing first etching on the middle part of the active region, avoid the two ends of the active region from being damaged by etching, ensure the structural integrity of the two ends of the active region, and improve the yield of the semiconductor structure.

[0039] Other aspects can become apparent from the following detailed description, when considered in conjunction with the accompanying drawings and the detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings, like reference numerals are used to represent similar elements. The accompanying drawings are of some embodiments of the present disclosure, but not all embodiments. Other drawings can be derived from these drawings by one skilled in the art without paying creative labor.

[0041] Figure 1 is a flow chart of a forming method of a semiconductor structure according to an example embodiment.

[0042] Figure 2 is a flow chart of a forming method of a semiconductor structure according to an example embodiment.

[0043] Figure 3 is a flow chart of a forming method of a semiconductor structure according to an example embodiment.

[0044] Figure 4 is a flow chart of a forming method of a semiconductor structure according to an example embodiment.

[0045] Figure 5 is a projection view of a substrate provided by a forming method of a semiconductor structure according to an example embodiment.

[0046] Figure 6 is a cross-sectional view of a substrate in A-A section provided by a forming method of a semiconductor structure according to an example embodiment.

[0047] Figure 7 is a cross-sectional view of forming a gate mask layer on the top surface of a substrate in A-A section in a forming method of a semiconductor structure according to an example embodiment.

[0048] Figure 8 is a cross-sectional view of forming a first gate electrode in a substrate in A-A section in a forming method of a semiconductor structure according to an example embodiment.

[0049] Figure 9A projection view of a first gate electrode formed in a method of forming a semiconductor structure according to an example embodiment formed on a substrate.

[0050] Figure 10 A cross-sectional view of a hard mask layer formed in a method of forming a semiconductor structure according to an example embodiment at A-A section.

[0051] Figure 11 A cross-sectional view of a first sub-mask formed in a method of forming a semiconductor structure according to an example embodiment at A-A section.

[0052] Figure 12 A projection view of a first sub-mask formed in a method of forming a semiconductor structure according to an example embodiment formed on a substrate.

[0053] Figure 13 A cross-sectional view of a second sub-mask layer formed in a method of forming a semiconductor structure according to an example embodiment at A-A section.

[0054] Figure 14 A cross-sectional view of a second sub-mask formed in a method of forming a semiconductor structure according to an example embodiment at A-A section.

[0055] Figure 15 A projection view of a first sub-mask, a second sub-mask formed in a method of forming a semiconductor structure according to an example embodiment formed on a substrate.

[0056] Figure 16 A cross-sectional view of a first sub-mask removed in a method of forming a semiconductor structure according to an example embodiment at A-A section.

[0057] Figure 17 A projection view of a second sub-mask formed in a method of forming a semiconductor structure according to an example embodiment formed on a substrate.

[0058] Figure 18 A cross-sectional view of a part of a hard mask layer removed according to a second sub-mask in a method of forming a semiconductor structure according to an example embodiment at A-A section.

[0059] Figure 19 A cross-sectional view of a third sub-mask formed in a method of forming a semiconductor structure according to an example embodiment at A-A section.

[0060] Figure 20 A cross-sectional view of a fourth sub-mask filled between third sub-masks in a method of forming a semiconductor structure according to an example embodiment at A-A section.

[0061] Figure 21 is a cross-sectional view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a first mask layer formed on a substrate.

[0062] Figure 22 is a projection view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a first mask layer formed on a substrate.

[0063] Figure 23 is a cross-sectional view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a contact hole formed by a first etching at an A-A cross-section.

[0064] Figure 24 is a projection view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a first mask layer formed on a substrate after a contact hole is formed.

[0065] Figure 25 is a cross-sectional view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a first material layer formed at an A-A cross-section.

[0066] Figure 26 is a cross-sectional view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a first contact layer formed by etching back a first material layer at an A-A cross-section.

[0067] Figure 27 is a cross-sectional view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a contact junction formed at an A-A cross-section.

[0068] Figure 28 is a cross-sectional view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a bit line structure formed at an A-A cross-section.

[0069] Figure 29 is a projection view of a semiconductor structure in a method of forming a semiconductor structure according to an example embodiment, showing a first gate electrode and a bit line structure formed on a substrate.

[0070] Reference numerals:

[0071] 100, substrate; 01, active array; 110, active region; 111, first end of active region; 112, second end of active region; 113, middle portion of active region; 114, contact hole; 120, isolation structure; 130, first trench; 150, isolation layer;

[0072] 200, hard mask layer; 210, first hard mask; 220, second hard mask;

[0073] 300, first mask layer; 300a, first mask pattern; 310, first sub-mask; 311, first pattern; 320, second sub-mask; 330, third sub-mask; 340, second sub-mask layer; 350, photoresist layer; 360, fourth sub-mask;

[0074] 400, contact structure; 410, first contact layer; 411, first material layer; 412, void filling; 420, second contact layer;

[0075] 500, first gate electrode; 510, gate barrier layer; 520, gate conductive layer; 530, gate insulating layer;

[0076] 600, gate mask layer; 600a, gate pattern;

[0077] 700, bit line structure; 710, bit line barrier layer; 720, bit line conductive layer; 730, bit line insulating layer;

[0078] D1, first direction; D2, second direction; D3, third direction; D4, fourth direction; D5, fifth direction;

[0079] L1, first interval; L2, second interval;

[0080] α, first included angle. DETAILED DESCRIPTION

[0081] So that the objectives, technical solutions and advantages of the embodiments of the present disclosure are more apparent, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present disclosure. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other at will.

[0082] An example embodiment of the present disclosure provides a semiconductor structure forming method, as shown in Figure 1 Figure 1 An example embodiment of the present disclosure provides a semiconductor structure forming method, as shown in Figures 4-22 An example embodiment of the present disclosure provides a semiconductor structure forming method, as shown in Figures 4-22 An example embodiment of the present disclosure provides a semiconductor structure forming method, as shown in An example embodiment of the present disclosure provides a semiconductor structure forming method, as shown in

[0083] The semiconductor structure is not limited in the embodiment, and the semiconductor structure is taken as a dynamic random access memory (DRAM) as an example for description below, but the embodiment is not limited thereto, and the semiconductor structure in the embodiment can also be other structures.

[0084] As shown in Figure 1 , the embodiment of the disclosure provides a forming method of a semiconductor structure, including the following steps:

[0085] Step S110: providing a substrate, the substrate including an active array, the active array including a plurality of rows of active regions arranged in an interlaced manner, each active region including a first end, a second end and a middle part, the first ends and the second ends of the active regions in the same row being arranged alternately along a first direction.

[0086] As shown in Figure 5 , Figure 6 , the substrate 100 includes an active array 01 and an isolation structure 120, the isolation structure 120 can be formed by a shallow trench process, and the isolation structure 120 is arranged between the active arrays 01 for separating the active arrays 01. Figure 6 As shown in Figure 5 , a cross-sectional view of the substrate 100 provided in A-A is shown, as shown in Figure 6 , the substrate 100 in A-A has the active regions 110 and the isolation structures 120 arranged alternately.

[0087] As shown in Figure 5 , Figure 6 , the active array 01 includes a plurality of arrayed active regions 110, and the active regions 110 extend along a first direction D1. The active region 110 includes a first end 111, a second end 112 and a middle part 113, and the first ends 111 and the second ends 112 of the active regions 110 in the same row are arranged alternately along the first direction D1. The active region 110 includes a semiconductor material. The semiconductor material can include one or more of silicon, germanium, silicon germanium compound and silicon carbon compound. The material of the isolation structure 120 can be a low-k dielectric material, for example, the material of the isolation structure 120 can be silicon dioxide.

[0088] Step S120: performing first etching on the middle part of the active region to form a contact hole in the middle part of the active region.

[0089] As shown in Figure 23 , the width of the top of the contact hole 114 is greater than or equal to the width of the bottom of the contact hole 114.

[0090] In the embodiment, the first etching is performed on the middle part of the active region to form the contact hole, so as to avoid the two ends of the active region from being damaged by etching, ensure the structural integrity of the two ends of the active region, and improve the yield of the semiconductor structure.

[0091] AsFigure 2 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0092] Step S210: Provide a substrate, the substrate including an active array, the active array including multiple rows of staggered active regions, each active region including a first end, a second end and a middle part, the first end and the second end of the active regions in the same row are alternately arranged along a first direction.

[0093] The implementation method of step S210 in this embodiment is the same as that of step S110 in the above embodiment, and will not be described again here.

[0094] Step S220: A hard mask layer is formed over the substrate, and a first mask layer is formed over the hard mask layer.

[0095] Figure 10 The hard mask layer 200 formed above the substrate is shown in section AA (reference). Figure 5 A cross-sectional view, such as Figure 10 As shown, a hard mask layer 200 can be formed by depositing a hard mask material using chemical vapor deposition (CVD) or physical vapor deposition (PVD). The hard mask layer 200 covers the top surface of the active array 01 and the isolation structure 120. The material of the hard mask layer 200 can include nitrides, oxides of nitride, or oxides; for example, the material of the hard mask layer 200 can be silicon nitride. The hard mask layer 200 can include a single-layer or multi-layer structure.

[0096] Figure 21 The first mask layer formed is shown in section AA (reference). Figure 22 ) cross-sectional view, Figure 22 The projection of the first mask layer formed on the substrate is shown. (See diagram.) Figure 21 , Figure 22 As shown, a first mask layer 300 is formed, which covers a portion of the top surface of the hard mask layer 200. The first mask layer 300 includes multiple first mask patterns 300a, which are arranged along the second direction D2.

[0097] In some embodiments, the first direction D1 and the second direction D2 intersect obliquely at a first included angle α, where the first included angle α is an obtuse angle. Multiple first mask patterns 300a are arranged parallel to each other at equal intervals with a first interval L1 on a third direction D3 perpendicular to the second direction D2.

[0098] In some embodiments, the first interval L1 is less than 1 / 3 of the length of the active region 110 in the first direction D1.

[0099] Step S230: Perform the first etching on the middle part of the active region to form a contact hole in the middle part of the active region.

[0100] like Figure 23 , Figure 24 As shown, refer to Figure 21 , Figure 22 Using the first mask layer 300 as a mask, the hard mask layer 200 exposed by the first mask layer 300 is removed by dry etching or wet etching. The remaining hard mask layer 200 exposes the middle portion 113 of the active region 110 and part of the top surface of the isolation structure 120. Using the remaining hard mask layer 200 as a mask, the exposed middle portion 113 of the active region 110 and the isolation structure 120 are etched, removing part of the middle portion 113 of the active region 110, forming a contact hole 114 in the middle portion 113 of the active region 100. In the first etching, the etching rate of the hard mask layer 200 is less than the etching rate of the middle portion 113 of the active region 110.

[0101] like Figure 23 As shown, the width of the top of the contact hole 114 is greater than or equal to the width of the bottom of the contact hole 114. In this embodiment, the etching process has a high etching selectivity for the active region 110 and the isolation structure 120, that is, the etching speed of the active region 110 is greater than the etching speed of the isolation structure 120. The contact hole 114 is formed in the middle part 113 of the active region 110, and the bottom surface of the contact hole 114 is lower than the top surface of the isolation structure 120. In the second direction D2 section, the isolation structure 120 is on both sides of the contact hole 114.

[0102] In this embodiment, the middle part of the active region is exposed by patterning the hard mask layer through the first mask layer. The two ends of the active region are covered by the hard mask layer, which avoids the two ends of the active region being etched and damaged during the process of forming contact holes. This ensures the structural integrity of the two ends of the active region and improves the yield of the semiconductor structure.

[0103] like Figure 3 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0104] Step S310: Provide a substrate, the substrate including an active array, the active array including multiple rows of staggered active regions, each active region including a first end, a second end and a middle part, the first end and the second end of the active regions in the same row are alternately arranged along a first direction.

[0105] The implementation method of step S310 in this embodiment is the same as that of step S110 in the above embodiment, and will not be repeated here.

[0106] Step S320: Form a hard mask layer over the substrate.

[0107] As shown in Figure 7 , with reference to Figure 6 , the hard mask layer 200 is a laminated structure, and the hard mask layer 200 includes a first hard mask 210 and a second hard mask 220 arranged in sequence on the top surface of the substrate 110.

[0108] Step S330: Form a first sub-mask above the hard mask layer, and form a second sub-mask on the sidewall of the first sub-mask, the second sub-mask extending along a second direction, and the projection of the second sub-mask on the substrate covering the middle part of the active region.

[0109] Form a first sub-mask 310 above the hard mask layer 200, including: as shown in Figure 10 , coat a photoresist on the top surface of the hard mask layer 200 to form a photoresist layer 350, use a light-shielding mask to block the photoresist layer 350, and expose and develop the photoresist layer 350 to transfer the mask pattern of the light-shielding mask to the photoresist layer 350. As shown in Figure 11 , with reference to Figure 10 , remove the un-developed photoresist layer 350 to form the first sub-mask 310, and the first sub-mask 310 covers part of the top surface of the hard mask layer 200. As shown in Figure 11 Figure 12 , the first sub-mask 310 includes a plurality of first patterns 311, the plurality of first patterns 311 extend along a second direction D2, and the plurality of first patterns 311 are arranged at a second interval L2 in a third direction D3, the third direction D3 is perpendicular to the second direction D2, and the second interval L2 is greater than the first interval L1.

[0110] Form a second sub-mask 320 on the sidewall of the first sub-mask 310, including: as shown in Figure 13 , with reference to Figure 11 , the second sub-mask material can be deposited by an atomic layer deposition process, and the second sub-mask material covers the top surface of the first sub-mask 310 and the hard mask layer 200 exposed to form a second sub-mask layer 340. By forming the second sub-mask 200 through the atomic layer deposition process, the thickness of the second sub-mask 200 can be controlled to be smaller, and the thickness of the second sub-mask 200 is the size of the opening formed on the first mask layer 300 subsequently, and the smaller the thickness of the second sub-mask 200, the smaller the size of the opening formed on the first mask layer 300.

[0111] As shown in Figure 14 , with reference to Figure 13 , then etch the second sub-mask layer 340 by an anisotropic etching process, the etching speed of the anisotropic etching process in the vertical direction is greater than that in the horizontal direction, and the second sub-mask layer 340 covering the hard mask layer 200 and the second sub-mask layer 340 covering the first sub-mask 310 are removed, and the remaining second sub-mask layer 340 forms the second sub-mask 320. As shown inFigure 14 、 Figure 13 As shown in FIG. 3B, the second sub-mask 320 covers the sidewall of the first sub-mask 310 to reduce the second interval L2 between the adjacent first patterns 311 to the first interval L1, and the projection of the second sub-mask 320 on the substrate 100 covers the middle part 113 of the active region 110. The material of the second sub-mask 320 and the material of the hard mask layer 200 and the material of the first sub-mask 310 have etching selectivity, and the hard mask layer 200 and the first sub-mask 310 will not be etched and removed when etching the second sub-mask layer 340.

[0112] Step S340: etching part of the hard mask layer according to the second sub-mask to form a third sub-mask; filling a fourth sub-mask in the middle of the third sub-mask, removing the third sub-mask to form a first mask layer.

[0113] As shown in FIG. 3C, referring to FIG. 3B, the first sub-mask 310 is removed, and the second sub-mask 320 is used as a mask to etch the hard mask layer 200. As shown in FIG. 3D, referring to FIG. 3C, the second hard mask 220 exposed by removing the second sub-mask 200 is removed, and the pattern of the second sub-mask 320 is transferred to the second hard mask 220. The remaining second hard mask 200 forms a third sub-mask 330, and the projection of the third sub-mask 330 on the substrate 100 covers the middle part 113 of the active region 110. Figure 16 、 Figure 17 As shown in FIG. 3D, referring to FIG. 3C, the second hard mask 220 exposed by removing the second sub-mask 200 is removed, and the pattern of the second sub-mask 320 is transferred to the second hard mask 220. The remaining second hard mask 200 forms a third sub-mask 330, and the projection of the third sub-mask 330 on the substrate 100 covers the middle part 113 of the active region 110. Figure 14 、 Figure 18 As shown in FIG. 3E, referring to FIG. 3D, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed between the third sub-masks 330. As shown in FIG. 3F, referring to FIG. 3E, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed relative to the first hard mask 210. The projection of the first mask layer 300 on the substrate 100 exposes the middle part 113 of the active region 110. Figure 16 、 Figure 19 As shown in FIG. 3E, referring to FIG. 3D, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed between the third sub-masks 330. As shown in FIG. 3F, referring to FIG. 3E, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed relative to the first hard mask 210. The projection of the first mask layer 300 on the substrate 100 exposes the middle part 113 of the active region 110.

[0114] As shown in FIG. 3E, referring to FIG. 3D, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed between the third sub-masks 330. As shown in FIG. 3F, referring to FIG. 3E, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed relative to the first hard mask 210. The projection of the first mask layer 300 on the substrate 100 exposes the middle part 113 of the active region 110. Figure 20 、 Figure 19 As shown in FIG. 3E, referring to FIG. 3D, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed between the third sub-masks 330. As shown in FIG. 3F, referring to FIG. 3E, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed relative to the first hard mask 210. The projection of the first mask layer 300 on the substrate 100 exposes the middle part 113 of the active region 110. Figure 21 、 Figure 20 As shown in FIG. 3E, referring to FIG. 3D, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed between the third sub-masks 330. As shown in FIG. 3F, referring to FIG. 3E, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed relative to the first hard mask 210. The projection of the first mask layer 300 on the substrate 100 exposes the middle part 113 of the active region 110. Figure 21 、 Figure 22 As shown in FIG. 3E, referring to FIG. 3D, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed between the third sub-masks 330. As shown in FIG. 3F, referring to FIG. 3E, the third sub-mask 330 is removed by dry etching or wet etching, and the fourth sub-mask 360 is formed relative to the first hard mask 210. The projection of the first mask layer 300 on the substrate 100 exposes the middle part 113 of the active region 110.

[0115] Step S350: etching the middle part of the active region for the first time to form a contact hole in the middle part of the active region.

[0116] The implementation manner of step S350 of the embodiment is the same as the implementation manner of step S230 in the above embodiment, and details are not repeated here.

[0117] Step S360: depositing a first material layer in the contact hole to form a contact structure.

[0118] The first material can be deposited by atomic layer deposition (ALD) or chemical vapor deposition, and the first material fills the contact hole 114 to form the contact structure 400.

[0119] In some embodiments, depositing the first material layer 114 to form the contact structure 400 includes: as shown in FIG. 4A, referring to FIG. 3, depositing the first material to fill the contact hole 114, and the first material is affected by the edge effect during the deposition process, and a filling gap 412 is formed in the first material. Figure 25 As shown in FIG. 4B, referring to FIG. 3, etching back part of the first material to expose the filling gap and etch the filling gap to form a U-shaped or V-shaped groove in the first material, and the remaining first material forms a first contact layer 410. Figure 23 As shown in FIG. 4C, then depositing the first material again to fill the U-shaped or V-shaped groove to form a second contact layer 420, and the first contact layer 410 and the second contact layer 420 form the first material layer 114, and the first material layer 114 forms the contact structure 400. The contact structure 400 formed in this embodiment has no filling gap, and the electrical performance of the contact structure is better. In some embodiments, the first material can be doped polysilicon or conductive metal. Figure 26 Figure 27 In this embodiment, in the process of forming the contact hole, only one light irradiation is performed in the process of forming the first sub-mask, the light irradiation cost is saved, and the process of forming the contact hole is reduced. Moreover, in the process of forming the contact structure, after the first material is deposited to fill the contact hole, part of the first material is etched back to form a U-shaped or V-shaped groove in the contact hole, and the first material is deposited again to fill the U-shaped or V-shaped groove to form the first material layer, so that the first material layer formed has no filling gap.

[0120] As shown in FIG. 4D, the first material layer 114 formed in this embodiment has no filling gap, and the electrical performance of the contact structure 400 is better.

[0121] As shown in FIG. 5, an example embodiment of the present disclosure provides a method for forming a semiconductor structure, including the following steps: Figure 4 Step S410: providing a substrate, the substrate including an active array, and the active array including a plurality of rows of active regions arranged in staggered intervals, and each active region including a first end, a second end, and an intermediate portion, and the first ends and the second ends of the active regions in the same row are arranged alternately along a first direction.

[0122] The implementation of step S410 in this embodiment is the same as the implementation of step S310 in the above-mentioned embodiments, and will not be described here.

[0123] Step S420: forming a first gate in the substrate.

[0124]

[0125] ​​In the present embodiment, forming the first gate electrode 500 includes:

[0126] Step S421: forming a gate pattern above the substrate, the gate pattern extending in a fourth direction parallel to the top surface of the substrate, the gate pattern being spaced apart in a fifth direction, the fourth direction being perpendicular to the fifth direction.

[0127] Forming the gate pattern 600a above the substrate 100 includes: as shown in Figure 7 forming a gate mask layer 600, the gate mask layer 600 including a plurality of gate patterns 600a extending along a fourth direction D4 (refer to Figure 9 ), the fourth direction D4 intersecting the first direction D1, in some embodiments, the fourth direction D4 being different from the second direction D2. The gate pattern 600a is a strip pattern extending in the fourth direction, the gate pattern 600a exposing the partial first end 111 and the partial second end 112 of the active region 110, the gate patterns 600a being equally spaced apart in a fifth direction D5 perpendicular to the fourth direction D4, the distance between adjacent gate patterns 600a being greater than the first interval L1.

[0128] Step S422: forming a plurality of first trenches in the substrate by using the gate pattern as an etching mask.

[0129] As shown in Figure 8 , referring to Figure 7 , removing the partial substrate 110 exposed by the gate pattern 600a, exposing the partial active region 110 and the partial isolation structure 120, forming a plurality of first trenches 130 intersecting the active region 110 in the substrate 100, the first end 111 and the second end 112 of each active region 110 respectively intersecting a first trench 130.

[0130] Step S423: forming a plurality of first gate electrodes in the plurality of first trenches.

[0131] Forming the first gate electrode 500 includes: as shown in Figure 8 , referring to Figure 7 , depositing silicon oxide in the first trench 130 to form a gate oxide layer, and then sequentially forming a gate blocking layer 510, a gate conductive layer 520, and a gate insulating layer 530 in the first trench 130 covering the gate oxide layer. In the present embodiment, the gate blocking layer 510 includes silicon nitride, the gate conductive layer 520 includes tungsten or a tungsten compound, and the gate insulating layer 530 includes silicon oxide. The gate blocking layer 510, the gate conductive layer 520, and the gate insulating layer 530 form the first gate electrode 500, the first gate electrode 500 being separated from the active region 110 and the isolation structure by the gate oxide layer.

[0132] Referring to Figure 9Each active region 110 intersects with two first gate electrodes 500, one of which passes through the first end 111 of the active region 110 and the other passes through the second end 112 of the active region 110.

[0133] In this embodiment, refer to Figure 8 After forming the first gate electrode 500, the method further includes the step of depositing an insulating material to cover the substrate 100 and the top surface of the first gate electrode 500 to form an isolation layer 150. The isolation layer 150 is used to isolate the active region 110 from contact with air to prevent oxidation of the semiconductor material in the active region 110. The material of the isolation layer 150 can be silicon nitride or silicon oxynitride.

[0134] Step S430: A hard mask layer is formed over the substrate, and a first mask layer is formed over the hard mask layer.

[0135] like Figure 21 , Figure 22 As shown, the first mask layer 300 includes multiple parallel first mask patterns 300a. The first mask patterns 300a extend in a second direction D2 parallel to the top surface of the substrate 100 and are arranged at a first interval L1 in a third direction D3. The second direction D2 is perpendicular to the third direction D3. The projection of the first mask layer 300 on the substrate 100 covers the first end 111 or the second end 112 of two adjacent rows of active regions 110, exposing the middle portion 113 between the two ends of the active regions 110.

[0136] The implementation of step S430 in this embodiment is the same as that of steps S330-S340 in the above embodiment. In this embodiment, the hard mask layer 200 covers the top surface of the isolation layer 150.

[0137] Step S440: Perform the first etching on the middle part of the active region to form a contact hole in the middle part of the active region.

[0138] The implementation of step S440 in this embodiment is the same as that of step S330 in the above embodiment. The difference is that after the first etching removes part of the hard mask layer 200, a portion of the isolation layer 150 is also etched to expose the middle portion 113 of the active region 110.

[0139] Step S450: Deposit a first material layer in the contact hole to form a contact structure.

[0140] The implementation of step S350 in this embodiment is the same as that of steps S250 and S260 in the above embodiments, and will not be repeated here.

[0141] Step S460: a plurality of bit line structures are formed, the bit line structures extend along a fifth direction, and each bit line structure is connected with the plurality of contact structures.

[0142] As shown in Figure 28 、 Figure 29 , referring to Figure 27 , forming the plurality of bit line structures 700 includes: forming a protection layer on the top surface of the substrate 100, forming bit line trenches in the protection layer, the bit line trenches extend along the fifth direction D5, the bit line trenches expose the middle part 113 of the active region 100 and the top surface of the contact structure 400, and the bit line trenches are equally spaced in the fourth direction D4. The bit line barrier layer 710, the bit line conductive layer 720 and the bit line insulating layer 730 are sequentially formed in the bit line trench, the bit line barrier layer 710, the bit line conductive layer 720 and the bit line insulating layer 730 together form the bit line structure 700, and the bit line structure 700 is equally spaced in the fourth direction D4. Remove the protection layer, and the plurality of bit line structures 700 are independently arranged on the top surface of the substrate 100, and each bit line structure 700 is connected with the plurality of contact structures 400.

[0143] The semiconductor structure formed in the embodiment, the first gate electrode is embedded in the substrate, which fully utilizes the application space of the semiconductor structure, improves the integration of the semiconductor structure, and the first gate electrode is embedded in the substrate to avoid or reduce the short channel effect of the first gate electrode and reduce the gate current leakage. At the same time, the semiconductor structure formed in the embodiment has complete structure of the first end and the second end of the active region, and can form a capacitor contact between adjacent bit line structures, further improving the integration density of the semiconductor structure.

[0144] In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, as shown in Figure 21 、 Figure 22 , referring to Figure 5 , the semiconductor structure comprises: a substrate 100, a hard mask layer 200 covering the top surface of the substrate 100, and a first mask layer 300 covering part of the hard mask layer 200. The substrate 100 includes an active array 01, the active array 01 includes a plurality of rows of active regions 110 arranged at staggered intervals, each active region 110 includes a first end 111, a second end 112 and a middle part 113, and the first ends 111 and the second ends 112 of the active regions 110 in the same row are alternately arranged along a first direction D1. The first mask layer 300 includes a plurality of first mask patterns 300a parallel to each other, the first mask patterns 300a extend in a second direction D2 parallel to the top surface of the substrate 100 and are arranged at a first interval L1 in a third direction D3, and the second direction D2 is perpendicular to the third direction D3; the projection of the first mask layer 300 on the substrate 100 covers the first end 111 or the second end 112 of the active regions 110 in two adjacent rows, and exposes the middle part 113 between the two end parts of the active region 110.

[0145] In some embodiments, the first direction D1 and the second direction D2 are obliquely intersected at a first included angle a, the first included angle a is an obtuse angle.

[0146] In some embodiments, the first interval L1 is less than 1 / 3 of the length of the active region 110 in the first direction D1.

[0147] In some embodiments, as shown in Figure 21 、 Figure 22 , the semiconductor structure further comprises: a plurality of first gate electrodes 500, the plurality of first gate electrodes 500 are arranged in the substrate 100, the first gate electrodes 500 extend along a fourth direction D4, the plurality of first gate electrodes 500 are arranged at equal intervals in a fifth direction D5 perpendicular to the fourth direction D4, the fourth direction D4 obliquely intersects with the first direction D1; the first end 111 of the active region 110 and the second end 112 of the active region respectively intersect with one first gate electrode 500. In this embodiment, the fourth direction D4 is different from the second direction D2. Figure 8 、 Figure 9

[0148] The semiconductor structure provided by the embodiment forms a first mask layer on the top surface of the substrate, the first mask layer comprises a plurality of strip-shaped first mask patterns, the first mask patterns cover the first end and the second end of the active region, and the projection of the first mask patterns formed on the substrate exposes the middle part of the active region.

[0149] In the exemplary embodiments of the present disclosure, a semiconductor structure is provided, as shown in Figure 28 、 Figure 29 , the semiconductor structure comprises: an active array 01 and an isolation structure 120 arranged between the active array 01, the active array 01 comprises a plurality of rows of active regions 110 arranged at staggered intervals, each active region 110 comprises a first end 111, a second end 112 and a middle part 113, and the first ends 111 and the second ends 112 of the active regions 110 in the same row are alternately arranged along a first direction. Referring to Figure 23 、 Figure 24 , the middle part 113 of each active region 110 is provided with a bit line contact hole 114. In some embodiments, the projection of the bit line contact hole 114 in the first direction D1 is an inverted isosceles trapezoid.

[0150] In some embodiments, referring to Figure 27 , the semiconductor structure further comprises a contact structure 400, and the contact structure 400 fills the bit line contact hole 114.

[0151] In some embodiments, as shown in Figure 28 、 Figure 29 ​As shown in FIG. 7, the semiconductor structure further includes a plurality of bit line structures 700, the plurality of bit line structures 700 are arranged on the top surface of the semiconductor structure along a fifth direction D5, the plurality of bit line structures 700 are arranged equidistantly and in parallel along a fourth direction D4, the fifth direction D5 and the first direction D1 are obliquely intersected, the fifth direction D5 and the fourth direction D4 are perpendicular, and each bit line structure 700 is connected with the plurality of contact structures 400.

[0152] In some embodiments, as shown in FIG. 7, with reference to FIGS. 1-6, Figure 28 、 Figure 29 As shown in FIG. 7, with reference to FIGS. 1-6, Figure 8 、 Figure 9 The semiconductor structure further includes a plurality of first gate electrodes 500, the plurality of first gate electrodes 500 are arranged in the semiconductor structure, the first gate electrode 500 extends along the fourth direction D4, and a projection range of the first gate electrode 500 on the first direction D1 falls in a projection range of the first end 111 of the active region 100 on the first direction D1 or falls in a projection range of the second end 112 of the active region 100 on the first direction D1.

[0153] The semiconductor structure provided by the embodiment has no filling gap in the contact structure, has better electrical performance, and has high product yield. In addition, the semiconductor structure provided by the embodiment has complete structures of the first end and the second end of the active region, reserves sufficient process space for forming a capacitive contact between the connected bit line structures, and can further improve the integration density of the semiconductor structure.

[0154] The embodiments or implementations in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be mutually referred to.

[0155] In the description of the specification, the description of the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the disclosure.

[0156] In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0157] In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship, and are only for the purpose of facilitating the description of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0158] It can be understood that the terms "first", "second" and the like used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish the first structure from another structure.

[0159] In one or more drawings, the same elements are denoted by similar reference numerals. For the sake of clarity, parts of the drawings are not drawn to scale. In addition, certain known parts can not be shown. For the sake of simplicity, structures obtained after several steps can be described in one drawing. Many specific details of the present disclosure are described below, such as the structure, material, size, processing process and technique of the device, in order to make the present disclosure more clearly understood. But as those skilled in the art can understand, the present disclosure can be implemented without these specific details.

[0160] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate comprising an active array, the active array comprising a plurality of rows of active regions arranged in an interlaced manner, each of the active regions comprising a first end, a second end and a middle portion, the first ends and the second ends of the active regions in a same row being arranged in an alternating manner along a first direction; performing a first etching on the middle portions of the active regions to form contact holes in the middle portions of the active regions; depositing a first material in the contact holes to form contact structures; and depositing a first material in the contact holes to form contact structures, comprising: depositing the first material to fill the contact holes, forming filling voids in the first material, etching part of the first material to expose the filling voids and etching the filling voids to form a U-shaped or V-shaped groove in the first material, and depositing the first material again to fill the U-shaped or V-shaped groove. 2.The method of claim 1, wherein the performing a first etching on the middle portions of the active regions comprises: forming a first mask layer above the substrate, a projection of the first mask layer on the substrate covering the first ends or the second ends of the active regions in two adjacent rows to expose the middle portions of the active regions, and performing a first etching on the middle portions of the active regions according to the first mask layer. 3.The method of claim 2, wherein the method further comprises: forming a hard mask layer above the substrate, and forming the first mask layer above the hard mask layer. 4.The method of claim 3, wherein the forming the first mask layer above the hard mask layer comprises: forming a first sub-mask above the hard mask layer, forming a second sub-mask on sidewalls of the first sub-mask, the second sub-mask extending along a second direction, a projection of the second sub-mask on the substrate covering the middle portions of the active regions, etching part of the hard mask layer according to the second sub-mask to form a third sub-mask, filling a fourth sub-mask in the middle of the third sub-mask, and removing the third sub-mask to form the first mask layer. 5.The method of claim 4, wherein the first direction and the second direction intersect at a first included angle, and the first included angle is an obtuse angle. 6.The method of claim 2, wherein the performing a first etching on the middle portions of the active regions according to the first mask layer comprises: etching a hard mask layer above the substrate according to the first mask layer to remove part of the hard mask layer above the substrate exposed by the first mask layer, and etching the middle portions of the active regions exposed by the first mask layer to remove part of the middle portions of the active regions exposed by the first mask layer to form the contact holes. 7.The method of claim 4, wherein in the first etching, an etching rate of the hard mask layer is less than an etching rate of the middle portions of the active regions. 8.The method of claim 4, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The width of the top of the contact hole is greater than or equal to the width of the bottom of the contact hole.

9. The method of claim 4, wherein, In the second direction section, the contact hole is flanked by isolation structures.

10. The method of claim 3, wherein, Before forming a hard mask layer over the substrate, comprising: forming a gate pattern over the substrate, the gate pattern extending in a fourth direction parallel to a top surface of the substrate, the gate pattern spaced apart in a fifth direction, the fourth direction perpendicular to the fifth direction; forming a plurality of first trenches in the substrate by using the gate pattern as an etching mask; forming a plurality of first gate electrodes in the plurality of first trenches.

11. The method of claim 1, wherein, After forming a contact hole in the middle portion of the active region, further comprising, forming a plurality of bit line structures, each of the bit line structures extending in the fifth direction, each of the bit line structures connected to a plurality of the contact structures.

12. The method of claim 2, wherein, a spacing between adjacent first mask layers is less than or equal to 1 / 3 of a length of the active region in the first direction.

13. A semiconductor structure formed by the method of any one of claims 1-12, comprising: a substrate comprising an active array, the active array comprising a plurality of rows of active regions spaced apart in a staggered manner, each of the active regions comprising a first end, a second end, and a middle portion, the first ends and the second ends of the active regions in the same row arranged in an alternating manner along a first direction; a hard mask layer covering a top surface of the substrate; a first mask layer covering a portion of the hard mask layer, the first mask layer comprising a plurality of first mask patterns parallel to each other, the first mask patterns extending in a second direction parallel to the top surface of the substrate, the first mask patterns spaced apart in a third direction at a first spacing, the second direction perpendicular to the third direction; a projection of the first mask layer on the substrate covering the first ends or the second ends of the active regions in two adjacent rows, exposing the middle portions between the first ends and the second ends of the active regions.

14. The semiconductor structure of claim 13, wherein: the first direction and the second direction obliquely intersect at a first included angle, the first included angle being an obtuse angle.

15. The semiconductor structure of claim 13, wherein: the first spacing is less than 1 / 3 of a length of the active region in the first direction.

16. The semiconductor structure of claim 15, further comprising: a plurality of first gate electrodes disposed in the substrate, the first gate electrodes extending in a fourth direction, the first gate electrodes spaced apart in a fifth direction perpendicular to the fourth direction, the fourth direction obliquely intersecting the first direction; the first ends of the active regions and the second ends of the active regions each intersecting one of the first gate electrodes. ​ ​ ​

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