Multiple clock control

Abstract

Two clocks, a fast clock and a slow clock, are provided for clocking a processing unit. A plurality of frequency settings, referred to as gears, are defined for the two clocks. Each of the gears indicates a maximum frequency for the fast clock and a minimum frequency for the slow clock such that the gap between the two frequencies can be kept at a manageable level in order to reduce transients when switching between the two clocks. The system switches between gears as needed. In response to determining to increase the frequency of the clock signal, a higher gear is selected for which the maximum and minimum frequencies defined for the gear are higher than the previously selected gear. Likewise, in response to determining to decrease the frequency of the clock signal, a lower gear is selected for which the maximum and minimum frequencies defined for the gear are lower than the previously selected gear.

Description

Technical Field

[0001] The present invention relates to a method and apparatus for controlling two clock generators to provide clock signals to a processing unit. Background Art

[0002] When an application executes on a processing unit, many different variables affect the performance of the processing unit while executing that application. These variables include the voltage at which the processing unit operates, the current drawn by the processing unit, the temperature of the processing unit, and the clock frequency controlled by the processing unit's clock signal. In many cases, these factors become interdependent. This makes selecting the optimal frequency for the processing unit's clock signal very challenging.

[0003] When choosing a processor unit clock frequency, there are two potentially conflicting considerations. On the one hand, there's a general desire not to "waste power." The faster the clock runs, the more power the application running on the processor unit consumes. On the other hand, processors are increasingly being built with the ability to run "hot," meaning with a high power budget. The faster the processor clock runs, the more efficiently a particular application can execute and output. This is particularly true for processors acting as accelerators for demanding workloads in AI / machine learning applications.

[0004] One factor that adds to the challenge when trying to select the optimal clock frequency is that any given application running on the processing unit may have different power requirements during its execution. For example, when entering a computationally intensive phase of the application, the number of switching elements that switch per clock cycle in the processing unit increases. This increase in the amount of switching in the processing unit results in an increase in the amount of power that the processing unit must draw to prevent malfunctions in the processing unit's operation.

[0005] Because the power requirements of a processing unit vary as applications execute, there's a risk that the power drawn by the processing unit may exceed its power budget during certain periods. In these situations, it's desirable to reduce the clock frequency to prevent exceeding the power budget. On the other hand, when the processing unit is executing less computationally intensive code with lower power consumption, the clock frequency can be increased to enable applications to execute faster.

[0006] One way to modify the clock signal provided to the processing unit is to provide multiple clock generators and switch between them. For example, when an application is executing computationally intensive code, a clock signal from a lower-frequency clock generator can be provided to the processing unit to avoid exceeding the power budget. On the other hand, when an application is executing less computationally intensive code, a clock signal from a higher-frequency clock generator can be provided to the processing unit to increase the speed at which the application runs. Summary of the Invention

[0007] In some cases, when switching between clock generators as discussed above, the frequency difference between the two clock generators can become quite large in order to cover the appropriate frequency range for the processing unit. Switching between a very slow clock signal and a very fast clock signal can result in voltage drops and current transients. To reduce these effects, it is recommended to limit the difference between the fast and slow clocks to a certain maximum value. However, this reduces the dynamic frequency range of the clock signal provided to the processing unit.

[0008] According to an embodiment of the present application, a method for controlling the frequency of a clock signal of a processing unit is provided, the method comprising: switching between the following selections: a first clock generator for providing a processing unit clock signal for executing an application; and a second clock generator for providing a processing unit clock signal for executing the application, wherein the frequency of the clock signal provided by the second clock generator is less than the frequency of the clock signal provided by the first clock generator; accessing multiple settings in a memory, wherein each setting includes a maximum frequency of the first clock generator in the setting and a minimum frequency of the second clock generator in the setting; in response to at least one condition detected indicating a need to increase the frequency of the clock signal, changing from a current one of the settings to a higher one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator compared to the current one of the settings; and in response to at least one condition detected indicating a need to reduce the frequency of the clock signal, changing from the higher one of the settings to a lower one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator compared to the lower one of the settings.

[0009] Therefore, in a system where two clocks are provided, the clocks are adjusted between different settings, each setting having a minimum frequency for the slower clock and a maximum frequency for the faster clock. By doing so, it is possible to clock the processing unit at a new frequency that may be outside the range previously provided by the clocks, while not suppressing any increase in the gap between the clocks, which would result in larger transients.

[0010] In some embodiments, for each of the settings, the frequency of the clock signal provided by the second clock generator is fixed at a minimum frequency of the second clock generator for the corresponding setting.

[0011] In some embodiments, the detected at least one condition indicating a need to increase the frequency of the clock signal comprises a determination that the first clock generator has been selected to provide the processing unit clock signal for more than a predetermined amount of time.

[0012] In some embodiments, the detected at least one condition indicating a need to increase the frequency of the clock signal further comprises determining that the frequency of the first clock generator is set to a maximum frequency of the first clock generator in a current setting.

[0013] In some embodiments, the at least one condition detected indicating a need to reduce the frequency of the clock signal includes a determination that the second clock generator has been selected for more than a predetermined amount of time.

[0014] In some embodiments, the at least one condition detected indicating a need to reduce the frequency of the clock signal includes determining that the frequency of the first clock generator has been set to be equal to or less than the frequency of the second clock generator.

[0015] In some embodiments, a current one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than a lower one of the settings.

[0016] In some embodiments, the lower one of the settings and the current one of the settings are the same.

[0017] In some embodiments, the method includes: measuring the current drawn by the processing unit at a comparator to determine whether the processing unit exceeds a power budget; using an output signal from the comparator to control selection of a first clock generator and a second clock generator; receiving the output signal at a controller device; and using the output signal from the comparator at the controller device to perform the steps of detecting at least one condition indicating a need to increase the frequency of the clock signal and detecting at least one condition indicating a need to decrease the frequency of the clock signal.

[0018] In some embodiments, the method includes changing to a lowest one of the settings in response to a detected overcurrent event, wherein the lowest one of the settings has lower values ​​for minimum and maximum frequencies than any other setting of the plurality of settings.

[0019] In some embodiments, the comparator used to determine whether the power budget is exceeded is a first comparator, wherein detecting the overcurrent event is performed by a second comparator, wherein the first comparator and the second comparator are different, wherein the second comparator has a higher threshold than the first comparator.

[0020] In some embodiments, for the lowest one of the settings, the minimum frequency of the slow clock generator and the maximum frequency of the fast clock generator are the same frequency, wherein the step of changing to the lowest one of the settings includes: selecting the second clock generator for providing the processing unit clock signal; then, setting the frequency of the clock signal provided by the first clock generator to the same frequency; then, selecting the first clock generator for providing the processing unit clock signal; then, setting the frequency of the clock signal provided by the second clock generator to the same frequency.

[0021] In some embodiments, a difference between a minimum frequency of the second clock generator and a maximum frequency of the first clock generator is larger in a higher one of the settings than in the current one of the settings, wherein a difference between a minimum frequency of the second clock generator and a maximum frequency of the first clock generator is larger in a higher one of the settings than in a lower one of the settings.

[0022] In some embodiments, switching includes: selecting a first clock generator to provide a processing unit clock signal for executing an application; detecting a threshold event indicating that the application has exceeded a power budget allocated for its execution; selecting a second clock generator to provide a processing unit clock signal for executing the application; when the processing unit clock signal is provided by the second clock generator, reducing the frequency of the clock signal generated by the first clock generator; and reselecting the first clock generator to provide the processing unit clock signal after a predetermined time from selecting the second clock generator.

[0023] In some embodiments, the switching includes: cycling between selection of: a first clock generator for providing a processing unit clock signal for executing an application during a first portion of the cycle; and a second clock generator for providing a processing unit clock signal for executing an application during a second portion of the cycle; increasing an average clock frequency of the processing unit by increasing a ratio between a duration of the first portion of the cycle and a duration of the second portion of the cycle; and decreasing the average clock frequency of the processing unit by decreasing a ratio between a duration of the first portion of the cycle and a duration of the second portion of the cycle.

[0024] In some embodiments, the step of changing from a higher one of the settings to a lower one of the settings includes: selecting a second clock generator for providing a processing unit clock signal; then, setting the frequency of the clock signal provided by the first clock generator to a frequency less than the maximum frequency of the first clock generator defined by the lower one of the settings; then, selecting the first clock generator for providing the processing unit clock signal; then, setting the frequency of the clock signal provided by the second clock generator to the minimum frequency of the second clock generator defined by the lower one of the settings; and then, selecting the second clock generator to provide the processing unit clock signal.

[0025] In some embodiments, the frequency less than the maximum frequency of the first clock generator is the minimum frequency of the second clock generator defined by the lower one of the settings.

[0026] In some embodiments, this includes subsequently setting the frequency of the clock signal provided by the first clock generator to a maximum frequency of the first clock generator defined by the lower one of the settings.

[0027] In some embodiments, the processing unit includes a plurality of processors, and the method includes distributing a processor clock signal to each of the plurality of processors along a conductor of a clock tree of the processing unit.

[0028] In some embodiments, the conductive wire is a copper wire having a thickness greater than 0.2 microns.

[0029] According to a second aspect, a system is provided, comprising: a first clock generator for providing a processing unit clock signal for executing an application; and a second clock generator for providing the processing unit clock signal for executing the application, wherein the frequency of the clock signal provided by the second clock generator is less than the frequency of the clock signal provided by the first clock generator; a switching circuit configured to switch between selection of the first clock generator for providing the processing unit clock signal and the second clock generator for providing the processing unit clock signal; at least one memory configured to store a plurality of settings, wherein each setting includes a maximum frequency of the first clock generator in the setting and a minimum frequency of the second clock generator in the setting; and at least one processor configured to: in response to In response to at least one condition detected indicating a need to increase the frequency of the clock signal, modify the frequencies of the first clock generator and the second clock generator to change from a current one of the settings to a higher one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the current one of the settings; and in response to at least one condition detected indicating a need to decrease the frequency of the clock signal, modify the frequencies of the first clock generator and the second clock generator to change from the higher one of the settings to a lower one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the lower one of the settings.

[0030] According to a third aspect, there is provided a computer program executed by at least one processor of a system, the system comprising: a first clock generator for providing a processing unit clock signal for executing an application; and a second clock generator for providing a processing unit clock signal for executing the application, wherein the frequency of the clock signal provided by the second clock generator is less than the frequency of the clock signal provided by the first clock generator; a switching circuit configured to switch between selection of the first clock generator for providing the processing unit clock signal and the second clock generator for providing the processing unit clock signal, wherein the computer program is configured to, when executed by the at least one processor, cause a method to be performed, the method comprising: accessing a plurality of settings in a memory, wherein each of the settings comprises a maximum frequency of the first clock generator in the setting; rate and a minimum frequency of the second clock generator in the setting; in response to at least one detected condition indicating a need to increase the frequency of the clock signal, modifying the frequencies of the first clock generator and the second clock generator to change from a current one of the settings to a higher one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the current one of the settings; and in response to at least one detected condition indicating a need to decrease the frequency of the clock signal, modifying the frequencies of the first clock generator and the second clock generator to change from the higher one of the settings to a lower one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the lower one of the settings.

[0031] According to a fourth aspect, there is provided a non-transitory computer readable medium storing the computer program according to the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] For a better understanding of the invention and to show how it may be carried into effect, reference will now be made by way of example to the accompanying drawings:

[0033] Figure 1 is a schematic block diagram of a processing unit having a clock control system;

[0034] Figure 2 is a schematic block diagram of the clock generator module;

[0035] Figure 3 is a schematic block diagram of a control device for a clock;

[0036] Figure 4 shows an example of how the frequency of a clock signal provided to a processing unit varies over time when a clock dithering method is employed;

[0037] Figure 5An example is shown of how the frequency of the clock signal provided to the processing unit varies over time according to the proposal;

[0038] Figure 6 Another example is shown of how the frequency of the clock signal provided to the processing unit varies over time according to the proposal;

[0039] Figure 7 An example is shown of how the frequency of the clock signal provided to the processing unit varies over time when a multi-clock control scheme for shifting between gears is provided;

[0040] Figure 8 Another example is shown of how the frequency of the clock signal provided to the processing unit varies over time when a multi-clock control scheme for switching between gears is provided;

[0041] Figure 9 An example is shown of a set of gears that can be used in two clock generators in a system;

[0042] Figure 10A A procedure is shown of shifting the frequency of a clock generator down one gear;

[0043] Figure 10B A procedure is shown of shifting the frequency of a clock generator up one gear;

[0044] Figure 11 An example timeline is shown that illustrates how the frequency of a clock signal varies over time when a gear box scheme is used;

[0045] Figure 12 An example power management controller is shown in more detail;

[0046] Figure 13 An example is shown of how the frequency of a clock signal provided to a processor varies over time when a gear box and dithering concept are combined;

[0047] Figure 14 is a schematic block diagram of a processor chip comprising a plurality of tiles;

[0048] Figure 15 is a schematic diagram of a bulk synchronous parallel (BSP) computing model;

[0049] Figure 16 is another schematic diagram of the BSP model;

[0050] Figure 17 is a schematic diagram illustrating the distribution of a clock signal along wires arranged in a clock tree structure to tiles;

[0051] Figure 18 is a method according to an embodiment of the first invention; and

[0052] Figure 19 This is a method according to an embodiment of the second invention. DETAILED DESCRIPTION

[0053] The following describes the embodiment of the first invention and the embodiment of the second invention with reference to the accompanying drawings. These two inventions can be used independently or in combination with each other. Figure 1 and Figure 2 A system is described that can implement the first and / or second invention.

[0054] Figure 1 is a schematic block diagram of a computer system including a processing unit 2. For example, the computer system may be a single-chip processing unit including a plurality of processors (tiles) 3. The processing unit 2 is clocked by a clock 4 which provides a reference clock ref_clk to the processing unit 2 at a base frequency. The processing unit 2 is connected to a management control unit (MCU) module 6 which may be implemented on-chip or off-chip. The MCU 6 manages various services of the processing unit 2 and, in this context, controls the frequency of the clock signal which governs the operation of the tiles 3 on the processing unit 2. The power management integrated circuit (PMIC) 7 is provided by a power supply denoted by V DD The processing unit 2 is powered by a power rail and is connected to the MCU 6 via a bidirectional serial bus 30 and an interrupt pin ((one or more) physical wires) 32. The processing unit 2 can be an accelerator that is used to process the workload assigned to it by the host 8. The host 8 can provide workload data to the processing unit 2 via an interface 10. There can be a single processing unit 2, or multiple instances of the processing unit 2 connected on a card and multiple cards in a rack. The processing unit 2 can be of a type known as an Intelligence Processor Unit (IPU), which is designed to handle workloads in the field of artificial intelligence or machine learning. A description of the IPU is given in U.S. application No. 15 / 886,065, which is incorporated herein by reference.

[0055] The clock 4 can serve one processing unit 2 or multiple processing units 2. The clock provides a reference clock ref_clk to the on-chip clock generator module 12 via the card connector. The on-chip clock generator module 12 generates an IPU clock signal Φ, which is provided to the tiles 3 on the processing unit 2. Figure 1 The physical clock lines that power each tile 3 are not shown to avoid overcomplicating the diagram. Note that other parts of the processing unit 2, such as the switch 5 that controls inter-chip communication, can be clocked by the clock signal Φ or the reference clock (or other clock).

[0056] As an alternative to the clock 4 being provided via a card connector or similar, there can be an on-board clock source. That is, the clock 4 can be implemented within the processing unit 2. The clock signal from the clock source 4 is a reference clock ref clk from which a clock signal Φ for processing unit operations is derived. System clocks for certain aspects of the chip logic can also be derived from ref clk.

[0057] According to embodiments of the application, the clock generator module 12 receives the ref clk signal and generates the IPU clock signal Φ as described herein.

[0058] The on-chip clock generator module 12 receives input from an IPU clock selection board 22 which is connected to the interrupt pin 32 of the PMIC 7. It also receives a frequency control signal from the MCU 6 via the JTAG interface 38.

[0059] The clock generator module 12 comprises two phase-locked loops (PLLs) 14, 16 as shown in Figure 2 It will be appreciated that whilst the clock generator module 12 is described as comprising various circuits, these (PLLs, OR gates, multiplexers (MUXs), registers) need not be located in particular blocks, but can be distributed throughout the chip. Thus, the clock controller 12 is described as a convenient way of explaining how the embodiments of the application operate to control the generation of the IPU clock Φ. It is also noted that whilst the clock signal generators 14, 16 are referred to as PLLs 14, 16, these components can more generally be any type of clock signal generator.

[0060] The PLLs 14, 16 receive the reference clock ref clk. The first PLL 14 generates from ref clk a so-called fast clock, and the second PLL 16 generates from ref clk a so-called slow clock. A glitchless multiplexer 18 receives outputs from the PLLs’ 14, 16 and can switch between the fast and slow clocks to provide the IPU clock Φ. The multiplexer 18 is controlled by a MUX control signal 34. It is described herein that the MUX control signal 34 is asserted high to control the multiplexer 18 to select the output of the slow PLL 16, and is not asserted (low) in the opposite case. Of course, it is possible to use the opposite protocol, where the MUX control signal 34 would be asserted low to select the output of the slow PLL 16, and high in the opposite case.

[0061] There are two mechanisms by which the MUX control signal 34 can be asserted and, therefore, either the fast PLL 14 or the slow PLL 16 can be selected. According to the first mechanism, an alert from the PMIC 7 asserted on the interrupt pin 32 to the MCU 6 is also provided to the input pad 22 which feeds a signal to one input of the OR gate 36. This provides for immediate "throttling back" if it is detected that the current has exceeded a current threshold. Figure 2 , the signal received at input pad 22 is shown as IPUCKSEL. The second mechanism involves the MCU 6 writing a "1" to register 23 so that (even though the IPUCKSEL signal at input pad 22 is not asserted) the multiplexer 18 is controlled to cause the application to run from the slow PLL 16.

[0062] The frequency at which the PLLs 14, 16 operate can be set based on signals received from the MCU 6 on the wires 14a, 16a. The wires 14a, 16a may include two wires for transmitting two different adaptation signals for adjusting the PLLs 14, 16. As shown, the MCU 6 provides these signals to the clock generator module 12 via the JTAG interface 38. Figure 2 , reference numeral 14a denotes an adaptation signal for the fast PLL 14, and reference numeral 16a denotes an adaptation signal for the slow PLL 16. The fast and slow PLLs may be of the same or different types.

[0063] refer to Figure 3 , Figure 3 MCU 6 is shown in more detail. MCU 6 includes processing circuitry 310 and at least one memory 320 for performing the functions described herein. Preferably, processing circuitry 310 is a processor, such as a CPU, configured to execute instructions stored in memory 320 to perform the functions described therein. Additionally or alternatively, processing circuitry 310 may include a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) configured to perform the functions described herein.

[0064] Now, embodiments of the first invention will be described.

[0065] In the first embodiment of the present invention, cycling is performed between fast PLL 14 and slow PLL 16. In other words, repeated switching occurs between fast PLL 14 and slow PLL 16. This results in processing unit 2 being clocked at an average clock frequency that has a value between the clock frequencies of fast PLL 14 and slow PLL 16. The average clock frequency is determined by comparing the proportion of time during a cycle in which the signal of fast PLL 14 is supplied to processing unit 2 with the proportion of time during a cycle in which the signal of slow PLL 16 is supplied to processing unit 2. The proportion of time that fast PLL 14 is in operation relative to slow PLL 16 is determined by the control signal received by clock generation circuit 12. Therefore, the average clock frequency increases as the proportion of time spent in fast PLL 14 increases in response to an increase in the control signal. Similarly, the average clock frequency decreases as the proportion of time spent in fast PLL 14 and slow PLL 16 decreases in response to a decrease in the control signal.

[0066] Each control signal received at the clock generation circuit 12 indicates whether the processing unit 2 has exceeded a set power budget. The power budget is set for the specific application or workload to be executed by the processing unit 2. Although other possibilities exist, the power budget will typically be set by the host 8 and communicated to the MCU 6 (either via the processing unit 2 or directly). For example, the MCU 6 may be aware of similar applications previously run for the chip and can set the power budget based on this stored historical data. In any case, the MCU 6 is aware of the power budget. In the case of multiple chips on a card, the MCU 6 will determine the power budget for each chip. When running applications in the fields of machine learning and artificial intelligence, the processing requirements mean that the power budget should be met but not exceeded. In other words, the goal is to run the chip as "hot" as possible within the constraints of the power budget. Based on the power budget, the MCU 6 determines the current threshold to be managed by the PMIC 7. The MCU 6 communicates with the PMIC 7 via bus 30 to provide an indication of the power budget. This enables the PMIC 7 to determine the current threshold to be applied. In some embodiments, the PMIC 7 provides a constant supply voltage VDD (e.g., 0.8 volts) to the power rail of the processing unit 2, so that the current threshold can be derived by dividing the power budget by the supply voltage VDD. In other cases, some complex calculations may be required to determine the current threshold to be used by the PMIC 7. The PMIC 7 includes appropriate circuitry for calculating the current threshold.

[0067] The PMIC 7 includes an ammeter 11 or other type of sensor that is capable of detecting when the current drawn by the processing unit 2 exceeds a current threshold. The PMIC 7 is suitably connected to the processing unit 2 to measure the current, although these connections are not in the Figure 1The current is the current drawn by the processing unit 2 to execute the application or workload.

[0068] PMIC 7 also includes a comparator 15 and a filtering circuit 13. Comparator 15 is configured to receive an indication of a current threshold. Comparator 15 is configured to compare the current threshold with the indication of the current provided to processing unit 2 to determine when the threshold is exceeded. The indication of the current provided to processing unit 2 is received as input to comparator 15 from filtering circuit 13. Filtering circuit 13 is configured to receive a current measurement from ammeter 11. Filtering circuit 13 filters the current measurement to provide a moving average of the current. Filtering circuit 13 can filter the current to a time constant of 60 microseconds.

[0069] Comparator 15 itself is associated with a certain delay. The magnitude of the delay depends on the time required to charge / discharge the capacitor of comparator 15. The delay is such that if the current indication received by the comparator exceeds a current threshold, comparator 15 will not assert an output signal indicating so until the received current indication has exceeded the threshold for a certain amount of time. Similarly, if the current indication received by the comparator is below the threshold, comparator 15 will not assert an output signal indicating so until the received current indication has been below the threshold for a certain amount of time. The amount of time after the current falls below the threshold until the comparator is triggered depends on the time required to discharge the capacitor of comparator 15. The amount of time after the current rises above the threshold until the comparator is triggered depends on the time required to charge the capacitor of comparator 15.

[0070] Comparator 15 receives the indication of the current and compares it to a current threshold. If the current threshold is exceeded, comparator 15 issues a signal (IPUCKSEL) on conductor 32. This signal is received at clock input selector board 22 and from there provided to clock generator module 12. Figure 2 , the IPUCKSEL signal is received at the multiplexer 18 and is used to select the slow PLL 16 so that the output of the slow PLL 16 is provided as the clock signal for the processing unit 2. Thus, in the event that an overcurrent event is detected, the PMIC 7 causes the slow PLL 16 to be selected.

[0071] On the other hand, if comparator 15 determines that the current indication provided to processing unit 2 is below the current threshold, the output of comparator 15 causes the IPUCLSEL signal to not be asserted on conductor 32. As a result, multiplexer 18 does not receive the IPUCLSEL signal, and thus fast PLL 14 is selected. The output of fast PLL 14 is provided to processing unit 2 as the clock signal for processing unit 2. Therefore, in the absence of a detected overcurrent event, PMIC 7 causes fast PLL 16 to be selected.

[0072] The filtering provided by filter circuit 13 and the delay of comparator 15 increase the amount of time required for the output of the comparator to repeatedly switch between high and low in response to changes in the current measured by ammeter 11, thereby appropriately reducing the switching rate between fast PLL 14 and slow PLL 16.

[0073] The frequencies of fast PLL 14 and slow PLL 16 are set so that during operation of processing unit 2, the threshold clock frequency at which an overcurrent event occurs lies between the frequencies of fast PLL 14 and slow PLL 16. Thus, fast PLL 14 and slow PLL 16 are able to cover the dynamic range of the application. For example, the output frequency of the fast PLL may be 1.6 GHz, and the output frequency of the slow PLL may be 800 MHz. However, during a particular phase of execution of an application running on processing unit 2, the threshold frequency at which an overcurrent event occurs may be, for example, 1.2 GHz. If the clock of processing unit 2 is above this frequency, processing unit 2 will exceed the set power budget. If the clock of processing unit 2 is below this frequency, processing unit 2 will not exceed the set power budget.

[0074] It should be understood that the threshold frequency is not a fixed amount throughout the operation of the processing unit 2, but will vary depending on the stage of the application executed by the processing unit 2. In particular, if the application is in a computationally intensive stage, the threshold frequency will be lower. If the application is in a less computationally intensive stage, the threshold frequency will be higher.

[0075] The clock signal Φ cycles between the outputs of the slow PLL 16 and the fast PLL 14, causing the average clock frequency to approach the threshold frequency. The resulting average clock frequency is slightly lower than the threshold frequency, causing the average power consumed by the processing unit 2 to be slightly below the power budget.

[0076] Consider the case where fast PLL 14 is first selected. In this case, because the frequency of clock signal Φ is above the threshold frequency, ammeter 11 outputs a current indication that is above the threshold current. Comparator 15 determines from a filtered version of the current indication that the threshold has been exceeded and, in response, outputs a signal on conductor 32, which causes slow PLL 16 to be selected. Once slow PLL 16 is selected, because the frequency of clock signal Φ is below the threshold frequency, ammeter 11 outputs a current indication that is below the threshold current. Comparator 15 determines from the filtered version of the current indication that the threshold has not been exceeded and, in response, deasserts the signal on conductor 32, causing fast PLL 14 to be selected again. Thus, there is jitter (i.e., cycling) between the selection of fast PLL 14 and slow PLL 16.

[0077] Multiplexer 18 dithers between selection of the fast PLL 14 output and the slow PLL 16 output so that the average current of processing unit 2 is close to a threshold, thereby providing good performance while avoiding power consumption exceeding the power budget when the power consumption is averaged over a sufficiently long time period.

[0078] Figure 4 An example of a dithering process that can be performed during application execution on processing unit 2 is shown. Graph 400 shows how the frequency of clock signal Φ varies over time while the application is executing. Line 420 shows the average frequency of clock signal Φ since t=0. In this example, the current threshold is set to 125 amps. Above this current threshold, the power budget is exceeded.

[0079] Figure 4 The sample application exhibits a 1ms cycle of activity. Within each cycle, the application has periods of high computational intensity and periods of low computational intensity. The pattern of high computational intensity and low computational intensity periods repeats every 1 millisecond (ms). This type of pattern can occur when you run an application that involves repeatedly performing the same set of operations within a loop. An example of such an application is an application for training a neural network that performs multiple training iterations, where each training iteration involves the same process repeated with different data. When an application repeatedly performs the same set of operations, a repeating pattern appears in the application's activity level. Figure 4 In the example shown, the period of the active mode is 1 millisecond. An example of a period of the active mode is represented by period 430. Figure 4 A high computationally intensive phase 440 and a low computationally intensive phase 450 are shown as part of a cycle 430. As shown, each of the high computationally intensive phases and each of the low computationally intensive phases repeats every 1 millisecond.

[0080] Despite Figure 4 In the example, each cycle of the application consists of a phase of high computational intensity and a phase of low computational intensity, but other applications may exhibit different patterns of activity with more distinct phases in each cycle.

[0081] As shown in the graph 400, initially at t=0, the frequency of the clock signal Φ is set to the frequency of the fast PLL 14. Since the current through the processing unit 2 will be zero before the application starts, the current measured by the comparator 15 is a filtered current, and the comparator 15 has an associated delay, the comparator 15 will not detect that the current exceeds the threshold until the application has been operating for a period of time, even if the application is executing in a high-intensity phase. This is reflected in Figure 4 middle, Figure 4This frequency is shown to remain at the frequency of the fast PLL 14 for a period of time until the comparator 15 asserts a signal to indicate that the current threshold has been exceeded.

[0082] Once the comparator 15 detects that the filtered current exceeds the threshold, the comparator 15 asserts a signal which causes the slow PLL 16 to be selected. This is shown in Figure 4 Once the frequency has decreased, comparator 15 detects that the filtered current has fallen below a threshold value and, in response, asserts a signal to select slow PLL 16, causing fast PLL 14 to be again selected to provide clock signal Φ to processing unit 2. After fast PLL 14 has been selected for a certain duration, comparator 15 again detects that the filtered current has exceeded a threshold value and, in response, asserts a signal to switch to slow PLL 16.

[0083] The application's active phase 440 is a relatively high activity phase where the processing unit 2 executes computationally intensive code. Figure 4 This is demonstrated by the relatively small proportion of time spent on the fast clock compared to the other phases 450 of the application shown. After phase 440, the application enters phase 450, which is a less computationally intensive phase. As shown, the proportion of time spent on the fast clock in phase 450 is greater than the proportion of time spent on the fast clock in phase 440. Therefore, the average clock frequency at which processing unit 2 operates during phase 450 is greater than the average clock frequency at which processing unit 2 operates during phase 440. This provides a performance advantage, which is desirable because during the less intensive phases of the application, processing unit 2 can be clocked faster without exceeding the application's power budget.

[0084] like Figure 4 As shown, the average frequency 420 of the clock signal Φ converges to a certain value over time. In this example, the value is 1190 MHz. For the application being executed, this average clock frequency corresponds to an average current of 112.5 amps. This average current is lower than that in Figure 4 In the example of FIG. 1 , a current threshold of 125 amperes is set for the processing unit 2. Thus, the first invention achieves a good compromise between the performance of the processing unit 2 and not exceeding the power budget of the processing unit 2.

[0085] In some cases, the activity level of an application can vary on very short timescales, making it unnecessary to switch from fast PLL 14 to slow PLL 16 if the duration of the high activity period is very short. This is achieved by a delay in comparator 15, which switches its output only when the current changes above a threshold for a specified period of time. For example, suppose the application enters a computationally intensive phase for a short period of time. In response to this change, the current drawn by processing unit 2 exceeds a set threshold, causing the filtered version of the current provided by filtering circuit 13 to also exceed the threshold after a certain amount of time. Comparator 15 receives the filtered current indication and, if the filtered current indication remains above the threshold for less than a time constant set by comparator 15, comparator 15 deasserts the signal selecting slow PLL 16. Thus, the delay associated with comparator 15 enables the application to enter a computationally intensive phase for a short period of time without switching to slow PLL 16.

[0086] The present invention has been described using a current comparator that, when detecting a current exceeding a threshold, selects the slow clock by asserting a signal. However, other implementations are possible. For example, when it is determined that the current is below the threshold, the comparator 15 can assert a signal to select the fast clock, and de-assert the signal when the indication rises above the threshold. In other examples, another device other than the comparator 15 (e.g., another input current monitor or a thermistor) can be used to indicate whether the power budget has been exceeded, and thus control the switching between the fast PLL 14 and the slow PLL 16. In other examples, the MCU 6 can be programmed to control the cycle between the fast PLL 14 and the slow PLL 16 according to a predetermined schedule programmed into the software or firmware of the MCU 6.

[0087] An embodiment of the second invention will now be described. The embodiment of the second invention is implemented in a system having a fast and a slow clock generator, such as Figure 2A fast PLL 14 and a slow PLL 16 are shown. As described above, the fast PLL 14 and the slow PLL 16 can be used to maximize the performance of the processing unit 2 while preventing the power budget from being exceeded. The example described above uses a dithering mechanism to cycle between the selection of the two PLLs 14 and 16. However, other schemes utilizing the two PLLs 14 and 16 can be implemented. For example, in such a scheme, one of the PLLs 14 and 16 can be assigned to provide the processor clock φ for the majority of the normal workload processing operations of the processing unit 2. However, if that PLL needs to be adjusted to a new frequency, the system switches to the other PLL while simultaneously performing the adjustment of the main PLL. After the adjustment is complete, the system switches back to the main PLL. This scheme is referred to herein as a "step change" scheme and is described in detail in U.S. Application No. 16 / 428,797, which is incorporated herein by reference. Therefore, the second invention can be implemented in any system in which switching between fast and slow clock generators for clocking a processing unit is performed.

[0088] In the following description, the embodiment of the second invention is described as follows. Figure 1 is implemented in the system shown.

[0089] One problem that may arise when using two PLLs 14, 16 to clock the processing unit 2 is that if the frequency gap between the fast clock frequency and the slow clock frequency is too large, an undesirably large voltage drop may occur when switching from the slow clock PLL 16 to the fast PLL 14. This voltage drop is caused by a drop in impedance across the processing unit 2. The impedance Z across the processing unit 2 is a function of the frequency f and the switch capacitance C. S Related, the relationship is as follows:

[0090]

[0091] As can be understood from Equation 1, when the fast PLL 14 is selected, the sudden increase in the frequency of the clock signal Φ will cause the impedance across the processing unit 2 to suddenly drop. This sudden drop in impedance causes the voltage across the processing unit 2 to drop before the PMIC 7 has time to react. The voltage drop is particularly severe when the application enters a high activity phase at the moment the frequency of the clock signal Φ increases. When the application enters a high activity phase, the switched capacitance C of the processing unit S As can be understood from Equation 1, a sudden increase in the clock frequency and the switch capacitance will cause a large drop in the impedance of the processing unit 2 and, therefore, a large voltage drop.

[0092] To address this issue, a maximum difference between the fast clock frequency and the slow clock frequency can be enforced. If the difference between these frequencies is constrained, the voltage drop caused by switching between the two frequencies can be limited to a more manageable level. However, limiting the difference in this way can cause problems when trying to select an appropriate frequency to run the processing unit 2. This problem is illustrated in Figure 5 and Figure 6 shown.

[0093] refer to Figure 5 , Figure 5 An example graph 500 illustrating how the frequency of processing unit 2 varies over time is shown. Graph 500 shows a threshold frequency (above which an overcurrent event will occur) for processing unit 2 during the time period shown. As discussed, it is desirable to operate close to the threshold frequency (for performance reasons) without exceeding the threshold frequency (in order to avoid exceeding the power budget). Figure 5 As shown, both the fast clock frequency and the slow clock frequency are set to levels far below the threshold frequency, so that the performance of the processing unit 2 is not optimal. This situation may occur when the application executed on the processing unit 2 has entered a low activity phase. In order to improve the performance of the processing unit 2 during this phase, one possible solution is to increase the frequency of the fast PLL 14 to a new higher frequency, such as Figure 5 However, the maximum gap constraint imposed to limit voltage droop prevents the fast PLL 14 from being adjusted to a higher frequency level that would optimize performance.

[0094] refer to Figure 6 , Figure 6 Another example graph 600 is shown which illustrates how the frequency of processing unit 2 varies over time. Graph 600 illustrates the threshold frequency of processing unit 2 during the illustrated time period. As discussed, while it may be desirable to run processing unit 2 at high speed for performance reasons, there is a set power budget that should not be exceeded. As shown in graph 600, both the fast clock frequency and the slow clock frequency are set to levels well above the threshold frequencies, meaning that the power budget is exceeded. This may occur when the application executing on processing unit 2 is in a high activity phase. To improve the performance of processing unit 2, the frequency of slow PLL 16 may be updated to, for example, Figure 6 However, the maximum gap constraint imposed to reduce voltage droop prevents the slow clock from being reduced below the threshold frequency. Therefore, even after updating to the frequency of the slow PLL 16, the power consumption of the processing unit 2 will still exceed the power budget.

[0095] According to an embodiment of the second invention, a plurality of frequency settings are defined, each of which indicates the maximum frequency of the fast PLL 14 and the minimum frequency of the slow PLL 16, so that the gap between the two frequencies is kept at a manageable level. In this specification, each setting is referred to as a "gear." The system switches between gears as needed. In response to a determination to increase the frequency of the clock signal Φ, a higher gear is selected, at which the maximum and minimum frequencies defined for the gear are higher than the previously selected gear. Similarly, in response to a determination to decrease the frequency of the clock signal Φ, a lower gear is selected, at which the maximum and minimum frequencies defined for the gear are higher than the previously selected gear.

[0096] As described above, reference Figure 1 and Figure 2 , the MCU 6 is configured to provide control signals to the clock generator circuit 12 via the JTAG interface 38 to adjust the frequencies of the fast PLL 14 and the slow PLL 16. These control signals are shown as being provided to the fast PLL 14 and the slow PLL 16 on wires 14a and 16a. In an embodiment of the second invention, when the MCU 6 determines to change to a higher gear in response to the received information, the MCU 6 adjusts the frequencies of the PLLs 14 and 16 to the levels of the new gear by issuing signals on wires 14a and 16a. When changing to a new gear, the MCU 6 can set the frequency of the fast PLL 14 to the maximum frequency of the fast PLL 14 defined for that gear, and can set the frequency of the slow PLL 16 to the minimum frequency of the slow PLL 16 defined for the new gear.

[0097] refer to Figure 7 , which shows how to adjust the fast clock frequency and the slow clock frequency from a lower gear to a higher gear in response to the control signal received from the MCU 6. Figure 7 As shown, the initial slow and fast clock frequencies are well below the threshold frequencies. For the lower gear, the initial slow and fast clock frequencies are set to the minimum slow clock frequency and the maximum fast clock frequency, respectively. After the fast PLL 14 and slow PLL 16 receive control signals, the frequencies of these PLLs 14 and 16 are updated as shown. These control signals set the slow and fast clock frequencies to the minimum slow clock frequency and the maximum fast clock frequency, respectively, for the higher gear. The slow PLL 16 is updated to have a frequency greater than its initial frequency but less than the initial fast clock frequency. The fast PLL 14 is updated to have a frequency greater than its initial frequency.

[0098] like Figure 7As shown, the update frequency of fast PLL 14 may be greater than the threshold frequency. In this case, the frequency of fast PLL 16 may be gradually reduced until it is below the threshold frequency. Optionally, dithering between fast PLL 14 and slow PLL 16 as described for the first invention may be performed to provide an average clock frequency of clock signal Φ that is less than the frequency of the fast PLL and less than the threshold frequency, but greater than the frequency of the slow PLL.

[0099] refer to Figure 8 , Figure 8 FIG. 4 shows how the fast clock frequency and the slow clock frequency are adjusted from a higher gear to a lower gear in response to a control signal received from the MCU 6. Figure 8 As shown, the initial slow and fast clock frequencies are well below the threshold frequencies. In this example, the initial slow and fast clock frequencies are set to the minimum slow clock frequency and maximum fast clock frequency, respectively, for the higher gear. After fast PLL 14 and slow PLL 16 receive control signals, the frequencies of these PLLs 14 and 16 are updated as shown. These control signals set the low-speed and high-speed clock frequencies to the minimum low-speed clock frequency and maximum high-speed clock frequency, respectively, for the low-speed gear. Slow PLL 16 is updated to have a frequency lower than its initial frequency. Fast PLL 14 is updated to have a frequency lower than its initial frequency but higher than the initial slow clock frequency.

[0100] like Figure 8 As shown, the updated fast clock frequency may be greater than the threshold frequency. In this case, the frequency of the fast PLL 14 can be gradually reduced until it is below the threshold frequency. Alternatively, the dithering described for the first invention can be performed to provide an average clock frequency of the clock signal Φ that is less than the threshold frequency.

[0101] The process of moving from a lower gear to a higher gear, where the higher gear has a higher maximum fast clock frequency value and a higher minimum slow clock frequency value than the lower gear, is referred to herein as "shifting up a gear," "increasing a gear," etc. Similarly, the process of moving from a higher gear to a lower gear, where the higher gear has a higher maximum fast clock frequency value and a higher minimum slow clock frequency value than the lower gear, is referred to as "shifting down a gear," "decreasing a gear," etc. The gear increase or decrease may be performed in response to detection of a particular condition by the MCU 6.

[0102] like Figure 7 and Figure 8As shown, adjacent notches overlap, such that when the frequencies of the fast PLL 14 and slow PLL 16 increase by a notch, the updated slow PLL 16 frequency is less than the previous fast PLL 14 frequency at the lower notch. Similarly, when the frequencies of the fast PLL 14 and slow PLL 16 decrease by a notch, the updated fast PLL 16 frequency is greater than the previous slow PLL 14 frequency at the higher notch. This overlap allows the dynamic range of the application to be fully covered by the notches, allowing any frequency of the clock signal Φ (less than the possible maximum achievable by the fast PLL 14) to be provided.

[0103] like Figure 7 and Figure 8 As shown, by defining the maximum and minimum frequencies for each gear, MCU 6 imposes a maximum difference between the initial fast clock frequency and the slow clock frequency. Note that during the gear change process, as can be understood from FIG10 , the maximum frequency difference between the two PLLs 14, 16 may be exceeded. However, no switch from the slow PLL 16 to the fast PLL 14 occurs during this gear change process, and therefore, the dropout issues associated with a large frequency difference are not encountered. Once the gear change process is complete, the new frequency values ​​of the PLLs 14, 16 will not exceed the maximum value defined for the new gear.

[0104] In some embodiments, the difference between the maximum and minimum frequencies can be constant, i.e., the frequency difference defined for each gear is the same. In other embodiments, the difference can vary depending on the gear. In this case, the lower gears have a smaller difference between the maximum fast PLL 14 frequency and the minimum slow PLL 16 frequency than the higher gears. This is allowed because, at lower frequencies, changes in processor clock frequency will produce larger impedance changes (as can be understood from Equation 1), resulting in a larger voltage drop effect.

[0105] As described above, the MCU 6 stores settings that define each of the gears. Each of these gears is defined by a maximum frequency for the fast PLL 14 and a minimum frequency for the slow PLL 16. In some embodiments, when in a particular gear, the MCU 6 can set the frequency of the fast PLL 14 to a frequency lower than the maximum frequency set for that gear. On the other hand, the frequency of the slow PLL 16 can be fixed, that is, the MCU 6 will not adjust the frequency of the slow PLL 16 to a value greater than the minimum value defined for the gear. In other embodiments, the MCU 6 can change the frequency of the slow PLL 16 while in a particular gear while keeping the frequency of the fast PLL 16 fixed. In some embodiments, the frequencies of both PLLs can remain fixed when in a particular gear.

[0106] Accordingly, although the frequencies defined for a gear are referred to as "maximum" and "minimum" frequencies, in some embodiments the frequencies of the fast PLL 14 and the slow PLL 16 do not deviate from these frequencies when in a particular gear. In other words, the "maximum" and "minimum" frequencies can be the only frequencies for that gear. This can be the case when a dithering scheme is applied in the gear. In other embodiments, the frequency of the fast PLL 14 can decrease below the maximum frequency defined for the gear. This can occur when a step change scheme is applied in the gear.

[0107] Reference is made to Figure 9 which shows an example of different gears that the MCU 6 can apply when adjusting the frequencies of the fast PLL 14 and the slow PLL 16. The figure shows four different gears, each having a different maximum frequency for the fast PLL 14 and a different minimum frequency for the slow PLL 16. As shown, for a number of the gears, the difference between the minimum frequency and the maximum frequency monotonically increases with the amplitude of the minimum and maximum frequencies.

[0108] How the MCU 6 determines to change gears and how the update to the gear change is implemented in different embodiments will now be described. In brief, the MCU 6 determines to move up one gear in response to a determination that the fast PLL 14 has been selected for more than a predetermined duration. The MCU 6 can determine to move down one or more gears in two ways. In one embodiment, the MCU 6 determines to move down a gear in response to a determination that the slow PLL 16 has been selected for more than a predetermined amount of time. This technique is used when the second invention is implemented using a dithering scheme. In another embodiment, the MCU 6 determines to move down two gears in response to a determination that the frequency of the fast PLL 14 is equal to or less than the frequency of the slow PLL 16. This technique is implemented when the second invention is implemented using a step change scheme.

[0109] The MCU 6 determines the determination that the fast PLL 14 or the slow PLL 16 has been selected for more than a predetermined amount of time in the following manner. As described above with respect to Figure 1 the comparator 15 receives an indication of the current measured by the current meter 11. The indication is a filtered measurement of the current received from the filter circuit 13. In response to a determination that the current threshold is exceeded, the comparator 15 causes a signal to be provided on the wire(s) 32 to the clock generator circuit 12 and the MCU 6. When received at the clock generator circuit 12, the signal causes the slow PLL 16 to be selected. When the signal is de-asserted, the fast PLL 14 is again selected.

[0110] Since the MCU 6 receives the same signal on the (one or more) wires 32 that control clock selection, the MCU 6 is able to determine when the fast PLL 14 is selected and when the slow PLL 16 is selected. The MCU 6 uses this information to determine when a gear change in frequency is required. When one of the PLLs 14, 16 has been selected for more than a predetermined length of time, the MCU 6 determines that a gear change is to be performed. For example, when the fast PLL 14 has been selected for more than a predetermined amount of time (e.g., 200 microseconds), the MCU 6 can determine that the frequency of the PLLs 14, 16 will be shifted up. Similarly, when the slow PLL 16 is selected for less than a predetermined amount of time (e.g., 200 microseconds), the MCU 6 can determine that the frequency of the PLLs 14, 16 will be shifted down.

[0111] refer to Figure 10A , which shows an example process of shifting down in response to determining that the slow PLL 16 has been selected for more than a predetermined amount of time. This mechanism can be applied when the clock is jittering between the fast PLL 14 and the slow PLL 16. Figure 10A In FIG, the fast PLL frequency is represented by the dotted line, while the slow PLL frequency is represented by the solid line. Initially, the MCU 6 selects the slow PLL 16 by writing to register 23. Figure 10A At step (1) shown, the MCU 6 sends a signal on conductor 14a to adjust the frequency of the fast PLL 14 downward to the new frequency of the slow PLL 16. Thereafter, the MCU 6 deselects the slow PLL 16 by clearing register 23, thereby selecting the fast PLL 14. Figure 10A 16. In step (2) shown, the MCU 6 then sends a signal on conductor 16a to adjust the slow PLL 16 down to the new frequency of the slow PLL 16. After step (2), the MCU 6 again writes to register 23 to select the slow PLL 16. In step (3), the MCU then sends a signal on conductor 14a to adjust the fast PLL 14 to the new frequency of the fast PLL 14. The process of shifting down is completed. This technique of shifting down prevents the difference between the fast clock frequency and the slow clock frequency from exceeding a maximum value, and during the shift switching process, the clock signal Φ is provided by the one of the two PLLs 14, 16 having the lowest frequency.

[0112] although Figure 10A The example shows that the frequency of the fast PLL 14 is reduced (in step (1)) to the updated slow PLL frequency, but in other embodiments, the frequency of the fast PLL 14 can be reduced to a different frequency that is lower than the frequency of the updated fast PLL 14, but this still reduces the difference between the frequency of the fast PLL 14 and the frequency of the slow PLL 16 during the conversion process.

[0113] Note that although the fast PLL 14 is referred to as a "fast clock" throughout the description, Figure 10A As shown in the portion of the conversion process, the clock signal it generates has a lower frequency than the signal generated by the slow PLL 16. Therefore, the fast PLL 14 is not required to always output a signal at a higher frequency than the signal of the slow PLL 16, even when not downshifting.

[0114] refer to Figure 10B , which shows the process of shifting up in response to determining that the fast PLL 14 has been selected for more than a predetermined amount of time. This mechanism can be applied when the clock is dithering between the fast PLL 14 and the slow PLL 16, as well as when a step change in the fast PLL 14 frequency scheme is applied. Figure 10B In FIG, the fast PLL frequency is represented by a dotted line, and the slow PLL frequency is represented by a solid line. Initially, the MCU 6 selects the fast PLL 14. Figure 10B As shown in step (1), MCU 6 then sends a signal on lead 16a to adjust the slow PLL 16 to the new slow frequency. MCU 6 then selects the slow PLL 16 by writing to register 23. In step (2), MCU 6 then sends a signal on lead 14a to adjust the fast PLL 14 to the new fast frequency. The process of shifting up is complete.

[0115] In some cases, after the gear change occurs, the condition that caused the gear change will be eliminated. For example, the output of the fast PLL 14 is selected to exceed a predetermined amount of time (e.g., 200 microseconds). When the gear change occurs to move to a higher gear, the higher gear can cause the threshold frequency to fall between the updated fast and slow frequencies. In this case, the clock signal Φ will no longer stay on the fast PLL 16, but the system can dither between the fast and slow PLLs 14, 16, or reduce the frequency of the fast PLL 16 according to a step change scheme to properly manage the frequency of the clock signal Φ. However, if the condition is not eliminated and the clock signal Φ remains on the output of the fast PLL 14 for another predetermined amount of time (e.g., 200 microseconds), the MCU 6 can send a signal to cause a further gear change to a higher gear. The MCU 6 will continue to change gears until the condition is eliminated or until the highest gear is reached, for example, the fast PLL 14 outputs its highest possible frequency.

[0116] Referenced above Figure 10A The process for shifting down a gear when using a dithering scheme is described. Figure 11, which shows an alternative process for shifting down. In this example, the shift to a lower gear is performed in response to the frequency of the fast PLL 14 being set to be substantially equal to or less than the frequency of the slow PLL 16. This mechanism can be applied when the fast PLL 14 is gradually adjusted to provide the appropriate frequency. Figure 10A In FIG, the fast PLL frequency is represented by the dotted line, while the slow PLL frequency is represented by the solid line.

[0117] exist Figure 11 In the example shown, each gear shift involves downshifting two gears. However, in other embodiments, each gear shift may include downshifting a different number of gears.

[0118] Initially, PLLs 14 and 16 are set to a gear called gear 5. When comparator 15 detects an overcurrent event, slow PLL 16 is selected, and MCU 6 reduces the frequency of fast PLL 14 by 25 MHz. Fast PLL 14 is then selected again. If the overcurrent event persists, the process of reducing the frequency of fast PLL 14 by 25 MHz is performed again.

[0119] It can be seen that after this process is repeated so many times without eliminating the overcurrent event, the frequency of the fast PLL 14 can be reduced to the frequency of the slow PLL 16. This is caused by Figure 11 1. Upon determining that the frequency of the fast PLL 14 is the same as the frequency of the slow PLL 16, the MCU 6 implements a gear change to a lower gear. To achieve this, the fast PLL 14 is selected while simultaneously reducing the frequency of the slow PLL 16 to the slow PLL 16 frequency defined for gear 3. The slow PLL 16 is then selected while the MCU 6 increases the frequency of the fast PLL 14 to the maximum fast PLL 14 frequency for gear 3. The fast PLL 14 is then selected.

[0120] After the gear change, the overcurrent event is triggered again, causing the frequency of the fast PLL 14 to step down again. Figure 11 At point (2) shown, after gradually reducing the frequency of the fast PLL 14, the overcurrent event no longer occurs when the fast PLL 14 is selected. As a result, the fast PLL 14 can remain selected without triggering an overcurrent event.

[0121] Over time, the application's behavior may enter a more computationally intensive phase. Figure 11As shown at point (3) in FIG. 1 , this causes the frequency of the fast PLL 14 to be gradually decreased again. Once the frequency of the fast PLL 14 is equal to the frequency of the slow PLL 16 again, the MCU 6 determines to perform a gear change to gear 1 as shown in the figure. When the fast PLL 14 is selected, the frequency of the fast PLL 14 increases to the maximum frequency of gear 1 and then gradually decreases until the overcurrent event is eliminated.

[0122] In some embodiments, in addition to the comparator 15 whose output controls the up-shift gear and the down-shift gear, the PMIC 7 may include another comparator ( Figure 1 Not shown). Figure 12 , which shows an example of a PMIC 7 according to an embodiment of the second invention. The PMIC 7 includes an ammeter 11, a filter circuit 13, and a comparator 15, as shown in FIG. Figure 1 The PMIC 7 also includes another comparator 17 that receives an indication of the current measured by the ammeter 11. The current indication received by the comparator 17 is the same as the filtered output of the filter circuit 13 received by the comparator 15.

[0123] Comparator 17 has a higher threshold than comparator 15. It also has a slightly higher time constant than comparator 15. Comparator 17 can be considered an emergency comparator 17 that is triggered in response to a larger overcurrent event.

[0124] When the comparator 17 is triggered, a signal indicating so is provided to the MCU 6. This can be done via bus 30 or Figure 1 In response to receipt of the signal, the MCU 6 reduces the frequency of the fast PLL 14 and the slow PLL 14 to bring them to the lowest gear in a possible set of gears stored by the MCU 6.

[0125] In some embodiments, other devices in addition to or in place of the comparators 15, 17 may provide a signal that causes the MCU 6 to reduce the clock frequency to the lowest gear. Such a signal may be provided, for example, by an input current monitor ( Figure 1 The input current monitors (not shown) are provided to different components of the system, such as the processing unit 2, or other components that are part of the same integrated circuit as the processing unit 2. If one of these input current monitors detects a current above a threshold, it signals the MCU 6 to reduce the frequency of the fast PLL 14 and the slow PLL 16 to the lowest possible level.

[0126] The signal that causes the shift to the lowest gear can be generated by a thermistor ( Figure 1A thermistor (not shown) is provided, which is connected to or is part of the processing unit 2. The thermistor will determine whether the temperature of the processing unit 2 rises above a certain level (an overheating condition). In response to detecting such a condition, the thermistor signals the MCU 6, which causes the MCU 6 to reduce the frequency of the fast PLL 14 and the slow PLL 16 to the lowest possible gear.

[0127] In some embodiments, the maximum fast PLL 14 frequency and the minimum slow PLL 16 frequency in the lowest gear can be the same. In this case, when in the lowest gear, both the fast PLL 14 and the slow PLL 16 are fixed at the same frequency (e.g. 200 MHz). This provides a higher level of safety than having a lower gear in which the fast PLL 14 can be set to a higher frequency and is at risk of exceeding the threshold. The process of switching to the lowest gear is similar to Figure 10A the process of switching to a lower gear shown, but step (3) is eliminated from the process. Specifically, the slow PLL 16 is initially selected, and then the MCU 6 reduces the frequency of the fast PLL 14 to the frequency of the lowest gear (e.g. 200 MHz). The MCU 6 then causes the fast PLL 14 to be selected, and then reduces the frequency of the slow PLL 16 to the same frequency as the fast PLL 14 (e.g. 200 MHz). When in this lowest gear, either the slow or fast PLL 14, 16 can be selected, as they are both set to the same frequency.

[0128] The first and second inventions have been described above. In some embodiments, the first and second inventions can be combined together. Reference is made to Figure 13 which shows an example of using a combination of the jitter and gear box techniques.

[0129] Figure 13 The dashed line represents the threshold frequency, which varies with changes in application behavior. The solid line represents the frequency of the clock signal Φ. The output of the fast PLL 14 is at the maximum fast clock frequency for the current gear. The output of the slow PLL 16 is at the minimum slow clock frequency for the current gear. The graph 1300 is shown divided into three different time periods 1310, 1320, 1330, and illustrates how the PLLs 14, 16 switch between gears in response to changes in application behavior as illustrated by changes in clock frequency.

[0130] During most of the first cycle 1310, clock signal Φ switches between the output of fast PLL 14 and the output of slow PLL 16 to produce an appropriate average frequency for clock signal Φ. As shown, after a period of time, in response to changes in application behavior, the threshold frequency drops to a reduced level below the slow PLL frequency level. As a result, comparator 15 asserts its signal to indicate an overcurrent event that cannot be eliminated by remaining on slow PLL 16. MCU 6 detects that slow PLL 16 has been selected for more than a predetermined amount of time and, in response, determines to change from the currently selected gear to a lower gear. MCU 6 executes the gear change process described above.

[0131] exist Figure 13 , once the gear change process is complete, the clock generation circuit 12 changes between the outputs of the slow PLL 16 and the fast PLL 14 when the clock signal Φ is provided. This is shown during time period 1320. After a period of time, the threshold frequency increases above the frequency of the fast PLL 14 in the selected gear. As a result, the comparator 15 does not detect an overcurrent event, and the fast PLL 14 remains selected. In response to determining that the fast PLL 14 has been selected for more than a predetermined amount of time, the MCU 6 determines to increase the gear to a higher gear. The MCU 6 is described above with reference to Figure 10B The higher gear selected during time period 1330 is the same gear selected during time period 1310. However, as shown, because the threshold frequency is lower during most of period 1330, a greater proportion of time is spent in slow PLL 16 during period 1330 than during period 1310.

[0132] The power management techniques described above can be implemented to manage the power of the multi-tile processing unit 2. Figures 14 to 17 An example multi-tile processing unit 2 is described in more detail.

[0133] refer to Figure 14 , which shows an example of a multi-tile processing unit 2. The processing unit 2 includes an array 46 of multiple processor tiles 3 and interconnects 44 connecting the tiles 3. The processing unit 2 can be implemented separately as one of multiple dies packaged in the same IC package. The interconnect 44 may also be referred to herein as an "exchange fabric" 44 because it enables the tiles 3 to exchange data with each other. Each tile 3 includes a respective instance of a processor and memory. For example, for example, the processing unit 2 may include hundreds or even thousands of tiles 4. For the sake of completeness, it is also noted that the "array" referred to here does not necessarily mean any specific number of dimensions or physical layout of the tiles 4.

[0134] In an embodiment, each processing unit 2 also includes one or more external links 48 that enable the processing unit 2 to be connected to one or more other processing units (e.g., one or more other instances of the same processing unit 2). These external links 48 may include any one or more of the following: one or more processor-to-host links for connecting the processing unit 2 to a host processor, and / or one or more processor-to-processor links for connecting to one or more other instances of the processing unit 2 on the same IC package or card or on different cards. In one example arrangement, the processing unit 2 receives work from a host processor (not shown), which is connected to the processing unit via one of the processor-to-host links in the form of input data to be processed by the processing unit 2. Multiple instances of the processing unit 2 can be connected together into the card via the processor-to-processor links. Thus, depending on the workload required by the host application, the host access is constructed as a computer on a chip multi-tile system.

[0135] Interconnect 44 is configured to enable different tiles 3 in array 46 to communicate with each other. However, in addition to dependencies that may exist between threads on the same tile 3, dependencies may also exist between portions of a program running on different tiles 3 in array 46. Therefore, a technique is needed to prevent a section of code on one tile 3 from running before the data it depends on is obtained by another section of code on another tile 4.

[0136] Each tile 3 is itself a processor capable of executing instructions (code) from a local instruction memory and processing data in a local data memory. A tile 3 may include a barrel-threaded processor and corresponding instances of memory. For example, a processing unit 2 may include hundreds or even thousands of tiles 3. For the sake of completeness, it should also be noted that references to an "array" herein do not necessarily imply any specific number of dimensions or physical layout of tiles 3.

[0137] Communication between tiles 3 on a processing unit 2 occurs in a time-determined manner. However, other forms of inter-tile communication are possible. Dependencies may exist between program portions running on different tiles 3 in array 46. That is, processing data on one tile may depend on results from another tile, for example, providing results that another tile depends on. Therefore, a technique is needed to prevent a piece of code on one tile 3 from running before the data it depends on, which is then obtained by another piece of code on another tile 3.

[0138] Parallel programming models for AI and data science typically follow a three-phase iterative execution model: compute, barrier, and exchange. This means that data transfers in and out of processing units typically rely on barriers to provide data consistency between processing units and between each processing unit and the host. Commonly used data consistency models include bulk synchronous parallelism (BSP), stale synchronous parallelism (SSP), and asynchronous. The embodiments described herein use the BSP model, but other synchronization models can obviously be used as an alternative.

[0139] refer to Figure 15 and Figure 16 , which shows an implementation of a BSP exchange scheme, where each tile 3 performs a computation phase 43 and an exchange phase 42 in alternating cycles, separated from each other by barrier synchronization 40 between tiles. Figure 15 and Figure 16 In the case shown, a barrier synchronization is placed between each calculation phase 43 and the subsequent exchange phase 42 .

[0140] During the calculation phase 43, each tile 3 performs one or more computation tasks locally on the tile, but does not communicate any results of these computations with any other tile 3. In the exchange phase 42, each tile 3 is allowed to exchange one or more computation results from the previous calculation phase with one or more other tiles, but does not perform any new computations until it has received any data from other tiles 3 on which its task(s) have dependencies. It also does not send any data to any other tile other than the data computed in the previous calculation phase. It is not excluded that other operations, such as internal control related operations, may be performed in the exchange phase 42. Communication outside the tile group may optionally utilize the BSP mechanism, but alternatively may not utilize the BSP and instead use some other synchronization mechanism of its own.

[0141] According to the BSP principle, barrier synchronization 40 is placed at the juncture of the transition from computation phase 43 to exchange phase 42, or at the juncture of the transition from exchange phase 42 to computation phase 43, or both. That is, either: (a) all tiles 3 in the group are required to complete their respective computation phase 43 before any tile in the group is allowed to proceed to the next exchange phase 42, or (b) all tiles 3 in the group are required to complete their respective exchange phase 42 before any tile in the group is allowed to proceed to the next computation phase 43, or (c) both conditions are implemented. In all three variations, it is the individual tiles that alternate between phases while the entire assembly is synchronized. The sequence of exchange and computation phases can then be repeated multiple times. In BSP terminology, each repetition of the exchange phase and computation phase is sometimes referred to as a "superstep" (although note that this terminology is not always used consistently in the literature: sometimes each individual exchange phase and computation phase is individually referred to as a superstep, while elsewhere, as in the terminology adopted herein, the exchange and computation phases are collectively referred to as a superstep).

[0142] It is also noted that it is not excluded that multiple different independent tile groups 3 on the same processing unit 2 or different processing units can each form a separate corresponding BSP group that operates asynchronously with each other, with the BSP cycle of calculation, synchronization, and exchange only being performed within each given group, but each group being performed independently of the other groups. That is, the multi-tile array 46 can include multiple internal synchronization groups, each group operating independently and asynchronously with other such groups (discussed in more detail later). In some embodiments, there is a hierarchical grouping of synchronization and exchange, which will be discussed in more detail later.

[0143] Figure 16 The BSP principle is shown implemented in groups 4i, 4ii, 4iii of some or all tiles in an array 46, in this case applying: (a) barrier synchronization (see above) from the computation phase 43 to the exchange phase 42. Note that in this arrangement, some tiles 3 are allowed to start computation 43 while some other tiles are still being exchanged.

[0144] Figure 17 1 shows how clock signal Φ is distributed from clock generator circuit 12 to tiles 3 of processing unit 2. In this example, tiles 3 are shown arranged in columns. Each tile in tiles 3 is connected to copper wire 112, which provides a clock signal to each tile in tiles 3. Copper wire 112 provides a clock tree for processing unit 2. Copper wire 112 is selected to have a thickness between 0.2 microns and 2 microns. For example, copper wire 112 can be 1 micron thick and 0.5 micron wide. The high thickness of copper wire 112 reduces the insertion delay of the clock signal and allows the clock signal to propagate very quickly to each tile in tiles 3.

[0145] refer to Figure 18 , which illustrates method 1800 according to an embodiment of the first invention. It should be understood that although the steps of method 1800 are shown in a sequential order, there is some temporal overlap between the steps. Specifically, step S1810 is executed throughout the duration of method 1800 and overlaps with steps S1820 and S1830.

[0146] At S1810, the switching circuit cycles between selecting a first clock generator for clocking the processing unit and selecting a second clock generator for clocking the processing unit. The first clock generator is selected during a first portion of the cycle, and the second clock generator is selected during a second portion of the cycle. The frequency of the clock signal provided by the first clock generator is greater than the frequency of the clock signal provided by the second clock generator.

[0147] At S1820 , the switching circuit increases the average clock frequency of the processing unit by increasing a ratio between a duration of the first portion of the cycle and a duration of the second portion of the cycle.

[0148] At S1830 , the switching circuit increases the reduction in the average clock frequency of the processing unit by reducing a ratio between the duration of the first portion of the cycle and the duration of the second portion of the cycle.

[0149] refer to Figure 19 , which shows a method 1900 according to an embodiment of the second invention. It should be understood that the steps of method 1900 do not need to be performed in the order shown, and the execution of these steps can overlap in time. Specifically, steps S1910 and S1920 can be repeated at different points throughout method 1900.

[0150] At S1910 , the switching circuit is configured to switch between selecting a first clock generator for providing a processor clock signal and a second clock generator for providing a processor clock signal.

[0151] At S1920 , at least one processor accesses a plurality of settings in a memory of a system, wherein each setting includes a maximum frequency of a first clock generator for the setting and a minimum frequency of a second clock generator for the setting.

[0152] At S1930, at least one processor detects at least one condition indicating a need to increase the frequency of the clock signal.

[0153] At S1940, in response to S1930, at least one processor causes a change from the currently selected setting to a higher one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the currently selected one of the settings.

[0154] At S1950, at least one processor detects at least one condition indicating a requirement to reduce the frequency of the clock signal.

[0155] At S1960, the at least one processor causes a change from a higher one of the settings selected at S1940 to a lower one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the lower one of the settings.

[0156] It should be understood that the above embodiments are described by way of example only.

Claims

1. A method for controlling the frequency of a clock signal of a processing unit, the method comprising: Toggle between selections for: a first clock generator for providing a processing unit clock signal for executing an application; as well as a second clock generator for providing a processing unit clock signal for executing the application, wherein a frequency of the clock signal provided by the second clock generator is less than a frequency of the clock signal provided by the first clock generator; accessing a plurality of settings in a memory, wherein each setting includes a maximum frequency of a first clock generator in the setting and a minimum frequency of a second clock generator in the setting; responsive to detecting at least one condition indicating a need to increase the frequency of the clock signal, changing from a current one of the settings to a higher one of the settings, wherein the higher one of the settings has a higher maximum frequency for the first clock generator and a higher minimum frequency for the second clock generator than the current one of the settings; as well as In response to at least one condition detected indicating a need to reduce the frequency of the clock signal, change from a higher one of the settings to a lower one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the lower one of the settings.

2. The method according to claim 1, wherein For each of the settings, the frequency of the clock signal provided by the second clock generator is fixed to the minimum frequency of the second clock generator for the corresponding setting.

3. The method according to any one of claims 1 to 2, wherein The at least one condition detected indicating a need to increase the frequency of the clock signal includes a determination that the first clock generator has been selected to provide the processing unit clock signal for more than a predetermined amount of time.

4. The method according to claim 3, wherein: The detected at least one condition indicating a need to increase the frequency of the clock signal further includes determining that the frequency of the first clock generator is set to a maximum frequency of the first clock generator in a current setting.

5. The method according to any one of claims 1 to 2, wherein The at least one condition detected indicating a need to reduce the frequency of the clock signal includes a determination that the second clock generator has been selected for more than a predetermined amount of time.

6. The method according to any one of claims 1 to 2, wherein: The detected at least one condition indicating a requirement to reduce the frequency of the clock signal includes determining that the frequency of the first clock generator has been set to be equal to or less than the frequency of the second clock generator.

7. The method according to claim 6, wherein: The current one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the lower one of the settings.

8. The method according to any one of claims 1 to 2, wherein: The lower one in the setting and the current one in the setting are the same.

9. The method according to any one of claims 1 to 2, comprising: measuring a current drawn by the processing unit at a comparator to determine whether the processing unit exceeds a power budget; using an output signal from the comparator to control selection of the first clock generator and the second clock generator; receiving an output signal at a controller device; as well as The steps of detecting at least one condition indicating a need to increase the frequency of the clock signal and detecting at least one condition indicating a need to decrease the frequency of the clock signal are performed at the controller device using the output signal from the comparator.

10. The method of any one of claims 1 to 2, comprising changing to a lowest one of the settings in response to a detected overcurrent event, wherein the lowest one of the settings has lower values ​​for the minimum frequency and the maximum frequency than any other setting of the plurality of settings.

11. The method of claim 9 , comprising, in response to a detected overcurrent event, changing to a lowest one of the settings, wherein the lowest one of the settings has a lower value for the minimum frequency and the maximum frequency than any other setting of the plurality of settings, wherein The comparator used to determine whether the power budget is exceeded is a first comparator, wherein detecting an overcurrent event is performed by a second comparator, wherein the first comparator and the second comparator are different, wherein the second comparator has a higher threshold than the first comparator.

12. The method according to claim 10, wherein: For the lowest one of the settings, the minimum frequency of the second clock generator and the maximum frequency of the first clock generator are the same frequency, wherein the step of changing to the lowest one of the settings comprises: selecting a second clock generator for providing a clock signal for the processing unit; Subsequently, the frequency of the clock signal provided by the first clock generator is set to the same frequency; Then, selecting a first clock generator for providing a clock signal for the processing unit; Subsequently, the frequency of the clock signal provided by the second clock generator is set to the same frequency.

13. The method according to any one of claims 1 to 2, wherein: The gap between the minimum frequency of the second clock generator and the maximum frequency of the first clock generator of the higher one in the setting is larger than that of the current one in the setting, Therein, the difference between the minimum frequency of the second clock generator and the maximum frequency of the first clock generator is larger in the higher one of the settings than in the lower one of the settings.

14. The method according to any one of claims 1 to 2, wherein: Switching includes: selecting a first clock generator to provide a processing unit clock signal for executing an application; detecting a threshold event indicating that the application has exceeded a power budget allocated for its execution; selecting a second clock generator to provide a processing unit clock signal for executing the application; When the processing unit clock signal is provided by the second clock generator, reducing the frequency of the clock signal generated by the first clock generator; and After a predetermined time from the selection of the second clock generator, the first clock generator is reselected to provide the processing unit clock signal.

15. The method according to any one of claims 1 to 2, wherein: Switching includes: Cycles through the following choices: a first clock generator for providing a processing unit clock signal for executing an application during a first portion of a cycle; and a second clock generator for providing a processing unit clock signal for executing the application during a second portion of the cycle; increasing the average clock frequency of the processing unit by increasing the ratio between the duration of the first portion of the cycle and the duration of the second portion of the cycle; and The average clock frequency of the processing unit is reduced by reducing the ratio between the duration of the first part of the cycle and the duration of the second part of the cycle.

16. The method according to any one of claims 1 to 2, wherein: The steps for changing from a higher setting to a lower setting are: selecting a second clock generator for providing a clock signal for the processing unit; subsequently setting the frequency of the clock signal provided by the first clock generator to a frequency less than a maximum frequency of the first clock generator defined by a lower one of the settings; Then, selecting a first clock generator for providing a clock signal for the processing unit; subsequently setting the frequency of the clock signal provided by the second clock generator to the minimum frequency of the second clock generator defined by the lower one of the settings; and Subsequently, a second clock generator for providing a clock signal for the processing unit is selected.

17. The method according to claim 16, wherein The frequency less than the maximum frequency of the first clock generator is the minimum frequency of the second clock generator defined by the lower one of the settings.

18. The method of claim 16, comprising subsequently setting the frequency of the clock signal provided by the first clock generator to the maximum frequency of the first clock generator defined by the lower one of the settings.

19. The method according to any one of claims 1 to 2, wherein: The processing unit includes a plurality of processors, and the method includes distributing a processor clock signal to each of the plurality of processors along conductors of a clock tree of the processing unit.

20. The method according to claim 19, wherein The conductors are copper wires with a thickness greater than 0.2 microns.

21. A system for controlling the frequency of a clock signal of a processing unit, the system comprising: a first clock generator for providing a processing unit clock signal for executing an application; as well as a second clock generator for providing a processing unit clock signal for executing the application, wherein a frequency of the clock signal provided by the second clock generator is less than a frequency of the clock signal provided by the first clock generator; a switching circuit configured to switch between selection of a first clock generator for providing a processing unit clock signal and a second clock generator for providing a processing unit clock signal; at least one memory configured to store a plurality of settings, wherein each setting includes a maximum frequency of a first clock generator in the setting and a minimum frequency of a second clock generator in the setting; At least one processor configured to: responsive to detecting at least one condition indicating a need to increase the frequency of the clock signal, modifying the frequencies of the first clock generator and the second clock generator to change from a current one of the settings to a higher one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the current one of the settings; as well as In response to at least one condition detected indicating a need to reduce the frequency of the clock signal, the frequencies of the first clock generator and the second clock generator are modified to change from a higher one of the settings to a lower one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the lower one of the settings.

22. A computer program for execution by at least one processor of a system, the system comprising: a first clock generator for providing a processing unit clock signal for executing an application; as well as a second clock generator for providing a processing unit clock signal for executing the application, wherein a frequency of the clock signal provided by the second clock generator is less than a frequency of the clock signal provided by the first clock generator; a switching circuit configured to switch between selection of a first clock generator for providing a processing unit clock signal and a second clock generator for providing a processing unit clock signal, The computer program is configured to, when executed by at least one processor, cause a method to be performed, the method comprising: accessing a plurality of settings in a memory, wherein each of the settings includes a maximum frequency of a first clock generator in the setting and a minimum frequency of a second clock generator in the setting; responsive to detecting at least one condition indicating a need to increase the frequency of the clock signal, modifying the frequencies of the first clock generator and the second clock generator to change from a current one of the settings to a higher one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the current one of the settings; and In response to at least one condition detected indicating a need to reduce the frequency of the clock signal, the frequencies of the first clock generator and the second clock generator are modified to change from a higher one of the settings to a lower one of the settings, wherein the higher one of the settings has a higher maximum frequency of the first clock generator and a higher minimum frequency of the second clock generator than the lower one of the settings.

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