Pseudo-three-port sram data path

Abstract

A pseudo-three-port memory is provided with a read data path and a write data path. The pseudo-three-port memory includes multiple pseudo-three-port bit cells, each pseudo-three-port bit cell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and the second bit line.

Description

[0001] Priority claim according to 35 U.SC § 119

[0002] This patent application claims priority to non-provisional application No. 17 / 028,965, entitled “PSEUDO-TRIPLE-PORT SRAMDATAPATHS”, filed on September 22, 2020, which is assigned to the assignee of this patent application and is expressly incorporated herein by reference. Technical Field

[0003] This application relates to memory, and more specifically to pseudo-three-port SRAM. Background Technology

[0004] In conventional static random access memory (SRAM), during a read operation, a bit cell is connected to a pair of bit lines via a corresponding pair of access transistors. To turn on the access transistors during a read operation, a word line controller asserts the voltage of the word line connected to the gate of each access transistor. During a write operation, the controller also asserts the word line to turn on the access transistors. Therefore, the pair of access transistors and the corresponding bit lines can be considered as a single read port and a single write port for the bit cell. This pair of bit lines is shared by other bit cells and their corresponding access transistors. The resulting set of bit cells linked by their common bit line pair is typically represented as a bit cell column. Since this column has only one bit line pair, only a single read operation or a single write operation can occur each time a word line is asserted.

[0005] To accommodate applications such as video processing that require simultaneous multiple read or write operations on the same column, dual-port SRAMs have been developed. In a dual-port SRAM, each column has two pairs of bit lines. Therefore, each bit cell can have one pair of access transistors for coupling to one bit line pair in the bit line pair, and another pair of access transistors for coupling to the other bit line pair in the bit line pair. While such dual-port SRAMs can perform simultaneous read / write operations, the density of additional access transistors per bit cell is relatively low.

[0006] Therefore, there is a need in the art for multi-port memories with increased density. Summary of the Invention

[0007] According to a first aspect of this disclosure, a memory is provided, the memory comprising: a first bit line for a first column; a second bit line for the first column; the first column comprising a plurality of first bit cells, each first bit cell having a first read port coupled to the first bit line, a second read port coupled to the second bit line, and a write port coupled to the first bit line and the second bit line; a first global read bit line; a second global read bit line; a first logic gate having a first input coupled to the first bit line and an output coupled to the first global read bit line; and a second logic gate having a first input connected to the second bit line and an output coupled to the second global bit line.

[0008] According to a second aspect of this disclosure, a memory is provided, comprising: a first bit line for a first column; a second bit line for the first column; the first column comprising a plurality of first bit cells, each first bit cell having a first read port coupled to the first bit line, a second read port coupled to the second bit line, and a write port coupled to the first bit line and the second bit line; a first transmission gate having an output connected to the first bit line and an input for receiving write data bits; and a second transmission gate having an output connected to the second bit line and an input for receiving the complement of the write data bits.

[0009] According to a third aspect of this disclosure, a method for providing a pseudo three-port memory is provided, the method comprising: in a read cycle responsive to the start of a periodic memory clock signal, performing a first single-ended read of a first cell in a column via a first bit line to charge the first bit line to a power supply voltage; simultaneously performing the first single-ended read, performing a second single-ended read of a second cell in the column via a second bit line to discharge the second bit line; and in a write cycle following the read cycle, writing to the first cell via the first bit line and via the second bit line, wherein the first bit line remains charged to the power supply voltage from the end of the read cycle to the end of the write cycle, and the second bit line remains discharged from the end of the read cycle to the end of the write cycle.

[0010] These and other advantages can be better understood through the following detailed description. Attached Figure Description

[0011] Figure 1 A column of pseudo-three-port SRAM bit cells according to one aspect of this disclosure is shown.

[0012] Figure 2A This is a high-level diagram of the read data path for a MUX2 array of pseudo-three-port SRAM bit cells, according to one aspect of this disclosure.

[0013] Figure 2BThis is a high-level diagram of the write data path for a MUX2 array of pseudo-three-port SRAM bit cells according to one aspect of this disclosure.

[0014] Figure 3A This is a circuit diagram of the read port A data path of a MUX2 array of pseudo-three-port SRAM bit cells according to one aspect of this disclosure.

[0015] Figure 3B This is a circuit diagram of the read port B data path of a MUX2 array of pseudo-three-port SRAM bit cells according to one aspect of this disclosure.

[0016] Figure 4 This is a circuit diagram of the read data path and write data path of a MUX1 array for pseudo-three-port SRAM bit cells, according to one aspect of this disclosure.

[0017] Figure 5A The diagram illustrates some operating waveforms of a pseudo-three-port memory according to one aspect of this disclosure during read and write cycles, wherein power is consumed during a pre-charge period prior to a write operation.

[0018] Figure 5B The diagram illustrates some operating waveforms of a pseudo-three-port memory with reduced power consumption during a pre-charge period prior to a write operation, according to one aspect of this disclosure, during read and write cycles.

[0019] Figure 6 This is a flowchart of an operation method for a pseudo-three-port memory according to one aspect of this disclosure.

[0020] Figure 7 Some example electronic systems combining pseudo-three-port memories according to one aspect of this disclosure are shown.

[0021] The embodiments and advantages of this disclosure can be better understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more of the figures. Detailed Implementation

[0022] To address the density issues of dual-port memory, SRAM bit cells are configured with two independent word lines. The first word line drives the gate of a first access transistor for the bit cell. Similarly, the second word line drives the gate of a second access transistor for the bit cell. The first access transistor is coupled between the true output node for the bit cell and the bit line. Similarly, the second access transistor is coupled between the two's complement output node for the bit cell and the two's complement bit line.

[0023] Read operations on bit cells are single-ended because they involve only one bit line. Multiple bit cells are arranged in columns and share bit lines and two's complement bit lines. Each bit cell has its own first and second access transistors controlled by a corresponding pair of word lines. Figure 1 Example column 100 of bit cells is shown. Column 100 includes a first bit cell 105 and a second bit cell 110, but it should be understood that column 100 includes additional bit cells not shown for clarity. Each bit cell is located within its own row of other bit cells (not shown) defined by a corresponding pair of word lines. For example, bit cell 105 is arranged in the zeroth row of bit cells. Similarly, bit cell 110 is located in the first row of bit cells.

[0024] The word line WLA0 of read port A extends through the zero row and drives the first n-type metal-oxide-semiconductor (NMOS) access transistor M1 in bit cell 105. Similarly, the word line WLA0 of read port A drives the other first access transistors in the remaining bit cells (not shown) in the zero row. The word line WLB0 of read port B also extends through the zero row and drives the second NMOS access transistor M2 in bit cell 105. Similarly, the word line WLB0 of read port B drives the other second access transistors (not shown in the zero row). Since the word lines are independently controlled during read operations, the combination of the bit lines, the word line WLA0 of read port A, and the access transistor M1 forms read port A of bit cell 105. Therefore, the bit line BL can also be represented as the read port A bit line. Similarly, the combination of the two's complement bit line, the word line WLB0 of read port B, and the access transistor M2 forms read port B of bit cell 105. Therefore, the two's complement bit line BLB can also be represented as the read port B two's complement bit line.

[0025] The word lines for the first row of bit cells are similar. For example, read port A word line WLA1 extends through the first row to drive access transistor M1 in bit cell 110. Read port B word line WLB1 extends through the first row to drive access transistor M2 in bit cell 110. Therefore, bit cell 110 has a read port A derived from a combination of its access transistor M1, bit line BL, and read port A word line WLA1. Similarly, bit cell 110 has a read port B derived from a combination of its access transistor M2, two's complement bit line BLB, and read port B word line WLB1.

[0026] During a read operation on column 100, two different bit cells can be accessed simultaneously. For example, read port A in dummy location cell 105 is accessed via an assertion of the voltage of word line WLA0. Since access transistor M1 is coupled between the true (Q) output nodes of bit cell 105, when the voltage of word line WLA0 of read port A is asserted, the voltage of bit line BL will be charged correspondingly to the binary content of bit cell 105. For example, dummy location line BL is precharged to the power supply voltage for bit cell 105, and bit cell 105 stores binary one with a binary high convention. Therefore, the output node Q of bit cell 105 will be charged to the power supply voltage. During a read operation on read port A, bit line BL will therefore remain charged to the power supply voltage. However, if bit cell 105 has been storing binary zero, a read operation on read port A will cause bit line BL to discharge toward ground, while access transistor M1 is turned on.

[0027] With a read operation occurring at read port A for bit cell 105, no other bit cell (such as bit cell 110 in column 100) can be read through its read port A because there will be contention for bit decisions on bit line BL. However, for another cell in column 100, a simultaneous read operation may occur at read port B. For example, a read operation may occur through read port B in bit cell 110, while a read operation may occur simultaneously through read port A in bit cell 105. During read port B access, read port B word line WLB1 is asserted to turn on the access transistor M2 for bit cell 110. Each access transistor M2 is connected between its bit cell's two's complement output node (QB) and two's complement bit line BLB. If bit cell 110 stores binary zero, a read access through read port B will cause bit line BLB to remain charged to the supply voltage. Conversely, if bit cell 110 stores binary zero, a read access through read port B will cause bit line BLB to discharge, while its access transistor M2 turns on. Therefore, a read access via read port B will cause the two's complement bit line (BLB) to be charged according to the two's complement of the binary value stored in the accessed bit cell. Note that the same bit cell can be accessed simultaneously via read port A and read port B, although the bit decision is of course the same in this case.

[0028] Since access via one of the read ports A and B does not utilize the voltage of the remaining read port's bit line, the resulting read operation is single-ended. Therefore, an inverter and latch combination can be used as a latch-sensing amplifier for such single-ended bit decisions. It will be understood that column 100 is shown in simplified form, where bit line BL drives the global read bit line (global read bit line A) for read port A, which is not shown in the diagram for clarity. Figure 1This is shown in the diagram, but will be discussed further in this article. Similarly, the bitline BLB driver is used to read the global read bitline (global read bitline B) of port B, which is also not shown in the diagram. Figure 1 As shown in the diagram, but will be discussed further herein. A global read bit line drives a sense amplifier. For example, inverter 115 inverts the voltage of global read bit line A to drive latch 125, which latches the bit decision for a bit cell (such as bit cell 105) accessed by read port A. Similarly, inverter 120 inverts the voltage of global read bit line B to drive latch 130, which latches the bit decision for a bit cell (such as bit cell 110) accessed by read port B. Since the bit stored in bit cell 105 is inverted by inverter 115, latch 125 inverts the output of inverter 115 to provide a data output signal. In this case, since the read operation is to read port A, the resulting data output signal from latch 125 can be designated as DOUTA. In some embodiments, buffer 135 can buffer the DOUTA signal. Conversely, since read port B is driving the two's complement bit line (BLB) inverted by inverter 120, latch 130 is arranged not to invert the output of inverter 120. In this way, the output of latch 130 will be equal to the bit value (true or false) of the bit cell (such as bit cell 110) accessed by read port B. The resulting data output signal from read port B can be designated as DOUTB. In some embodiments, buffer 140 can buffer the DOUTB signal.

[0029] Since each bit cell has only two access transistors and a pair of bit lines, the resulting dual read ports A and B for the bit cells in column 100 are “pseudo-read ports.” In contrast, a bit cell with conventional dual read ports would have a pair of bit lines and a pair of access transistors for each port. Read ports A and B advantageously increase density because each bit cell can be formed by six transistors: a pair of access transistors M1 and M2 and four transistors to form a cross-coupled inverter within the bit cell.

[0030] Read operations occur during the first portion of the memory clock cycle. Write operations can occur during the remaining second portion of the memory clock cycle. Therefore, the resulting read and write operations can be described as "double-pumped" because both read and write operations occur within a single memory clock cycle. Although word line pairs for each row are controlled independently during read operations, word lines are not controlled independently during write operations. To write to a bit cell, the write driver, further discussed herein, charges the bit line pairs in a complementary manner. For example, the write driver charges bit line BL to the supply voltage and discharges the two's complement bit line BLB to ground to write binary 1 to a bit cell in a row with an asserted word line pair. Conversely, the write driver charges the two's complement bit line BLB to the supply voltage and discharges the bit line BL to ground to write binary 0 to such a bit cell. As the bit lines are correctly charged according to the written data bits, both word lines to the bit cell are charged to the supply voltage to turn on the access transistors of the bit cell. For example, assume a write operation occurs to bit cell 105. After the write driver charges the bit line pairs according to the write data bits, the word line controller asserts both the word line WLA0 of read access port A and the word line WLB0 of read access port B to write to bit cell 105. The combination of word line pairs, bit line pairs, and access transistor pairs forms the write port for the bit cell during the write operation. Therefore, bit cells such as bit cells 105 and 110 can be designated as pseudo-three-port SRAM bit cells because each such bit cell can be accessed through its read port A, read port B, and write port. For simplicity, the pseudo-three-port SRAM bit cell will be simply referred to as a "bit cell" in the following discussion.

[0031] Although write operations differ from pseudo-three-port SRAM, read operations are single-ended. As the number of rows increases, the capacitance of the bit lines in a column increases. This increased capacitance results in a longer time required for the accessed bit cell to charge (or discharge) the accessed bit line to trigger a relatively simple single-ended sense amplifier (such as inverters 115 and 120) to make a bit decision for the read operation. Therefore, it is advantageous to divide the bit cell array into groups. As defined herein, a bank refers to a subdivision of a column of bit cells such that bit cells in a column portion allocated to one bank share a global read bit line with bit cells in the same column portion allocated to an adjacent bank. For example, suppose a column of bit cells is divided into an upper bank column and a lower bank column. Therefore, there exists a global read bit line A (GRBLA) for read port A and a global read bit line B (GRBLB) for read port B, shared by the upper and lower bank columns. In some embodiments disclosed herein, multiple columns in each bank share a pair of global read bit lines. Specifically, it is assumed that the two columns in each memory bank also share a pair of global read bit lines. The two columns in each memory bank are therefore multiplexed onto a pair of global read bit lines, depending on which column and memory bank is accessed and which read port is accessed. Since the resulting multiplexer selects between two columns, such a memory embodiment is referred to herein as "MUX2". Note that the MUX2 multiplexer selects not only between adjacent columns in a memory bank but also from corresponding column pairs in adjacent memory banks. On the other hand, if each column in a memory bank does not share its global read bit lines with adjacent columns of the memory bank, multiplexing to a shared pair of global read bit lines still exists between the same columns in adjacent memory banks. Such a memory embodiment is referred to herein as "MUX1".

[0032] The read data path is formed from the bit cell through the accessed bit line to the corresponding global read bit line. Therefore, there are read data paths for the MUX1 array and read data paths for the MUX2 array. Similarly, there are write data paths from the write driver through the accessed pair of bit lines to the bit cell. Regardless of whether the array is MUX1 or MUX2, the write data paths can be substantially the same.

[0033] The read and write data paths for the MUX2 array will now be discussed in more detail. Figure 2AThe diagram illustrates some example read data paths for a MUX2 array 200. The MUX2 array 200 is divided into an upper memory bank and a lower memory bank. Therefore, each bit line for the upper memory bank can be designated as an upper parting line, and each bit line for the lower memory bank can be designated as a lower parting line. For clarity, only two columns are shown for the upper and lower memory banks: column zero and column one. The bit lines in column zero of the upper memory bank are designated as upper parting line 0 (UBL0) and upper complement bit line 0 (UBLB0). The bit lines in column one of the upper memory banks are designated as upper parting line 1 (UBL1) and upper complement bit line 1 (UBLB1). Similarly, the bit lines in column zero of the lower memory bank are designated as lower parting line 0 (LBL0) and lower complement bit line 0 (LBLB0). Finally, the bit lines of the first column in the lower memory are designated as lower part bit line 1 (LBL1) and lower complement bit line 1 (LBLB1).

[0034] recall Figure 1 The bit lines BL in column 100 form part of the read port A for each bit cell, while the two's complement bit lines in column 100 form part of the read port B for each bit cell. See again. Figure 2A Bit lines UBL0 and LBL0 are therefore part of the read port A of their corresponding bit cells. Similarly, bit lines UBL1 and LBL1 are part of the read port A of their corresponding bit cells. All these "read port A associated" bit lines can drive the global read bit line A (GRBLA), depending on the memory bank / column addressed for read port A access. For example, multiplexer 205 selects between the UBL0 and UBL1 bit lines based on the upper column address (column U address). If the upper column address is directed to read port A in column 0, multiplexer 205 selects the UBL0 bit line to drive the global read bit line A. Conversely, if the upper column address is directed to read port A in column 1, multiplexer 205 selects the UBL1 bit line to drive the global read bit line A.

[0035] Multiplexer 210 is similar to multiplexer 205: when these columns are determined by the lower column address (L column address), multiplexer 210 selects between the read port A related bit lines of the lower memory in column zero and column one. If the lower column address is directed to read port A in column zero, multiplexer 210 selects the LBL0 bit line to drive global read bit line A. Conversely, if the lower column address is directed to read port A in column one, multiplexer 210 selects the LBL1 bit line to drive global read bit line A.

[0036] The selection of bit lines for the Global Read Bit Line B (GRBLB) is similar. For example, multiplexer 215 selects between the UBLB0 and UBLB1 bit lines based on the upper column address (column U address). If the upper column address is directed to read port B in column 0, multiplexer 215 selects the UBLB0 bit line to drive the Global Read Bit Line B. Conversely, if the upper column address is directed to read port B in column 1, multiplexer 215 selects the UBLB1 bit line to drive the Global Read Bit Line B.

[0037] Multiplexer 220 is similar to multiplexer 21: when these columns in the lower memory are addressed as determined by the lower column address, multiplexer 220 selects between the relevant bit lines of read port B in column zero and column one. If the lower column address is directed to read port B in column zero, multiplexer 220 selects the LBLB0 bit line to drive the global read bit line B. Conversely, if the lower column address is directed to read port B in column one, multiplexer 220 selects the LBLB1 bit line to drive the global read bit line B.

[0038] The write data path for the MUX2 array is as follows: Figure 2B As shown. Depending on which bank and column are addressed during the write operation, the write data bits (WD) and the two's complement write data bits (WDB) pass through the corresponding pass gate. The pass gate acts as a column multiplexer to allocate the write data bits WD and the two's complement write data bits WDB to the addressed bank and column. For example, if the upper column address (column U address) is addressed to the zeroth column in the upper bank, pass gate 225 is open, causing the write data bits WD to drive the UBL0 bit line and the two's complement write data bits WDB to drive the UBLB0 bit line. Conversely, if the upper column address is addressed to the first column in the upper bank, pass gate 235 is open, causing the write data bits WD to drive the UBL1 bit line and the two's complement write data bits WDB to drive the UBLB1 bit line.

[0039] The write data path to the lower memory bank is similar. For example, if the lower column address (L: column address) is addressed to the zeroth column in the lower memory bank, pass gate 230 is opened, causing the write data bit WD to drive the LBL0 bit line and the two's complement write data bit to drive the LBLB0 bit line. Conversely, if the lower column address is addressed to the first column in the lower memory bank, pass gate 240 is opened, causing the write data bit WD to drive the LBL1 bit line and the two's complement write data bit WDB to drive the LBLB1 bit line.

[0040] The MUX2 data path used to drive global read bit line A (GRBLA) is in Figure 3A This is shown in more detail below. For clarity, Figure 3AOnly the data path for read port A is shown. Before the read operation, a precharge circuit (not shown) precharges the global read bit line A to the supply voltage. Logic gates such as the first NAND gate (NAND1) receive the zeroth column of the read port A bit line UBLA. and LBLA <0> The NAND1 logic gate is powered by a PMOS switching transistor P3, which is controlled by a low-level active-low column 0 read port A address (column 0 port A). This low-level active-low column 0 read port A address is asserted when a read operation addresses the read port A of column 0 in both the upper and lower memory banks. As defined herein, a signal is considered "asserted" if it is logically true, regardless of whether the logically true state is represented by an active-high or active-low convention. In the active-high convention, the signal is asserted by being charged to the supply voltage. In the active-low convention, the signal is asserted by being discharged to ground.

[0041] If the column 0 port A address signal is true, transistor P3 is turned on. The source of transistor P3 is connected to the node of the power supply voltage. The drain of transistor P3 is connected to the power node of the NAND1 logic gate. The assertion of the column 0 port A address signal thus powers on the NAND1 logic gate. If the column 0 port A address signal is not asserted, the NAND1 logic gate is powered off, and its output node 305 is thus floating. Output node 305 is coupled to ground through NMOS transistor M5, which has a source bonded to ground and a drain connected to output node 305. The column 0 port A address signal drives the gate of transistor M5. If the column 0 port A address signal is false, transistor M5 thus turns on to ground output node 305.

[0042] Output node 305 is connected to the gate of NMOS transistor M6, which has a source connected to ground and a drain connected to the global read port A bit line (GRBLA). If the column 0 port A address signal is false, output node 305 is grounded, causing transistor M6 to be turned off. Therefore, the global read port A bit line will remain in its default precharge state. However, it is assumed that the UBLA is accessing a binary zero value. <0> Or LBLA <0> A read port A operation occurs on the bit line. Since the read operation is performed through one of these column 0 read port A data paths, the column 0 port A address signal will be true, energizing the NAND1 logic gate and turning off transistor M5. The resulting zero on one bit line of the NAND1 logic gate causes the NAND1 logic gate to charge output node 305 to the supply voltage. This charging of output node 305 turns on transistor M6 to ground the global read bit line A. Therefore, the global read bit line A voltage will be discharged to represent a zero read from any read port A data path active in the column 0 of the upper and lower memory banks.

[0043] Conversely, assume there is an access to read port A of the zeroth column in both the upper and lower memory banks, where the accessed bit cell stores a binary value. In this case, bit line UBLA... <0> and LBLA <0> The transistors remain in their pre-charged state and are therefore charged to the supply voltage. In response, the NAND1 logic gate grounds output node 305, causing transistor M6 to remain off. Therefore, the global read bit line A remains charged to the supply voltage to correctly represent the binary value read from the accessed bit cell.

[0044] The read data path for accessing the first column of the upper and lower memory banks is similar. For example, the NAND gate (NAND2) receives the upper part line UBLA. <1> and lower part line LBLA <1> PMOS transistor P4 is coupled between the power node for the NAND2 logic gate and the power node for the supply voltage. When accessing read port B for the first column in the upper and lower memory banks, the column 1 port A address signal, which is active low, is asserted on the gate of transistor P4. Therefore, the NAND2 logic gate will be powered on in response to the assertion of the column 1 port A address signal. If bit line UBLA... <1> and LBLA <1> If a bit cell being accessed is discharged due to reading a binary zero from the accessed bit cell, then the output node 310 of the NAND2 logic gate will be charged to the supply voltage. Output node 310 is connected to the gate of an NMOS transistor M7, which has a source connected to ground and a drain connected to the global read bit line B. Transistor M7 will therefore respond to the bit line UBLA. <1> and LBLA <1> One of the bit lines is turned on to read the binary zero value so as to discharge the global read bit line B.

[0045] If bit line UBLA <1> and LBLA <1> A read operation on a bit line accessed reads a binary one value, and the NAND2 logic gate discharges its output node 310. Transistor M7 thus remains off, allowing the global read bit line B to remain charged to the supply voltage to represent the result of the binary one read operation. Similar to transistor M5, NMOS transistor M8 has a source connected to ground and a drain connected to output node 310. The column 1 port A address signal drives the gate of transistor M8. If read port B is not active for the first column of the upper memory bank and the first column of the lower memory bank, the column 1 port A address signal is false, and therefore transistor M8 is turned on to ground output node 310 and ensure that transistor M7 remains off. Figure 3A The MUX2 data reading path shown is... Figure 2A Comparing the paths shown, it can be seen that the set of NAND1 logic gates, transistors P3, M5, M6, M7, M8, NAND2 logic gates, and transistor P4 is used as multiplexers 1105 and 1110 to select between the read port A bit lines to drive the global read bit line A.

[0046] The data path for reading port B is as follows Figure 3B As shown, and similar to the data path read from read port A. For clarity, the data path for read port A is not shown in... Figure 3B As shown in the diagram. The zeroth column is the B bit line (UBLB) for reading from the upper memory bank. <0> ) and the zeroth column for reading the lower memory B (LBLB) <0> This can drive a NAND gate (NAND3), which is similar to a NAND1 gate: the NAND3 is coupled to the analog of transistors P3, M5, and M6 to drive the global read bit line B. Specifically, the NAND3 gate is powered by a PMOS switching transistor P9, which is controlled by a low-level active zero column read port B address (column 0 port B). This low-level active zero column read port B address is asserted when a read operation is addressed to the zero column read port B in both the upper and lower memory banks.

[0047] If the column 0 port B address signal is true, transistor P9 is turned on. The source of transistor P9 is connected to the node corresponding to the supply voltage. The drain of transistor P9 is connected to the power node corresponding to the NAND3 logic gate. The assertion of the column 0 port B address signal thus powers on the NAND3 logic gate. If the column 0 port B address signal is not asserted, the NAND3 logic gate is powered off, and its output node 315 is thus floated. Output node 315 is coupled to ground through NMOS transistor M13, which has a source bonded to ground and a drain connected to output node 315. The column 0 port B address signal drives the gate of transistor M13. If the column 0 port B address signal is false, transistor M13 thus turns on to ground output node 315.

[0048] Output node 315 is connected to the gate of NMOS transistor M14, which has a source connected to ground and a drain connected to the global read port B bit line (GRBLB). If the column 0 port B address signal is false, output node 315 is grounded, causing transistor M14 to be turned off. Therefore, the global read port B bit line will remain in its default precharge state. However, it is assumed that the UBLB is accessing a binary zero value. <0> Or LBLB <0> A read port B operation occurs on the bit line. Since the read operation is performed through one of these column 0 read port B data paths, the column 0 port B address signal will be true, energizing the NAND3 logic gate and turning off transistor M13. The resulting zero on one of the bit lines of the NAND3 logic gate causes the NAND3 logic gate to charge output node 315 to the supply voltage. This charging of output node 315 turns on transistor M14 to ground the global read bit line B. Therefore, the global read bit line B voltage will be discharged to represent a zero read from any read port B data path active in the column 0 of the upper and lower memory banks.

[0049] Conversely, assume there is a read port B access to the zeroth column in both the upper and lower memory banks, where the accessed bit cell stores a binary value. In this case, bit line UBLB... <0> and LBLB <0> The transistors remain in their pre-charged state and are therefore charged to the supply voltage. In response, the NAND3 logic gate grounds output node 315, causing transistor M14 to remain off. Therefore, the global read bit line B remains charged to the supply voltage to correctly represent the binary value read from the accessed bit cell.

[0050] The read data paths for accessing the first column of the upper and lower memory banks via read port B are similar. For example, the NAND gate (NAND4) receives the upper part line UBLB. <1> and the lower part line LBLB <1> PMOS transistor P10 is coupled between the power node for the NAND4 logic gate and the power node for the supply voltage. When accessing read port B for the first column in the upper and lower memory banks, a low-level active column 1 port B address signal is asserted on the gate of transistor P10. Therefore, the NAND4 logic gate will be powered on in response to the assertion of the low-level active column 1 port B address signal. If bit line UBLB <1> and LBLB <1> If a bit line being accessed is discharged due to reading a binary zero from the accessed bit cell, then the output node 320 of the NAND4 logic gate will be charged to the supply voltage. Output node 320 is connected to the gate of an NMOS transistor M15, which has a source connected to ground and a drain connected to the global read bit line B. Transistor M15 will therefore respond to the reading through bit line UBLB. <1> and LBLB <1> One of the bit lines is turned on to read the binary zero value so as to discharge the global read bit line B.

[0051] If the bit line UBLB <1> and LBLB <1> A read operation on a bit line accessed reads a binary value of 1, and the NAND4 logic gate discharges its output node 320. Transistor M15 is therefore kept off, allowing the global read bit line B to remain charged to the supply voltage to represent the result of the binary read operation. Similar to transistor M5, NMOS transistor M16 has a source connected to ground and a drain connected to output node 320. The column 1 port B address signal drives the gate of transistor M16. If read port B is not active for the first column of the upper memory bank and the first column of the lower memory bank, the column 1 port B address signal is false, and therefore transistor M16 is turned on to ground output node 320 and ensure that transistor M15 remains off.

[0052] Figure 4 The image shows the read data path for a MUX1 array with upper and lower memory banks. Because... Figure 4The data is routed to the MUX1 array, therefore only the zeroth column of the upper and lower memory banks is shown, as the read data path is similar for the remaining columns. The zeroth column in the upper memory bank includes the read port A bit line (UBLA). <0> and read port B bit line UBLB <0> Similarly, the zeroth column in the lower memory bank includes the read port A bit line (LBLA). <0> ) and read port B bit line (LBLB) <0> Read port A bit line UBLA. <0> and LBLA <0> A NAND gate (NAND5) drives the gate of an NMOS transistor M10, which in turn drives the gate of the NMOS transistor M10, which has a source connected to ground and a global read bit line (GRBLA) connected to the read port A of column zero. <0> The drain of the NAND gate is the read port A. If a binary zero is read from read port A, the NAND5 gate turns on transistor M10 to discharge the global read bit line A of column 0. However, if a binary one is read from read port A, transistor M10 turns off, keeping the global read bit line A of column 0 charged to the supply voltage to reflect a successful read of the binary one value. The analog NAND gate (NAND6) discharges the global read bit line UBLB of read port B. <0> and LBLB <0> A NAND signal is generated to drive the gate of NMOS transistor M12. Transistor M12 is similar to transistor M10 and therefore has a source connected to ground and a global read bit line (GRBLB) connected to the read port B of column zero. <0> The drain of port B. Therefore, accessing port B is similar to accessing port A.

[0053] The write data path for the MUX1 array is also as follows Figure 4As shown. The write data path to the zeroth column in the upper memory bank occurs through a pair of transmission gates T1 and T2. Transmission gate T1 is formed by a parallel combination of NMOS transistor M9 and PMOS transistor P5. The write data bit WD drives transmission gate T1. Similarly, transmission gate T2 is formed by a parallel combination of NMOS transistor M11 and PMOS transistor P8. The two's complement write data bit WDB drives transmission gate T2. The zeroth column (UWM) <0> The upper memory bank is written with multiplexer signals and their complement (UWMB). <0> Control transmission gates T1 and T2 to determine whether they are open or closed. (UWM) <0> This is a high-level active signal, asserted when a write operation is initiated to the zeroth column of the upper memory bank. UWMB <0> It's UWM <0> The complement of UWM. <0> The gates of driving transistors M9 and M11. Similarly, UWMB <0> The gates of transistors P5 and P8 are driven. Therefore, when UWM <0> When asserted, transmission gates T1 and T2 are closed (conducted), causing the write bit signal WD to control UBLA. <0> The voltage of the bit line, and causes the two's complement write bit signal WDB to control UBLB. <0> The voltage of the bit line. Conversely, if UWM <0> If the assertion is canceled, then transmission gates T1 and T2 are disconnected (not conducting).

[0054] The write data paths to the bit lines of the lower memory in column zero are formed by a pair of transmission gates, similar to transmission gates T1 and T2, that receive the same write data bit and its complement. The lower memory write multiplexing signal controls whether this pair of lower memory transmission gates is closed or open. If the write operation is to column zero of the lower memory, the pair of lower memory transmission gates will be closed, causing the write data bit WD to control LBLA. <0> The voltage of the bit line, and enables the WDB control of the two's complement write data bit LBLB. <0> The voltage of the line.

[0055] Refer again Figure 2B Note that the MUX2 write data path can be similar because write access uses two bit lines from the column being accessed. Therefore, there will be a pair of transmit gates for each column in the upper or lower memory bank. For example, transmit gate 225 can be formed by two transmit gates, transmit gate 230 can be formed by two transmit gates, and so on. Since two columns are multiplexed, the common write data bit WD and its complement WDB will drive the resulting four pairs of transmit gates. Depending on which column is to be written, a pair of transmit gates for that column will close, allowing a write operation to occur on the appropriate column.

[0056] Regardless of whether the array is a MUX1 or MUX2 array, the bit lines can be precharged before the read operation. Because this precharging is implemented independently of MUX1 / MUX2, it is possible to... Figure 4Only the precharge transistor of the zeroth column of the lower memory bank is shown. Read port A bit line LBLA. <0> It can be precharged by a PMOS transistor P6, which has a source connected to the power node and a terminal connected to the LBLA. <0> The drain of the bit line. Low-level active precharge signal (IprechargeA) <0> The gate of transistor P6 is driven. During the precharge period before the read operation, the precharge signal IprechargeA... <0> It is asserted that transistor P6 is turned on to turn on LBLA <0> The bit line is charged to the supply voltage. Similarly, the bit line LBLB is read from port B. <0> It can be precharged by a PMOS transistor P7, which has a source connected to the power node and a terminal connected to LBLB. <0> The drain of the bit line. Low-level active precharge signal (IprechargeB) <0> The gate of transistor P7 is driven. During the precharge period before the read operation, the precharge signal IprechargeB... <0> It is asserted that transistor P6 is turned on to switch LBLB. <0> The bit lines are charged to the supply voltage. It should be understood that the remaining columns in the MUX1 and MUX2 implementations can be pre-charged similarly using a pair of transistors, such as those discussed with respect to transistors P6 and P7.

[0057] Some example operating waveforms of the MUX1 or MUX2 array are as follows: Figure 5A As shown. Below is... Figure 5A The discussion will also refer to Figure 1 Column 100. The memory clock signal CLK is asserted at time t0 to begin a read cycle within one period of the memory clock signal CLK, followed by a write cycle. From time t1 to time t2, the read port A word line WLA0 of row zero is asserted. In this example, dummy positioning unit 105 stores binary one, causing the Q output node of bit unit 105 to be charged to the power supply voltage. Therefore, bit line BL remains charged to the power supply voltage at time t2. During the same word line assertion period from time t1 to time t2, the read port B word line WLB1 is asserted to perform a read port B access to bit unit 110. In this example, dummy positioning unit 110 also stores binary one, causing its QB output node to be discharged to ground. Therefore, the two's complement bit line BLB is discharged at time t2. Therefore, the DOUTA data output signal of read port A is binary one at time t3. Similarly, the DOUTB data output signal of the read port B is also binary one at time t3 because bit cell 110 stores the binary one value.

[0058] Then, a write operation to bit cell 105 occurs at time t4. Before time t3, the column write multiplexed signal UWM is asserted, causing its complement UWMB to be deasserted. The write bit signal WD is binary zero, therefore the complement write bit signal WDB is binary one. Note that, apart from that generated by the write driver, there is no separate precharge for the bit lines B1 and BLB for the write operation. This contrasts with conventional memory where all bit line pairs are precharged before the write operation. Since the write operation precharge is only generated by passing through... Figure 4 The write drivers of transmission gates T1 and T2 cause this, so if there is no binary change in the bit line from a read operation to a write operation, this results in power saving. Figure 5A In this context, the write bit signal WD is the complement of the DOUTA data output signal from the read operation, causing line BL to be discharged from its charged state and the complement bit line BLB to be charged from its discharged state. Therefore, there is no power saving during the bit line pre-charging period from time t2 to time t4. As previously mentioned, the write operation is two-ended (or differential), causing both word lines WLA0 and WLB0 of bit unit 105 to be asserted during the write operation from time t4 to time t5.

[0059] and Figure 5A The read operation is the opposite of the write operation, such as... Figure 5B As shown, power saving occurs during the pre-charge period of the bit line. In this example, the clock signal CLK is asserted again at time t0 to begin the read and write cycles. Again, spurious positioning cells 105 and 110 store a binary one value. (See also: Regarding...) Figure 5A The discussed accesses to read port A of alignment unit 105 and read port B of alignment unit 110 occur from time t1 to time t2. Therefore, in Figure 5B At time t2, due to the binary value stored in bit cell 105, bit line BL is charged to the power supply, while due to the reading of the binary value stored in bit cell 110, the two's complement bit line BLB is discharged. Therefore, both the DOUTA and DOUTB data output signals go high at time t3. However, in... Figure 5B In the sequence, the write data bit WD is binary one before time t2, making the two's complement write data bit WDB binary zero. Therefore, the write drive of bit lines BL and BLB that occurs after time t2 when the column write multiplexer signal UWM is asserted is the same as the binary state of these bit lines that occurs after the read operation. When the word line is asserted... Figure 5B The write drive on the bit lines between time t2 and time t4 consumes virtually no power because the bit line voltage remains constant: bit line BL remains charged and the complementary bit line BLB remains discharged. Between time t4 and time t5, the port A word lines WLA0 and WLB0 are asserted to complete the write operation.

[0060] The read port A to each pseudo-triple-port bit cell disclosed herein can also be referred to as the first read port. Similarly, the read port B to each pseudo-triple-port bit cell can also be referred to as the second read port. Referring again to column 100, the bit line BL of read port A can also be referred to as the first read bit line. Similarly, the bit line BLB of read port B can also be referred to as the second read bit line. Given these first and second read port terms, it can be understood that each pseudo-triple-port bit cell can be considered as having a first read port coupled to the first bit line, a second read port coupled to the second bit line, and a write port coupled to both the first and second bit lines.

[0061] Global read bit line A can also be represented as the first global read bit line. Similarly, global read bit line B can also be represented as the second global read bit line. A NAND1 logic gate can then be represented as a first logic gate having an input coupled to the first bit line and an output coupled to the first global read bit line. A NAND5 logic gate is another example of such a first logic gate. A NAND3 logic gate can also be represented as a second logic gate having an input connected to the second bit line and an output coupled to the second global bit line. A NAND6 logic gate is another example of a second logic gate.

[0062] Given the first line terminology and the second line terminology, now refer to Figure 6 The flowchart describes a method for a pseudo three-port memory. The method includes a read cycle in response to the start of a cycle memory clock signal, comprising an action 600 of performing a first single-ended read of the first cell in the column via the first bit line to charge the first bit line to the supply voltage. The charging of the bit line BL during the word line assertion period from time t1 to time t2 is also described. Figure 5B An example of such a first single-ended read is shown. The method also includes an action 605 occurring during the first single-ended read, which includes performing a second single-ended read of the second bit cell in the column via the second bit line to discharge the second bit line. Regarding the discharge of the two's complement bit line BLB from time t1 to time t2, in Figure 5B An example of such a second single-ended read is shown. Finally, the method includes action 610 occurring in a write cycle following a read cycle, action 610 including writing to the first cell via a first bit line and via a second bit line, wherein the first bit line remains charged to the power supply voltage from the end of the read cycle to the end of the write cycle, and the second bit line remains discharged from the end of the read cycle to the end of the write cycle. Figure 5B An example of such a write operation is shown, in which the bit line voltages of bit lines BL and BLB do not change from time t2 to time t5.

[0063] The pseudo-three-port memory disclosed in this paper can be incorporated into various electronic systems. For example, such as Figure 7 As shown, cellular phone 700, laptop 705, and tablet computer 710 can all include a pseudo-triple-port memory with a data path according to this disclosure. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, can also be configured with a pseudo-triple-port memory with a data path constructed according to this disclosure.

[0064] As will now be recognized by those skilled in the art, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the devices disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments shown and described herein, as they are given merely as examples, and the scope of this disclosure should be fully proportionate to the scope of the appended claims and their functional equivalents.

Claims

1. A memory, comprising: The first line used for the first upper column; The second bit line used for the first upper column; The first upper column includes a plurality of first bit units, each first bit unit having a first read port coupled to the first bit line, a second read port coupled to the second bit line, and a write port coupled to the first bit line and the second bit line; The first line used for the first bottom column; The second bit line used for the first lower column; The first lower column includes a plurality of second bit units, each second bit unit having a first read port coupled to the first bit line for the first lower column, a second read port coupled to the second bit line for the first lower column, and a write port coupled to the first bit line and the second bit line for the first lower column. First global read bit line; Second global read bit line; A first logic gate has a first input coupled to the first bit line for the first upper column, a second input coupled to the first bit line for the first lower column, and an output coupled to the first global read bit line. as well as The second logic gate has a first input coupled to the second bit line for the first upper column, a second input coupled to the second bit line for the first lower column, and an output coupled to the second global read bit line.

2. The memory according to claim 1, further comprising: Power nodes used for power supply voltage; A first transistor coupled between the power node of the first logic gate and the power supply node, wherein the first transistor is configured to turn on in response to an assertion of a first address signal for the first upper column, the first lower column and the first global read bit line.

3. The memory according to claim 2, wherein the first transistor is a PMOS transistor.

4. The memory according to claim 2, further comprising: A second transistor coupled between the power node of the second logic gate and the power supply node, wherein the second transistor is configured to turn on in response to an assertion of a second address signal for the first upper column, the first lower column and the second global read bit line.

5. The memory according to claim 4, wherein the second transistor is a PMOS transistor.

6. The memory of claim 3, wherein the first upper column is included in an upper memory bank, the upper memory bank further comprising: Used for the first line of the second upper column; The second bit line used for the second upper column; The second upper column includes a plurality of third bit units, each third bit unit having a first read port coupled to the first bit line for the second upper column, a second read port coupled to the second bit line for the second upper column, and a write port coupled to the first bit line for the second upper column and the second bit line for the second upper column. as well as A third logic gate has a first input coupled to the first bit line for the second upper column and an output coupled to the first global read bit line.

7. The memory of claim 6, wherein the first lower column is included in a lower memory bank, the lower memory bank further comprising: The first line used for the second bottom column; The second bit line used for the second lower column; The second lower column includes a plurality of fourth bit units, each fourth bit unit having a first read port coupled to the first bit line for the second lower column, a second read port coupled to the second bit line for the second lower column, and a write port coupled to the first bit line for the second lower column and the second bit line for the second lower column. as well as A fourth logic gate has a first input coupled to the second bit line for the second upper column and a second input coupled to the second bit line for the second lower column. The third logic gate further includes a second input coupled to the first bit line used for the second lower column.

8. The memory according to claim 3, further comprising: The first NMOS transistor has a gate coupled to the output of the first logic gate and a drain coupled to the first global read bit line.

9. The memory according to claim 8, further comprising: The second NMOS transistor has a drain coupled to the output of the first logic gate and a source coupled to ground, and is configured to turn on in response to a deassertion of the first address signal for the first upper column, the first lower column and the first global read bit line.

10. The memory according to claim 1, further comprising a plurality of word line pairs corresponding to the plurality of first-bit units, each word line pair comprising a first read port word line and a second read port word line.

11. The memory of claim 10, wherein the first bit cell includes a first access transistor coupled to the first bit line for the first upper column and a second access transistor coupled to the second bit line for the first upper column.

12. The memory according to claim 1, further comprising: A first sensing amplifier has an input coupled to the first global readout bit line; as well as The second sensing amplifier has an input coupled to the second global readout bit line.

13. The memory of claim 12, wherein the first sensing amplifier is a first inverter and the second sensing amplifier is a second inverter.

14. The memory of claim 7, wherein the first logic gate is a first NAND gate, the second logic gate is a second NAND gate, the third logic gate is a third NAND gate, and the fourth logic gate is a fourth NAND gate.

15. The memory of claim 1, wherein the first logic gate is a first NAND gate, and the second logic gate is a second NAND gate.

16. The memory of claim 15, further comprising: The first NMOS transistor has a source coupled to ground, a drain coupled to a first global read bit line, and a gate coupled to the output of the first NAND gate; as well as The second NMOS transistor has a source coupled to ground, a drain coupled to a second global read bit line, and a gate coupled to the output of the second NAND gate.

17. The memory according to claim 1, further comprising: A first transmission gate has an output coupled to the first bit line for the first upper column and an input for receiving written data bits; as well as The second transmission gate has an output coupled to the second bit line for the first upper column and an input for receiving the complement of the written data bits.

18. The memory of claim 17, wherein both the first transmission gate and the second transmission gate are configured to close in response to an assertion of a write multiplexed address signal.

19. The memory of claim 1, wherein the memory is included within a cellular phone.

20. A method for a memory comprising an upper column and a lower column, the method comprising: During a read cycle that begins in response to the start of a period of the memory clock signal, a first single-ended read of the first cell in the upper column is performed via the first bit line to charge the first bit line to the power supply voltage. While performing the first single-ended read, a second single-ended read of the second bit cell in the upper column is performed through the second bit line to discharge the second bit line; Based on the single-ended read of the first bit unit, a first global read bit line is driven by a first logic gate with a first bit decision, wherein the first logic gate has a first input coupled to the first bit line for the upper column, a second input coupled to the first bit line for the lower column, and an output coupled to the first global read bit line. Based on the single-ended read of the second bit unit, a second global read bit line is driven by a second bit decision through a second logic gate, wherein the second logic gate has a first input coupled to the second bit line for the upper column, a second input coupled to the second bit line for the lower column, and an output coupled to the second global read bit line; as well as In the write cycle following the read cycle, the first bit cell is written to via the first bit line for the upper column and via the second bit line for the upper column, wherein the first bit line for the upper column remains charged to the power supply voltage from the end of the read cycle to the end of the write cycle, and the second bit line for the upper column remains discharged from the end of the read cycle to the end of the write cycle.

21. The method of claim 20, further comprising: During the read cycle, an assertion is made that the first word line coupled to the first bit cell is simultaneously de-asserted that the second word line coupled to the first bit cell; as well as During the read cycle, an assertion is made that the second word line coupled to the second bit cell is simultaneously decoupled from the first word line coupled to the second bit cell.

22. The method of claim 21, further comprising: During the write cycle, assert the first word line coupled to the first bit cell; as well as During the write cycle, the second word line coupled to the first bit cell is asserted.

23. The method of claim 20, wherein both the read cycle and the write cycle occur during a single cycle of the memory clock signal.

24. The method of claim 20, further comprising: The first bit decision is formed by reversing the voltage applied to the first bit line for the upper column; as well as The second bit decision is formed by reversing the voltage applied to the second bit line for the upper column.

25. The method of claim 20, wherein the first logic gate comprises a first NAND gate, and the second logic gate comprises a second NAND gate. The first global read bit line is driven by the first bit decision, which includes: The voltage of the first bit line for the upper column is processed by the first NAND gate, and The second global read bit line is driven by the second bit decision, which includes processing the voltage of the second bit line for the upper column through the second NAND gate.

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