Iii-v semiconductor-on-insulator integrated photonic devices and methods of making the same

Abstract

The application relates to an integrated photonic device of III-V semiconductor on insulator and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method of the integrated photonic device of III-V semiconductor on insulator comprises the following steps: growing an epitaxial layer based on III-V semiconductor material on a first wafer, performing pattern treatment on the epitaxial layer to form a micro-nano pattern, so as to obtain a patterned optical waveguide device layer; depositing a first optical medium layer on the optical waveguide device layer as a cladding layer of the waveguide device; and bonding the first optical medium layer with a second wafer to form a heterogeneous integrated wafer. The epitaxial layer of III-V semiconductor material grown in advance is subjected to pattern treatment to form an optical waveguide device layer, and then bonding treatment is performed, so that the subsequent bonding operation can avoid affecting the pattern treatment of the epitaxial layer, and thus the yield of the optical waveguide device on the heterogeneous integrated wafer can be improved, and the integration degree of the optical waveguide device on the heterogeneous integrated wafer can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an integrated III-V semiconductor photonic device on an insulator and a preparation method thereof. BACKGROUND

[0002] On-chip optical modulator is the core device in integrated optical communication chips. All-optical modulator based on nonlinear optics has the advantages of large channel capacity, fast response speed, and no need for electro-optical conversion, which is expected to further reduce the energy consumption of optical communication and improve the bandwidth of optical communication. The refractive index of III-V semiconductor material is large, which can provide strong binding ability to the optical mode field. The on-chip all-optical modulation device based on III-V semiconductor material has smaller power threshold, higher modulation rate and more compact device area, and has great application prospect in the field of optical communication.

[0003] The traditional semiconductor epitaxial structure lacks effective binding on the longitudinal optical mode field, so III-V integrated photonic devices often use a suspended thin film structure, but this structure limits the integration with other optoelectronic devices and cannot fully utilize the advantages of the material. The emergence of III-V semiconductor-on-insulator architecture has completely released the performance potential of III-V semiconductor nonlinear integrated photonic devices. The III-V semiconductor-on-insulator architecture has smaller device size, stronger optical mode binding ability, higher mechanical strength, and stronger nonlinear response, which will promote the development of all-optical modulation photonic chips to a new level.

[0004] At present, the process of integrating high-quality III-V semiconductor integrated photonic devices on an insulator optical medium material mainly includes epitaxial growth, wafer bonding, selective etching, exposure etching, and deposition of optical medium layer. The wafer bonding method is divided into direct bonding and intermediate layer bonding according to whether an intermediate layer material is needed. The method based on intermediate layer bonding has the advantages of small material lattice mismatch and thermal mismatch, low wafer flatness and cleanliness requirements, flexible solidification mode, etc., and has higher yield and lower cost. Therefore, the process combination based on intermediate layer bonding / selective etching / exposure etching device is a common process for preparing III-V semiconductor-on-insulator integrated photonic devices and micro-nano patterns.

[0005] However, the III-V semiconductor-on-insulator thin film prepared by the intermediate bonding / selective etching / exposure etching device process at present has the problems of low thickness consistency and low flatness, which limits the usable area and integrity of the bonded wafer and restricts the number and integration of photonic devices. SUMMARY

[0006] Based on the above deficiencies, the present application provides an integrated photonic device on an insulator III-V semiconductor and a preparation method thereof to partially or totally improve the low integration of the integrated photonic device in the related art.

[0007] The present application is implemented as follows:

[0008] In the first aspect, examples of the present application provide a preparation method of an integrated photonic device on an insulator III-V semiconductor, comprising:

[0009] Step one: growing an epitaxial layer based on III-V semiconductor material on a first wafer; patterning the epitaxial layer to form a micro-nano pattern to obtain a patterned optical waveguide device layer;

[0010] Step two: depositing a first optical medium layer on the optical waveguide device layer as a cladding layer of the optical waveguide device layer;

[0011] Step three: bonding the first optical medium layer on the first wafer with a second wafer.

[0012] In the above implementation process, the epitaxial layer of III-V semiconductor material is first formed on the first wafer, and the epitaxial layer of III-V semiconductor material is patterned to form a micro-nano pattern to obtain an optical waveguide device layer. A first optical medium layer is deposited on the optical waveguide device layer as a cladding layer of the waveguide device, and then the first optical medium layer on the first wafer is bonded with the second wafer to form a heterogeneous integrated wafer. This can avoid the influence of subsequent bonding operation on the patterning process of the epitaxial layer, thereby improving the yield of the optical waveguide device on the heterogeneous integrated wafer and improving the integration of the optical waveguide device on the heterogeneous integrated wafer.

[0013] Moreover, the first optical medium layer with relatively small refractive index is prepared on the optical waveguide device layer, which can provide the waveguide mode of the optical waveguide device layer with a confinement along the thickness direction thereof (i.e., provide the longitudinal confinement of the waveguide mode).

[0014] In combination with the first aspect, in a possible implementation, a bonding adhesive layer is formed on the first optical medium layer, and the first optical medium layer and the second wafer are bonded through the bonding adhesive layer.

[0015] Optionally, the material for forming the bonding adhesive layer includes a UV optical adhesive or a thermosetting optical adhesive.

[0016] In the above implementation process, the indirect bonding through the bonding adhesive layer has the characteristics of small lattice mismatch and thermal mismatch, low wafer flatness and cleanliness requirements, and flexible solidification, which can improve the bonding quality and reduce the bonding cost.

[0017] In combination with the first aspect, in a possible implementation, the epitaxial layer at least includes a sacrificial layer and a device layer disposed on the sacrificial layer; and in the step one, the device layer is subjected to a patterning process.

[0018] Optionally, the micro-nano pattern has a depth not exceeding a thickness of the device layer.

[0019] Optionally, the device layer can be a single-layer film or a multi-layer film, and the device layer contains one or more of quantum dots, quantum wells, quantum wires, and quantum dashes.

[0020] In the implementation process, the epitaxial layer formed on the first wafer includes a sacrificial layer and a device layer, and the substrate of the first wafer and the sacrificial layer are subsequently separated from the device layer by means of selective wet etching. When the device layer is subjected to the patterning process, the micro-nano pattern has a depth not exceeding the device layer, so that the side of the device layer close to the sacrificial layer is not subjected to the patterning process (i.e., the side of the device layer is not etched through during the patterning process), thereby providing a certain mechanical strength for the patterned optical waveguide device layer and improving the stability of the subsequent bonding operation.

[0021] In combination with the first aspect, in an implementation, the preparation method further includes a step four of removing the first wafer in the hetero-integrated wafer formed after the bonding in the step three.

[0022] In combination with the first aspect, in an implementation, after the first wafer is removed in the step four, the sacrificial layer is removed.

[0023] In combination with the first aspect, in an optional implementation, a second optical medium layer is formed on the exposed optical waveguide device layer.

[0024] In the implementation process, the first wafer after the bonding is removed to facilitate subsequent processing of the optical waveguide device layer, so that the sacrificial layer is exposed, and then the sacrificial layer is removed to expose the optical waveguide device layer, and a second optical medium layer can be formed on the other side of the optical waveguide device layer, thereby further providing a confinement along the thickness direction of the waveguide mode of the optical waveguide device layer (i.e., providing a longitudinal confinement of the waveguide mode).

[0025] In combination with the first aspect, in a possible implementation, the materials of the sacrificial layer and the device layer are different and are independently selected from one or more of gallium phosphide, gallium arsenide, gallium nitride, indium phosphide, aluminum nitride, aluminum gallium arsenide, aluminum gallium phosphide, and aluminum gallium indium phosphide.

[0026] Optionally, the material of the sacrificial layer is aluminum gallium indium phosphide.

[0027] Optionally, the material of the device layer is gallium phosphide.

[0028] In combination with the first aspect, in a possible implementation, the material forming the first optical medium layer and the material forming the second optical medium layer are each independently selected from one or more of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, and tantalicum.

[0029] In the implementation process, the materials with a refractive index less than that of the III-V semiconductor film layer, such as silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, and tantalicum, are used to form the cladding layer of the optical waveguide device layer, and the longitudinal confinement of the waveguide mode of the optical waveguide device layer is formed.

[0030] In combination with the first aspect, in a possible implementation, the second wafer is selected from one of a silicon wafer, a germanium wafer, a III-V semiconductor wafer, a silicon-on-insulator wafer, a silicon dioxide wafer, an aluminum oxide wafer, or a fluoride wafer.

[0031] In the implementation process, the silicon wafer, the germanium wafer, the III-V semiconductor wafer, the silicon-on-insulator wafer, the silicon dioxide wafer, the aluminum oxide wafer, or the fluoride wafer is bonded with the optical waveguide device layer to form the silicon-on-insulator III-V semiconductor integrated photonic device.

[0032] In the second aspect, examples of the present application provide a silicon-on-insulator III-V semiconductor integrated photonic device, comprising a second wafer, a bonding glue layer arranged on the second wafer, a first optical medium layer arranged on the bonding glue layer, an optical waveguide device layer based on III-V semiconductor material arranged on the first optical medium layer, and a second optical medium layer arranged on the optical waveguide device layer.

[0033] The second wafer is selected from one of a silicon wafer, a germanium wafer, a III-V semiconductor wafer, a silicon-on-insulator wafer, a silicon dioxide wafer, an aluminum oxide wafer, or a fluoride wafer.

[0034] Optionally, the first optical medium layer and the second optical medium layer are each independently selected from one or more of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, and tantalicum; and optionally, the material forming the bonding glue layer comprises a UV optical adhesive or a thermosetting optical adhesive.

[0035] In the implementation process, the first optical medium layer formed on the optical waveguide device layer is bonded to the second wafer in an indirect bonding manner through the bonding glue layer, so as to realize the transfer of the patterned optical waveguide device layer to the second wafer and form the silicon-on-insulator III-V semiconductor integrated photonic device. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description.

[0037] Figure 1 schematic flowchart of a method for fabricating an integrated photonic device on an insulator-on-III-V semiconductor according to the prior art;

[0038] Figure 2 schematic cross-sectional view of a structure formed after step S101;

[0039] Figure 3 schematic cross-sectional view of a structure formed after step S102;

[0040] Figure 4 schematic cross-sectional view of a structure formed after step S103;

[0041] Figure 5 schematic cross-sectional view of a structure formed after step S104;

[0042] Figure 6 schematic cross-sectional view of a structure formed after step S105;

[0043] Figure 7 schematic cross-sectional view of a structure formed after step S106;

[0044] Figure 8 schematic flowchart of a method for fabricating an integrated photonic device on an insulator-on-III-V semiconductor according to the present application;

[0045] Figure 9 schematic cross-sectional view of a structure formed after step S201;

[0046] Figure 10 schematic cross-sectional view of a structure after forming a lithography pattern in step S202;

[0047] Figure 11 schematic cross-sectional view of a structure after forming an optical waveguide device layer in step S202;

[0048] Figure 12 schematic cross-sectional view of a structure formed after step S203;

[0049] Figure 13 schematic cross-sectional view of a structure formed after step S204;

[0050] Figure 14 schematic cross-sectional view of a structure formed after step S205;

[0051] Figure 15 schematic cross-sectional view of a structure formed after step S206.

[0052] Icons: 101-First III-V wafer; 102-First sacrificial layer; 103-First device layer; 104-First cladding layer; 105-Intermediate layer; 106-Second silicon wafer; 107-First optical waveguide; 108-Second cladding layer;

[0053] 201-First wafer; 202-Sacrificial layer; 203-Device layer; 204-Photoresist pattern; 205-Optical waveguide device layer; 206-First optical dielectric layer; 207-Bonding adhesive layer; 208-Second wafer; 209-Second optical dielectric layer. Detailed Implementation

[0054] The embodiments of this application will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of this application. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0055] III-V semiconductor integrated photonic devices on insulators have smaller device size, stronger optical mode confinement capability, higher mechanical strength and stronger nonlinear response, which will drive the development of all-optically modulated photonic chips to a new level.

[0056] Currently, the process for integrating high-quality III-V semiconductor photonic devices on insulators mainly includes steps such as epitaxial growth, wafer bonding, selective etching, exposure etching, and deposition of an optical dielectric layer. Wafer bonding methods are broadly classified into direct bonding and intermediate layer bonding based on whether an intermediate layer material is required. Intermediate layer bonding methods offer advantages such as lower lattice and thermal mismatch effects, lower requirements for wafer flatness and cleanliness, and flexible curing methods, resulting in higher yields and lower costs. Therefore, the process combination of intermediate layer bonding / selective etching / exposure etching is a commonly used workflow for fabricating III-V semiconductor integrated photonic devices and micro / nano patterns on insulators.

[0057] For example, please refer to Figure 1 The process flow for devices based on intermediate layer bonding / selective etching / exposure etching includes:

[0058] S101, A first sacrificial layer 102 and a first device layer 103 based on a III-V semiconductor material are formed on the substrate of the first III-V wafer 101. Figure 2 for Figure 1 The diagram shows a cross-sectional view of the structure obtained after step S101.

[0059] S102, A first cladding layer 104 is formed on the first device layer 103. Figure 3For Figure 1 A cross-sectional view of the structure obtained after the S102 step shown.

[0060] S103, apply bonding glue on the first cladding layer 104 to form an intermediate layer 105, and contact it with the surface of the second silicon wafer 106, and bond the first III-V wafer 101 and the second silicon wafer 106 together by curing. Figure 4 For Figure 1 A cross-sectional view of the structure obtained after the S103 step shown.

[0061] S104, remove the first III-V wafer 101 by grinding, grinding, etching, etc. to expose the first sacrificial layer 102. Then remove the first sacrificial layer 102 by selective etching technology, and retain the first device layer 103. Figure 5 For Figure 1 A cross-sectional view of the structure obtained after the S104 step shown.

[0062] S105, select a part of the first device layer 103 with higher surface flatness for patterning to form a micro-nano pattern, and obtain a first optical waveguide 107. Figure 6 For Figure 1 A cross-sectional view of the structure obtained after the S105 step shown.

[0063] S106, form a second cladding layer 108 on the first optical waveguide 107. Figure 7 For Figure 1 A cross-sectional view of the structure obtained after the S106 step shown.

[0064] However, the III-V semiconductor thin film on an insulator prepared based on the above process has the problems of low thickness consistency and low flatness, which limits the usable area and integrity of the bonded wafer, and restricts the number and integration of photonic devices.

[0065] For example, when subsequent patterning is performed, only the relatively flat part of the heterogeneously integrated wafer can be selected, and the utilization rate of the whole bonded wafer is low.

[0066] Therefore, the present application provides an insulator-based III-V semiconductor integrated photonic device and a preparation method thereof. The following will be described in detail for the preparation method of the insulator-based III-V semiconductor integrated photonic device of the present application:

[0067] The preparation method of the insulator-based III-V semiconductor integrated photonic device comprises:

[0068] Step one: growing an epitaxial layer based on III-V semiconductor material on a first wafer; patterning the epitaxial layer to form a micro-nano pattern to obtain an optical waveguide device layer;

[0069] Step two: depositing a first optical medium layer on the optical waveguide device layer as a cladding layer of the optical waveguide device layer;

[0070] Step three: bonding the first optical medium layer on the first wafer with the second wafer.

[0071] The III-V semiconductor material epitaxial layer is formed on the first wafer first, and the III-V semiconductor material epitaxial layer is patterned to form a micro-nano pattern to obtain a patterned optical waveguide device layer. A first optical medium layer is deposited on the optical waveguide device layer as a cladding layer of the optical waveguide device. Then, the first optical medium layer on the first wafer is bonded with the second wafer to form a heterogeneous integrated wafer. That is, the patterning is performed first, and then the bonding is performed. This can avoid the influence of the subsequent bonding operation on the patterning of the epitaxial layer (for example, uneven thickness of the bonding layer leads to uneven thickness of the entire heterogeneous integrated wafer, which leads to the fact that only a relatively flat position of the heterogeneous integrated wafer can be selected for patterning to obtain an optical waveguide device), thereby improving the yield of the optical waveguide device on the heterogeneous integrated wafer and improving the integration of the optical waveguide device on the heterogeneous integrated wafer.

[0072] The preparation method of the III-V semiconductor-on-insulator integrated photonic device will be described in further detail below with reference to the accompanying drawings.

[0073] Please refer to Figure 8 The preparation method of the III-V semiconductor-on-insulator integrated photonic device includes the following steps.

[0074] S201, forming an epitaxial layer based on III-V semiconductor material on a first wafer 201.

[0075] The present application does not limit the type of the first wafer 201. For example, the first wafer 201 is a gallium arsenide wafer.

[0076] The epitaxial layer can be a multilayer film structure. In one possible embodiment, please refer to Figure 9 The epitaxial layer includes a sacrificial layer 202 and a device layer 203 disposed on the sacrificial layer 202.

[0077] The materials of the sacrificial layer 202 and the device layer 203 are different and are selected from III-V semiconductor materials.

[0078] For example, the III-V semiconductor material includes gallium phosphide, gallium arsenide, gallium nitride, indium phosphide, aluminum nitride, aluminum gallium arsenide, aluminum gallium phosphide, and aluminum gallium indium phosphide.

[0079] For example, the material of the sacrificial layer 202 is aluminum gallium indium phosphide, and the material of the device layer 203 is gallium phosphide.

[0080] Exemplarily, the device layer 203 can be a multi-layer film structure or a single-layer film structure.

[0081] Further, the device layer 203 can contain quantum dots, quantum wells, quantum wires or quantum dash structures.

[0082] Further, the sacrificial layer 202 and the device layer 203 can be epitaxially grown on the first wafer 201 by metal organic vapor deposition.

[0083] S202, the device layer 203 is patterned to form a photoresist pattern 204 as an etching mask, and an etched patterned optical waveguide device layer 205 is formed. Figure 10 Figure 8 A cross-sectional view of the structure after the photoresist pattern 204 is formed in S202. Figure 11 Figure 8 A cross-sectional view of the structure after the patterned optical waveguide device layer 205 is formed in S202.

[0084] Exemplarily, the photoresist pattern 204 can be formed on the epitaxially grown first wafer 201 by one or more of ultraviolet exposure, electron beam exposure or laser direct writing.

[0085] Exemplarily, the device layer 203 of gallium phosphide can be patterned and etched by dry etching to form a ridge-shaped optical waveguide device layer 205.

[0086] Further, the present application does not limit the specific shape of the optical waveguide device layer 205, and relevant personnel can make corresponding selection according to needs. In one possible implementation, the shape of the optical waveguide device layer 205 can be a strip-shaped waveguide structure.

[0087] In one possible implementation, after dry etching to form the optical waveguide device layer 205, the device layer 203 is not etched through, and the side of the device layer 203 close to the sacrificial layer 202 is not etched, thereby providing certain mechanical strength for the ridge-shaped optical waveguide device layer 205.

[0088] S203, a first optical medium layer 206 is formed on the optical waveguide device layer 205. Figure 12 Figure 8 A cross-sectional view of the structure after S203.

[0089] Exemplarily, the material of the first optical medium layer 206 can be selected from one or more of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride or tantalicum dioxide, which has a smaller refractive index than the device layer 203.

[0090] ​​​Exemplarily, a silicon dioxide is deposited on the optical waveguide device layer 205 as the first optical medium layer 206, with a thickness of 1000-3000 nm.

[0091] S204, a bonding glue layer 207 is formed on the first optical medium layer 206, and the second wafer 208 is bonded to the first optical medium layer 206 through the bonding glue layer 207. Figure 13 For Figure 8 A cross-sectional view of the structure after the S204 step.

[0092] The material forming the bonding glue layer 207 can be a UV-curable optical adhesive or a thermally-curable optical adhesive. Exemplarily, it is selected from Norland Optical Adhesives (NOA60, NOA61, NOA63, NOA65, NOA68, NOA68T, NOA71, NOA72, NOA73, NOA74, NOA75, NOA76, NOA78, NOA81, NOA84, NOA88, NOA89 or NOA83H) or Sylgard 184 or BCB and other thermally-curable silicone resins or UV-curable optical adhesives.

[0093] Exemplarily, the bonding material NOA83H (Norland Optical Adhesive 83H) is coated on the first optical medium layer 206 to form the bonding glue layer 207, with a thickness of 1000-3000 nm. The bonding glue layer 207 and the surface of the second wafer 208 are in contact, and the first optical medium layer 206 and the second wafer 208 are bonded through curing.

[0094] In order to further improve the optical performance of the integrated photonic device, in an embodiment, the preparation method of the III-V semiconductor-on-insulator integrated photonic device provided by the present example further comprises:

[0095] S205, the first wafer 201 in the hetero-integrated wafer formed after the bonding of the S204 step is removed, and then the sacrificial layer 202 is removed. Figure 14 For Figure 8 A cross-sectional view of the structure after the S205 step.

[0096] Exemplarily, the first wafer 201 is removed by grinding, grinding, etching and other processes to expose the sacrificial layer 202 on the first wafer 201. Then, the sacrificial layer 202 is continuously removed by using a selective etching technique, and the optical waveguide device layer 205 is reserved.

[0097] S206, a second optical medium layer 209 is formed on the optical waveguide device layer 205 exposed after the removal of the sacrificial layer 202 in the S205 step. Figure 15 For Figure 8A cross-sectional view of the structure after the step S206.

[0098] For example, the material forming the second optical medium layer 209 can be selected from one or more of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, tantalicum dioxide, and the like, which have a refractive index less than that of the optical medium material of the device layer 203.

[0099] By the above preparation method, the examples of the present application further provide an integrated photonic device of III-V semiconductor on insulator, comprising a second wafer 208, a bonding glue layer 207 disposed on the second wafer 208, a first optical medium layer 206 disposed on the bonding glue layer 207, a III-V semiconductor material-based optical waveguide device layer 205 disposed on the first optical medium layer 206, and a second optical medium layer 209 disposed on the optical waveguide device layer 205.

[0100] In a possible implementation, the second optical medium layer 209 can be replaced by air.

[0101] The integrated photonic device of III-V semiconductor on insulator of the present application is further described in detail below in combination with examples.

[0102] Example 1

[0103] Example 1 provides an integrated photonic device of III-V semiconductor on insulator, which is prepared by the following preparation method:

[0104] S1, growing a III-V semiconductor epitaxial layer on a first wafer 201 by metal organic vapor deposition (MOCVD), including an aluminum gallium indium phosphorus sacrificial layer 202 and a gallium phosphide device layer 203.

[0105] S2, making a photoresist pattern 204 on the gallium phosphide device layer 203 by ultraviolet exposure, and forming an optical waveguide device layer 205 by dry etching. The device layer 203 is not etched through, and the side close to the sacrificial layer 202 is not etched.

[0106] S3, depositing silicon dioxide as a first optical medium layer 206 on the etched optical waveguide device layer 205.

[0107] S4, coating a bonding material (NOA83H) on the first optical medium layer 206, and contacting it with the surface of a second wafer 208, and bonding the first optical medium layer 206 and the second wafer 208 by solidification.

[0108] S5, removing the first wafer 201 by grinding to expose the sacrificial layer 202 on the first wafer 201. Then, the sacrificial layer 202 is removed by selective etching, and the gallium phosphide optical waveguide device layer 205 is reserved.

[0109] S6, depositing silicon dioxide as a second optical medium layer 209 on the back surface of the gallium phosphide optical waveguide device layer 205 after selective etching.

[0110] The above description is merely illustrative of the application, and not in limitation thereof. It will be understood by those skilled in the art that various changes can be made and equivalents can be substituted for elements without departing from the spirit and scope of the application. In addition, many modifications can be made to adapt to a particular situation and the application is intended to cover any and all such modifications without limitation.

Claims

1. A method for fabricating a III-V semiconductor integrated photonic device on an insulator, characterized in that, include: Step 1: An epitaxial layer based on a III-V semiconductor material is grown on a first wafer; the epitaxial layer includes at least a sacrificial layer and a device layer disposed on the sacrificial layer; the device layer is patterned to form a micro-nano pattern to obtain a patterned optical waveguide device layer; the first wafer is a gallium arsenide wafer; Step 2: Deposit a first optical dielectric layer on the optical waveguide device layer as the cladding of the optical waveguide device layer; Step 3: A bonding adhesive layer is formed on the first optical dielectric layer, and the first optical dielectric layer and the second wafer are bonded together through the bonding adhesive layer; The preparation method further includes step four: removing the first wafer from the heterogeneous integrated wafer formed after bonding in step three; removing the first wafer and then removing the sacrificial layer; and forming a second optical dielectric layer on the optical waveguide device layer after removing the sacrificial layer.

2. The preparation method according to claim 1, characterized in that, The materials forming the bonding adhesive layer include UV optical adhesives or thermosetting optical adhesives.

3. The preparation method according to claim 1, characterized in that, The depth of the micro / nano pattern does not exceed the thickness of the device layer.

4. The preparation method according to claim 1, characterized in that, The device layer is a single-layer film or a multi-layer film, and the device layer contains one or more of quantum dots, quantum wells, quantum wires, and quantum scribing.

5. The preparation method according to claim 1, characterized in that, The sacrificial layer and the device layer are made of different materials, and are each independently selected from one or more of gallium phosphide, gallium arsenide, gallium nitride, indium phosphide, aluminum nitride, aluminum gallium arsenide, aluminum gallium phosphide, and aluminum gallium indium phosphide.

6. The preparation method according to claim 5, characterized in that, The material of the sacrificial layer is aluminum gallium indium phosphorus.

7. The preparation method according to claim 5, characterized in that, The material of the device layer is gallium phosphide.

8. The preparation method according to claim 1, characterized in that, The materials forming the first optical dielectric layer and the second optical dielectric layer are each independently selected from one or more of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, and tandium pentoxide.

9. The preparation method according to claim 1, characterized in that, The second wafer is selected from one of the following: silicon wafer, germanium wafer, III-V semiconductor wafer, silicon-on-insulator wafer, silicon dioxide wafer, alumina wafer, or fluoride wafer.

10. An integrated photonic device of a group III-V semiconductor on an insulator, prepared by the method according to any one of claims 1 to 9, characterized in that, It includes a second wafer, a bonding adhesive layer disposed on the second wafer, a first optical dielectric layer disposed on the bonding adhesive layer, an optical waveguide device layer based on a III-V semiconductor material disposed on the first optical dielectric layer, and a second optical dielectric layer disposed on the optical waveguide device layer; The second wafer is selected from one of the following: silicon wafer, germanium wafer, III-V semiconductor wafer, silicon-on-insulator wafer, silicon dioxide wafer, alumina wafer, or fluoride wafer.

11. The insulator-on-insulator III-V semiconductor integrated photonic device according to claim 10, characterized in that, Both the first optical dielectric layer and the second optical dielectric layer are independently selected from one or more of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, and tandium pentoxide.

12. The insulator-on-insulator III-V semiconductor integrated photonic device according to claim 10, characterized in that, The materials forming the bonding adhesive layer include UV optical adhesives or thermosetting optical adhesives.

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