Method for correcting 1-second pulse signal and time service receiver

Abstract

The present invention provides a method for correcting a 1-second pulse signal and a timing receiver. In an embodiment of the present invention, the method of the present invention enables the timing receiver to provide a corrected 1PPS signal with better quality to a subsequent slave device, thereby ensuring that the synchronization effect of the slave device is not overly affected by jitter in a single 1PPS signal.

Description

Technical Field

[0001] The present invention relates to a mechanism for correcting a synchronization signal, and more particularly to a method for correcting a one-second pulse signal and a timing receiver. Background Art

[0002] Please refer to Figure 1 , which is a schematic diagram of the operation of an existing Global Navigation Satellite System (GNSS). As Figure 1 shown, when a GNSS receiver receives satellite signals from one or more satellites, a one-pulse-per-second (1PPS) signal and time-of-date (ToD) information can be obtained by decoding the satellite signals. Thereafter, the GNSS receiver can provide the obtained 1PPS signal and ToD information to other slave devices (such as various distributed nodes and / or base stations, etc.) so that these slave devices can perform phase and time synchronization respectively based on the 1PPS signal and ToD information.

[0003] However, when the GNSS receiver receives satellite signals, the 1PPS signal obtained by the GNSS receiver often has jitter of dozens to thousands of nanoseconds due to climate interference (for example, only receiving satellite signals from a few satellites due to cloud cover) or poor reception angle. In this case, the relevant slave devices cannot accurately perform the above synchronization operation.

[0004] In addition, when the GNSS receiver fails to receive satellite signals from any satellite for some reason, the 1PPS signal provided by it may become seriously inaccurate within a short period of time (for example, within 15 minutes). Summary of the Invention

[0005] In view of this, the present invention provides a method for correcting a one-second pulse signal and a timing receiver, which can be used to solve the above technical problems.

[0006] The present invention provides a method for correcting a 1-second pulse signal, which is suitable for a timing receiver, including: receiving a clock signal by a first counter and accumulating a first count value based on the clock signal; in response to receiving the i-th 1-second pulse signal, outputting the first count value corresponding to the i-th 1-second pulse signal and resetting the first counter, where i is an index value; obtaining a difference value between a reference value and the first count value corresponding to the i-th 1-second pulse signal, and storing the difference value in a queue, where the queue stores a plurality of specific difference values, and the plurality of specific difference values include the difference value corresponding to the i-th 1-second pulse signal to the difference value corresponding to the i-N+1-th 1-second pulse signal, and N is the depth of the queue; generating a reference count value corresponding to the i-th 1-second pulse signal based on the plurality of specific difference values and the reference value, and counting down from the reference count value by a signal generation circuit based on the clock signal; and in response to determining that the signal generation circuit counts down to a default level, outputting a corrected 1-second pulse signal.

[0007] The present invention provides a timing receiver, including a first counter, a comparator, a queue, an estimation circuit, and a signal generation circuit. The first counter is configured to: receive a clock signal and accumulate a first count value based on the clock signal; in response to receiving the i-th 1-second pulse signal, output the first count value corresponding to the i-th 1-second pulse signal and reset the first counter, where i is an index value. The comparator is coupled to the first counter, obtains a difference value between a reference value and the first count value corresponding to the i-th 1-second pulse signal, and stores the difference value in a queue. The queue is coupled to the comparator and stores a plurality of specific difference values, where the plurality of specific difference values include the difference value corresponding to the i-th 1-second pulse signal to the difference value corresponding to the i-N+1-th 1-second pulse signal, and N is the depth of the queue; the estimation circuit is coupled to the comparator and the queue, and generates a reference count value corresponding to the i-th 1-second pulse signal based on the plurality of specific difference values and the reference value. The signal generation circuit is coupled to the estimation circuit and is configured to: count down from the reference count value based on the clock signal; and in response to determining that the signal generation circuit counts down to a default value, output a corrected 1-second pulse signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention.

[0009] Figure 1 It is a schematic diagram of the operation of the existing satellite navigation system GNSS.

[0010] Figure 2 It is a schematic diagram of the timing receiver shown according to an embodiment of the present invention.

[0011] Figure 3 It is a flowchart of a method for correcting the 1PPS signal illustrated according to an embodiment of the present invention. Detailed implementation manners

[0012] Now, reference will be made in detail to exemplary embodiments of the present invention. Examples of the exemplary embodiments are illustrated in the accompanying drawings. As long as possible, the same component symbols are used in the drawings and the description to represent the same or similar parts.

[0013] Please refer to Figure 2 , which is a schematic diagram of a timing receiver illustrated according to an embodiment of the present invention. In Figure 2 , the timing receiver 200 includes a first counter 210, a comparator 230, a queue 240, an estimation circuit 250, and a signal generation circuit 260.

[0014] In an embodiment of the present invention, the first counter 210, the comparator 230, the queue 240, the estimation circuit 250, and the signal generation circuit 260 can cooperate to implement the method for correcting the 1PPS signal proposed by the present invention, and the details are described in detail below.

[0015] Please refer to Figure 3 , which is a flowchart of a method for correcting the 1PPS signal illustrated according to an embodiment of the present invention. The method of this embodiment can be executed by the timing receiver 200 of Figure 2 , and the details of each step will be described below in conjunction with the components shown in Figure 2 . Figure 3 Details of each step.

[0016] First, in step S310, the first counter 210 can be used to receive a clock signal CS and can accumulate a first count value based on the clock signal CS. In different embodiments, the clock signal CS can be provided by a corresponding clock source, where the clock source is, for example, an oven controlled crystal oscillator (OCXO) or other precisely controllable clock signal generators, but is not limited thereto.

[0017] In one embodiment, the above clock source can provide a clock signal CS including a plurality of pulses based on a set reference frequency, and the time difference between two adjacent pulses will be the reciprocal of this reference frequency. For ease of explanation, it is assumed below that the reference frequency of the clock source is 125 MHz, but the possible implementation manners of the present invention are not limited thereto. In the case where the reference frequency of the clock source is assumed to be 125 MHz, the time difference between two adjacent pulses of the clock signal CS will be 8 ns (i.e., 1 / 125 M seconds).

[0018] In one embodiment, the first counter 210 may increment its count value (i.e., the first count value) when detecting one of the above-mentioned pulses. That is, when the reference frequency of the clock source is 125 MHz, the first counter 210 increments the first count value by one every 8 ns.

[0019] In one embodiment, the first counter 210 may be used to receive a plurality of consecutive 1PPS signals from a GNSS receiver such as Figure 1 . The i-th 1PPS signal among them may be denoted as S i . Accordingly, in step S320, in response to the first counter 210 receiving the i-th 1PPS signal S i , the first counter 210 may output the first count value C i corresponding to the i-th 1PPS signal, and reset the first counter 210.

[0020] In one embodiment, the first counter 210 may start accumulating the first count value C i from the time when the (i - 1)-th 1PPS signal is received. That is, every time the first counter 210 receives a 1PPS signal, it starts accumulating the first count value from 0, outputs the first count value when receiving the next 1PPS signal, and starts accumulating the first count value from 0 again.

[0021] As previously mentioned, the first counter 210 increments by 1 every 8 ns, so the first count value it accumulates can be understood as corresponding to the time difference between two consecutive 1PPS signals. In other words, the first count value C i output by the first counter 210 in step S320 corresponding to the i-th 1PPS signal S i can be understood as corresponding to the time difference between the (i - 1)-th 1PPS signal S i-1 and the i-th 1PPS signal S i .

[0022] Specifically, ideally, the GNSS receiver can provide one 1PPS signal to the first counter 210 per second. That is, the time difference between two consecutive 1PPS signals should be exactly 1 second, and the corresponding first count value should be 125,000,000. However, due to the jitter mentioned above for these 1PPS signals, the time difference between two consecutive 1PPS signals from the GNSS receiver may not be exactly 1 second. In other words, the first count value may not be exactly 125,000,000.

[0023] In this case, the first counter 210 can be used to estimate the time difference between two consecutive 1PPS signals, so that the timing receiver 200 can perform subsequent operations.

[0024] In one embodiment, the first counter 210 may be coupled to the comparator 230, and the first counter 210 may directly output the first count value C corresponding to the i-th 1PPS signal S i to the comparator 230 for the comparator 230 to perform subsequent operations based thereon. i

[0025] In another embodiment, the timing receiver 200 may further include a determination circuit 220 coupled between the first counter 210 and the comparator 230. In one embodiment, the determination circuit 220 may determine whether the first count value C i is between the lower limit value and the upper limit value. In different embodiments, the designer may set the lower limit value and the upper limit value to values corresponding to the normal range of the first count value, but it is not limited thereto.

[0026] In one embodiment, in response to the determination circuit 220 determining that the first count value C i is between the lower limit value and the upper limit value, this means that the value of the first count value C i is reasonable. In this case, the determination circuit 220 may output the first count value C i to the comparator 230 for the comparator 230 to perform subsequent operations based thereon.

[0027] On the other hand, in response to the determination circuit 220 determining that the first count value C i is not between the lower limit value and the upper limit value, this means that the value of the first count value C i is unreasonable. In this case, the determination circuit 220 may ignore the first count value C i . That is, the determination circuit 220 may not output the first count value C i to the comparator 230, but it is not limited thereto.

[0028] After the comparator 230 obtains the first count value C i , in step S330, the comparator 230 obtains the difference value D i between the reference value and the first count value C corresponding to the i-th 1PPS signal S i , and stores the difference value D i in the queue 240. i

[0029] In one embodiment, the above reference value may be set to be equal to the reference frequency of the clock signal CS. That is, when the reference frequency is assumed to be 125 MHz, the reference value may be set to 125,000,000.

[0030] In one embodiment, the comparator 230 may subtract the reference value from the first count value C i to obtain the difference value D​​i In an embodiment of the present invention, the difference value D i can be represented by K-bit data, where the first bit (e.g., the most significant bit (MSB)) of this K-bit data can be used to represent the sign of the difference value D i . For example, if the difference value D i is positive, its MSB can be recorded as 0; if the difference value D i is negative, its MSB can be recorded as 1, but it is not limited thereto.

[0031] In different embodiments, the value of K can be selected according to the designer's requirements. Hereinafter, the case where K is equal to 29 will be taken as an example for illustration, but it is not limited thereto. For example, assume that the first count value C i is 125,000,007, then the corresponding difference value D i is, for example, 7 (i.e., 125,000,007 - 125,000,000). In this case, the difference value D i can be correspondingly represented as 29-bit data, where the MSB of this data can be represented as "1'b0" (b represents binary), and the remaining 28 bits can be represented as "28'h0000007" (h represents hexadecimal).

[0032] Take another example. Assume that the first count value C i is 124,999,993, then the corresponding difference value D i is, for example, -7 (i.e., 124,999,993 - 125,000,000). In this case, the difference value D i can be correspondingly represented as 29-bit data, where the MSB of this data can be represented as "1'b1" (b represents binary), and the remaining 28 bits can be represented as "28'h0000007" (h represents hexadecimal), but it is not limited thereto.

[0033] In another embodiment, the comparator 230 can also subtract the first count value C i from the reference value to obtain the difference value D i , and the corresponding data representation can be adjusted according to the above teachings, but it is not limited thereto.

[0034] In an embodiment of the present invention, the queue 240 coupled to the comparator 230 is, for example, a first-in-first-out (FIFO) queue, and its depth is, for example, N (N is a positive integer). In one embodiment, the queue 240 can be understood to include N (for example, 1024) data storage locations (represented as Diff[0] to Diff[N-1]), and Diff[0] to Diff[N-1] can be respectively used to store N specific difference values.

[0035] In some embodiments, the N specific difference values, for example, include the difference value D corresponding to the i-th 1PPS signal S i to the difference value D corresponding to the (i-N+1)-th 1PPS signal S i i-N+1 i-N+1 .

[0036] In one embodiment, before the comparator 230 outputs the difference value D i to the queue 240, Diff[0] to Diff[N-1] of the queue 240 can respectively store the difference value D corresponding to the (i-1)-th 1PPS signal S i-1 to the difference value D corresponding to the (i-N)-th 1PPS signal S i-1 i-N i-N . However, after the comparator 230 outputs the difference value D i to the queue 240, since the queue 240 is a FIFO queue, the difference value D i-N will be removed from the queue 240, so that Diff[0] to Diff[N-1] of the queue 240 become respectively storing the difference value D corresponding to the (i-1)-th 1PPS signal S i-1 to the difference value D corresponding to the (i-N+1)-th 1PPS signal S i i-N+1 i-N+1 .

[0037] After that, in step S340, the estimation circuit 250 coupled to the queue 240 generates a reference count value RC corresponding to the i-th 1PPS signal S i based on the multiple specific difference values and a reference value. i

[0038] In one embodiment, the estimation circuit 250 can obtain the statistical characteristic values of the above N specific difference values (that is, the difference values D i to D i-N+1 ). In one embodiment, the estimation circuit 250, for example, can obtain the average value of the difference values D i to D i-N+1 (that is, (D i +…+D​​​​​​​i-N+1 ) / N) as the above statistical characteristic value, but it is not limited thereto. Thereafter, the estimation circuit 250 can add this statistical characteristic value to a reference value (e.g., 125,000,000) to generate a reference count value RC i .

[0039] In another embodiment, the estimation circuit 250 can first obtain a reference count value RC corresponding to the (i - 1)-th 1PPS signal S i-1 . i-1 Thereafter, the estimation circuit 250 can obtain a difference value D corresponding to the i-th 1PPS signal S i and a difference value D corresponding to the (i - N)-th 1PPS signal S i , and determine a correction factor based thereon. Then, the estimation circuit 250 can add this correction factor to the reference count value RC corresponding to the (i - 1)-th 1PPS signal S i-N to generate a reference count value RC corresponding to the i-th 1PPS signal S i-N . i-1 . i-1 Thereafter, in step S350, the signal generation circuit 260 coupled to the estimation circuit 250 counts down from the reference count value RC based on the clock signal CS i . i .

[0040] In one embodiment, during the process of determining the above correction factor, the estimation circuit 250 can subtract the difference value D corresponding to the (i - N)-th 1PPS signal S i from the difference value D corresponding to the i-th 1PPS signal S i to generate a reference difference value. Thereafter, the estimation circuit 250 can divide this reference difference value by N to generate the above correction factor (i.e., (D i-N - D i-N ) / N), but it is not limited thereto. i - D i-N ) / N), but it is not limited thereto.

[0041] Thereafter, in step S350, the signal generation circuit 260 coupled to the estimation circuit 250 counts down from the reference count value RC based on the clock signal CS i .

[0042] In step S360, in response to the determination that the signal generation circuit 260 counts down to a default value (e.g., 0), the signal generation circuit 260 outputs a corrected 1PPS signal S' i .

[0043] In one embodiment, the signal generation circuit 260 can send a load signal LS to the estimation circuit 250 when outputting the (i - 1)-th 1PPS signal S i-1 , and the estimation circuit 250 can, in response to the load signal LS, use the reference count value RC iLoaded into the signal generation circuit 260 as the second count value of the signal generation circuit 260. In one embodiment, the signal generation circuit 260 may include a counter, which is used to start from the reference count value RC i To perform counting down.

[0044] In one embodiment, in response to the signal generation circuit 260 detecting one of the pulses of the clock signal CS, the signal generation circuit 260 may decrement the second count value. That is, when the reference frequency of the clock source is 125 MHz, the signal generation circuit 260 will decrement the second count value by one every 8 ns.

[0045] Moreover, when the second count value is decremented to the default value (such as 0), the signal generation circuit 260 may correspondingly output the corrected 1PPS signal S'. i In different embodiments, the signal generation circuit 260 may output the corrected 1PPS signal S' i To the various slave devices mentioned above (such as various distributed nodes and / or base stations, etc.), so that these slave devices can respectively synchronize their phases according to the corrected 1PPS signal S' i To achieve a better synchronization effect.

[0046] Specifically, as previously mentioned, since there may be jitter in the i-th 1PPS signal S i If the above-mentioned slave devices directly synchronize their phases according to the i-th 1PPS signal S i It may result in a synchronization effect with lower accuracy.

[0047] However, through the method proposed in the embodiments of the present invention, the comparator 230 can represent the degree of deviation of the time difference between two consecutive 1PPS signals from 1 second by a corresponding difference value. Then, through the operations performed by the estimation circuit 250, the difference values corresponding to N consecutive 1PPS signals can be smoothed, and the smoothed difference values are added to the reference value to generate the reference count value RC i And this reference count value RC i Can enable the signal generation circuit 260 to output the corrected 1PPS signal S' at a time point different from the i-th 1PPS signal S i In this way, the synchronization effect of the slave devices will not be overly affected by the jitter in the i-th 1PPS signal S i i i Thereby, the synchronization effect of the slave devices will not be overly affected by the jitter in the i-th 1PPS signal S.

[0048] In addition, for certain situations where the 1PPS signal cannot be received from the GNSS receiver, the method of the present invention can also provide a certain degree of holdover effect. For example, when the GNSS receiver cannot provide the 1PPS signal to the timing receiver 200 because it cannot receive the satellite signals of any satellite, the timing receiver 200 can still continue to operate for about N seconds, so as to ensure that the slave device can still be synchronized within this N-second time interval.

[0049] In summary, the method of the present invention enables the timing receiver to provide a corrected 1PPS signal with better quality to the subsequent slave device, so as to ensure that the synchronization effect of the slave device will not be overly affected by the jitter in a single 1PPS signal.

[0050] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for correcting a 1-second pulse signal, applicable to a time service receiver, characterized in that, Comprising: A first counter receives a clock signal and accumulates a first count value based on the clock signal; In response to receiving the i-th 1-second pulse signal, output the first count value corresponding to the i-th 1-second pulse signal and reset the first counter, where i is an index value; Obtain a difference value between a reference value and the first count value corresponding to the i-th 1-second pulse signal, and store the difference value in a queue, where the queue stores a plurality of specific difference values, and the plurality of specific difference values include the difference value corresponding to the i-th 1-second pulse signal to the difference value corresponding to the i-N+1-th 1-second pulse signal, and N is the depth of the queue; Generate a reference count value corresponding to the i-th 1-second pulse signal based on the plurality of specific difference values and the reference value, including: Obtain a statistical characteristic value of the plurality of specific difference values, and add the statistical characteristic value to the reference value to generate the reference count value; or Obtain the reference count value corresponding to the i-1-th 1-second pulse signal, obtain the difference value corresponding to the i-th 1-second pulse signal and the difference value corresponding to the i-N-th 1-second pulse signal, and determine a correction factor based thereon, and add the correction factor to the reference count value corresponding to the i-1-th 1-second pulse signal to generate the reference count value corresponding to the i-th 1-second pulse signal; A signal generation circuit counts down from the reference count value based on the clock signal; and In response to determining that the signal generation circuit counts down to a default value, output a corrected 1-second pulse signal.

2. The method according to claim 1, wherein the clock signal includes a plurality of pulses, and the step of accumulating the first count value based on the clock signal includes: In response to detecting one of the plurality of pulses of the clock signal, accumulate the first count value.

3. The method according to claim 1, wherein the clock signal has a reference frequency, and the reference value is equal to the reference frequency.

4. The method according to claim 1, wherein after the step of outputting the first count value corresponding to the i-th 1-second pulse signal, further includes: In response to determining that the first count value is between a lower limit value and an upper limit value, obtain the difference value between the reference value and the first count value corresponding to the i-th 1-second pulse signal; In response to determining that the first count value is not between the lower limit value and the upper limit value, ignore the first count value.

5. The method according to claim 1, wherein the queue is a first-in-first-out queue.

6. The method according to claim 1, wherein the statistical characteristic value of the plurality of specific difference values is an average value of the plurality of specific difference values.

7. The method according to claim 1, wherein the step of determining the correction factor includes: Subtract the difference value corresponding to the i-N-th 1-second pulse signal from the difference value corresponding to the i-th 1-second pulse signal to generate a reference difference value; And Divide the reference difference value by N to generate the correction factor.

8. The method according to claim 1, wherein the signal generation circuit records a second count value, the clock signal includes a plurality of pulses, and the step of counting down from the reference count value based on the clock signal includes: In response to detecting one of the plurality of pulses of the clock signal, decrement the second count value.

9. A timing receiver, characterized in that, Comprising: A first counter configured to: Receive a clock signal and accumulate a first count value based on the clock signal; In response to receiving the i-th 1-second pulse signal, output the first count value corresponding to the i-th 1-second pulse signal and reset the first counter, where i is an index value; A comparator coupled to the first counter, obtaining a difference value between a reference value and the first count value corresponding to the i-th 1-second pulse signal, and storing the difference value in a queue; The queue coupled to the comparator and storing a plurality of specific difference values, wherein the plurality of specific difference values include the difference value corresponding to the i-th 1-second pulse signal to the difference value corresponding to the i-N+1-th 1-second pulse signal, and N is the depth of the queue; An estimation circuit coupled to the comparator and the queue, and generating a reference count value corresponding to the i-th 1-second pulse signal based on the plurality of specific difference values and the reference value, including: Obtaining a statistical characteristic value of the plurality of specific difference values and adding the statistical characteristic value to the reference value to generate the reference count value; or Obtaining the reference count value corresponding to the i-1-th 1-second pulse signal, obtaining the difference value corresponding to the i-th 1-second pulse signal and the difference value corresponding to the i-N-th 1-second pulse signal, and determining a correction factor therefrom, and adding the correction factor to the reference count value corresponding to the i-1-th 1-second pulse signal to generate the reference count value corresponding to the i-th 1-second pulse signal; A signal generation circuit coupled to the estimation circuit and configured to: Count down from the reference count value based on the clock signal; and In response to determining that the signal generation circuit counts down to a default value, output a corrected 1-second pulse signal.

10. The timing receiver according to claim 9, wherein the clock signal includes a plurality of pulses, and the first counter is configured to: In response to detecting one of the plurality of pulses of the clock signal, increment the first count value.

11. The timing receiver according to claim 9, wherein the clock signal has a reference frequency, and the reference value is equal to the reference frequency.

12. The timing receiver according to claim 9, further comprising a judgment circuit coupled between the first counter and the comparator, and configured to: Receive the first count value corresponding to the i-th 1-second pulse signal from the first counter; In response to determining that the first count value is between a lower limit value and an upper limit value, transfer the first count value to the comparator; In response to determining that the first count value is not between the lower limit value and the upper limit value, ignore the first count value.

13. The timing receiver according to claim 9, wherein the queue is a first-in-first-out queue.

14. The timing receiver according to claim 9, wherein the statistical characteristic value of the plurality of specific difference values is the average value of the plurality of specific difference values.

15. The timing receiver according to claim 9, wherein the estimation circuit is configured to: subtract the difference value corresponding to the i-th 1-second pulse signal from the difference value corresponding to the (i - N)-th 1-second pulse signal to generate a reference difference value; and divide the reference difference value by N to generate the correction factor.

16. The timing receiver according to claim 9, wherein the signal generation circuit records a second count value, the clock signal includes a plurality of pulses, and the signal generation circuit is configured to: decrement the second count value in response to detecting one of the plurality of pulses of the clock signal.

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