Highest Voltage Selection Circuit, Chip and Electronic Device

Abstract

Embodiments of the present disclosure provide a maximum voltage selection circuit, a chip, and an electronic device. The maximum voltage selection circuit includes: an enabling circuit, a static operation control circuit, a voltage comparison circuit, first and second level conversion circuits, and first and second output circuits. The enabling circuit generates first and second enabling signals according to an external enabling signal. The voltage comparison circuit compares the magnitudes of first and second input voltages to generate a first voltage indication signal when the second enabling signal is at an effective level. The first level conversion circuit generates a second voltage indication signal according to the first enabling signal and the first voltage indication signal. The static operation control circuit generates a static control signal according to the first and second enabling signals. The second level conversion circuit generates a third voltage indication signal according to the static control signal and the second voltage indication signal. The first and second output circuits respectively output the second and first input voltages as output voltages when the second and third voltage indication signals are at low levels.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and more particularly, to a highest voltage selection circuit, a chip, and an electronic device. Background Art

[0002] Integrated circuit technologies are widely used in all aspects of people's lives. In actual chip design and applications, some chips have multiple power supplies. Considering the power supply voltage range required for the operation of internal modules of the chip and the correct establishment of biasing, in some cases, it is necessary to provide the maximum power supply among multiple power supplies for the internal modules and biasing of the chip. Therefore, there is a need for a highest voltage selection circuit that can automatically select the highest supply voltage for the chip. Summary of the Invention

[0003] Embodiments described herein provide a highest voltage selection circuit, a chip, and an electronic device.

[0004] According to a first aspect of the present disclosure, there is provided a highest voltage selection circuit. The highest voltage selection circuit includes: an enable circuit, a static operation control circuit, a voltage comparison circuit, a first level conversion circuit, a second level conversion circuit, a first output circuit, and a second output circuit. The enable circuit is configured to: generate a first enable signal and a second enable signal according to an external enable signal. The second enable signal is an inverted signal of the first enable signal. The voltage comparison circuit is configured to: compare the magnitude of a first input voltage from a first input terminal and a second input voltage from a second input terminal to generate a first voltage indication signal when the second enable signal is at an effective level. The first level conversion circuit is configured to: generate a second voltage indication signal according to the first enable signal and the first voltage indication signal. Wherein, when the first voltage indication signal is at a high level and the first enable signal is at an effective level, the second voltage indication signal is converted to a low level; otherwise, the second voltage indication signal is converted to the first input voltage. The static operation control circuit is configured to: generate a static control signal according to the first enable signal and the second enable signal. The second level conversion circuit is configured to: generate a third voltage indication signal according to the static control signal and the second voltage indication signal. Wherein, when the second voltage indication signal is at the first input voltage and the static control signal is at the second input voltage, the third voltage indication signal is converted to a low level; otherwise, the third voltage indication signal is converted to the second input voltage. The first output circuit is configured to: output the second input voltage from an output terminal as an output voltage when the second voltage indication signal is at a low level. The second output circuit is configured to: output the first input voltage from the output terminal as an output voltage when the third voltage indication signal is at a low level.

[0005] In some embodiments of the present disclosure, the voltage comparison circuit includes: a first current source, a first transistor to a fifth transistor, and an eighth transistor. Wherein, the first current source is configured to provide a first current to the eighth transistor. The control electrode of the eighth transistor is provided with a second enable signal. The first electrode of the eighth transistor is coupled to the first current source. The second electrode of the eighth transistor is coupled to the control electrode and the second electrode of the first transistor. The first electrode of the first transistor is coupled to the second voltage terminal. The control electrode of the second transistor is coupled to the control electrode of the first transistor and the control electrode of the third transistor. The first electrode of the second transistor is coupled to the second voltage terminal. The second electrode of the second transistor is coupled to the control electrode and the second electrode of the fourth transistor. The first electrode of the third transistor is coupled to the second voltage terminal. The second electrode of the third transistor is coupled to the second electrode of the fifth transistor. The first electrode of the fourth transistor is coupled to the first input terminal. The control electrode of the fifth transistor is coupled to the control electrode of the fourth transistor. The first electrode of the fifth transistor is coupled to the second input terminal. Wherein, the voltage at the second electrode of the third transistor is the first voltage indication signal.

[0006] In some embodiments of the present disclosure, the first level conversion circuit includes: a first NAND gate. Wherein, the first input terminal of the first NAND gate is provided with the first voltage indication signal. The second input terminal of the first NAND gate is provided with the first enable signal. The second voltage indication signal is output from the output terminal of the first NAND gate. The power supply terminal of the first NAND gate is coupled to the first input terminal.

[0007] In some embodiments of the present disclosure, the second level conversion circuit includes: a second NAND gate. Wherein, the first input terminal of the second NAND gate is provided with the second voltage indication signal. The second input terminal of the second NAND gate is provided with the static control signal. The third voltage indication signal is output from the output terminal of the second NAND gate. The power supply terminal of the second NAND gate is coupled to the second input terminal.

[0008] In some embodiments of the present disclosure, the first output circuit includes: a sixth transistor. Wherein, the control electrode of the sixth transistor is provided with the second voltage indication signal. The first electrode of the sixth transistor is coupled to the output terminal. The second electrode of the sixth transistor is coupled to the second input terminal.

[0009] In some embodiments of the present disclosure, the second output circuit includes: a seventh transistor. Wherein, the control electrode of the seventh transistor is provided with the third voltage indication signal. The first electrode of the seventh transistor is coupled to the output terminal. The second electrode of the seventh transistor is coupled to the first input terminal.

[0010] In some embodiments of the present disclosure, the enabling circuit includes: a hysteresis voltage comparator and an inverter. Among them, the input terminal of the hysteresis voltage comparator is provided with an external enabling signal. The power supply terminal of the hysteresis voltage comparator is coupled to the first input terminal. The output terminal of the hysteresis voltage comparator is coupled to the input terminal of the inverter. A first enabling signal is output from the output terminal of the hysteresis voltage comparator. The power supply terminal of the inverter is coupled to the first input terminal. A second enabling signal is output from the output terminal of the inverter.

[0011] In some embodiments of the present disclosure, the static operating control circuit includes: a ninth transistor to a twelfth transistor. Among them, the control electrode of the ninth transistor is coupled to the second electrode of the tenth transistor and the second electrode of the twelfth transistor. The first electrode of the ninth transistor is coupled to the second input terminal. The second electrode of the ninth transistor is coupled to the control electrode of the tenth transistor and the second electrode of the eleventh transistor. The first electrode of the tenth transistor is coupled to the second input terminal. The control electrode of the eleventh transistor is provided with the second enabling signal. The first electrode of the eleventh transistor is coupled to the second voltage terminal. The control electrode of the twelfth transistor is provided with the first enabling signal. The first electrode of the twelfth transistor is coupled to the second voltage terminal.

[0012] According to a second aspect of the present disclosure, a maximum voltage selection circuit is provided. The maximum voltage selection circuit includes: a first current source, a first transistor to a twelfth transistor, a first NAND gate, a second NAND gate, a hysteresis voltage comparator, and an inverter. Among them, the first current source is configured to provide a first current to the eighth transistor. The control electrode of the eighth transistor is coupled to the output terminal of the inverter. The first electrode of the eighth transistor is coupled to the first current source. The second electrode of the eighth transistor is coupled to the control electrode and the second electrode of the first transistor. The first electrode of the first transistor is coupled to the second voltage terminal. The control electrode of the second transistor is coupled to the control electrode of the first transistor and the control electrode of the third transistor. The first electrode of the second transistor is coupled to the second voltage terminal. The second electrode of the second transistor is coupled to the control electrode and the second electrode of the fourth transistor. The first electrode of the third transistor is coupled to the second voltage terminal. The second electrode of the third transistor is coupled to the second electrode of the fifth transistor. The first electrode of the fourth transistor is coupled to the first input terminal. The control electrode of the fifth transistor is coupled to the control electrode of the fourth transistor. The first electrode of the fifth transistor is coupled to the second input terminal. The first input terminal of the first NAND gate is coupled to the second electrode of the fifth transistor. The second input terminal of the first NAND gate is coupled to the output terminal of the hysteresis voltage comparator and the control electrode of the twelfth transistor. The output terminal of the first NAND gate is coupled to the first input terminal of the second NAND gate. The power supply terminal of the first NAND gate is coupled to the first input terminal. The second input terminal of the second NAND gate is coupled to the second electrode of the ninth transistor, the control electrode of the tenth transistor, and the second electrode of the eleventh transistor. The output terminal of the second NAND gate is coupled to the control electrode of the seventh transistor. The power supply terminal of the second NAND gate is coupled to the second input terminal. The control electrode of the sixth transistor is coupled to the output terminal of the first NAND gate. The first electrode of the sixth transistor is coupled to the output terminal. The second electrode of the sixth transistor is coupled to the second input terminal. The first electrode of the seventh transistor is coupled to the output terminal. The second electrode of the seventh transistor is coupled to the first input terminal. The input terminal of the hysteresis voltage comparator is provided with an external enable signal. The power supply terminal of the hysteresis voltage comparator is coupled to the first input terminal. The output terminal of the hysteresis voltage comparator is coupled to the input terminal of the inverter. The power supply terminal of the inverter is coupled to the first input terminal. The control electrode of the ninth transistor is coupled to the second electrode of the tenth transistor and the second electrode of the twelfth transistor. The first electrode of the ninth transistor is coupled to the second input terminal. The first electrode of the tenth transistor is coupled to the second input terminal. The control electrode of the eleventh transistor is coupled to the output terminal of the inverter. The first electrode of the eleventh transistor is coupled to the second voltage terminal. The first electrode of the twelfth transistor is coupled to the second voltage terminal.

[0013] In some embodiments of the present disclosure, the first transistor to the third transistor and the eleventh transistor to the twelfth transistor are N-type transistors. The fourth transistor to the tenth transistor are P-type transistors.

[0014] According to a third aspect of the present disclosure, a chip is provided. The chip includes: the maximum voltage selection circuit according to the first aspect or the second aspect of the present disclosure.

[0015] According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device includes: a chip according to the third aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0017] Figure 1 is a schematic block diagram of a highest voltage selection circuit according to an embodiment of the present disclosure;

[0018] Figure 2 is Figure 1 an exemplary circuit diagram of the highest voltage selection circuit shown;

[0019] Figure 3 is another exemplary circuit diagram of the highest voltage selection circuit according to an embodiment of the present disclosure;

[0020] Figure 4 is another schematic block diagram of the highest voltage selection circuit according to an embodiment of the present disclosure; and

[0021] Figure 5 is Figure 4 an exemplary circuit diagram of the highest voltage selection circuit shown.

[0022] It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the subject matter of the present disclosure belongs. Further, it will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of the present disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetric, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled intermediate terminal of the MOS transistor is referred to as the control electrode, and the remaining two terminals of the MOS transistor are respectively referred to as the first electrode and the second electrode. Additionally, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] Figure 1 FIG. 6 shows a schematic block diagram of a maximum voltage selection circuit 100 according to an embodiment of the present disclosure. The maximum voltage selection circuit 100 includes: a voltage comparison circuit 110, a first level conversion circuit 120, a second level conversion circuit 130, a first output circuit 140, and a second output circuit 150.

[0027] The voltage comparison circuit 110 is coupled to a first input terminal Vin1 and a second input terminal Vin2. The voltage comparison circuit 110 is coupled to the first level conversion circuit 120 via a first node N1. The voltage comparison circuit 110 is configured to: compare the magnitudes of a first input voltage Vin1 from the first input terminal Vin1 and a second input voltage Vin2 from the second input terminal Vin2 to generate a first voltage indication signal, and provide the first voltage indication signal to the first level conversion circuit 120 via the first node N1. In some embodiments of the present disclosure, the first input voltage Vin1 and the second input voltage Vin2 can be used as the power supply voltages of a lower-level circuit.

[0028] In some embodiments of the present disclosure, when the first input voltage Vin1 is greater than or equal to the second input voltage Vin2, the first voltage indication signal is at a low level. When the first input voltage Vin1 is less than the second input voltage Vin2, the first voltage indication signal is at a high level. In other embodiments of the present disclosure, when the first input voltage Vin1 is greater than the second input voltage Vin2, the first voltage indication signal is at a low level. When the first input voltage Vin1 is less than or equal to the second input voltage Vin2, the first voltage indication signal is at a high level.

[0029] The first level conversion circuit 120 is coupled to the voltage comparison circuit 110 via the first node N1. The first level conversion circuit 120 is coupled to the second level conversion circuit 130 and the first output circuit 140 via the second node N2. The first level conversion circuit 120 is further coupled to the first input terminal Vin1. The first level conversion circuit 120 is configured to: generate a second voltage indication signal according to the first voltage indication signal, and provide the second voltage indication signal to the second level conversion circuit 130 and the first output circuit 140 via the second node N2. Wherein, when the first voltage indication signal is at a low level, the second voltage indication signal is converted into the first input voltage Vin1. When the first voltage indication signal is at a high level, the second voltage indication signal is converted into a low level.

[0030] The second level conversion circuit 130 is coupled to the first level conversion circuit 120 and the first output circuit 140 via the second node N2. The second level conversion circuit 130 is coupled to the second output circuit 150 via the third node N3. The second level conversion circuit 130 is further coupled to the second input terminal Vin2. The second level conversion circuit 130 is configured to: generate a third voltage indication signal according to the second voltage indication signal, and provide the third voltage indication signal to the second output circuit 150 via the third node N3. Wherein, when the second voltage indication signal is at a low level, the third voltage indication signal is converted into the second input voltage Vin2. When the second voltage indication signal is at the first input voltage Vin1, the third voltage indication signal is converted into a low level.

[0031] The first output circuit 140 is coupled to the first level conversion circuit 120 and the second level conversion circuit 130 via the second node N2. The first output circuit 140 is further coupled to the second input terminal Vin2. The first output circuit 140 is configured to: output the second input voltage Vin2 from the output terminal Vout as the output voltage when the second voltage indication signal is at a low level. The first output circuit 140 is further configured to: stop working when the second voltage indication signal is at the first input voltage Vin1, so as not to affect the magnitude of the output voltage.

[0032] The second output circuit 150 is coupled to the second level conversion circuit 130 via the third node N3. The second output circuit 150 is further coupled to the first input terminal Vin1. The second output circuit 150 is configured to: output the first input voltage Vin1 from the output terminal Vout as the output voltage when the third voltage indication signal is at a low level. The second output circuit 150 is further configured to: stop working when the third voltage indication signal is at the second input voltage Vin2, so as not to affect the magnitude of the output voltage.

[0033] When the first input voltage Vin1 is greater than or equal to the second input voltage Vin2, the first voltage indication signal is at a low level. The second voltage indication signal is at the first input voltage Vin1. The third voltage indication signal is at a low level. Therefore, the second output circuit 150 outputs the first input voltage Vin1 from the output terminal Vout as the output voltage.

[0034] When the first input voltage Vin1 is less than the second input voltage Vin2, the first voltage indication signal is at a high level. The second voltage indication signal is at a low level. The third voltage indication signal is at the second input voltage Vin2. Therefore, the first output circuit 140 outputs the second input voltage Vin2 from the output terminal Vout as the output voltage.

[0035] In this way, the highest voltage selection circuit 100 according to the embodiment of the present disclosure can automatically output the maximum voltage of the first input voltage Vin1 and the second input voltage Vin2 as the power supply voltage for the subsequent circuit.

[0036] Figure 2 The exemplary circuit diagram of the highest voltage selection circuit 200 according to the embodiment of the present disclosure is shown. The voltage comparison circuit 210 includes: a first current source Ib1, and a first transistor M1 to a fifth transistor M5. Among them, the first current source Ib1 is configured to provide a first current to the first transistor M1. The control electrode of the first transistor M1 is coupled to the second electrode of the first transistor M1 and the first current source Ib1. The first electrode of the first transistor M1 is coupled to the second voltage terminal V2. The control electrode of the second transistor M2 is coupled to the control electrode of the first transistor M1 and the control electrode of the third transistor M3. The first electrode of the second transistor M2 is coupled to the second voltage terminal V2. The second electrode of the second transistor M2 is coupled to the control electrode and the second electrode of the fourth transistor M4. The first electrode of the third transistor M3 is coupled to the second voltage terminal V2. The second electrode of the third transistor M3 is coupled to the first node N1 and the second electrode of the fifth transistor M5. The first electrode of the fourth transistor M4 is coupled to the first input terminal Vin1. The control electrode of the fifth transistor M5 is coupled to the control electrode of the fourth transistor M4. The first electrode of the fifth transistor M5 is coupled to the second input terminal Vin2.

[0037] The first level conversion circuit 220 includes: a first inverter Ng1. Among them, the input terminal of the first inverter Ng1 is coupled to the first node N1. The output terminal Vout of the first inverter Ng1 is coupled to the second node N2. The power supply terminal of the first inverter Ng1 is coupled to the first input terminal Vin1.

[0038] The second level conversion circuit 230 includes: a second inverter Ng2. Wherein, the input terminal of the second inverter Ng2 is coupled to the second node N2. The output terminal Vout of the second inverter Ng2 is coupled to the third node N3. The power supply terminal of the second inverter Ng2 is coupled to the second input terminal Vin2.

[0039] The first output circuit 240 includes: a sixth transistor M6. Wherein, the control electrode of the sixth transistor M6 is coupled to the second node N2. The first pole of the sixth transistor M6 is coupled to the output terminal Vout. The second pole of the sixth transistor M6 is coupled to the second input terminal Vin2.

[0040] The second output circuit 250 includes: a seventh transistor M7. Wherein, the control electrode of the seventh transistor M7 is coupled to the third node N3. The first pole of the seventh transistor M7 is coupled to the output terminal Vout. The second pole of the seventh transistor M7 is coupled to the first input terminal Vin1.

[0041] In Figure 2 the example, the second voltage terminal V2 is grounded. The first transistor M1 to the third transistor M3 are NMOS transistors. The fourth transistor M4 to the seventh transistor M7 are PMOS transistors. Those skilled in the art should understand that based on the above inventive concept, the Figure 2 circuit shown in Figure 2 should also fall within the protection scope of the present disclosure. In this variant, the above transistors and voltage terminals can also have settings different from those of the

[0042] example shown. Figure 2 Those skilled in the art should understand that the internal structures of the [[ID=ed22]]

[0043] circuits in Figure 2 are exemplary, and can also be implemented by other circuits. The embodiments of the present disclosure do not limit the specific implementation manners of these circuits.

[0044] When the first input voltage Vin1 is greater than or equal to the second input voltage Vin2, the absolute value of the gate-source voltage of the fourth transistor M4 is greater than the absolute value of the gate-source voltage of the fifth transistor M5. The current flowing through the fifth transistor M5 is less than the current flowing through the third transistor M3. Therefore, the voltage of the first node N1 is at a low level. After the inversion of the first inverter Ng1, the voltage of the second node N2 is equal to the supply voltage of the first inverter Ng1 (i.e., the first input voltage Vin1). Since the first input voltage Vin1 is greater than or equal to the second input voltage Vin2, the sixth transistor M6 is turned off. On the other hand, after the inversion of the second inverter Ng2, the voltage of the third node N3 is equal to the low level. Therefore, the seventh transistor M7 is turned on, and the first input voltage Vin1 is output from the output terminal Vout as the output voltage.

[0045] When the first input voltage Vin1 is less than the second input voltage Vin2, the absolute value of the gate-source voltage of the fourth transistor M4 is less than the absolute value of the gate-source voltage of the fifth transistor M5. The current flowing through the fifth transistor M5 is greater than the current flowing through the third transistor M3. Therefore, the voltage of the first node N1 is at a high level. After the inversion of the first inverter Ng1, the voltage of the second node N2 is equal to the low level. After the inversion of the second inverter Ng2, the voltage of the third node N3 is equal to the supply voltage of the second inverter Ng2 (i.e., the second input voltage Vin2). Since the first input voltage Vin1 is less than the second input voltage Vin2, the seventh transistor M7 is turned off. Since the second node N2 is at a low level, the sixth transistor M6 is turned on, and the second input voltage Vin2 is output from the output terminal Vout as the output voltage.

[0046] In this way, the maximum voltage selection circuit 200 according to the embodiment of the present disclosure realizes automatically outputting the maximum voltage of the first input voltage Vin1 and the second input voltage Vin2 as the power supply voltage of the subsequent circuit through a simple circuit structure.

[0047] In some application scenarios, it is desired that the chip using the highest voltage selection circuit can be turned off under the control of an external enable signal to save the power consumption of the chip. To ensure that the highest voltage selection circuit can be properly biased when the chip is turned off and the sixth transistor M6 and the seventh transistor M7 are not interconnected (the sixth transistor M6 and the seventh transistor M7 are not turned on simultaneously), a weak current source Ib2 needs to be generated inside the chip when the chip is turned off to bias the original highest voltage selection circuit instead of the first current source Ib1 when the chip is operating normally. If the highest voltage selection circuit is not biased when the chip is turned off, the voltage at the first node N1 may not output a pure high or low level, but instead be at an intermediate level. This is very dangerous for the first inverter Ng1. If the voltage at the first node N1 is within the linear region of the first inverter Ng1, it will cause the NMOS transistor and the PMOS transistor inside the first inverter Ng1 to be turned on simultaneously, and a current of dozens or even hundreds of microamperes will flow into the ground terminal of the chip, thus greatly increasing the static power consumption of the chip when it is turned off.

[0048] Figure 3 The highest voltage selection circuit with this structure is shown. When the external enable signal EN is at a low level, the chip is turned off. The hysteresis comparator CMP outputs a low level, which causes the ninth transistor M9 to conduct. The first input voltage Vin1 output by the inverter Ng3 turns off the eighth transistor M8. Therefore, the current source Ib2 biases the original highest voltage selection circuit instead of the first current source Ib1, thereby avoiding the voltage at the first node N1 from not outputting a pure high or low level. The highest voltage selection circuit with this structure can still operate normally when the chip is turned off, but it also brings two drawbacks:

[0049] (1) To a certain extent, it increases the static current when the chip is turned off: Since the voltage comparison circuit needs to be made to work when the chip is turned off, the current source Ib2 is required to bias the voltage comparison circuit, which will increase the static current when the chip is turned off to a certain extent.

[0050] (2) There is a risk of significantly increasing the static current when the chip is turned off: the bias current of the voltage comparison circuit decreases significantly compared to when the chip is operating normally. Then, the transconductance values of the fourth transistor M4 and the fifth transistor M5 in the voltage comparison circuit will decrease. However, the mismatch between the fourth transistor M4 and the fifth transistor M5 will not decrease with the decrease of the bias current. This will cause a larger input voltage difference between the fourth transistor M4 and the fifth transistor M5 to overcome the influence of the mismatch between the fourth transistor M4 and the fifth transistor M5 on the comparison result. Therefore, when the input voltage difference between the fourth transistor M4 and the fifth transistor M5 is not large enough and falls within the influence range of the mismatch between the fourth transistor M4 and the fifth transistor M5, a pure high or low level cannot be output from the first node N1, but is at an intermediate level. This is very dangerous for the first inverter Ng1. If the voltage at the first node N1 is within the linear region of the first inverter Ng1, it will cause the NMOS transistor and the PMOS transistor in the first inverter Ng1 to conduct simultaneously, and a current of dozens or even hundreds of microamperes will flow into the ground terminal of the chip, thus greatly increasing the static power consumption of the chip when it is turned off.

[0051] Therefore, an embodiment of the present disclosure further provides a highest voltage selection circuit, aiming to reduce the static power consumption of the chip when it is turned off. Figure 4 A schematic block diagram of a highest voltage selection circuit 400 according to an embodiment of the present disclosure is shown. The highest voltage selection circuit 400 includes: an enable circuit 460, a static operation control circuit 470, a voltage comparison circuit 410, a first level conversion circuit 420, a second level conversion circuit 430, a first output circuit 440, and a second output circuit 450.

[0052] The enable circuit 460 is coupled to the static operation control circuit 470 and the first level conversion circuit 420 via the fourth node N4. The enable circuit 460 is coupled to the static operation control circuit 470 and the voltage comparison circuit 410 via the fifth node N5. The enable circuit 460 is further coupled to an external enable signal terminal EN and a first input terminal Vin1. The enable circuit 460 is configured to: generate a first enable signal and a second enable signal according to the external enable signal EN. The second enable signal is the inverted signal of the first enable signal. In some embodiments of the present disclosure, when the external enable signal EN is at a low level, the first enable signal is at a low level, and the second enable signal is at the first input voltage Vin1. When the external enable signal EN is at a high level, the first enable signal is at the first input voltage Vin1, and the second enable signal is at a low level. In some embodiments of the present disclosure, the signal at the fourth node N4 is the first enable signal, and the signal at the fifth node N5 is the second enable signal.

[0053] The voltage comparison circuit 410 is coupled to the first input terminal Vin1 and the second input terminal Vin2. The voltage comparison circuit 410 is coupled to the first level conversion circuit 420 via the first node N1. The voltage comparison circuit 410 is coupled to the enable circuit 460 and the static operation control circuit 470 via the fifth node N5. The voltage comparison circuit 410 is configured to: when the second enable signal is at an active level (e.g., low level), compare the magnitude of the first input voltage Vin1 from the first input terminal Vin1 and the second input voltage Vin2 from the second input terminal Vin2 to generate a first voltage indication signal, and provide the first voltage indication signal to the first level conversion circuit 420 via the first node N1. In some embodiments of the present disclosure, the first input voltage Vin1 and the second input voltage Vin2 can be used as the power supply voltages of the lower-level circuit. The voltage comparison circuit 410 is further configured to: stop operating when the second enable signal is at an inactive level (e.g., high level).

[0054] In some embodiments of the present disclosure, when the first input voltage Vin1 is greater than or equal to the second input voltage Vin2, the first voltage indication signal is at a low level. When the first input voltage Vin1 is less than the second input voltage Vin2, the first voltage indication signal is at a high level. In some other embodiments of the present disclosure, when the first input voltage Vin1 is greater than the second input voltage Vin2, the first voltage indication signal is at a low level. When the first input voltage Vin1 is less than or equal to the second input voltage Vin2, the first voltage indication signal is at a high level.

[0055] The first level conversion circuit 420 is coupled to the voltage comparison circuit 410 via the first node N1. The first level conversion circuit 420 is coupled to the second level conversion circuit 430 and the first output circuit 440 via the second node N2. The first level conversion circuit 420 is further coupled to the first input terminal Vin1. The first level conversion circuit 420 is configured to: generate a second voltage indication signal according to the first enable signal and the first voltage indication signal. Wherein, when the first voltage indication signal is at a high level and the first enable signal is at an active level (e.g., high level), the second voltage indication signal is converted to a low level, otherwise the second voltage indication signal is converted to the first input voltage Vin1.

[0056] The static operating control circuit 470 is coupled to the enabling circuit 460 via the fourth node N4 and the fifth node N5. The static operating control circuit 470 is also coupled to the second input terminal Vin2. The static operating control circuit 470 is configured to generate a static control signal according to the first enabling signal and the second enabling signal. In some embodiments of the present disclosure, when the first enabling signal and the second enabling signal are at an invalid level, the static control signal is at a low level. When the first enabling signal and the second enabling signal are at an effective level, the static control signal is at the second input voltage Vin2.

[0057] The second level conversion circuit 430 is coupled to the first level conversion circuit 420 and the first output circuit 440 via the second node N2. The second level conversion circuit 430 is coupled to the second output circuit 450 via the third node N3. The second level conversion circuit 430 is also coupled to the second input terminal Vin2. The second level conversion circuit 430 is configured to generate a third voltage indication signal according to the static control signal and the second voltage indication signal. Wherein, when the second voltage indication signal is at the first input voltage Vin1 and the static control signal is at the second input voltage Vin2, the third voltage indication signal is converted to a low level, otherwise the third voltage indication signal is converted to the second input voltage Vin2.

[0058] The first output circuit 440 is coupled to the first level conversion circuit 420 and the second level conversion circuit 430 via the second node N2. The first output circuit 440 is also coupled to the second input terminal Vin2. The first output circuit 440 is configured to output the second input voltage Vin2 from the output terminal Vout as the output voltage when the second voltage indication signal is at a low level. The first output circuit 440 is also configured to stop operating when the second voltage indication signal is at the first input voltage Vin1, so as not to affect the magnitude of the output voltage.

[0059] The second output circuit 450 is coupled to the second level conversion circuit 430 via the third node N3. The second output circuit 450 is also coupled to the first input terminal Vin1. The second output circuit 450 is configured to output the first input voltage Vin1 from the output terminal Vout as the output voltage when the third voltage indication signal is at a low level. The second output circuit 450 is also configured to stop operating when the third voltage indication signal is at the second input voltage Vin2, so as not to affect the magnitude of the output voltage.

[0060] When the external enable signal EN is at a low level, the chip is turned off. The first enable signal is at a low level, and the second enable signal is at the first input voltage Vin1. The voltage comparison circuit 410 stops working and no bias current (the first current Ib1) is required. The outputs of the first level conversion circuit 420 and the second level conversion circuit 430 are both at a definite high level. Therefore, the static power consumption of the highest voltage selection circuit 400 is reduced compared to that of Figure 3 the structure.

[0061] When the external enable signal EN is at a high level, the first enable signal is at the first input voltage Vin1, and the second enable signal is at a low level. The voltage comparison circuit 410 works normally. The state changes of the second voltage indication signal and the third voltage indication signal are the same as those of Figure 3 the structure, so the highest voltage selection circuit 400 can work normally.

[0062] Figure 5 is Figure 4 The exemplary circuit diagram of the highest voltage selection circuit 500 shown. The voltage comparison circuit 510 includes: a first current source Ib1, a first transistor M1 to a fifth transistor M5, and an eighth transistor M8. Among them, the first current source Ib1 is configured to provide the first current to the eighth transistor M8. The control electrode of the eighth transistor M8 is provided with the second enable signal. The first electrode of the eighth transistor M8 is coupled to the first current source Ib1. The second electrode of the eighth transistor M8 is coupled to the control electrode and the second electrode of the first transistor M1. The first electrode of the first transistor M1 is coupled to the second voltage terminal V2. The control electrode of the second transistor M2 is coupled to the control electrode of the first transistor M1 and the control electrode of the third transistor M3. The first electrode of the second transistor M2 is coupled to the second voltage terminal V2. The second electrode of the second transistor M2 is coupled to the control electrode and the second electrode of the fourth transistor M4. The first electrode of the third transistor M3 is coupled to the second voltage terminal V2. The second electrode of the third transistor M3 is coupled to the second electrode of the fifth transistor M5. The first electrode of the fourth transistor M4 is coupled to the first input terminal Vin1. The control electrode of the fifth transistor M5 is coupled to the control electrode of the fourth transistor M4. The first electrode of the fifth transistor M5 is coupled to the second input terminal Vin2. Among them, the voltage at the second electrode of the third transistor M3 is the first voltage indication signal.

[0063] The first level conversion circuit 520 includes: a first NAND gate NAND1. Among them, the first input terminal of the first NAND gate NAND1 is provided with the first voltage indication signal. The second input terminal of the first NAND gate NAND1 is provided with the first enable signal. The second voltage indication signal is output from the output terminal of the first NAND gate NAND1. The power supply terminal of the first NAND gate NAND1 is coupled to the first input terminal Vin1.

[0064] The second level conversion circuit 530 includes: a second NAND gate NAND2. Among them, the first input terminal of the second NAND gate NAND2 is provided with a second voltage indication signal. The second input terminal of the second NAND gate NAND2 is provided with a static control signal. A third voltage indication signal is output from the output terminal of the second NAND gate NAND2. The power supply terminal of the second NAND gate NAND2 is coupled to the second input terminal Vin2.

[0065] The first output circuit 540 includes: a sixth transistor M6. Among them, the control electrode of the sixth transistor M6 is provided with a second voltage indication signal. The first pole of the sixth transistor M6 is coupled to the output terminal Vout. The second pole of the sixth transistor M6 is coupled to the second input terminal Vin2.

[0066] The second output circuit 550 includes: a seventh transistor M7. Among them, the control electrode of the seventh transistor M7 is provided with a third voltage indication signal. The first pole of the seventh transistor M7 is coupled to the output terminal Vout. The second pole of the seventh transistor M7 is coupled to the first input terminal Vin1.

[0067] The enable circuit 560 includes: a hysteresis voltage comparator CMP and an inverter Ng3. Among them, the input terminal of the hysteresis voltage comparator CMP is provided with an external enable signal EN. The power supply terminal of the hysteresis voltage comparator CMP is coupled to the first input terminal Vin1. The output terminal of the hysteresis voltage comparator CMP is coupled to the input terminal of the inverter Ng3. A first enable signal is output from the output terminal of the hysteresis voltage comparator CMP. The power supply terminal of the inverter Ng3 is coupled to the first input terminal Vin1. A second enable signal is output from the output terminal of the inverter Ng3.

[0068] The static operating control circuit 570 includes: ninth transistors M9 to twelfth transistors M12. Among them, the control electrode of the ninth transistor M9 is coupled to the second pole of the tenth transistor M10 and the second pole of the twelfth transistor M12. The first pole of the ninth transistor M9 is coupled to the second input terminal Vin2. The second pole of the ninth transistor M9 is coupled to the control electrode of the tenth transistor M10 and the second pole of the eleventh transistor M11. The first pole of the tenth transistor M10 is coupled to the second input terminal Vin2. The control electrode of the eleventh transistor M11 is provided with a second enable signal. The first pole of the eleventh transistor M11 is coupled to the second voltage terminal V2. The control electrode of the twelfth transistor M12 is provided with a first enable signal. The first pole of the twelfth transistor M12 is coupled to the second voltage terminal V2.

[0069] When the external enable signal EN is at a low level, the chip is turned off. The first enable signal is at a low level, and the second enable signal is at the first input voltage Vin1. The eighth transistor M8 is cut off, and the first current source Ib1 is not connected to the voltage comparison circuit 510. The voltage of the fourth node N4 is at a low level. Therefore, the voltage of the second node N2 is equal to the first input voltage Vin1. The voltage of the fifth node N5 is equal to the first input voltage Vin1. Therefore, the eleventh transistor M11 is turned on, and the voltage of the sixth node N6 is equal to the second voltage V2 (low level). Therefore, the voltage of the third node N3 is equal to the second input voltage Vin2. Since the input voltages of the first NAND gate NAND1 and the second NAND gate NAND2 are both a definite low level, there are no simultaneously conducting NMOS transistors and PMOS transistors inside the first NAND gate NAND1 and the second NAND gate NAND2. The static power consumption of the highest voltage selection circuit 500 is reduced compared to Figure 3 the structure of

[0070] When the difference between the first input voltage Vin1 and the second input voltage Vin2 is greater than the absolute value of the threshold voltage of the seventh transistor M7, the seventh transistor M7 is turned on, and the output voltage Vout is equal to the first input voltage Vin1. When the difference between the second input voltage Vin2 and the first input voltage Vin1 is greater than the absolute value of the threshold voltage of the sixth transistor M6, the sixth transistor M6 is turned on, and the output voltage Vout is equal to the second input voltage Vin2. When the first input voltage Vin1 is equal to the second input voltage Vin2, both the sixth transistor M6 and the seventh transistor M7 are cut off, and the output voltage Vout is equal to the first input voltage Vin1 minus the voltage difference across the body diodes of the sixth transistor M6 or the seventh transistor M7. However, at this time, since the external enable signal EN is at a low level, the downstream circuit powered by the output voltage Vout is also turned off, so this effect can be ignored.

[0071] When the external enable signal EN is at a high level, the first enable signal is at the first input voltage Vin1, and the second enable signal is at a low level. The voltage comparison circuit 510 operates normally. The voltage of the fourth node N4 is equal to the first input voltage Vin1. Therefore, the voltage of the second node N2 only changes following the voltage of the first node N1. The twelfth transistor M12 is turned on, which causes the ninth transistor M9 to be turned on. The voltage of the sixth node N6 is equal to the second input voltage Vin2. Therefore, the voltage of the third node N3 only changes following the voltage of the second node N2. The state changes of the second voltage indication signal and the third voltage indication signal are the same as those of Figure 3 the structure of

[0072] In the highest voltage selection circuit according to the embodiment of the present disclosure, there is no need to provide a static operating current source (Figure 3 in Ib2). Even if the voltage comparison circuit loses the current bias due to the external enable signal EN being at a low level, resulting in abnormal operation (i.e., when the output terminal (the first node N1) of the voltage comparison circuit cannot output effective high / low levels), since the second input terminals of the two NAND gates in the subsequent stage are both driven by a determined low level, it will not cause the leakage risk caused by the simultaneous conduction of the NMOS transistor and the PMOS transistor inside the subsequent circuit. The highest voltage selection circuit according to the embodiment of the present disclosure can operate without consuming static current when the external enable signal EN is at a low level.

[0073] The embodiment of the present disclosure also provides a chip. The chip includes the highest voltage selection circuit according to the embodiment of the present disclosure. The chip is, for example, a power management chip.

[0074] The embodiment of the present disclosure also provides an electronic device. The electronic device includes the chip according to the embodiment of the present disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer, a smart phone, etc.

[0075] In summary, the embodiment of the present disclosure proposes a practical and low-cost highest voltage selection circuit. The embodiment of the present disclosure realizes the function of automatically outputting the maximum voltage among two power supply voltages through a simple circuit structure, and can provide the maximum power supply voltage for the subsequent circuit. Further, the embodiment of the present disclosure also considers the static power consumption of the highest voltage selection circuit, and controls the state of the highest voltage selection circuit when the chip is turned off by setting an enable circuit and a static operation control circuit, avoiding the problem of large static current when the chip is turned off.

[0076] Unless the context clearly indicates otherwise, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, it generally includes the corresponding plural terms. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used in this specification, particularly when it is located after a group of terms, the "example" is merely exemplary and explanatory, and should not be considered exclusive or extensive.

[0077] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that the various aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description herein and the specific embodiments are intended for illustrative purposes only and are not intended to limit the scope of the present application.

[0078] The above has described several embodiments of the present disclosure in detail. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A maximum voltage selection circuit, comprising: An enabling circuit, a static operation control circuit, a voltage comparison circuit, a first level conversion circuit, a second level conversion circuit, a first output circuit, and a second output circuit Wherein, the enabling circuit is configured to: generate a first enabling signal and a second enabling signal according to an external enabling signal, and the second enabling signal is an inverted signal of the first enabling signal; The voltage comparison circuit is configured to: when the second enabling signal is at an effective level, compare the magnitudes of a first input voltage from a first input terminal and a second input voltage from a second input terminal to generate a first voltage indication signal; The first level conversion circuit is configured to: generate a second voltage indication signal according to the first enabling signal and the first voltage indication signal, wherein when the first voltage indication signal is at a high level and the first enabling signal is at an effective level, the second voltage indication signal is converted to a low level, otherwise the second voltage indication signal is converted to the first input voltage; The static operation control circuit is configured to: generate a static control signal according to the first enabling signal and the second enabling signal; The second level conversion circuit is configured to: generate a third voltage indication signal according to the static control signal and the second voltage indication signal, wherein when the second voltage indication signal is at the first input voltage and the static control signal is at the second input voltage, the third voltage indication signal is converted to a low level, otherwise the third voltage indication signal is converted to the second input voltage; The first output circuit is configured to: output the second input voltage from an output terminal as an output voltage when the second voltage indication signal is at a low level; The second output circuit is configured to: output the first input voltage from the output terminal as the output voltage when the third voltage indication signal is at a low level.

2. The highest voltage selection circuit according to claim 1, wherein The voltage comparison circuit includes: a first current source, a first transistor to a fifth transistor, and an eighth transistor Wherein, the first current source is configured to provide a first current to the eighth transistor; The control electrode of the eighth transistor is provided with the second enabling signal, the first electrode of the eighth transistor is coupled to the first current source, and the second electrode of the eighth transistor is coupled to the control electrode and the second electrode of the first transistor; The first electrode of the first transistor is coupled to a second voltage terminal; The control electrode of the second transistor is coupled to the control electrode of the first transistor and the control electrode of the third transistor, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the control electrode and the second electrode of the fourth transistor; The first electrode of the third transistor is coupled to the second voltage terminal, and the second electrode of the third transistor is coupled to the second electrode of the fifth transistor; The first electrode of the fourth transistor is coupled to the first input terminal; The control electrode of the fifth transistor is coupled to the control electrode of the fourth transistor, and the first electrode of the fifth transistor is coupled to the second input terminal; Wherein, the voltage at the second pole of the third transistor is the first voltage indication signal.

3. The highest voltage selection circuit according to claim 1, wherein, The first level conversion circuit includes: a first NAND gate, wherein, the first input terminal of the first NAND gate is provided with the first voltage indication signal, the second input terminal of the first NAND gate is provided with the first enable signal, the second voltage indication signal is output from the output terminal of the first NAND gate, and the power supply terminal of the first NAND gate is coupled to the first input terminal.

4. The highest voltage selection circuit according to claim 1, wherein, The second level conversion circuit includes: a second NAND gate, wherein, the first input terminal of the second NAND gate is provided with the second voltage indication signal, the second input terminal of the second NAND gate is provided with the static control signal, the third voltage indication signal is output from the output terminal of the second NAND gate, and the power supply terminal of the second NAND gate is coupled to the second input terminal.

5. The highest voltage selection circuit according to any one of claims 1 to 4, wherein, The first output circuit includes: a sixth transistor, wherein, the control electrode of the sixth transistor is provided with the second voltage indication signal, the first pole of the sixth transistor is coupled to the output terminal, and the second pole of the sixth transistor is coupled to the second input terminal; and / or wherein, the second output circuit includes: a seventh transistor, wherein, the control electrode of the seventh transistor is provided with the third voltage indication signal, the first pole of the seventh transistor is coupled to the output terminal, and the second pole of the seventh transistor is coupled to the first input terminal.

6. The highest voltage selection circuit according to any one of claims 1 to 4, wherein, The enable circuit includes: a hysteresis voltage comparator and an inverter, wherein, the input terminal of the hysteresis voltage comparator is provided with the external enable signal, the power supply terminal of the hysteresis voltage comparator is coupled to the first input terminal, the output terminal of the hysteresis voltage comparator is coupled to the input terminal of the inverter, and the first enable signal is output from the output terminal of the hysteresis voltage comparator; the power supply terminal of the inverter is coupled to the first input terminal, and the second enable signal is output from the output terminal of the inverter.

7. The highest voltage selection circuit according to any one of claims 1 to 4, wherein, The static operation control circuit includes: a ninth transistor to a twelfth transistor, wherein, the control electrode of the ninth transistor is coupled to the second pole of the tenth transistor and the second pole of the twelfth transistor, the first pole of the ninth transistor is coupled to the second input terminal, and the second pole of the ninth transistor is coupled to the control electrode of the tenth transistor and the second pole of the eleventh transistor; the first pole of the tenth transistor is coupled to the second input terminal; the control electrode of the eleventh transistor is provided with the second enable signal, the first pole of the eleventh transistor is coupled to the second voltage terminal; the control electrode of the twelfth transistor is provided with the first enable signal, the first pole of the twelfth transistor is coupled to the second voltage terminal.

8. A maximum voltage selection circuit, comprising: A first current source, a first transistor to a twelfth transistor, a first NAND gate, a second NAND gate, a hysteresis voltage comparator, and an inverter, wherein, the first current source is configured to provide a first current to an eighth transistor; the control electrode of the eighth transistor is coupled to the output terminal of the inverter, the first pole of the eighth transistor is coupled to the first current source, and the second pole of the eighth transistor is coupled to the control electrode and the second pole of the first transistor. The first pole of the first transistor is coupled to the second voltage terminal; The control pole of the second transistor is coupled to the control pole of the first transistor and the control pole of the third transistor. The first pole of the second transistor is coupled to the second voltage terminal, and the second pole of the second transistor is coupled to the control pole and the second pole of the fourth transistor; The first pole of the third transistor is coupled to the second voltage terminal, and the second pole of the third transistor is coupled to the second pole of the fifth transistor; The first pole of the fourth transistor is coupled to the first input terminal; The control pole of the fifth transistor is coupled to the control pole of the fourth transistor, and the first pole of the fifth transistor is coupled to the second input terminal; The first input terminal of the first NAND gate is coupled to the second pole of the fifth transistor. The second input terminal of the first NAND gate is coupled to the output terminal of the hysteresis voltage comparator and the control pole of the twelfth transistor. The output terminal of the first NAND gate is coupled to the first input terminal of the second NAND gate, and the power supply terminal of the first NAND gate is coupled to the first input terminal; The second input terminal of the second NAND gate is coupled to the second pole of the ninth transistor, the control pole of the tenth transistor, and the second pole of the eleventh transistor. The output terminal of the second NAND gate is coupled to the control pole of the seventh transistor, and the power supply terminal of the second NAND gate is coupled to the second input terminal; The control pole of the sixth transistor is coupled to the output terminal of the first NAND gate. The first pole of the sixth transistor is coupled to the output terminal, and the second pole of the sixth transistor is coupled to the second input terminal; The first pole of the seventh transistor is coupled to the output terminal, and the second pole of the seventh transistor is coupled to the first input terminal; The input terminal of the hysteresis voltage comparator is provided with an external enable signal. The power supply terminal of the hysteresis voltage comparator is coupled to the first input terminal, and the output terminal of the hysteresis voltage comparator is coupled to the input terminal of the inverter; The power supply terminal of the inverter is coupled to the first input terminal; The control pole of the ninth transistor is coupled to the second pole of the tenth transistor and the second pole of the twelfth transistor. The first pole of the ninth transistor is coupled to the second input terminal; The first pole of the tenth transistor is coupled to the second input terminal; The control pole of the eleventh transistor is coupled to the output terminal of the inverter, and the first pole of the eleventh transistor is coupled to the second voltage terminal; The first pole of the twelfth transistor is coupled to the second voltage terminal.

9. A chip, comprising: The highest voltage selection circuit according to any one of claims 1-8.

10. An electronic device, comprising: The chip according to claim 9.

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