Storage device sharing system and method of operating the same

Abstract

Embodiments of the present disclosure relate to a storage device sharing system and an operating method thereof. According to embodiments of the present disclosure, the storage device sharing system can include i) a plurality of storage devices each including a first memory buffer including a plurality of first type storage blocks and a second memory buffer including a plurality of second type storage blocks, ii) a host device configured to determine whether to set the first memory buffer of a first storage device among the plurality of storage devices as an area for storing data to be written to a second storage device among the plurality of storage devices based on a sharing state set for the first storage device.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0155840, filed on November 12, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a storage device sharing system and its operation method. Background Technology

[0004] Memory systems include memory devices that store data based on requests from a host device such as a computer, server, smartphone, tablet, or other electronic device. Examples of memory systems range from traditional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash memory (UFS) devices, or embedded MMC (eMMC) devices.

[0005] The memory system may further include a memory controller for controlling the memory devices. The memory controller can receive commands from a host and can execute commands or control read / write / erase operations on the memory devices in the memory system based on the received commands. The memory controller can be used to run firmware operations for performing logical operations to control these operations.

[0006] On the other hand, systems that process large amounts of data (e.g., cloud computing systems, data centers) can use multiple storage devices to handle such large volumes. In this case, if one of the storage devices fails, the system will no longer use the failed storage device. Summary of the Invention

[0007] Embodiments of this disclosure may provide a storage device sharing system and its operating method, which can utilize some resources of one storage device to improve the performance of another storage device.

[0008] Furthermore, embodiments of this disclosure can provide a storage device sharing system and its operating method, which can avoid the problem of resources contained in a faulty storage device not being used.

[0009] On one hand, embodiments of this disclosure may provide a storage device sharing system, the storage device sharing system comprising: i) a plurality of storage devices, each storage device including a first memory buffer and a second memory buffer, the first memory buffer including a plurality of first type storage blocks and the second memory buffer including a plurality of second type storage blocks; ii) a host device configured to determine, based on a sharing state set for the first storage device among the plurality of storage devices, whether to set the first memory buffer of the first storage device as an area for storing data to be written to the second storage device among the plurality of storage devices.

[0010] On the other hand, embodiments of this disclosure may provide an operation method for a storage device sharing system, the operation method comprising: setting a sharing state for a first storage device among a plurality of storage devices included in the storage device sharing system, each storage device including a first memory buffer and a second memory buffer, the first memory buffer including a plurality of first type storage blocks, and the second memory buffer including a plurality of second type storage blocks; and determining, based on the sharing state of the first storage device, whether to configure the first memory buffer of the first storage device as an area for storing data to be written to a second storage device among the plurality of storage devices.

[0011] According to embodiments of this disclosure, some resources in a failed storage device can be used to improve the performance of another storage device, and the problem of unused resources included in the failed storage device can be avoided. Attached Figure Description

[0012] Figure 1 The configuration of a memory system according to an embodiment of the present disclosure is shown.

[0013] Figure 2 A memory device according to an embodiment of the disclosed technology is shown.

[0014] Figure 3 The structure of word lines and bit lines of a memory device according to an embodiment of the present disclosure is shown.

[0015] Figure 4 A system for sharing multiple storage devices according to an embodiment of the present disclosure is illustrated.

[0016] Figure 5 A storage device sharing system according to an embodiment of the present disclosure is shown.

[0017] Figure 6 The present disclosure illustrates an operation in which a storage device sharing system, according to an embodiment of the present disclosure, sets a first memory buffer of a first storage device to be shared by a second storage device.

[0018] Figure 7The operation of changing the sharing state of a first storage device is illustrated in a storage device sharing system according to an embodiment of the present disclosure.

[0019] Figure 8 This illustrates the operation of the storage device sharing system when the sharing state of the first storage device is in a first state, according to an embodiment of the present disclosure.

[0020] Figure 9 This illustrates the operation of the storage device sharing system when the sharing state of the first storage device is in a second state, according to an embodiment of the present disclosure.

[0021] Figure 10 This illustrates the operation of a host device, according to an embodiment of the present disclosure, determining whether to change the shared state of a first storage device.

[0022] Figure 11 This illustrates the operation of a storage device sharing system after changing the shared state of a first storage device to a second state, according to an embodiment of the present disclosure.

[0023] Figure 12 The operation of a storage device sharing system according to an embodiment of the present disclosure is illustrated in which the priority of each of a plurality of storage devices is determined.

[0024] Figure 13 This invention illustrates a method of operating a storage device sharing system according to an embodiment of the present disclosure.

[0025] Figure 14 The configuration of a computing system based on some embodiments of the disclosed technology is shown. Detailed Implementation

[0026] In the following description, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, references to "embodiment," "another embodiment," etc., are not necessarily limited to only one embodiment, and different references to any such phrases are not necessarily limited to the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments.

[0027] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and variations and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various figures and embodiments of the invention.

[0028] The methods, processes, and / or operations described herein may be executed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The code or instructions may be stored on a non-transitory computer-readable medium. The computer, processor, controller, or other signal processing device may be those elements described herein, or elements other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can transform a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0029] When implemented at least in part as software, the controller, processor, device, module unit, multiplexer, generator, logic, interface, decoder, driver, generator, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device.

[0030] Figure 1 A memory system 100 according to an embodiment of the present disclosure is shown.

[0031] In some embodiments, memory system 100 may include a memory device 110 configured to store data, and a memory controller 120 configured to control the memory device 110. In this disclosure, solid-state devices such as flash memory are used as illustrative examples of memory devices, but embodiments are not limited thereto.

[0032] Memory device 110 may include multiple memory blocks, each memory block including multiple memory cells for storing data. Memory device 110 may be configured to operate in response to control signals received from memory controller 120. Operation of memory device 110 may include, for example, read operations, programming operations (also referred to as "write operations"), erase operations, etc.

[0033] The memory cells in memory device 110 are used to store data and can be arranged in an array of memory cells. The array of memory cells can be divided into blocks of memory cells, and each block includes different pages of memory cells. In a typical implementation of a NAND flash memory device, a page of a memory cell is the smallest unit of memory that can be programmed or written, and the data stored in the memory cell can be erased on a block-by-block basis.

[0034] In some implementations, the memory device 110 may be implemented using various types of devices such as: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR). Dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin-transfer torque random access memory (STT-RAM). In some embodiments, the memory device may include a hard disk drive (HDD) or other types of electromechanical data storage devices.

[0035] The memory device 110 can be implemented using a three-dimensional array structure. Some embodiments of the disclosed technology can be applied to any type of flash memory device having a charge storage layer. In one embodiment, the charge storage layer can be formed of a conductive material, and such a charge storage layer can be referred to as a floating gate. In another embodiment, the charge storage layer can be formed of an insulating material, and such a flash memory device can be referred to as charge-fetch flash (CTF).

[0036] The memory device 110 can be configured to receive commands and addresses from the memory controller 120 to access a region in the memory cell array selected using that address. In other words, the memory device 110 can perform an operation corresponding to the received command on a memory region in the memory device having a physical address corresponding to the address received from the memory controller 120.

[0037] In some implementations, the memory device 110 can perform programming operations, reading operations, erasing operations, etc. During a programming operation, the memory device 110 can write data to an address-selected region. During a reading operation, the memory device 110 can read data from an address-selected memory region. During an erasing operation, the memory device 110 can erase data stored in an address-selected memory region.

[0038] The memory controller 120 can control write (programming) operations, read operations, erase operations, and background operations performed on the memory device 110. For example, background operations may include operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0039] The memory controller 120 can control the operation of the memory device 110 upon request from the host. Optionally, when the memory controller 120 performs such background operation of the memory device 110, the memory controller 120 can control the operation of the memory device 110 even without a request from the host.

[0040] The memory controller 120 and the host may be separate devices. In some embodiments, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, by way of example, the memory controller 120 and the host will be discussed as separate devices.

[0041] Reference Figure 1 The memory controller 120 may include a memory interface (memory I / F) 122, a control circuit 123, and a host interface (host I / F) 121.

[0042] Host interface 121 can be configured to provide an interface for communicating with a host.

[0043] When a command is received from the host, the control circuit 123 can receive the command through the host interface 121 and perform operations to process the received command.

[0044] The memory interface 122 can be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 can be configured to provide an interface to the memory device 110 and the memory controller 120 so that the memory controller 120 can perform memory operations on the memory device 110 based on control signals and instructions from the control circuit 123.

[0045] The control circuit 123 can be configured to control the operation of the memory device 110 via the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126, etc.

[0046] Processor 124 can control all operations of memory controller 120. Processor 124 can perform logical operations. Processor 124 can communicate with host via host interface 121. Processor 124 can communicate with memory device 110 via memory interface 122.

[0047] Processor 124 can be used to perform operations associated with the Flash Translation Layer (FTL) to efficiently manage memory operations on memory system 100. Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) via the FTL. The FTL can receive LBAs and translate them into PBAs using a mapping table.

[0048] Based on the mapping unit, FTL can employ various address mapping methods. Typical address mapping methods include page mapping, block mapping, and hybrid mapping.

[0049] Processor 124 can be configured to randomize data received from the host to write the randomized data into the memory cell array. For example, processor 124 can randomize data received from the host by using a randomization seed. The randomized data is provided to memory device 110 and written into the memory cell array.

[0050] Processor 124 can be configured to derandomize data received from memory device 110 during a read operation. For example, processor 124 can derandomize data received from memory device 110 by using a derandomization seed. The derandomized data can be output to the host.

[0051] Processor 124 can run firmware (FW) to control the operation of memory controller 120. In other words, processor 124 can control all operations of memory controller 120, and in order to perform logical operations, it can execute (drive) the firmware loaded into working memory 125 during startup.

[0052] Firmware can refer to a program or software stored in non-volatile memory and executed within memory system 100.

[0053] In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL), a host interface layer (HIL), and a flash interface layer (FIL), wherein the flash translation layer (FTL) is configured to translate a logical address in a host request into a physical address of the memory device 110, the host interface layer (HIL) is configured to interpret commands issued by the host to a data storage device such as the memory system 100 and pass the commands to the FTL, and the flash interface layer (FIL) is configured to pass commands issued by the FTL to the memory device 110.

[0054] For example, firmware can be stored in memory device 110 and then loaded into working memory 125.

[0055] The working memory 125 may store firmware, program code, commands, or data strips required to operate the memory controller 120. The working memory 125 may include, for example, at least one of static RAM (SRAM), dynamic RAM (DRAM), and synchronous RAM (SDRAM) as volatile memory.

[0056] Error detection / correction circuit 126 can be configured to detect and correct one or more error bits in data using error detection and correction codes. In some embodiments, the data for error detection and correction may include data stored in working memory 125 and data retrieved from memory device 110.

[0057] Error detection / correction circuit 126 can be implemented to decode data using error correction codes. Error detection / correction circuit 126 can be implemented using various decoding schemes. For example, a decoder performing non-system code decoding or a decoder performing system code decoding can be used.

[0058] In some implementations, the error detection / correction circuit 126 can detect one or more error bits based on sectors. That is, each read data entry can include multiple sectors. In this patent application, a sector can refer to a data unit smaller than a read unit (e.g., a page) of flash memory. The sectors constituting each read data entry can be mapped based on addresses.

[0059] In some implementations, the error detection / correction circuit 126 can calculate the bit error rate (BER) and determine, sector by sector, whether the number of erroneous bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 can determine that the erroneous bits in the corresponding sector are uncorrectable and mark the corresponding sector as "failed". If the BER is less than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable, or can mark the corresponding sector as "passed".

[0060] Error detection / correction circuit 126 can sequentially perform error detection and correction operations on all read data. When a sector included in the read data is correctable, error detection / correction circuit 126 can continue to the next sector to check whether error correction is required for the next sector. After completing error detection and correction operations on all read data in this way, error detection / correction circuit 126 can obtain information about which sector in the read data was considered uncorrectable. Error detection / correction circuit 126 can provide this information (e.g., the address of the uncorrectable bit) to processor 124.

[0061] The memory system 100 may also include a bus 127 to provide a channel between the constituent elements of the memory controller 120 (e.g., host interface 121, memory interface 122, processor 124, working memory 125, error detection / correction circuitry 126). The bus 127 may include, for example, a control bus for transmitting various types of control signals and commands, and a data bus for transmitting various types of data.

[0062] As an example, Figure 1 The aforementioned constituent elements of the memory controller 120 are shown. Note that some of the elements shown in the figures may be omitted, or some of the aforementioned constituent elements of the memory controller 120 may be integrated into a single element. Additionally, in some embodiments, one or more other constituent elements may be added to the aforementioned constituent elements of the memory controller 120.

[0063] Figure 2 This is a block diagram schematically illustrating a memory device 110 based on an embodiment of the disclosed technology.

[0064] In some implementations, the memory device 110 based on the disclosed technology may include a memory cell array 210, an address decoder 220, a read / write circuit 230, control logic 240, and a voltage generation circuit 250.

[0065] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz, where z is a natural number equal to or greater than 2.

[0066] In multiple memory blocks BLK1 to BLKz, multiple word lines WL and multiple bit lines BL can be set by row and column, and multiple memory cells MC can be arranged by row and column.

[0067] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read / write circuit 230 via multiple bit lines BL.

[0068] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. In embodiments, the plurality of memory cells are non-volatile memory cells. In some embodiments, the non-volatile memory cells may be arranged in a vertical channel configuration.

[0069] In an embodiment, the memory cell array 210 may be configured as a memory cell array with a two-dimensional structure, a memory cell array with a three-dimensional structure, or a combination thereof.

[0070] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) configured to store one bit of data. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) configured to store three bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) configured to store four bits of data per memory cell. As another example, the memory cell array 210 can include a plurality of memory cells, each of which can be configured to store at least five bits of data per memory cell. In embodiments, the number of bits stored in some memory cells can be dynamically configured; for example, for memory cells capable of storing two or more bits of data, a subset of memory cells can be dynamically configured to operate as an SLC storing one bit of data. The size of a subset of SLC operations can also be dynamically configured.

[0071] Reference Figure 2 The address decoder 220, read / write circuit 230, control logic 240, and voltage generation circuit 250 can operate as peripheral circuitry configured to drive the memory cell array 210.

[0072] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0073] Address decoder 220 can be configured to operate in response to commands and control signals from control logic 240.

[0074] Address decoder 220 can receive addresses through an input / output buffer within memory device 110. Address decoder 220 can be configured to decode block addresses among the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0075] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0076] During a read operation, the address decoder 220 can apply a read voltage Vread to the selected word line WL inside the selected memory block and apply a pass voltage Vpass to the remaining unselected word lines WL.

[0077] During the programming verification operation, the address decoder 220 can apply a verification voltage generated by the voltage generation circuit 250 to the selected word line WL inside the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0078] Address decoder 220 can be configured to decode column addresses from received addresses. Address decoder 220 can then transmit the decoded column addresses to read / write circuitry 230.

[0079] The memory device 110 can perform read and program operations page by page. The address received when requesting a read or program operation may include at least one of a block address, a row address, and a column address.

[0080] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read / write circuitry 230.

[0081] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0082] The read / write circuit 230 may include multiple page buffers PB. When the memory cell array 210 performs a read operation, the read / write circuit 230 can operate as a "read circuit", and when the memory cell array 210 performs a write operation, the read / write circuit 230 can operate as a "write circuit".

[0083] The aforementioned read / write circuit 230 is also referred to as a page buffer circuit including multiple page buffers PB or as a data register circuit. The read / write circuit 230 may include data buffers involved in data processing functions, and in some embodiments, the read / write circuit 230 may further include cache buffers for data caching.

[0084] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cell during read operations and program verification operations, the multiple page buffers PB can continuously provide sensing current to the bit lines BL connected to the memory cell to detect changes in current proportional to the amount of current changing according to the programming state of the corresponding memory cell at the sensing node, and can hold or latch the corresponding voltage as sensing data.

[0085] The read / write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0086] During a read operation, the read / write circuit 230 senses the voltage value of the memory cell and reads that voltage value as data. The read / write circuit 230 temporarily stores the retrieved data and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, in addition to the page buffer PB or page register, the read / write circuit 230 may also include column select circuitry.

[0087] Control logic 240 can be connected to address decoder 220, read / write circuit 230, and voltage generation circuit 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory device 110.

[0088] Control logic 240 can be configured to control all operations of memory device 110 in response to control signal CTRL. Control logic 240 can output control signals to adjust the voltage levels of the sensing nodes of multiple page buffers PB to precharge voltage levels.

[0089] Control logic 240 can control read / write circuitry 230 to perform read operations in memory cell array 210. Voltage generation circuitry 250 can generate read voltage Vread and pass voltage Vpass used during read operations in response to voltage generation circuitry control signals output from control logic 240.

[0090] The memory block BLK included in the memory device 110 may include multiple pages PG. In some embodiments, multiple memory cells arranged in columns form a memory cell string, and multiple memory cells arranged in rows form a memory block. Each of the multiple pages PG is connected to one of the word lines WL, and each of the memory cell strings STR is connected to one of the bit lines BL.

[0091] In a storage block BLK, multiple word lines (WLs) and multiple bit lines (BLs) can be arranged in rows and columns. For example, each of the multiple word lines (WLs) can be arranged along the row direction, and each of the multiple bit lines (BLs) can be arranged along the column direction. As another example, each of the multiple word lines (WLs) can be arranged along the column direction, and each of the multiple bit lines (BLs) can be arranged along the row direction.

[0092] In some implementations, multiple word lines (WL) and multiple bit lines (BL) may intersect each other, thereby addressing a single memory cell in an array of multiple memory cells (MC). In some implementations, each memory cell (MC) may include a transistor (TR), which includes a layer of material capable of retaining charge.

[0093] For example, a transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of transistor TR may be connected directly or via another transistor TR to the corresponding bit line BL. The source (or drain) of transistor TR may be connected directly or via another transistor TR to the source line (which may be ground). The gate of transistor TR may include a floating gate (FG) surrounded by an insulator and a control gate (CG) to which a gate voltage is applied from the word line WL.

[0094] In each of the multiple memory blocks BLK1 to BLKz, the first select line (also called the source select line or drain select line) may be additionally arranged outside the first outermost word line of the two outermost word lines, closer to the first outermost word line of the read / write circuit 230, and the second select line (also called the drain select line or source select line) may be additionally arranged outside the other second outermost word line.

[0095] In some implementations, at least one additional dummy word line may be arranged between the first outermost word line and the first selection line. Additionally, at least one additional dummy word line may be arranged between the second outermost word line and the second selection line.

[0096] It can perform read and write operations on storage blocks one page at a time, and it can also perform erase operations on storage blocks one by one.

[0097] Figure 3 This is a diagram illustrating the structure of the word line WL and bit line BL of a memory device 110 based on an embodiment of the disclosed technology.

[0098] Reference Figure 3 The memory device 110 has a core region and an auxiliary region (the remaining region other than the core region). The core region contains memory cells MC, and the auxiliary region includes circuitry for performing operations on the memory cell array 210.

[0099] In the kernel region, a certain number of memory cells arranged in one direction can be called a "page" (PG), and a certain number of memory cells connected in series can be called a "memory cell string" (STR).

[0100] Word lines WL1 to WL9 can be connected to row decoder 310. Bit line BL can be connected to column decoder 320. (Corresponding to...) Figure 2 The data register 330 of the read / write circuit 230 can exist between multiple bit lines BL and column decoder 320.

[0101] Multiple word lines WL1 to WL9 can correspond to multiple pages PG.

[0102] For example, such as Figure 3As shown, each of the multiple word lines WL1 to WL9 can correspond to a page PG. When each of the multiple word lines WL1 to WL9 has a large size, each of the multiple word lines WL1 to WL9 can correspond to at least two (e.g., two or four) page PGs. Each page PG is the smallest unit in programming and reading operations, and when performing programming and reading operations, all memory cells MC within the same page PG can be operated on simultaneously.

[0103] Multiple bit lines BL can be connected to column decoder 320. In some implementations, the multiple bit lines BL can be divided into odd-numbered bit lines BL and even-numbered bit lines BL, such that a pair of odd-numbered bit lines and even-numbered bit lines are connected together to column decoder 320.

[0104] When accessing a memory cell MC, the row decoder 310 and column decoder 320 are used to locate the desired memory cell based on its address.

[0105] In some implementations, the data register 330 plays a crucial role because all data processing performed by the memory device 110, including programming and reading operations, is conducted through the data register 330. If data processing in the data register 330 is delayed, all other areas must wait until the data register 330 has completed its data processing, thereby reducing the overall performance of the memory device 110.

[0106] Reference Figure 3 In the example shown, in a memory cell string STR, multiple transistors TR1 to TR9 can be connected to multiple word lines WL1 to WL9, respectively. In some embodiments, the multiple transistors TR1 to TR9 correspond to memory cells MC. In this example, the multiple transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0107] The multiple word lines WL1 to WL9 include two outermost word lines WL1 and WL9. A first select line DSL can be additionally positioned outside the first outermost word line WL1, which is closer to the data register 330 and has a shorter signal path compared to the other outermost word line WL9. A second select line SSL can additionally be positioned outside another second outermost word line WL9.

[0108] The first selection transistor D-TR, controlled by the first selection line DSL to be turned on / off, has a gate electrode connected to the first selection line DSL, but does not include a floating gate FG. The second selection transistor S-TR, controlled by the second selection line SSL to be turned on / off, has a gate electrode connected to the second selection line SSL, but does not include a floating gate FG.

[0109] The first selection transistor D-TR serves as a switching circuit to connect the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR serves as a switching circuit to connect the corresponding memory cell string STR to the source line SL. That is, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0110] In some embodiments, the memory device 110 applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR to turn on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR to turn off the second selection transistor S-TR.

[0111] During a read or verify operation, memory device 110 turns on both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, during a read or verify operation, current can flow through the corresponding memory cell string STR and to the source line SL corresponding to ground, allowing measurement of the voltage level of the bit line BL. However, during a read operation, there may be a time difference in the on / off timing between the first selection transistor D-TR and the second selection transistor S-TR.

[0112] During the erase operation, memory device 110 can apply a predetermined voltage (e.g., +20V) to the substrate via the source line SL. During the erase operation, memory device 110 applies a specific voltage to allow both the first selection transistor D-TR and the second selection transistor S-TR to float. Therefore, the applied erase voltage can remove charge from the floating gate FG of the selected memory cell.

[0113] Figure 4 A plurality of storage device sharing systems according to embodiments of the present disclosure are illustrated. The plurality of storage device sharing systems include a first storage device sharing system 401 and a second storage device sharing system 402. Although Figure 4 A multi-storage-device sharing system including two storage devices sharing a system is shown, but the embodiments are not limited thereto.

[0114] Each of the storage device sharing systems 401 and 402 may include a host device HOST_DEV and multiple storage devices STR_DEV, respectively. The number of storage devices STR_DEV included in the first storage device sharing system 401 may differ from the number of storage devices STR_DEV included in the second storage device sharing system 402.

[0115] Multiple storage devices sharing a system can be interconnected via a network or communication interface. A host device (HOST_DEV) within one of these shared storage devices can transmit / receive data to / from another host device (HOST_DEV) within the same system via a communication interface (e.g., USB (Universal Serial Bus), SCSI (Small Computer System Interface), High-Speed ​​PCI (Peripheral Component Interconnect), ATA (AT Accessories), PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial SCSI)) or via a network (e.g., LAN (Local Area Network), WLAN (Wireless LAN), 5G (5th Generation Wireless Network), LTE (Long Term Evolution Wireless Network), or Bluetooth network).

[0116] In the following text, reference will be made to Figure 5 Detailed descriptions such as may be included in Figure 4 A schematic structure of a storage device sharing system in a multi-storage device sharing system.

[0117] Figure 5 A schematic structure of a storage device sharing system 10 according to an embodiment of the present disclosure is shown.

[0118] The storage device sharing system 10 may include a host device HOST_DEV and multiple storage devices STR_DEV. The multiple storage devices STR_DEV may be connected to the host device HOST_DEV.

[0119] Multiple storage devices STR_DEV include devices capable of storing data, such as one or more hard disk drives (HDDs), one or more solid-state drives (SSDs), one or more universal flash memory (UFS) devices, one or more eMMC (embedded MMC) devices, or combinations thereof.

[0120] In this embodiment, multiple storage devices STR_DEV can correspond to the above reference. Figure 1 The memory system 100 is described.

[0121] Multiple storage devices STR_DEV can each include a first memory buffer MB_1 and a second memory buffer MB_2.

[0122] The first memory buffer MB_1 may include multiple first-type memory blocks MB_TYPE1, and the second memory buffer MB_2 may include multiple second-type memory blocks MB_TYPE2.

[0123] In this case, the number of data bits that can be stored in the memory cells included in the first type of memory block MB_TYPE1 can be less than the number of data bits that can be stored in the memory cells included in the second type of memory block MB_TYPE2. For example, the first type of memory block MB_TYPE1 can be an SLC memory block including SLC memory cells. And the second type of memory block MB_TYPE2 can be a TLC memory block including TLC memory cells or a QLC memory block including QLC memory cells.

[0124] On the other hand, the number of data bits that can be stored in the memory cells included in the first type of memory block MB_TYPE1 can be greater than or equal to the number of data bits that can be stored in the memory cells included in the second type of memory block MB_TYPE2.

[0125] The host device HOST_DEV can write data to multiple storage devices STR_DEV, or read data stored in multiple storage devices STR_DEV.

[0126] When multiple storage devices STR_DEV respectively correspond to Figure 1 When the memory system 100 described in the document is used, the host device HOST_DEV can correspond to Figure 1 The host described in the document.

[0127] The host device (HOST_DEV) can be a computing device (e.g., a desktop computer, laptop computer, server) capable of running an operating system (OS) and running multiple applications based on the OS. The host device (HOST_DEV) can communicate with multiple storage devices (STR_DEV) via predetermined interfaces (e.g., USB, SATA, SCSI, high-speed PCI). For this purpose, drivers supporting the corresponding interfaces can be installed in the host device (HOST_DEV). The host device (HOST_DEV) may include a CPU (Central Processing Unit) and volatile memory (e.g., SRAM, DRAM, i.e., non-transitory computer-readable media) communicating with the CPU. The volatile memory stores i) data for the CPU to execute to provide operations for the aforementioned operating system and multiple applications, and for performing communication operations with the multiple storage devices (STR_DEV), and ii) data to be written to or read from the multiple storage devices (STR_DEV).

[0128] In embodiments of this disclosure, the host device HOST_DEV can change the settings of the first memory buffer MB_1 included in the first storage device according to the shared state set for the first storage device among a plurality of storage devices STR_DEV.

[0129] The shared state of the first storage device indicates whether some resources included in the first storage device (e.g., the first memory buffer MB_1 of the first storage device) can be used to store data intended for use in another storage device.

[0130] The host device (HOST_DEV) can transfer the shared state of multiple storage devices (STR_DEV) to multiple storage devices (STR_DEV), or receive the shared state of multiple storage devices (STR_DEV) from multiple storage devices (STR_DEV). Furthermore, the host device (HOST_DEV) can update the shared state of multiple storage devices (STR_DEV), and when a new storage device is added, it transfers the shared state of the added storage device to other storage devices.

[0131] Figure 6 The illustration shows an operation in which a storage device sharing system 10, according to an embodiment of the present disclosure, sets a first memory buffer MB_1 of a first storage device STR_DEV_1 to be shared by a second storage device STR_DEV_2.

[0132] Reference Figure 6 The host device HOST_DEV of the storage device sharing system 10 can allow the second storage device STR_DEV_2 to share the first memory buffer MB_1 of the first storage device STR_DEV_1.

[0133] The second storage device STR_DEV_2 sharing the first memory buffer MB_1 of the first storage device STR_DEV_1 means that the first memory buffer MB_1 of the first storage device STR_DEV is set up to store data to be written to the second storage device STR_DEV_2.

[0134] When the second storage device STR_DEV_2 shares the first memory buffer MB_1 of the first storage device STR_DEV_1, in operation S1, the host device HOST_DEV can first store the data to be written to the second storage device STR_DEV_2 in the first memory buffer MB_1 of the first storage device STR_DEV_1.

[0135] Subsequently, in operation S2, the host device HOST_DEV can migrate the data stored in the first memory buffer MB_1 of the first storage device STR_DEV_1 to the second memory buffer MB_2 of the second storage device STR_DEV_2.

[0136] In this scenario, data stored in the first memory buffer MB_1 of the first storage device STR_DEV_1 can be migrated to the second memory buffer MB_2 of the second storage device STR_DEV_2 via the host device HOST_DEV. In other words, the host device HOST_DEV can load data stored in the first memory buffer MB_1 of the first storage device STR_DEV_1 and write the loaded data to the second memory buffer MB_2 of the second storage device STR_DEV_2.

[0137] To this end, the host device HOST_DEV can establish a channel as a virtual path for transferring data between the first storage device STR_DEV_1 and the second storage device STR_DEV_2. The host device HOST_DEV can perform data input / output through this channel, which is a virtual logical configuration located above the physical layer of the protocol stack used by the first storage device STR_DEV_1 and the second storage device STR_DEV_2.

[0138] In this way, the host device HOST_DEV can use the first memory buffer MB_1 of the first storage device STR_DEV_1 as a region for temporarily storing data to be stored in the second memory buffer MB_2 of the second storage device STR_DEV_2. For example, the first memory buffer MB_1 of the first storage device STR_DEV_1 can be used as a write buffer or write cache for the data to be stored in the second memory buffer MB_2 of the second storage device STR_DEV_2.

[0139] In embodiments of this disclosure, the host device HOST_DEV can determine, based on a shared state set for a first storage device STR_DEV_1 among a plurality of storage devices STR_DEV, whether to set the first memory buffer MB_1 of the first storage device STR_DEV_1 as a region among the plurality of storage devices STR_DEV for storing data to be written to the second storage device STR_DEV_2. This will be described in detail below.

[0140] For example, the host device HOST_DEV can set the shared state of the first storage device STR_DEV_1 to one of the states shown in Table 1.

[0141] Table 1

[0142] Shared state value meaning standby 0 No sharing operation performed Ready 1 Enable sharing connect 2 Sharing in progress shared 3 Shared pause 4 Shared pause Notification (Disconnection) 5 Sharing complete

[0143] Furthermore, the host device HOST_DEV can set the sharing mode of, for example, the first storage device STR_DEV_1, to one of the modes shown in Table 2. The sharing mode of the first storage device STR_DEV_1 disclosed in Table 2 can indicate the resources shared in the first storage device STR_DEV_1 and the number of storage devices sharing those resources. In Table 2, an XLC memory block is a memory block where each memory cell stores two or more bits of data.

[0144] Table 2

[0145]

[0146]

[0147] Additionally, the host device HOST_DEV can set, for example, whether the first storage device STR_DEV_1 supports sharing to one of the values ​​shown in Table 3. When the first storage device STR_DEV_1 supports sharing, the first memory buffer MB_1 of the first storage device STR_DEV_1 can be set as an area for storing data to be written to the second storage device STR_DEV_2 among multiple storage devices STR_DEV.

[0148] Table 3

[0149] Shared support value meaning Not supported 0 Sharing is not supported. support 1 Support sharing Ready 2 Firmware update required to support sharing

[0150] In addition, the host device HOST_DEV can be set to one of the values ​​shown in Table 4, for example, whether the first storage device STR_DEV_1 is enabled.

[0151] Table 4

[0152] Enable value meaning Disable 0 Disable Enable 1 Enable

[0153] Figure 7 A flowchart illustrating an operation 700 in which the storage device sharing system 10, according to an embodiment of the present disclosure, can change the sharing state of the first storage device STR_DEV_1 is shown.

[0154] Reference Figure 7 In step S710, the host device HOST_DEV of the storage device sharing system 10 can monitor multiple storage devices STR_DEV. In this case, the host device HOST_DEV and the multiple storage devices STR_DEV are connected to each other to communicate. Each of the multiple storage devices STR_DEV can transmit its own status to the host device HOST_DEV, and the host device HOST_DEV can receive the transmitted status and check the status of each of the multiple storage devices STR_DEV.

[0155] In step S720, the host device HOST_DEV determines whether the first storage device STR_DEV_1 among the multiple storage devices STR_DEVs meets a predetermined sharing condition based on the results of monitoring the multiple storage devices STR_DEVs. The predetermined sharing condition may be related to the device health information of each of the multiple storage devices STR_DEVs, as described below.

[0156] If the first storage device STR_DEV_1 does not meet the sharing condition (S720-No), the host device HOST_DEV can terminate operation 700 without setting the first storage device STR_DEV_1 to be shared with other storage devices.

[0157] On the other hand, if the first storage device STR_DEV_1 meets the sharing condition (S720-Yes), then in step S730, the host device HOST_DEV can select the second storage device STR_DEV_2 from among the multiple storage devices STR_DEV connected to the host device HOST_DEV as the storage device that the first storage device STR_DEV_1 will share with.

[0158] In one embodiment, the host device HOST_DEV can automatically select a second storage device STR_DEV_2 from multiple storage devices STR_DEV according to a predetermined strategy or priority. Alternatively, the host device HOST_DEV can select a user-selected storage device as the second storage device STR_DEV_2 from multiple storage devices STR_DEV.

[0159] In step S740, the host device HOST_DEV can change the shared state of the first storage device STR_DEV_1 from a first state (e.g., the standby state of Table 1, value = 0) to a second state (e.g., the shared state of Table 1, value = 3).

[0160] In this case, for example, the host device HOST_DEV can perform the following operation to change the shared state of the first storage device STR_DEV_1 from a first state to a second state.

[0161] First, the host device HOST_DEV can change the shared state of the first storage device STR_DEV_1 to the ready state (value = 1) described in Table 1.

[0162] Then, the host device HOST_DEV can change the shared state of the first storage device STR_DEV_1 to the connected state described in Table 1 (value = 2). In this case, the first storage device STR_DEV_1 can transmit information about the storage blocks it includes (e.g., hot / cold data storage status, error bit occurrence status, wear leveling operation status, garbage collection operation status, bad block status) to the host device HOST_DEV.

[0163] Upon receiving information about the first storage device STR_DEV_1, the host device HOST_DEV can perform the operations necessary to place the first memory buffer MB_1 of the first storage device STR_DEV_1 into a state that can be shared by the second storage device STR_DEV_2. For example, the host device HOST_DEV can migrate data already stored in the first memory buffer MB_1 and the second memory buffer MB_2 of the first storage device STR_DEV_1 to another storage device to ensure data integrity, and suspend data input / output operations on the first storage device STR_DEV_1.

[0164] Subsequently, the host device HOST_DEV can change the shared state of the first storage device STR_DEV_1 to a second state (e.g., shared state, value = 3).

[0165] In step S750, the host device HOST_DEV can set the first memory buffer MB_1 of the first storage device STR_DEV_1 as an area for storing data to be written to the second storage device STR_DEV_2.

[0166] In this embodiment, the first memory buffer MB_1 of the first storage device STR_DEV_1 can also be configured to store data to be written not only to the second storage device STR_DEV_2 but also to other storage devices. In this case, the first memory buffer MB_1 of the first storage device STR_DEV_1 can be shared by two or more storage devices simultaneously.

[0167] In the following text, reference will be made to Figure 8 and Figure 9 Describes the operation of the storage device sharing system 10 based on the shared state of the first storage device STR_DEV_1.

[0168] Figure 8The diagram illustrates the operation that the storage device sharing system 10 can operate when the sharing state of the first storage device STR_DEV_1 is a first state STATE_1, according to an embodiment of the present disclosure, wherein the first state STATE_1 corresponds to the state in which the first storage device STR_DEV_1 does not share its storage with other devices.

[0169] Reference Figure 8 When the sharing state is in the first state STATE_1, the host device HOST_DEV of the storage device sharing system 10 can set the first memory buffer MB_1 of the first storage device STR_DEV_1 to store only the data to be written to the first storage device STR_DEV_1. In this case, data to be written to storage devices other than the first storage device STR_DEV_1 may not be stored in the first memory buffer MB_1 of the first storage device STR_DEV_1.

[0170] exist Figure 8 In operation S11, the host device HOST_DEV can store the data to be written to the first storage device STR_DEV_1 in the first memory buffer MB_1 of the first storage device STR_DEV_1. Subsequently, in operation S12, the host device HOST_DEV can migrate the data stored in the first memory buffer MB_1 of the first storage device STR_DEV_1 to the second memory buffer MB_2 of the first storage device STR_DEV_1.

[0171] In operation S13, the host device HOST_DEV can store the data to be written to the second storage device STR_DEV_2 in the first memory buffer MB_1 of the second storage device STR_DEV_2. Subsequently, in operation S14, the host device HOST_DEV can migrate the data stored in the first memory buffer MB_1 of the second storage device STR_DEV_2 to the second memory buffer MB_2 of the second storage device STR_DEV_2.

[0172] However, in Figure 8 In this case, the data stored in the first memory buffer MB_1 of the first storage device STR_DEV_1 is not migrated to the second memory buffer MB_2 of the second storage device STR_DEV_2. That is, when the sharing state is the first state STATE_1, which corresponds to the state where the first storage device STR_DEV_1 does not share storage with other devices, the first memory buffer MB_1 of the first storage device STR_DEV_1 is not allowed to be shared by the second storage device STR_DEV_2.

[0173] Figure 9This illustrates the operation that the storage device sharing system 10 can operate when the sharing state of the first storage device STR_DEV_1 is the second state STATE_2, according to an embodiment of the present disclosure. The second state STATE_2 corresponds to the state in which the first storage device STR_DEV_1 shares its storage with other devices.

[0174] Reference Figure 9 When the sharing state is in the second state STATE_2, the host device HOST_DEV of the storage device sharing system 10 can set the first memory buffer MB_1 of the first storage device STR_DEV_1 to store data to be written to the second storage device STR_DEV_2.

[0175] In other words, in operation S21, the host device HOST_DEV stores the data to be written to the second storage device STR_DEV_2 in the first memory buffer MB_1 of the first storage device STR_DEV_1. Subsequently, in operation S22, the host device HOST_DEV can migrate the data stored in the first memory buffer MB_1 of the first storage device STR_DEV_1 to the second memory buffer MB_2 of the second storage device STR_DEV_2.

[0176] Furthermore, in operation S23, the host device HOST_DEV can store the data to be written to the second storage device STR_DEV_2 in the first memory buffer MB_1 of the second storage device STR_DEV_2. Subsequently, in operation S24, the host device HOST_DEV can migrate the data stored in the first memory buffer MB_1 of the second storage device STR_DEV_2 to the second memory buffer MB_2 of the second storage device STR_DEV_2.

[0177] In other words, when the shared state of the first storage device STR_DEV_1 is the second state STATE_2, the first memory buffer MB_1 of the first storage device STR_DEV_1 and the first memory buffer MB_1 of the second storage device STR_DEV_2 can be used together as an area for storing data to be migrated to the second memory buffer MB_2 of the second storage device STR_DEV_2. Therefore, the performance of writing data to the second storage device STR_DEV_2 can be improved.

[0178] As described above, when predetermined sharing conditions are met, the host device HOST_DEV can change the sharing state of the first storage device STR_DEV_1. The following describes the operation by which the host device HOST_DEV determines whether to change the sharing state of the first storage device STR_DEV_1 by determining whether predetermined sharing conditions are met.

[0179] Figure 10 The present invention illustrates an operation 1000 of a host device HOST_DEV determining whether to change the shared state of a first storage device STR_DEV_1, according to an embodiment of the present disclosure.

[0180] Reference Figure 10 In step S1010, the host device HOST_DEV can count the number of bad memory blocks among the multiple second type memory blocks MB_TYPE2 included in the second memory buffer MB_2 of the first storage device STR_DEV_1.

[0181] In step S1020, the host device HOST_DEV determines whether the number of bad memory blocks counted in step S1010 is equal to or greater than the set threshold bad memory block count.

[0182] When the number of counted bad storage blocks is greater than or equal to the threshold bad storage block count (S1020 - Yes), the host device HOST_DEV can change the shared state of the first storage device STR_DEV_1 from the first state to the second state in step S1030.

[0183] If the number of bad blocks included in the second memory buffer MB_2 of the first storage device STR_DEV_1 is equal to or greater than the threshold bad block count, it indicates that the reliability of the data stored in the second memory buffer MB_2 of the first storage device STR_DEV_1 may not be guaranteed. Therefore, the host device HOST_DEV can determine that it no longer needs to use the second memory buffer MB_2 of the first storage device STR_DEV_1.

[0184] However, even in this situation, the first memory buffer MB_1 of the first storage device STR_DEV_1 is still available. Therefore, the host device HOST_DEV can change the sharing state of the first storage device STR_DEV_1 from a first state (sharing not allowed) to a second state (sharing allowed) to effectively utilize the first memory buffer MB_1 of the first storage device STR_DEV_1. Thus, the host device HOST_DEV can use the first memory buffer MB_1 of the first storage device STR_DEV_1 to store data to be written to the second storage device STR_DEV_2. Therefore, the host device HOST_DEV can prevent the problem that the first memory buffer MB_1 of the first storage device STR_DEV_1 is also unavailable when the second memory buffer MB_2 of the first storage device STR_DEV_1 is unavailable.

[0185] On the other hand, when the number of counted bad memory blocks is less than the threshold bad memory block count (S1020 - No), in step S1040, the host device HOST_DEV can maintain the shared state of the first storage device STR_DEV_1 in the first state. This is because the first memory buffer MB_1 of the first storage device STR_DEV_1 can be used to store data to be written to the second memory buffer MB_2 of the first storage device STR_DEV_1.

[0186] Figure 11 The operation of the storage device sharing system 10 is illustrated after the shared state of the first storage device STR_DEV_1 changes to the second state STATE_2, according to an embodiment of the present disclosure.

[0187] Reference Figure 11 When the shared state is changed from the first state to the second state, the host device HOST_DEV can prohibit access to the second memory buffer MB_2 of the first storage device STR_DEV_1.

[0188] Therefore, the host device HOST_DEV can suspend normal input / output operations to the first storage device STR_DEV_1 (e.g., input / output operations requested by an external source to store data in the second memory buffer MB_2 of the first storage device STR_DEV_1 or to retrieve data from the second memory buffer MB_2 of the first storage device STR_DEV_1). For example, the host device HOST_DEV can suspend input / output operations to the first storage device STR_DEV_1 when performing a power-off, restart, or suspension operation.

[0189] In addition, the host device HOST_DEV can migrate data that has been stored in the first memory buffer MB_1 and the second memory buffer MB_2 of the first storage device STR_DEV_1 to another storage device to ensure data integrity.

[0190] This is because the reliability of the data stored in the second memory buffer MB_2 of the first storage device STR_DEV_1 is no longer guaranteed because the number of bad memory blocks included in the second memory buffer MB_2 of the first storage device STR_DEV_1 is equal to or greater than the threshold bad memory block count THR.

[0191] Thus, when access to the second memory buffer MB_2 of the first storage device STR_DEV_1 is prohibited, data stored in the first memory buffer MB_1 of the first storage device STR_DEV_1 cannot be migrated to the second memory buffer MB_2 of the first storage device STR_DEV_1.

[0192] Furthermore, when access to the second memory buffer MB_2 of the first storage device STR_DEV_1 is prohibited, data stored in the first memory buffer MB_1 of the second storage device STR_DEV_2 cannot be migrated to the second memory buffer MB_2 of the first storage device STR_DEV_1.

[0193] Therefore, in order to utilize the first memory buffer MB_1 of the first storage device STR_DEV_1, the host device HOST_DEV can configure the first memory buffer MB_1 of the first storage device STR_DEV_1 as an area for storing data to be written to the second storage device STR_DEV_2. In this case, the data stored in the first memory buffer MB_1 of the first storage device STR_DEV_1 can be migrated to the second memory buffer MB_2 of the second storage device STR_DEV_2, as shown in operation S31. Alternatively, the data stored in the first memory buffer MB_1 of the second storage device STR_DEV_2 can be migrated to the second memory buffer MB_2 of the second storage device STR_DEV_2, as shown in operation S34.

[0194] Therefore, the host HOST_DEV can prevent the first memory buffer MB_1 of the first storage device STR_DEV_1 from being unused when access to the second memory buffer MB_2 of the first storage device STR_DEV_1 is prohibited.

[0195] The operation described above involves the host device HOST_DEV setting the first memory buffer MB_1 of the first storage device STR_DEV_1 as a region for storing data to be written to the second storage device STR_DEV_2.

[0196] The method by which the host device HOST_DEV determines the second storage device STR_DEV_2 from a plurality of storage devices STR_DEV will be described below.

[0197] Figure 12 The operation 1200 of a storage device sharing system 10 according to an embodiment of the present disclosure, which determines the priority of a plurality of storage devices STR_DEV, is illustrated.

[0198] Reference Figure 12During operation S1210, the host device HOST_DEV of the storage device sharing system 10 can check the status information of each of the multiple storage devices STR_DEV. In this case, as described above, the status information of each of the multiple storage devices STR_DEV can include information about the storage blocks included therein (e.g., storage status of hot / cold data, error bit occurrence status, wear leveling operation status, garbage collection operation status, bad storage block status, etc., or combinations thereof).

[0199] In operation S1220, the host device HOST_DEV can determine the priority of each of the multiple storage devices STR_DEV based on the status information of each of the multiple storage devices STR_DEV checked in operation S1210.

[0200] For example, the host device HOST_DEV can determine the priority of each of the multiple storage devices STR_DEV based on the size of the hot data stored in each of the multiple storage devices STR_DEV. Here, for example, hot data refers to data that is read or written an equal to or greater than a set threshold during a predetermined time period. On the other hand, cold data refers to data that is read or written less than a set threshold during the predetermined time period.

[0201] For example, the host device HOST_DEV can determine the priority of each of the multiple storage devices STR_DEV based on the total number of read operations, write operations, and erase operations performed on each of the multiple storage devices STR_DEV during a predetermined time period.

[0202] For example, the host device (HOST_DEV) can input the status information of each of multiple storage devices (STR_DEV) into a machine learning model to determine the priority of each of the storage devices (STR_DEV). The host device (HOST_DEV) can then determine the priority of each of the storage devices (STR_DEV) based on the output of the machine learning model. In this case, the machine learning model can be retrained based on the priority of each of the storage devices (STR_DEV) and the changes in the operational performance of the storage devices (STR_DEV).

[0203] The host device (HOST_DEV) can assign a higher priority to the storage device (STR_DEV) that stores more hot data among multiple storage devices (STR_DEV), and a lower priority to the storage device that stores less hot data among multiple storage devices (STR_DEV). Since storage devices with a large amount of hot data can perform a large number of read or write operations, the performance improvement of the storage device can be increased by using the resources of other storage devices to help perform those read and / or write operations.

[0204] In operation S1230, the host device HOST_DEV can identify the storage device with the highest priority among multiple storage devices STR_DEV as the second storage device STR_DEV_2 that shares storage with another storage device.

[0205] For example, the host device HOST_DEV can identify the storage device that stores the most hot data among multiple storage devices STR_DEV as the second storage device STR_DEV_2.

[0206] For example, the host device HOST_DEV can identify the storage device STR_DEV_2 as the second storage device among multiple storage devices STR_DEV that has the largest sum of read operations, write operations and erase operations performed during a predetermined time period.

[0207] Figure 13 A method of operation 1300 for a storage device sharing system according to an embodiment of the present disclosure is shown.

[0208] Reference Figure 13 The operation method 1300 of the storage device sharing system may include operation S1310, setting a sharing state for a first storage device STR_DEV_1 among a plurality of storage devices STR_DEV. In this case, each of the plurality of storage devices STR_DEV may include i) a first memory buffer MB_1, which includes a plurality of first type storage blocks MB_TYPE1, and ii) a second memory buffer MB_2, which includes a plurality of second type storage blocks MB_TYPE2.

[0209] The number of data bits that can be stored in the memory cells included in the first type of memory block MB_TYPE1 can be less than the number of data bits that can be stored in the memory cells included in the second type of memory block MB_TYPE2.

[0210] The operation method of the storage device sharing system may further include operation S1320, which, based on the sharing state of the first storage device STR_DEV_1, determines whether to set the first memory buffer MB_1 of the first storage device STR_DEV_1 as a region for storing data to be written to the second storage device STR_DEV_2 among the multiple storage devices STR_DEV.

[0211] For example, the first memory buffer MB_1 of the first storage device STR_DEV_1 is configured to store only the data to be written to the first storage device STR_DEV_1 when the shared state is the first state STATE_1, and is configured to store the data to be written to the second storage device STR_DEV_2 when the shared state is the second state STATE_2.

[0212] On the other hand, operation S1320 may include counting the number of bad memory blocks among the plurality of second-type memory blocks MB_TYPE2 included in the second memory buffer MB_2 of the first storage device STR_DEV_1. Furthermore, operation S1320 may include changing the shared state from a first state to a second state when the number of bad memory blocks is greater than or equal to a set threshold bad memory block count.

[0213] When the shared state of the first storage device STR_DEV_1 changes from the first state to the second state, access to the second memory buffer MB_2 of the first storage device STR_DEV_1 can be prohibited.

[0214] The operation method of the storage device sharing system may further include: determining the priority of each of the multiple storage devices STR_DEV based on the status information of each of the multiple storage devices STR_DEV, and determining the storage device with the highest priority among the multiple storage devices STR_DEV as the second storage device STR_DEV_2 that shares storage with the first device STR_DEV_1.

[0215] In an embodiment, the priority of each of the plurality of storage devices STR_DEV can be determined based on the size of the hot data stored in each of the plurality of storage devices STR_DEV.

[0216] Figure 14 A computing system 1400 based on an embodiment of the disclosed technology is shown.

[0217] Reference Figure 14The computing system 1400 based on the disclosed technology may include: a storage device sharing system 10 electrically connected to a system bus 1460; a CPU 1410 configured to control all operations of the computing system 1400; RAM 1420 configured to store data and information related to the operation of the computing system 1400; a user interface / user experience (UI / UX) module 1430 configured to provide a user environment to a user; a communication module 1440 configured to communicate with external devices in wired and / or wireless manner; and a power management module 1450 configured to manage the power used by the computing system 1400.

[0218] The computing system 1400 may be a personal computer (PC) or may include a mobile terminal such as a smartphone, tablet computer or various electronic devices.

[0219] The computing system 1400 may further include a battery for providing operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and DRAM. Other components will be apparent to those skilled in the art.

[0220] Storage device sharing system 10 can correspond to Figure 5 The storage device sharing system 10 may include a device configured to store data on a disk, such as a hard disk drive (HDD), a device configured to store data in non-volatile memory (e.g., a solid-state drive (SSD), a general-purpose flash memory device, or an embedded MMC (eMMC) device), or a combination thereof. The non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Furthermore, the storage device sharing system 10 can be implemented as various types of storage devices and installed within various electronic devices.

[0221] Based on the embodiments of the disclosed technology, the operational latency of a storage system comprising multiple storage devices can be advantageously reduced or minimized. Furthermore, based on the embodiments of the disclosed technology, the overhead incurred during the invocation of specific functions can be advantageously reduced or minimized. Although various embodiments of the disclosed technology have been described in particular detail and with varying degrees of detail for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made based on the content disclosed or described herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A storage device sharing system, comprising: Multiple storage devices, each storage device comprising: The first memory buffer comprises multiple first-type memory blocks, and A second memory buffer, comprising multiple second-type memory blocks; and The host device determines, based on the shared state set for the first storage device among the plurality of storage devices, whether to set the first memory buffer of the first storage device as an area for storing data to be written to the second storage device among the plurality of storage devices.

2. The storage device sharing system according to claim 1, The number of data bits that can be stored in the memory cells included in the first type of storage block is less than the number of data bits that can be stored in the memory cells included in the second type of storage block.

3. The storage device sharing system according to claim 1, When the shared state is in the first state, the host device configures the first memory buffer of the first storage device to store only the data to be written to the first storage device, and When the shared state is the second state, the host device configures the first memory buffer of the first storage device to store data to be written to the second storage device.

4. The storage device sharing system according to claim 3, When the number of bad storage blocks among the plurality of second-type storage blocks included in the second memory buffer of the first storage device is greater than or equal to a threshold bad storage block count, the host device changes the shared state from the first state to the second state.

5. The storage device sharing system according to claim 4, When the host device changes the shared state from the first state to the second state, it disables access to the second memory buffer of the first storage device.

6. The storage device sharing system according to claim 1, The host device determines the priority of each of the plurality of storage devices based on the status information of each of the plurality of storage devices, and The host device identifies the storage device with the highest priority among the plurality of storage devices as the second storage device.

7. The storage device sharing system according to claim 1, The host device determines the priority of each of the plurality of storage devices based on the size of the hot data stored in each of the plurality of storage devices.

8. A method of operating a storage device sharing system, the method comprising: A shared state is set for a first storage device among multiple storage devices included in the storage device sharing system. Each storage device includes a first memory buffer and a second memory buffer. The first memory buffer includes multiple first-type storage blocks, and the second memory buffer includes multiple second-type storage blocks. Based on the shared state of the first storage device, determine whether to configure the first memory buffer of the first storage device as an area for storing data to be written to the second storage device among the plurality of storage devices.

9. The operating method according to claim 8, The number of data bits that can be stored in the memory cells included in the first type of storage block is less than the number of data bits that can be stored in the memory cells included in the second type of storage block.

10. The operating method according to claim 8, When the shared state is in the first state, the first memory buffer of the first storage device only stores data to be written to the first storage device, and When the shared state is the second state, the first memory buffer of the first storage device stores the data to be written to the second storage device.

11. The operating method according to claim 10, The shared state of the first storage device includes: The number of bad memory blocks among the multiple second-type memory blocks included in the second memory buffer of the first storage device is counted; and When the number of bad storage blocks is greater than or equal to the set threshold bad storage block count, the shared state is changed from the first state to the second state.

12. The operating method according to claim 11, Changing the shared state of the first storage device from the first state to the second state includes disabling access to the second memory buffer of the first storage device.

13. The operating method according to claim 8, further comprising: The priority of each of the plurality of storage devices is determined based on the status information of each of the plurality of storage devices, and The storage device with the highest priority among the plurality of storage devices is designated as the second storage device.

14. The operating method according to claim 13, The priority of each of the plurality of storage devices is determined based on the size of the hot data stored in each of the plurality of storage devices.

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