High-performance layer allocation method under advanced through-hole pillar technology

Abstract

The present invention relates to a high-performance layer allocation method under advanced through-hole column technology. First, in order to enable timing-critical nets to better obtain priority in using wiring resources, a priority calculation of the initial wiring order is defined, so that the initial wiring order is more reasonable. Secondly, since the congestion cost of an edge is determined by the overflow cost and historical cost of the edge, in order not to ignore the congestion cost of the edge that has not overflowed, a reasonable definition is made for the historical cost of the edge when there is no overflow. In addition, in order to make the wiring scheme formed after each iteration in the iterative wiring stage more reasonable and to eliminate the illegal nets more quickly, the redistribution order of the illegal nets in this stage is standardized, so that the wiring order of this stage is more secure. The strategy proposed by the present invention defines the initial wiring order priority, takes into account the historical cost calculation of the edge when there is no overflow, and optimizes the redistribution order of the illegal nets to improve the effect of layer allocation.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit computer-aided design, in particular to a high-performance layer allocation method under advanced through-hole column technology. Background Art

[0002] The continuous expansion of integrated circuits (ICs) leads to increasing network latency. This increasing network latency negatively impacts chip performance. Layer allocation, a crucial step in chip physical design, plays an essential role in adjusting latency.

[0003] Overall routing latency is primarily composed of conductor latency and via latency. To reduce overall latency, one approach can address conductor latency by using lower-latency upper-layer routing resources or employing non-default-rule wire (NDR) technology. Alternatively, via latency can be addressed by employing via pillar technology. The best approach is to prioritize and qualify resources and technologies, and allocate them in a controlled and orderly manner.

[0004] Over time, various new technologies have been proposed and applied based on traditional layer allocation schemes. For example, via pillar technology is a recent and promising technology for optimizing via delay. However, despite its great potential, its current application within layer allocation schemes is limited. Layer allocation schemes that incorporate via pillar technology also have significant room for improvement in related performance. Summary of the Invention

[0005] The purpose of the present invention is to provide a high-performance layer allocation method under advanced through-hole column technology, which takes into account the historical cost calculation of edges without overflow and optimizes the reallocation order of illegal line networks to improve the effect of layer allocation.

[0006] To achieve the above objectives, the technical solution of the present invention is: a high-performance layer allocation method under advanced through-hole column technology, comprising:

[0007] (1) In the initial routing stage, in order to reduce the uncertainty of layer assignment and improve the stability of the algorithm, a sorting strategy is proposed that comprehensively considers the total path length of the network and the number of receivers in the network.

[0008] (2) A new strategy is proposed to dynamically adjust the historical cost of edges using a negotiation-based method, which makes the calculation of the historical cost of edges more reasonable while also improving the calculation of the congestion cost of edges, which is conducive to improving the accuracy of wiring during the layer allocation process.

[0009] (3) In the iterative routing phase, when redistributing the illegal nets, in order to improve the routing flexibility of this phase, a sorting strategy is proposed that comprehensively considers the net's delay, the net's total path length, and the number of receivers in the net.

[0010] Compared with the prior art, the present invention has the following beneficial effects: the method of the present invention takes into account the historical cost calculation of edges without overflow, optimizes the reallocation order of illegal network lines, and improves the effect of layer allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The width and spacing of wires in different layers are different.

[0012] Figure 2 Default rules: Wire Line, Parallel Line, Wide Line.

[0013] Figure 3 Grid cell.

[0014] Figure 4 Through-hole post type.

[0015] Figure 5 Flowchart of the layer allocation algorithm.

[0016] Figure 6 The total path is the same but the delay is different; (a) 2D wiring solution; (b) 3D wiring solution.

[0017] Figure 7 The edges that do not overflow have different levels of congestion. DETAILED DESCRIPTION

[0018] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] The present invention provides a high-performance layer allocation method using advanced through-hole column technology, comprising:

[0020] (1) In the initial routing stage, in order to reduce the uncertainty of layer assignment and improve the stability of the algorithm, a sorting strategy is proposed that comprehensively considers the total path length of the network and the number of receivers in the network.

[0021] (2) A new strategy is proposed to dynamically adjust the historical cost of edges using a negotiation-based method, which makes the calculation of the historical cost of edges more reasonable while also improving the calculation of the congestion cost of edges, which is conducive to improving the accuracy of wiring during the layer allocation process.

[0022] (3) In the iterative routing phase, when redistributing the illegal nets, in order to improve the routing flexibility of this phase, a sorting strategy is proposed that comprehensively considers the net's delay, the net's total path length, and the number of receivers in the net.

[0023] The following is a specific implementation process of the present invention.

[0024] 1. Multi-layer structure model:

[0025] Layer allocation is an important process from 2D routing to 3D routing. The design of the routing scheme has a multi-layer structure. In a multi-layer structure, different layers have different default wire widths and spacing between wires. The wiring directions of adjacent layers are perpendicular, and different layers are connected through through holes. The wires of the upper layer generally have a thicker width and a larger spacing (such as Figure 1 As shown in the figure, the resistance of the upper layer is usually smaller than that of the lower layer. Therefore, if the network with higher delay requirements, that is, the critical timing network, is allocated to the upper layer, it may be more beneficial to delay control. However, due to the thicker width and larger spacing, the wiring resources of the upper layer are usually less than those of the lower layer. At the same time, the wiring resources of the upper layer are also limited. Therefore, how to effectively allocate the critical timing path to the upper layer while avoiding congestion is a challenge. In addition, if too many wires are allocated to the same layer, the wiring density of the layer will increase, and the coupling capacitance of the wiring layer will also increase, which will have a negative impact on the delay results. Therefore, for the multi-layer structure model in the design process, only by comprehensively considering various factors can the optimal wiring solution be given.

[0026] 2. Non-default rule guide:

[0027] The wire with a predefined special width is called NDR wire. NDR wire is implemented in two forms: one is wide wire and the other is parallel wire. Figure 2 As shown in the figure. Wide lines are much wider than default regular wires. Because of their greater width, they require more wiring space while having lower resistance than regular wires. Due to manufacturing process constraints, they are generally used in upper layers of multilayer structures. Parallel lines, on the other hand, are connected via two parallel wires of the default width. This is similar to using wide lines to reduce wire resistance and thus delay. However, due to manufacturing process limitations, parallel lines are generally used in lower layers of multilayer structures.

[0028] 3. Basics of layer allocation:

[0029] 3.1 Line Network

[0030] The process of layer allocation involves hundreds of millions of wire nets, each of which has a transmitter and multiple receivers. Each receiver is connected to the transmitter via wires, forming paths. The distribution of these paths forms a wire net. Factors such as the total latency, total path length, congestion level, overflow, and the ability to use NDR wires are all factors that must be comprehensively considered in a high-performance cabling solution.

[0031] 3.2 Congestion

[0032] To ensure routability, layer assignments should avoid assigning too many wires to certain layers and also avoid overusing NDR wires. Therefore, congestion is controlled by following two constraints:

[0033] TWO(S k )=TWO(S) (1)

[0034]

[0035] Among them, S represents the given 2D global routing result, and represents the layer allocation result. TWO represents the total overflow of the wire, and MWO represents the maximum overflow of the wire. The first constraint ensures that the total overflow of the wire in the 3D routing scheme will not exceed the total overflow of the wire in the 2D routing scheme; the second constraint ensures that the maximum congestion of the edge in the 2D routing scheme can be evenly distributed to the corresponding edges in the 3D routing scheme, and these edges are allocated to the layer with the same preferred routing direction as the edge in the 2D routing scheme. Because the grid unit (g-cell) is usually abstracted into a point in the layer allocation process, the congestion of the through hole is often ignored, so it is necessary to restore the size of the g-cell, and then consider the congestion more comprehensively, while also reducing the occurrence of overflow, such as Figure 3 shown.

[0036] 3.3 Latency

[0037] Interconnect delays are estimated using the Elmore delay model. Each net has a transmitter (source) and one or more receivers (sinks), where the transmitter has a driving resistor and each receiver has its own corresponding load capacitor. In the 3D wiring tree of the net, the edges representing wire segments or vias are treated as independent RC units. Using the Elmore delay model, the delay d(s) of segment s is calculated as follows:

[0038]

[0039] Where R(s) represents the resistance of segment s, C(s) represents the capacitance of segment s, and C down(s) represents the downstream capacitance of segment s. For each receiver-to-transmitter path, its delay d(si) is the sum of the delays of each segment on the path. It is calculated as follows:

[0040] d(si)=∑ s∈path(si) d(s) (4)

[0041] The delay d(N) of the network N is the weighted sum of the delays of each path in the network, where the weights are specified by the user. It is calculated as follows:

[0042] d(N)=∑ si∈S(N) a si ×d(si) (5)

[0043] Where S(N) represents the set of N receivers, a si represents the corresponding weight of the path where receiver si is located. To make the delay of each receiver equally important, the corresponding weight of each receiver is set to 1 / |S(N)|, where |S(N)| represents the number of receivers in network N.

[0044] 3.4 Through-hole column technology

[0045] To further reduce latency while meeting congestion constraints while disassembling and reallocating all nets, via pillar technology was introduced to improve the timing of the final 3D routing solution. In advanced process technologies, via pillar technology offers significant advantages in optimizing via latency, making it an integral component of high-performance physical design. Each layer within the via pillar structure includes multiple vias and conductors, significantly reducing the via resistance of the via pillar structure, thereby minimizing via latency.

[0046] Due to latency, congestion, and the varying types and sizes of vias and wires, via post technology is often combined with NDR wires. Compared to standard vias and wires, via posts and NDR wires require more routing resources, so their use should be controlled to avoid degrading overall routing performance. Therefore, their use is generally limited to timing-critical segments within timing-critical nets. In this study, nets were sorted in descending order of latency, with the top 5 percent of nets designated as timing-critical. The timing-critical segment is determined by the following formula:

[0047]

[0048]

[0049] Among them, cv(nd i ) represents the node nd iThe eigenvalue of dist(nd i ) represents the node nd i The distance to the transmitter, dist(leafnd max-i ) represents the distance from the receiver to the transmitter and passing through the node nd i The value of the longest path among all the paths in the network. The second formula defines a limit value. Order(n) represents the order of the network n when the network is arranged in descending order of delay. k and b are user-defined parameters. If a node nd i cv(nd i ) value is less than the corresponding limit(n) value, the segment between the node and its parent node is called a timing critical segment, otherwise it is not.

[0050] In order to make the wiring more accurate, before using NDR wires and through-hole columns, it is necessary to clarify the types of wires and through-hole columns. The type of wires of the two adjacent layers connected by the through-hole column determines its type. Therefore, there are five types of through-hole columns: 2×1 type through-hole column, 2×2 type through-hole column, 3×1 type through-hole column, 3×2 type through-hole column, 3×3 type through-hole column, such as Figure 4 shown.

[0051] According to the type of wire connected to the through-hole column, the implementation method of the through-hole column can be freely adjusted from the through-hole column type mentioned above. At the same time, the through-hole column is also operable for multi-layer structures.

[0052] 4. Layer allocation process (such as Figure 5 、 6 , 7)

[0053] In the first CSLA stage, without considering congestion, in order to maximize the overall performance of the routing solution generated after the initial allocation, the initial routing order is controlled based on the premise that the greater the delay, the more priority it should have in using routing resources. A priority is determined for the initial allocation of each net, so that each net is allocated to the best layer, and then a layer allocation solution with higher overall performance is found in this CSLA stage. At the same time, in this early stage, in order to avoid the consumption of routing resources such as NDR wires and through-hole columns, NDR wires and through-hole columns are not allowed to be used during routing (but they are allowed in the other two stages). The layer allocation algorithm for a single net aims to minimize the following objective function for each net:

[0054] cost(N)=α×∑ e∈N cong(e)+β×d(N)+γ×#via N (8)

[0055] Where cost(N) represents the cost of the 3D routing solution for network N, cong(e) represents the congestion cost of edge e in network N, d(N) represents the delay of network N, and #via N Represents the number of vias in net N, where α, β, and γ are user-defined parameters.

[0056] The next phase, the RRLA phase, iteratively reallocates offending nets, gradually ensuring they meet the wire congestion constraints while utilizing routing resources as efficiently as possible to minimize latency. Based on the previous layer allocation results, the offending nets are first identified from all nets. A processing order for the offending nets is then defined, taking into account the total path length, number of receivers, and latency since the previous iteration. The offending nets are then disassembled and reallocated according to this defined processing order. After all offending nets have been reallocated, the nets are checked for congestion constraints. If the layer allocation results are found to violate the wire congestion constraints, the edge history cost of each 3D net that overflowed is increased according to the edge history cost calculation formula, thereby increasing their congestion costs. For edges that did not overflow in the layer allocation results, the edge history cost of these 3D nets that did not overflow is proportionally increased according to the edge history cost calculation formula, thereby increasing their congestion costs. After a traversal, when the historical costs and congestion costs of all edges have been dynamically adjusted, the process returns to the first step of RRLA and iterates until the layer allocation results after the iteration meet the specified congestion constraints. The increase in the congestion cost of edges that overflow will be greater than that of edges that do not overflow, ensuring that these edges that overflow will be used as little as possible during layer allocation. For edges that do not overflow, the greater their congestion level, the greater the increase in their congestion cost. As a result, among the edges that do not overflow, those with greater congestion levels are less likely to be used.

[0057] The final phase, the LO phase, further reduces latency and the number of vias by disassembling and redistributing each net while meeting congestion constraints. The congestion penalty is set to a high value when an edge overflows, allowing the nets to be redistributed while meeting the wire congestion constraints.

[0058] 5. Initial wiring order priority definition:

[0059] In the initial routing stage, a processing order for network allocation is proposed. In the initial routing process of the initial stage, the network is initially routed in the order of serial numbers from 1 to n. Routing in this order is not conducive to routing flexibility. In order to enhance the accuracy and flexibility of routing and reduce the latency of the network, the network with higher latency is often given priority in using routing resources. However, before obtaining a 3D routing solution, the latency of each network is unknown. At this time, according to the Elmore delay model, it is known that the calculation of delay is related to the total path length, resistance, capacitance, etc. of the network. Based on this information, considering that the larger the total path length of the network, the larger the corresponding delay of the network, the network can be determined according to the total path length of the network. That is, the larger the total path length of the network, the higher the priority of the network in using routing resources. Furthermore, considering that when the total path length is the same, the more paths a network has, that is, the more receivers a network has, the greater the network latency will tend to be. Therefore, we try to add the consideration of the number of network receivers to the original consideration of only the total path length of the network, to more comprehensively determine the network routing order during the initial routing process. In this case, the network routing priority is calculated as follows:

[0060] priority(n)=tpl n +sink n (9)

[0061] Among them, sink n Represents the number of receivers in net n. The initial routing order of a net is determined by both the total path length and the number of receivers in the net. However, because the magnitudes of the two factors are quite different, different weights are assigned to each to make their importance more reasonable, as shown below:

[0062] priority(n)=α×tpl n +β×sink n (10)

[0063] Among them, α and β are user-defined weights.

[0064] 6. Calculation of historical cost considering no overflow:

[0065] Because the priority of each edge is often determined by the size of the edge's congestion cost, the smaller the congestion cost of an edge, the greater the possibility of it being selected for use, and the more likely it is to overflow. Therefore, edge overflow is often closely related to the edge's congestion cost. In this study, the congestion cost of edge e is calculated as follows:

[0066] cong(e)=p e×h e (11)

[0067] Among them, p e represents the current overflow cost of edge e, h e represents the historical cost of the current iteration of edge e, that is, the congestion cost of the edge is the overflow cost of the edge multiplied by the historical cost of the edge. Therefore, in addition to the overflow cost of the edge, the historical cost of the edge is what affects the congestion cost of the edge. If the historical cost of edge e h e The calculation is only a unilateral dynamic adjustment, that is, only when edge e overflows, its historical cost will be assigned a corresponding value greater than zero. When edge e does not overflow, this calculation method directly assigns the historical cost of edge e to zero. Although this can well control the next iteration and prevent the network from rewiring these edges that have overflowed, this calculation method ignores the possibility that other edges that have not overflowed will overflow in the future.

[0068] Therefore, we cannot simply unilaterally calculate the historical cost of the edge and assign it a value of zero when no overflow occurs. At the same time, if the layer allocation algorithm introduces advanced through-hole column technology, the overflow of the through-hole column is often easily ignored. If the historical cost of the edge is unilaterally adjusted dynamically, the overflow caused by the through-hole column cannot be fully considered and handled. Therefore, the congestion of the edge without overflow should also be considered, that is, when the edge does not overflow, its historical cost should also be assigned a corresponding value greater than zero. This study proposes a balanced calculation of the historical cost of the edge, as shown below:

[0069]

[0070] in, Represents h after the i-th iteration e The value of ρ is a parameter whose value is defined by the user. used Represents the capacity used by edge e, e total represents the total capacity of edge e. This calculation method not only assigns different historical costs to edges that have overflowed and those that have not, distinguishing them from each other, but also assigns corresponding historical costs to edges that have not overflowed based on their respective proportions of used capacity, thereby distinguishing edges with different levels of congestion. Therefore, using this balanced calculation method for edge historical costs is more conducive to accurate and reliable routing.

[0071] 7. Standardize the order of redistribution of illegal lines:

[0072] The RRLA stage, also known as the iterative routing stage, is a very important stage in the layer allocation algorithm. It reallocates the illegal nets through multiple iterations until the congestion constraints of the nets are met. Because multiple net routing processes are required in this stage, the routing order of the nets is also particularly important. Originally, in the RRLA stage, the routing order of the nets was determined based on the delay size after the last iteration of the nets. However, after each split and reallocation, the delay of each net will change. Therefore, in the new iteration, the delay size order of the reallocated nets will change. If the illegal nets are still reallocated according to the delay size order after the last iteration, then the routing process will be unreasonable. Therefore, considering various factors comprehensively, the following formula is given to determine the routing order of the nets in the RRLA stage:

[0073] priority(n)=α×tpl n +β×sink n +γ×od n (13)

[0074] Among them, n represents the delay of net n in the previous iteration, and γ is the corresponding weight assigned. According to this formula, it can be seen that in the RRLA routing phase, the order in which illegal nets are reassigned is determined by the total path length of the net, the number of receivers in the net, and the delay after the previous iteration of the net. These three factors are comprehensively considered according to different weights to obtain the priority (n) of net n. The larger the priority (n) value of net n, the higher its rerouting order. Through this strategy, while enhancing routing flexibility, it also enhances the rationality of the use of NDR wires and through-hole columns, reduces the delay of the net after rerouting, and reduces the appearance of illegal nets in the next iteration.

[0075] The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions and effects do not exceed the scope of the technical solution of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A high performance layer allocation method under advanced through-hole pillar technology, characterized in that: include: In the initial routing stage, a sorting strategy is proposed that comprehensively considers the total path length of the wire net and the number of receivers in the wire net. A negotiation-based approach is proposed to dynamically adjust the historical cost of edges. During the iterative routing phase, a sorting strategy is proposed to reassign offending nets by comprehensively considering the net's latency, total path length, and number of receivers. The specific implementation of this method is as follows: The first phase, the CSLA phase, controls the initial routing order and prioritizes each net's initial allocation, without considering congestion. This prioritizes each net, assigning it to the optimal layer. NDR wires and vias are not permitted during routing. The layer allocation algorithm for a single net aims to minimize the following objective function for each net: cost(N)=α×∑ e∈N cong(e)+β×d(N)+γ×#via N Where cost(N) represents the cost of the 3D routing solution for network N, cong(e) represents the congestion cost of edge e in network N, d(N) represents the delay of network N, and #via N Represents the number of vias in net N, α, β, and γ are user-defined parameters; The second phase, the RRLA phase, iterates and repeatedly redistributes the offending network, gradually allowing it to meet the congestion constraints of the wires. After a traversal, the historical costs and congestion costs of all edges are dynamically adjusted, and the next round of iteration is performed until the layer allocation results after the iteration meet the specified congestion constraints. The third phase, the LO phase, further reduces latency and the number of vias by disassembling and redistributing each net while meeting congestion constraints. The congestion of the wire is subject to the following two constraints: TWO(S k )=TWO(S) Among them, S represents the given 2D global routing result, represents the layer allocation result; TWO represents the total overflow of the wire, and MWO represents the maximum overflow of the wire; the first constraint ensures that the total overflow of the wire in the 3D routing scheme does not exceed the total overflow of the wire in the 2D routing scheme; the second constraint ensures that the maximum congestion of the edge in the 2D routing scheme is evenly distributed to the corresponding edge in the 3D routing scheme.

2. The high performance layer allocation method under advanced through-hole pillar technology according to claim 1, characterized in that: In a layer allocation process, each net has a transmitter and one or more receivers, where the transmitter has a driving resistor and each receiver has its own corresponding load capacitor. In the 3D routing tree of the net, the edges representing the wire segments or vias are treated as independent RC units. Using the Elmore delay model, the delay d(s) of segment s is calculated as follows: Where R(s) represents the resistance of segment s, C(s) represents the capacitance of segment s, and C down (s) represents the downstream capacitance of segment s; for each receiver-to-transmitter path, its delay d(si) is the sum of the delays of each segment on the path; it is calculated as follows: d(si)=∑ s∈path(si) d(s) The delay d(N) of network N is the weighted sum of the delays of each path in the network, where the weights are specified by the user. It is calculated as follows: d(N)=∑ si∈S(N) and si ×d(si) Where S(N) represents the set of N receivers, a si Represents the corresponding weight of the path where the receiver si is located; to make the delay of each receiver equally important, the corresponding weight of each receiver is set to 1 / |S(N)|, where |S(N)| represents the number of receivers in the line network N.

3. The high performance layer allocation method under advanced through-hole pillar technology according to claim 1, characterized in that: When all nets are disassembled and reallocated, via pillar technology is introduced to improve the timing of the final 3D routing solution while meeting congestion constraints. Taking into account latency, congestion, and the different types and sizes of vias and wires, via pillar technology is combined with NDR wires. Via pillars and NDR wires are only used in the timing-critical sections of timing-critical nets. Nets are sorted in descending order of latency, and the top 5% of nets are called timing-critical nets. The timing-critical section is determined by the following formula: Among them, cv(nd i ) represents the node nd i The eigenvalue of dist(nd i ) represents the node nd i The distance to the transmitter, dist(leafnd max-i ) represents the distance from the receiver to the transmitter and passing through the node nd i The value of the longest path among all the paths in the formula; the second formula defines a limit value, order(n) represents the order of the network n when the network is arranged in descending order of delay, k and b are user-defined parameters; if a node nd i cv(nd i ) value is less than the corresponding limit(n) value, the segment between the node and its parent node is called a timing critical segment, otherwise it is not.

4. The high performance layer allocation method under advanced through-hole pillar technology according to claim 2, characterized in that: Initial routing order priority definition: In the initial routing stage, a processing order for net allocation is proposed; in the initial routing process, the priority of the net routing is calculated as follows: priority(n)=tpl n +sink n Among them, sink n Represents the number of receivers in net n. The priority of the initial routing order of the net is determined by both the total path length of the net and the number of receivers in the net. The two factors have different orders of magnitude and are given different weights, as shown below: priority(n)=α×tpl n +β×sink n Among them, α and β are user-defined weights.

5. The high performance layer allocation method under advanced through-hole pillar technology according to claim 1, characterized in that: The historical cost calculation process is as follows: The priority of each edge is determined by the size of the edge's congestion cost. The congestion cost of edge e is calculated as follows: cong(e)=p e ×h e Among them, p e represents the current overflow cost of edge e, h e represents the historical cost of the current iteration of edge e, that is, the congestion cost of the edge is the overflow cost of the edge multiplied by the historical cost of the edge; excluding the overflow cost of the edge, the historical cost of the edge is what affects the congestion cost of the edge. If the historical cost of edge e h e The calculation is only a unilateral dynamic adjustment, that is, only when edge e overflows, its historical cost will be assigned a value greater than zero. When edge e does not overflow, this calculation method directly assigns the historical cost of edge e to zero. This calculation method ignores the possibility that other edges that have not overflowed may overflow in the future. Therefore, a balanced calculation of the historical cost of edges is proposed, as shown below: in, Represents h after the i-th iteration e The value of ρ is a parameter whose value is defined by the user; e used Represents the capacity used by edge e, e total Represents the total capacity of edge e.

6. The high performance layer allocation method under advanced through-hole pillar technology according to claim 1, characterized in that: The specific implementation of the redistribution of illegal lines is as follows: The wiring order of the RRLA phase net is determined by the following formula: priority(n)=α×tpl n +β×sink n +γ×od n Among them, n represents the delay of network n in the previous iteration, and γ is the corresponding weight of the assignment. According to the above formula, in the RRLA routing phase, the order in which the illegal network is reassigned is determined by the total path length of the network, the number of receivers in the network, and the delay after the previous iteration of the network. The priority(n) of network n is obtained by comprehensively considering these three factors with different weights. The larger the priority(n) value of network n, the earlier it is rerouted.

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