Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate comprising a PMOS region and an NMOS region, a gate dielectric layer is formed on the substrate of the PMOS region and the NMOS region; forming a protective layer; forming a first work function layer, the first work function layer is located on the protective layer of the PMOS region, and the first work function layer has first adjusting ions; forming a second work function layer, the second work function layer has second adjusting ions; performing a diffusion process, so that the first adjusting ions diffuse into the gate dielectric layer of the PMOS region, and the second adjusting ions diffuse into the gate dielectric layer of the NMOS region; removing the second work function layer and the first work function layer until the protective layer is exposed; forming a first gate and a second gate, the first gate is located on the PMOS region, and the second gate is located on the NMOS region. At least the problem of etching damage caused by removing the work function layer of the PMOS region and the NMOS region to the gate dielectric layer can be solved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] In a CMOS transistor, by making the metal gate of the transistor in the range of a respective work function, the transistor can achieve its expected threshold voltage Vt. Different types of transistors in a semiconductor structure have different requirements for threshold voltage, and accordingly, different types of transistors have different requirements for work function value.

[0003] Specifically, in a semiconductor structure, a PMOS region corresponds to a PMOS transistor, and an NMOS region corresponds to an NMOS transistor, and different processes are taken to form the work function layer (WFM) corresponding to the PMOS transistor and the NMOS transistor, respectively. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which at least solve the problem of etching damage caused by removing the work function layer of the PMOS region and the NMOS region to the gate dielectric layer.

[0005] According to some embodiments of the present disclosure, the present disclosure provides a manufacturing method of a semiconductor structure, which includes: providing a substrate including a PMOS region and an NMOS region, the substrate of the PMOS region and the NMOS region being formed with a gate dielectric layer; forming a protective layer, the protective layer being located on the surface of the gate dielectric layer; forming a first work function layer, the first work function layer being located on the protective layer of the PMOS region, and the material of the first work function layer being different from the material of the protective layer, the first work function layer having first adjusting ions; forming a second work function layer, the second work function layer being located on the surface of the first work function layer and also being located on the surface of the protective layer, the second work function layer having second adjusting ions; performing a diffusion process, so that the first adjusting ions diffuse into the gate dielectric layer of the PMOS region, and the second adjusting ions diffuse into the gate dielectric layer of the NMOS region; removing the second work function layer and the first work function layer until the protective layer is exposed; forming a first gate and a second gate, the first gate being located on the gate dielectric layer of the PMOS region, and the second gate being located on the gate dielectric layer of the NMOS region.

[0006] According to some other embodiments of the present disclosure, the material of the protective layer includes tantalum nitride or tungsten nitride.

[0007] According to some other embodiments of the present disclosure, the thickness of the protective layer is 3nm-4nm.

[0008] According to some embodiments of the present disclosure, the removing the second work function layer and the first work function layer until the protective layer is exposed further comprises: thinning the protective layer.

[0009] According to some embodiments of the present disclosure, the thickness of the thinned protective layer is 0.5nm-1.5nm.

[0010] According to some embodiments of the present disclosure, the method of forming the first gate and the second gate comprises: forming the first gate on the surface of the protective layer of the PMOS region; and forming the second gate on the surface of the protective layer of the NMOS region.

[0011] According to some embodiments of the present disclosure, the removing the second work function layer and the first work function layer until the protective layer is exposed further comprises: removing the protective layer.

[0012] According to some embodiments of the present disclosure, the step of forming the first work function layer comprises: forming a first work function adjusting film on the gate dielectric layer of the NMOS region and the PMOS region, the first work function adjusting film having the first adjusting ions; forming a first initial cover layer on the surface of the first work function adjusting film; removing the first initial cover layer and the first work function adjusting film of the NMOS region, the first work function adjusting film of the PMOS region serving as a first work function adjusting layer, the first initial cover layer of the PMOS region serving as a first cover layer, and the first cover layer and the first work function adjusting layer constituting the first work function layer.

[0013] According to some embodiments of the present disclosure, the material of the first work function adjusting layer comprises an aluminum-containing material, and the first adjusting ions comprise aluminum ions; and the material of the first cover layer comprises titanium nitride.

[0014] According to some embodiments of the present disclosure, the process step of forming the second work function layer comprises: forming a second work function adjusting layer on the surface of the first work function layer and the surface of the protective layer, the second work function adjusting layer having the second adjusting ions; and forming a second cover layer on the surface of the second work function adjusting layer, the second cover layer and the second work function adjusting layer constituting the second work function layer.

[0015] According to some embodiments of the present disclosure, the material of the second work function adjusting layer comprises a lanthanum-containing material, and the second adjusting ions comprise lanthanum ions; and the material of the second cover layer comprises titanium oxide.

[0016] According to another embodiment of the present disclosure, the diffusion process is performed at a temperature of 900-1000℃, and the diffusion process is performed for 8-12s.

[0017] According to another embodiment of the present disclosure, before the diffusion process, the method further comprises: forming a first dummy gate on the surface of the second work function layer in the PMOS region; and forming a second dummy gate on the surface of the second work function layer in the NMOS region; and before removing the second work function layer and the first work function layer, the method further comprises: removing the first dummy gate and the second dummy gate.

[0018] According to another embodiment of the present disclosure, the forming of the gate dielectric layer comprises: forming an interface layer on the surface of the NMOS region and the PMOS region of the substrate; and forming a high-K dielectric layer on the surface of the interface layer.

[0019] According to another embodiment of the present disclosure, the method of removing the second work function layer and the first work function layer until the protective layer is exposed comprises: removing the second work function layer and the first work function layer by using a wet etching process; and cleaning the surface of the protective layer.

[0020] According to another embodiment of the present disclosure, the semiconductor structure comprises: a substrate comprising a PMOS region and an NMOS region; a gate dielectric layer on the NMOS region and the PMOS region of the substrate; a protective layer on the surface of the gate dielectric layer; a first gate on the gate dielectric layer in the PMOS region; and a second gate on the gate dielectric layer in the NMOS region.

[0021] According to another embodiment of the present disclosure, the thickness of the protective layer is 0.5-1.5nm.

[0022] According to another embodiment of the present disclosure, the first gate and the second gate are both metal gates.

[0023] According to another embodiment of the present disclosure, the gate dielectric layer comprises: an interface layer on the surface of the NMOS region and the PMOS region of the substrate; and a high-K dielectric layer on the surface of the interface layer.

[0024] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0025] The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure includes the following steps: forming a protection layer on the surface of the gate dielectric layer of the PMOS region before forming a first work function layer on the gate dielectric layer of the PMOS region and before forming a second work function layer on the PMOS region and the NMOS region; performing a diffusion process, so that first adjustment ions in the first work function layer diffuse into the gate dielectric layer of the PMOS region to adjust the threshold voltage of the PMOS transistor formed in the PMOS region, and so that second adjustment ions in the second work function layer diffuse into the gate dielectric layer of the NMOS region to adjust the threshold voltage of the NMOS transistor formed in the NMOS region; and then removing the second work function layer and the first work function layer. In the process step of removing the second work function layer and the first work function layer, the protection layer protects the gate dielectric layers of the PMOS region and the NMOS region from etching damage, and ensures that the top surface of the gate dielectric layer has good surface properties. Specifically, the work function layer to be removed in the NMOS region is the second work function layer, and the work function layer to be removed in the PMOS region is the second work function layer and the first work function layer, that is, the work function layer in the NMOS region is removed earlier than the work function layer in the PMOS region. Due to the presence of the protection layer, the gate dielectric layer in the NMOS region is protected by the protection layer in the process step of removing the work function layer, so that the gate dielectric layer in the NMOS region is prevented from being exposed to the etching environment for removing the work function layer in the PMOS region, thereby preventing the gate dielectric layer in the NMOS region from being damaged by etching, and further improving the electrical properties of the formed semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0026] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are not intended to limit the scope of the embodiments, unless otherwise specifically indicated, the drawings in which:

[0027] Figures 1 to 4 A structure diagram corresponding to each step of a manufacturing method of a semiconductor structure;

[0028] Figures 5 to 14 A structure diagram corresponding to each step of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Figures 1 to 4 A structure diagram corresponding to each step of a manufacturing method of a semiconductor structure.

[0030] REFERENCE Figure 1, a substrate 10 including a PMOS region 11 and an NMOS region 12 is provided; a gate dielectric layer 20 is formed on a surface of the substrate 10; a first work function layer 30 is formed on the PMOS region 11, the first work function layer 30 including a first barrier layer 31, a first work function film 32 and a first cap layer 33 stacked in sequence; a second work function layer 40 is formed on the PMOS region 11 and the NMOS region 12, the second work function layer 40 including a second work function film 41 and a second cap layer 42 stacked in sequence, the second work function film 41 of the PMOS region being located on a surface of the first work function layer 30, and the second work function film 41 of the NMOS region being located on a surface of the gate dielectric layer 20; and a dummy gate 50 is formed on a surface of the second work function layer 40.

[0031] The first barrier layer 31 and the first cap layer 33 can be typically made of titanium nitride (TiN).

[0032] The first work function film 32 has first adjusting ions therein, and the second work function film 41 has second adjusting ions therein. Diffusion processes are performed to diffuse the first adjusting ions and the second adjusting ions into the gate dielectric layer 20 of the PMOS region and the NMOS region respectively, so as to adjust threshold voltages of PMOS transistors and NMOS transistors respectively.

[0033] Referring to Figure 2 , the dummy gate 50 is removed (see Figure 1 ), and the process for removing the dummy gate 50 can be a wet etching process.

[0034] Referring to Figure 3 , the first work function layer 30 and the second work function layer 40 are removed (see Figure 2 ), and the process for removing the first work function layer 30 and the second work function layer 40 can be a wet etching process.

[0035] Specifically, the work function layer to be removed from the PMOS region 11 is a stack of the first work function layer 30 and the second work function layer 40, and the work function layer to be removed from the NMOS region 12 is the second work function layer 40, so the thickness of the work function layer to be removed from the PMOS region 11 is greater than the thickness of the work function layer to be removed from the NMOS region 12, so that the work function layer of the NMOS region 12 is removed first, and the surface of the gate dielectric layer of the PMOS region 11 is prone to have residues, which are typically made of the material of the first work function layer 30.

[0036] Referring to Figure 4 , a cleaning process is performed to remove the residues of the PMOS region 11.

[0037] During the removal of the residues, the gate dielectric layer 20 of the NMOS region 12 is exposed to the cleaning process environment, so that the surface of the gate dielectric layer 20 of the NMOS region 12 is damaged, resulting in uneven surface of the gate dielectric layer 20 of the NMOS region 12, which will cause the carrier mobility of the NMOS region to decrease after the gate is formed. If the etching damage of the gate dielectric layer 20 is to be improved, the cleaning process time for removing the residues needs to be shortened, which, however, will cause the residues to be incompletely removed, and thus affect the performance of the semiconductor structure.

[0038] In addition, in the aforementioned process step of removing the first work function layer 30 and the second work function layer 40, since the work function layer of the NMOS region 12 is removed first, the gate dielectric layer 20 of the NMOS region 12 will also be exposed to the etching environment for a certain period of time, which will also cause the gate dielectric layer 20 of the NMOS region 12 to be damaged by etching. In addition, during the removal of the residues, the gate dielectric layer 20 of the PMOS region 11 will also be exposed to the cleaning process environment, so that the gate dielectric layer 20 of the PMOS region 11 will also be damaged by etching.

[0039] The present disclosure provides a semiconductor structure capable of protecting the gate dielectric layer during the removal of the work function layer. Before the first work function layer is formed on the gate dielectric layer of the PMOS region, and before the second work function layer is formed on the PMOS region and the NMOS region, a protective layer is first formed on the surface of the gate dielectric layer. After the first work function layer and the second work function layer complete the task of adjusting the gate work function, the first work function layer and the second work function layer are removed, and the protective layer protects the gate dielectric layer of the PMOS region and the NMOS region, preventing the gate dielectric layer from being damaged by etching and ensuring that the top surface of the gate dielectric layer has good surface properties. Specifically, the work function layer to be removed in the NMOS region is the second work function layer, and the work function layer to be removed in the PMOS region is the second work function layer and the first work function layer, that is, the work function layer of the NMOS region is removed earlier than the work function layer of the PMOS region. Due to the presence of the protective layer, the gate dielectric layer of the NMOS region can be prevented from being exposed to the etching environment for removing the work function layer of the PMOS region, so that the gate dielectric layer of the NMOS region is prevented from being damaged by etching, and thus the electrical performance of the formed semiconductor structure is improved.

[0040] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those of ordinary skill in the art can understand that, in the embodiments of the present disclosure, many technical details are presented in order to make the readers better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0041] Figures 5 to 14The structure diagram corresponding to each step of the method for manufacturing the semiconductor structure provided by an embodiment of the present disclosure.

[0042] Referring to Figure 5 , a substrate 100 including a PMOS region 101 and an NMOS region 102 is provided, and a gate dielectric layer 110 is formed on the substrate 100 of the PMOS region 101 and the NMOS region 102.

[0043] The PMOS region 101 is used to form a PMOS transistor, and the NMOS region 102 is used to form an NMOS transistor. The PMOS region 101 and the NMOS region 102 jointly constitute the substrate 100. The substrate 100 is used to form the entire semiconductor structure. There can also be an isolation layer between the PMOS region 101 and the NMOS region 102, which is used to separate the PMOS region 101 and the NMOS region 102.

[0044] In some embodiments, the step of forming the gate dielectric layer 110 can include: forming an interface layer 111 on the surface of the NMOS region 102 and the PMOS region 101 of the substrate 100; and forming a high-k dielectric layer 112 on the surface of the interface layer 111.

[0045] For example, the material of the interface layer 111 can be silicon oxide or silicon oxynitride. The interface layer 111 can be used to improve the interface properties between the substrate 100 and the high-k dielectric layer 112, thereby enhancing the electron mobility properties. The high-k dielectric layer 112 can include a material having a dielectric constant k higher than that of silicon dioxide (about 3.9). The material of the high-k dielectric layer 112 can include a metal oxide, a metal silicate, or a metal silicate nitride. The metal in the metal oxide can include, for example, HF, AL, La, or Zr, and the metal oxide can include hafnium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, or a combination thereof. The metal in the metal silicate can include HF or Zr, and the metal silicate can include, for example, HfSiO, ZrSiO, or a combination thereof. The metal silicate compound can include, for example, hafnium silicon nitride (HfSiOn), zirconium silicon nitride (ZrSiOn), or a combination thereof.

[0046] It can be understood that, in other embodiments, the gate dielectric layer 110 can also be a single-layer structure including an oxide layer, for example, the material of the oxide layer can be silicon oxide or silicon oxynitride.

[0047] The process method for forming the interface layer 111 can include, for example, thermal treatment RTO, and the process method for forming the high-k dielectric layer 112 can include, for example, atomic layer deposition ALD.

[0048] Referring to Figure 6 , a protective layer 120 is formed on the surface of the gate dielectric layer 110.

[0049] Specifically, the protective layer 120 can be located on the surface of the gate dielectric layer 110 of the PMOS region 101 and the surface of the gate dielectric layer 110 of the NMOS region 102. In other embodiments, the protective layer 120 can also be located on the surface of the gate dielectric layer 110 of the NMOS region 102. This is because the work function layer to be removed in the NMOS region 102 is the second work function layer 140 (see Figure 8 ), and the work function layer to be removed in the PMOS region 102 is the second work function layer 140 and the first work function layer 130 (see Figure 8 ), that is, the work function layer of the NMOS region 102 is removed earlier than the work function layer of the PMOS region 101, and the protective layer 120 arranged on the surface of the gate dielectric layer 110 of the NMOS region 102 can avoid the damage of the gate dielectric layer 110 of the NMOS region 102 caused by etching.

[0050] The process method for forming the protective layer can be selected from atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0051] The protective layer 120 is used to protect the gate dielectric layer 110 from the etching environment, and therefore, the protective layer 120 should be made of a material having a high etching selectivity compared with the first work function layer 130 and the second work function layer 140 in the wet etching environment for etching the first work function layer 130 and the second work function layer 140. The etching rate of the wet etching process on the protective layer 120 is much smaller than the etching rate of the first work function layer 130 and the second work function layer 140, so that the protective layer 120 can have a better protective effect. For example, the first work function layer 130 (each material layer therein) has a high etching selectivity with the protective layer 120. For another example, the second work function layer 140 (each material layer therein) also has a high etching selectivity with the protective layer 120. In the present disclosure, the high etching selectivity refers to an etching selectivity of no less than 10:1. In some embodiments, the material of the protective layer 120 can include tantalum nitride and tungsten nitride. In other embodiments, the material of the protective layer 120 can also be selected from other materials having a high etching selectivity, for example, the material of the protective layer 120 can be WN and TiSiN.

[0052] For example, in the same wet etching environment, the etching rate of the wet etching solution to TaN is much lower than that to TiN (for example, TiN is included in both the first work function layer 130 and the second work function layer 140). When the first work function layer 130 and the second work function layer 140 are subjected to the wet etching process and the cleaning process, because the surface of the gate dielectric layer 110 has the protective layer 120 with a high selectivity in the wet etching environment for etching the first work function layer 130 and the second work function layer 140 compared with the first work function layer 130 and the second work function layer 140, the protective layer 120 is difficult to be etched by the wet etching solution, and the protective layer 120 can always be located on the surface of the gate dielectric layer 110 to protect the gate dielectric layer 110 from being exposed to the etching environment. The gate dielectric layer 110 is not etched by the etching solution, and thus the problem of the surface of the gate dielectric layer 110 being damaged by etching does not occur, so that the carrier mobility of the device channel can be improved.

[0053] In some embodiments, the thickness of the protective layer 120 is 3 nm to 4 nm. For example, the thickness of the protective layer 120 can be 3.1 nm, 3.3 nm, 3.4 nm, 3.6 nm, 3.9 nm, etc. Such a thickness of the protective layer 120 can ensure that the protective layer 120 is always located on the surface of the gate dielectric layer 110 during the entire etching and cleaning process, and can play a role in protecting the gate dielectric layer 110 from being damaged.

[0054] Reference Figure 7 The first work function layer 130 is formed on the protective layer 120 of the PMOS region 101, and the material of the first work function layer 130 is different from that of the protective layer 120, and the first work function layer 130 has the first adjusting ion. The first work function layer 130 is used to adjust the gate work function of the PMOS region 101. The gate work function of the PMOS region 101 needs to be adjusted to 4.7 eV to 5.1 eV.

[0055] In some embodiments, the first work function layer 130 can be a stacked structure, and the step of forming the first work function layer 130 can include: forming a first work function adjusting film on the gate dielectric layer 110 of the NMOS region 102 and the PMOS region 101, the first work function adjusting film having the first adjusting ion; forming a first initial cover layer on the surface of the first work function adjusting film; removing the first initial cover layer and the first work function adjusting film of the NMOS region 102, the first work function adjusting film located on the PMOS region 101 as the first work function adjusting layer 131, and the first initial cover layer located on the PMOS region as the first cover layer 132, and the first cover layer 132 and the first work function adjusting layer 131 constitute the first work function layer 130. That is, the work function layer is formed on the PMOS region 101 and the NMOS region 102, and then the work function layer on the NMOS region 102 is removed to obtain the first work function layer 131.

[0056] In some embodiments, the step of forming the first work function layer 130 can also include: forming the first work function adjusting layer 131 on the gate dielectric layer 110 of the PMOS region 101; and forming the first cap layer 132 on the surface of the first work function adjusting layer 131, the first work function adjusting layer 131 and the first cap layer 132 constituting the first work function layer 130. The first work function layer 130 is formed directly on the PMOS region 101 in the form of a mask, and there is no need to form the first work function layer 130 on the whole surface and then remove the first work function layer 130 on the NMOS region 102.

[0057] In some other embodiments, the first work function layer 130 can also be a single-layer structure, and the step of forming the first work function layer 130 can include: forming the first work function layer 130 on the PMOS region 101, the first work function layer 130 having the first adjusting ions therein. The single-layer structure of the first work function layer 130 does not include the first cap layer 132, but still has the first adjusting ions and has the function of adjusting the gate work function of the PMOS region 101.

[0058] Since the first work function layer 130 is used to adjust the gate work function of the PMOS region 101, the material of the first work function adjusting layer 131 in the first work function layer 130 can be a P-type work function material, and the work function value of the P-type work function material is in the range of 4.7 eV to 5.1 eV. The first work function adjusting layer 131 has the first adjusting ions therein, and the first adjusting ions are used to adjust the gate work function of the PMOS region 101. In some embodiments, the material of the first work function adjusting layer 131 can include an aluminum-containing material, and the first adjusting ions can include aluminum ions. The material of the first work function adjusting layer 131 can also be TiAl or TaAl, etc.

[0059] The first cap layer 132 is used to isolate the first work function adjusting layer 131 from other structures above the first work function adjusting layer 131, and the material of the first cap layer 132 can include titanium nitride (TiN). TiN has good thermal stability, a high work function (4.7 eV to 5.2 eV), and can absorb oxygen ions, which helps to form oxygen vacancies in the gate dielectric layer and helps to reduce the threshold voltage of the PMOS.

[0060] In addition, the thickness of the first work function adjusting layer 131 can be 5 to 15 angstroms, and the thickness of the first cap layer 132 can be 5 to 15 angstroms. For example, the thickness of the first work function adjusting layer 131 can be 6 angstroms, 10 angstroms, 13 angstroms, etc., and the thickness of the first cap layer 132 can be 6 angstroms, 9 angstroms, 14 angstroms, etc.

[0061] Reference Figure 8The second work function layer 140 is formed on the surface of the first work function layer 130 and the surface of the protective layer 120, and has second adjusting ions.

[0062] Since the second work function layer 140 for adjusting the gate work function of the NMOS region 102 can also exist above the PMOS region 101, the second work function layer 140 can be formed on the whole surface of the PMOS region 101 and the NMOS region 102. The second work function layer 140 can be formed on the surface of the first work function layer 130 and the surface of the protective layer 120.

[0063] In some embodiments, the second work function layer 140 can be a laminated structure, and the step of forming the second work function layer 140 can include: forming a second work function adjusting layer 141 on the surface of the first work function layer 130 and the surface of the protective layer 120, the second work function adjusting layer 141 having second adjusting ions; and forming a second cover layer 142 on the surface of the second work function adjusting layer 141, the second cover layer 142 and the second work function adjusting layer 141 constituting the second work function layer 140.

[0064] In other embodiments, the second work function layer 140 can also be a single-layer structure, and the step of forming the second work function layer 140 can include: forming the second work function layer 140 on the surface of the first work function layer 130 and the surface of the protective layer 120, the second work function layer 140 having second adjusting ions. The single-layer structure of the second work function layer 140 does not include the second cover layer 142, but still has the second adjusting ions and can adjust the gate work function of the NMOS region 102.

[0065] Since the second work function layer 140 is used to adjust the gate work function of the NMOS region 102, the material of the second work function adjusting layer 141 in the second work function layer 140 can be an N-type work function material, and the gate work function value of the N-type work function material is required to be about 4.5eV or lower. The second work function adjusting layer 141 has second adjusting ions, and the second adjusting ions are used to adjust the gate work function of the NMOS region 102. In some embodiments, the material of the second work function adjusting layer 141 includes lanthanum-containing material, and the second adjusting ions include lanthanum ions.

[0066] The second cover layer 142 is used to isolate the second work function adjusting layer 141 from other structures above the first work function adjusting layer 131, and the material of the second cover layer 142 can include titanium nitride (TiN). TiN has good thermal stability, a high work function (4.7eV-5.2eV), can absorb oxygen ions, and is helpful to form oxygen vacancies in the gate dielectric layer and reduce the threshold voltage of the PMOS.

[0067] In addition, the thickness of the second work function adjustment layer 141 can be 5-15 angstroms, and the thickness of the second cover layer 142 can be 5-15 angstroms. For example, the thickness of the second work function adjustment layer 141 can be 6 angstroms, 10 angstroms, 13 angstroms, etc., and the thickness of the second cover layer 142 can be 6 angstroms, 9 angstroms, 14 angstroms, etc. In addition, since the TiN material has a greater gate work function adjustment effect on the PMOS region, the thickness of the first cover layer 132 is greater than the thickness of the second cover layer 142.

[0068] The process method for forming the first work function layer 130 and the second work function layer 140 can be selected from, but not limited to, radio frequency sputtering physical vapor deposition (RFPVD).

[0069] Reference Figure 9 In some embodiments, the method for manufacturing the semiconductor structure can further include: forming a first dummy gate 151 on the surface of the second work function layer 140 of the PMOS region 101; and forming a second dummy gate 152 on the surface of the second work function layer 140 of the NMOS region 102.

[0070] The first dummy gate 151 and the second dummy gate 152 can serve as a position reference for the gate in the back gate process of semiconductor device manufacturing, and other components such as the source and the drain can be formed based on the first dummy gate 151 and the second dummy gate 152. For example, the source and the drain of the PMOS transistor can be formed based on the first dummy gate 151, and the source and the drain of the NMOS transistor can be formed based on the second dummy gate 152. The first dummy gate 151 and the second dummy gate 152 can also prevent the ions in the first work function layer 130 and the second work function layer 140 from diffusing into the chamber in the subsequent diffusion process, thereby avoiding contamination of the chamber.

[0071] The material of the first dummy gate 151 and the second dummy gate 152 can be polysilicon, but is not limited thereto.

[0072] In some embodiments, the surface of the first dummy gate 151 and the second dummy gate 152 can further include an oxide layer.

[0073] Reference Figure 10 The diffusion process is performed to diffuse the first adjustment ions into the gate dielectric layer 110 of the PMOS region 101 and to diffuse the second adjustment ions into the gate dielectric layer 110 of the NMOS region 102.

[0074] The diffusion process diffuses first regulating ions from the first work function layer 130 into the gate dielectric layer 110 of the PMOS region 101, and second regulating ions from the second work function layer 130 into the gate dielectric layer 110 of the NMOS region 102. This achieves adjustment of the gate work function of the PMOS region 101 and the NMOS region 102. The gate work function of the PMOS region 101 is adjusted to the range of 4.7 eV to 5.1 eV, and the gate work function of the NMOS region 102 is adjusted to approximately 4.5 eV or lower.

[0075] The diffusion process can be a rapid thermal annealing process, requiring the selection of appropriate process temperature and time. If the process temperature is too low, the first and second regulating ions may not be effectively diffused into the gate dielectric layer 110; if the process temperature is too high, energy will be wasted. If the process time is too short, too few first and second regulating ions may diffuse into the gate dielectric layer 110; if the process time is too long, energy will be wasted and process costs will increase. In some embodiments, the diffusion process can use a process temperature of 900℃ to 1000℃ and a process time of 8s to 12s. For example, the diffusion process can use process temperatures of 930℃, 950℃, 970℃, 989℃, etc., and process times of 9s, 10s, 11s, etc. Such process temperatures and times can effectively diffuse regulating ions into the gate dielectric layer 110 without wasting energy or increasing process costs, thereby regulating the gate work function of the PMOS region 101 and the NMOS region 102.

[0076] In some embodiments, if the surfaces of the first dummy gate 151 and the second dummy gate 152 still have an oxide layer, the oxide layer needs to be removed after the diffusion process is completed. The oxide layer removal process can employ oxidation etching. To achieve a better etching effect, the etching solution for oxidation etching can be an HF solution, where the volume ratio of HF to deionized water in the HF solution can be 1:300. The oxidation etching process time can be 300 seconds.

[0077] refer to Figure 11 If a first pseudo gate 151 and a second pseudo gate 152 are formed during the process steps (see reference) Figure 10 If the second work function layer 140 and the first work function layer 130 are removed, then the first pseudo gate 151 and the second pseudo gate 152 need to be removed before removing the second work function layer 140 and the first work function layer 130.

[0078] The process for removing the first dummy gate 151 and the second dummy gate 152 can be a wet etching process. In one example, to achieve a better etching effect, the etching solution used in the wet etching process can be a mixed solution of NH4OH and deionized water, where the volume ratio of NH4OH to deionized water can be 1:50, the etching temperature can be 60°C, and the etching time can be 360 seconds.

[0079] Referring to Figure 12 and Figure 13 , the second work function layer 140 and the first work function layer 130 are removed (see Figure 11 ) until the protective layer 120 is exposed.

[0080] In some embodiments, the method for removing the second work function layer 140 and the first work function layer 130 until the protective layer 120 is exposed includes: removing the second work function layer 140 and the first work function layer 130 by using a wet etching process; and cleaning the surface of the protective layer 120. This is because there can still be residues on the surface of the protective layer 120 after the wet etching process, so a cleaning process is further needed to clean the surface of the protective layer 120.

[0081] In one example, to achieve a better wet etching effect, the etching solution used in the wet etching process can be a mixed solution of NH4OH, H2O2, and deionized water. In the mixed solution of NH4OH, H2O2, and deionized water, the volume ratio of NH4OH, H2O2, and deionized water can be 1:1.5:50. The process temperature of the wet etching process can be 60°C. The process time of the wet etching process can be 600 seconds.

[0082] The cleaning solution used for cleaning the surface of the protective layer 120 can be a mixed solution of HCl and deionized water, where the volume ratio of HCl to deionized water can be 1:100. The process temperature of the cleaning process can be 60°C. The process time of the cleaning process can be 600 seconds. The cleaning process can remove the residues on the surface of the protective layer 120.

[0083] It should be understood that the etching rate of the above-mentioned etching solution and cleaning solution on the protective layer 120 (for example, the TaN layer) is very low, that is, the protective layer 120 is basically not etched by the above-mentioned etching solution and cleaning solution.

[0084] Since the thickness of the protective layer 120 between the gate dielectric layer 110 and the gate electrode in the semiconductor structure has an impact on the threshold voltage of the semiconductor structure, after the second work function layer 140 and the first work function layer 130 are removed, the protective layer 120 needs to be processed.

[0085] In some embodiments, after removing the second work function layer 140 and the first work function layer 130 until the protective layer 120 is exposed, the method further includes thinning the protective layer 120. In some embodiments, the thickness of the thinned protective layer 120 is 0.5 nm to 1.5 nm. For example, the thickness of the thinned protective layer 120 can be 0.6 nm, 0.8 nm, 1.1 nm, 1.4 nm, etc. Thinning the protective layer 120 to this thickness range can ensure that the protective layer 120 does not affect the threshold voltage of the semiconductor structure.

[0086] In other embodiments, after removing the second work function layer 140 and the first work function layer 130 until the protective layer 120 is exposed, the method can further include removing the protective layer 120. If the protective layer 120 is removed, the gate electrode is subsequently formed directly on the surface of the gate dielectric layer 110. Removing the protective layer 120 can also avoid the protective layer 120 affecting the threshold voltage of the semiconductor structure.

[0087] Reference Figure 14 The first gate electrode 161 is formed on the gate dielectric layer 110 of the PMOS region 101, and the second gate electrode 162 is formed on the gate dielectric layer 110 of the NMOS region 102. At this time, the first gate electrode 161 and the second gate electrode 162 are the real gate electrodes 160 of the semiconductor structure.

[0088] In some embodiments, if the protective layer 120 is not removed but is thinned, the method of forming the first gate electrode 161 and the second gate electrode 162 includes forming the first gate electrode 161 on the surface of the protective layer 120 of the PMOS region 101, and forming the second gate electrode 162 on the surface of the protective layer 120 of the NMOS region 101. It can be understood that thinning the protective layer 120 is better than removing the protective layer 120, and the process of removing the protective layer 120 can still damage the gate dielectric layer 110.

[0089] The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure provides a manufacturing method of forming a protective layer between the gate dielectric layer and the work function layer. In this way, in the semiconductor structure, since the protective layer is arranged between the gate dielectric layer and the work function layer, the protective layer can protect the gate dielectric layer from being damaged by etching in the process of removing the work function layer of the semiconductor structure, and the problem of uneven surface roughness of the gate dielectric layer of the semiconductor structure is improved, and the electrical performance of the formed semiconductor structure is further improved.

[0090] Correspondingly, another embodiment of the present disclosure also provides a semiconductor structure, which is manufactured by the above-mentioned manufacturing method of the semiconductor structure. The semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. The same or corresponding parts of the semiconductor structure provided by another embodiment of the present disclosure can refer to the corresponding description of the foregoing embodiments, and will not be described in detail below.

[0091] Reference Figure 14 The semiconductor structure comprises: a substrate 100, the substrate 100 comprising a PMOS region 101 and an NMOS region 102; a gate dielectric layer 110, the gate dielectric layer 110 being located on the NMOS region 101 and the PMOS region 102 of the substrate 100; a protective layer, the protective layer being located on the surface of the gate dielectric layer; a first gate 161 and a second gate 162, the first gate 161 being located on the gate dielectric layer 110 of the PMOS region 101, and the second gate 162 being located on the gate dielectric layer 110 of the NMOS region 102.

[0092] The PMOS region 101 is used to form a PMOS transistor, and the NMOS region 102 is used to form an NMOS transistor. The PMOS region 101 and the NMOS region 102 jointly constitute the substrate 100. The substrate 100 is used to form the entire semiconductor structure. There can also be an isolation layer between the PMOS region 101 and the NMOS region 102, which is used to separate the PMOS region 101 and the NMOS region 102.

[0093] In some embodiments, the thickness of the protective layer 120 is 0.5 nm to 1.5 nm. For example, the thickness of the protective layer 120 can be 0.6 nm, 0.8 nm, 1.1 nm, 1.4 nm, etc. At this time, the protective layer 120 is obtained after a one-step thinning step. If the thickness of the protective layer 120 is too thick, it will affect the threshold voltage of the semiconductor structure. If the thickness of the protective layer 120 is too small, it may affect the gate dielectric layer 110 during the thinning process. Therefore, it is necessary to select an appropriate thickness range of the protective layer 120 after thinning. Within this range, the protective layer 120 will neither affect the threshold voltage of the semiconductor device nor easily affect the gate dielectric layer 110.

[0094] In some embodiments, the first gate 161 and the second gate 162 are both metal gates. The material of the first gate 161 and the second gate 162 can be one or several of tungsten, molybdenum, nickel, nickel-manganese alloy, nickel-chromium alloy, or nickel-molybdenum-iron alloy.

[0095] In some embodiments, the gate dielectric layer 110 comprises: an interface layer 111, the interface layer 111 being located on the surface of the NMOS region 102 and the PMOS region 101 of the substrate 100; and a high-K dielectric layer 112, the high-K dielectric layer 112 being located on the surface of the interface layer 111.

[0096] The material of the interface layer 111 can be silicon oxide or silicon oxynitride. The interface layer 111 can be used to improve the interface characteristics between the substrate 100 and the high-k dielectric layer 112, thereby enhancing the electron mobility characteristics. The high-k dielectric layer 112 can include a material having a dielectric constant k higher than that of silicon dioxide (about 3.9). The material of the high-k dielectric layer 112 can include a metal oxide, a metal silicate, or a metal silicate nitride. The metal in the metal oxide can include, for example, Hf, Al, La, or Zr, and the metal oxide can include hafnium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, or a combination thereof. The metal in the metal silicate can include Hf or Zr, and the metal silicate can include, for example, HfSiO, ZrSiO, or a combination thereof. The metal silicate compound can include, for example, hafnium silicate nitride (HfSiOn), zirconium silicate nitride (ZrSiOn), or a combination thereof.

[0097] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The application relates to a method for forming a gate electrode of a PMOS and NMOS region. The method comprises the following steps: forming a substrate comprising a PMOS region and an NMOS region, a gate dielectric layer being formed on the substrate of the PMOS region and the NMOS region; forming a protective layer on the surface of the gate dielectric layer; forming a first work function layer on the protective layer of the PMOS region, the material of the first work function layer being different from that of the protective layer, and the first work function layer containing first adjusting ions; forming a second work function layer on the surface of the first work function layer and on the surface of the protective layer, the second work function layer containing second adjusting ions; carrying out a diffusion process to diffuse the first adjusting ions into the gate dielectric layer of the PMOS region and diffuse the second adjusting ions into the gate dielectric layer of the NMOS region; removing the second work function layer and the first work function layer until the protective layer is exposed; 2. The production method according to claim 1, wherein forming a first gate electrode on the gate dielectric layer of the PMOS region and a second gate electrode on the gate dielectric layer of the NMOS region.

3. The production method according to claim 1, wherein The material of the protective layer comprises tantalum nitride or tungsten nitride.

4. The production method according to claim 1, wherein The thickness of the protective layer is 3-4 nm.

5. The production method according to claim 4, wherein After the second work function layer and the first work function layer are removed until the protective layer is exposed, the method further comprises thinning the protective layer.

6. The production method according to claim 4, wherein The thickness of the thinned protective layer is 0.5-1.5 nm.

7. The production method according to claim 1, wherein The method for forming the first gate electrode and the second gate electrode comprises forming the first gate electrode on the surface of the protective layer of the PMOS region and forming the second gate electrode on the surface of the protective layer of the NMOS region.

8. The production method according to claim 1, wherein After the second work function layer and the first work function layer are removed until the protective layer is exposed, the method further comprises removing the protective layer. The step of forming the first work function layer comprises: forming a first work function adjusting film on the gate dielectric layer of the PMOS region and the NMOS region, the first work function adjusting film containing the first adjusting ions; forming a first initial cover layer on the surface of the first work function adjusting film; 9. The production method according to claim 8, wherein removing the first initial cover layer and the first work function adjusting film of the NMOS region, the first work function adjusting film of the PMOS region serving as a first work function adjusting layer, the first initial cover layer of the PMOS region serving as a first cover layer, and the first cover layer and the first work function adjusting layer constituting the first work function layer.

10. The production method according to claim 1, wherein The material of the first work function adjusting layer comprises an aluminum-containing material, and the first adjusting ions comprise aluminum ions; the material of the first cover layer comprises titanium nitride. The process step of forming the second work function layer comprises: forming a second work function adjusting layer on the surface of the first work function layer and on the surface of the protective layer, the second work function adjusting layer containing the second adjusting ions; forming a second cover layer on the surface of the second work function adjusting layer, the second cover layer and the second work function adjusting layer constituting the second work function layer.

11. The production method according to claim 10, wherein The material of the second work function adjusting layer comprises lanthanum-containing material, and the second adjusting ion comprises lanthanum ion; and the material of the second cover layer comprises titanium nitride.

12. The production method according to claim 1, wherein The diffusion process is performed at a temperature of 900-1000 DEG C for 8-12 seconds.

13. The production method according to claim 1, wherein Before the diffusion process, the method further comprises: forming a first dummy gate on the surface of the second work function layer in the PMOS region; forming a second dummy gate on the surface of the second work function layer in the NMOS region; Before the second work function layer and the first work function layer are removed, the method further comprises removing the first dummy gate and the second dummy gate.

14. The production method according to claim 1, wherein The forming of the gate dielectric layer comprises: forming an interface layer on the surface of the NMOS region and the PMOS region of the substrate; forming a high-K dielectric layer on the surface of the interface layer.

15. The production method according to Claim 1, wherein The method of removing the second work function layer and the first work function layer until the protective layer is exposed comprises: using a wet etching process to remove the second work function layer and the first work function layer; cleaning the surface of the protective layer.

16. A semiconductor structure obtained by the manufacturing method according to any one of claims 1 to 15, characterized in that, The method comprises: a substrate comprising a PMOS region and an NMOS region; a gate dielectric layer on the NMOS region and the PMOS region of the substrate; a protective layer on the surface of the gate dielectric layer; a first gate on the gate dielectric layer in the PMOS region and a second gate on the gate dielectric layer in the NMOS region.

17. The semiconductor structure of claim 16, wherein, The thickness of the protective layer is 0.5-1.5 nm.

18. The semiconductor structure of claim 16, wherein, The first gate and the second gate are both metal gates.

19. The semiconductor structure of claim 16, wherein, The gate dielectric layer comprises: an interface layer on the surface of the NMOS region and the PMOS region of the substrate; a high-K dielectric layer on the surface of the interface layer.

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