Transistors, display modules, display panels and display devices

Abstract

This invention discloses a transistor, a display module, a display panel, and a display device. The transistor includes: an active layer having a first conductive region, a second conductive region, and a semiconductor region located between the first and second conductive regions; a conductive layer disposed on one side surface of the active layer, spaced apart from the first conductive region and the second conductive region; a source electrically connected to the first conductive region; a drain electrically connected to the second conductive region; and a gate disposed on the other side of the active layer. In the transistor of this invention, the conductive layer is disposed on one side surface of the active layer, spaced apart from the first and second conductive regions, and the gate is disposed on the other side of the active layer. By disposing of a conductive layer on one side surface of the active layer, a depletion layer capacitance can be formed, increasing the subthreshold swing of the metal oxide TFT, reducing the sensitivity of OLED luminous brightness to voltage fluctuations, and improving display uniformity and display effect.

Description

Technical Field

[0001] This invention belongs to the field of display technology, specifically relating to a transistor, a display module, a display panel, and a display device. Background Technology

[0002] Organic Light-Emitting Diode (OLED) display technology is attracting increasing attention. OLED pixels emit light by driving thin-film transistors (TFTs). The driving TFTs in OLED pixels need a large subthreshold swing (SS) to improve the data range and reduce the sensitivity of OLED brightness to voltage fluctuations. If the data range is too small, i.e., the sensitivity is too high, it will lead to poor display uniformity. For high-generation lines, metal-oxide (Oxide) TFTs have significant advantages in terms of cost, uniformity, and leakage current. Companies are urgently developing pure metal-oxide OLEDs, i.e., OLED pixels that use only metal-oxide TFTs. Currently, the subthreshold swing of metal-oxide TFTs is relatively small, and the OLED brightness is highly sensitive to voltage fluctuations, resulting in poor display uniformity and poor display quality. Summary of the Invention

[0003] The purpose of this invention is to provide a transistor, display module, display panel, and display device to solve the problem of small subthreshold swing in metal oxide TFTs.

[0004] In a first aspect, embodiments of the present invention provide a transistor, comprising:

[0005] An active layer having a first conductive region and a second conductive region and a semiconductor region located between the first conductive region and the second conductive region;

[0006] A conductive layer is disposed on one side surface of the active layer, the conductive layer and the first conductive region are spaced apart, and the conductive layer and the second conductive region are spaced apart;

[0007] The source electrode electrically connected to the first conductive region;

[0008] The drain electrode electrically connected to the second conductive region;

[0009] A gate, which is disposed on the other side of the active layer.

[0010] Furthermore, the orthographic projection of the conductive layer on the active layer is spaced apart from the first conductive region, and the orthographic projection of the conductive layer on the active layer is spaced apart from the second conductive region.

[0011] Furthermore, the orthogonal projection of the conductive layer onto the active layer lies within the semiconductor region.

[0012] Furthermore, the first conductive region and the second conductive region are symmetrically arranged with respect to the conductive layer.

[0013] Furthermore, one side surface of the active layer has a first surface, the conductive layer is disposed on the first surface, and the side surface of the conductive layer near the active layer is a second surface, with the first surface and the second surface being disposed parallel to each other.

[0014] Furthermore, there are multiple conductive layers, which are spaced apart on one side surface of the active layer.

[0015] Furthermore, the spacing between the orthographic projection of the conductive layer onto the active layer and the first conductive region is 2-6 μm; and / or

[0016] The spacing between the orthographic projection of the conductive layer onto the active layer and the second conductive region is 2-6 μm; and / or

[0017] The thickness of the conductive layer is 50-100 nm; and / or

[0018] The thickness of the active layer is 100-400 nm; and / or

[0019] Furthermore, the active layer includes an oxide semiconductor material layer.

[0020] Secondly, embodiments of the present invention provide a display module, comprising:

[0021] The transistor described in the above embodiments.

[0022] Furthermore, the display module also includes:

[0023] A light-emitting unit, wherein the transistor is used to drive the light-emitting unit to emit light.

[0024] Thirdly, embodiments of the present invention provide a display panel, including:

[0025] The display module described in the above embodiments.

[0026] Fourthly, embodiments of the present invention provide a display device, including the display panel described in the above embodiments.

[0027] A transistor according to an embodiment of the present invention includes: an active layer having a first conductive region, a second conductive region, and a semiconductor region located between the first conductive region and the second conductive region; a conductive layer disposed on one side surface of the active layer, the conductive layer being spaced apart from the first conductive region and the second conductive region; a source electrically connected to the first conductive region; a drain electrically connected to the second conductive region; and a gate disposed on the other side of the active layer. In the transistor of this embodiment, the conductive layer is disposed on one side surface of the active layer, the conductive layer is spaced apart from the first conductive region, the conductive layer is spaced apart from the second conductive region, and the gate is disposed on the other side of the active layer. By disposing of a conductive layer on one side surface of the active layer, a depletion layer capacitance can be formed, which can increase the subthreshold swing of the metal oxide TFT, reduce the sensitivity of OLED luminous brightness to voltage fluctuations, improve display uniformity, and improve display effect. Attached Figure Description

[0028] Figure 1 This is a schematic diagram illustrating the arrangement of the active layer and the conductive layer in one embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a transistor structure in one embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of a transistor structure in another embodiment of the present invention;

[0031] Figure 4 A schematic diagram of a transistor where the active layer does not have a conductive layer.

[0032] Figure 5 A schematic diagram showing the depletion layer capacitance when a positive voltage is applied to the conductive layer in a transistor.

[0033] Figure 6 A schematic diagram showing the depletion of layer capacitance when a negative voltage is applied to the conductive layer in a transistor.

[0034] Figure Labels

[0035] Active layer 10;

[0036] First conductive region 11; Second conductive region 12;

[0037] Semiconductor region 13;

[0038] Conductive layer 20;

[0039] Source 31; Drain 32; Gate 33; Insulating layer 34. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0042] The following is in conjunction with the appendix Figures 1 to 6 As shown, the transistors, display modules, display panels, and display devices provided in the embodiments of the present invention will be described in detail through specific embodiments and application scenarios.

[0043] like Figures 1 to 3 As shown, the transistor of this embodiment includes: an active layer 10, a conductive layer 20, a source 31, a drain 32, and a gate 33. The active layer 10 has a first conductive region 11 and a second conductive region 12, and a semiconductor region 13 located between the first conductive region 11 and the second conductive region 12. The first conductive region 11 and the second conductive region 12 may be located in the edge region of the active layer 10, and the semiconductor region 13 may be located in the center region of the active layer 10. The edge region may be arranged around the center region, and the first conductive region 11 and the second conductive region 12 may be symmetrically arranged about the semiconductor region 13.

[0044] The conductive layer 20 can be disposed on one side surface of the active layer 10. The conductive layer 20 and the first conductive region 11 can be disposed at intervals. The interval between the conductive layer 20 and the first conductive region 11 can be greater than or equal to 2 μm. For example, the interval between the conductive layer 20 and the first conductive region 11 can be 4 μm. The interval between the conductive layer 20 and the first conductive region 11 can be selected according to the actual situation. The interval between the conductive layer 20 and the first conductive region 11 can make the conductive layer 20 and the first conductive region 11 have good insulation and prevent breakdown between the conductive layer 20 and the first conductive region 11 when a voltage is applied. The conductive layer 20 and the second conductive region 12 can be spaced apart. The spacing between the conductive layer 20 and the second conductive region 12 can be greater than or equal to 2 μm. For example, the spacing between the conductive layer 20 and the second conductive region 12 can be 5 μm. The spacing between the conductive layer 20 and the second conductive region 12 can be selected according to the actual situation. Spacing the conductive layer 20 and the second conductive region 12 apart can make the conductive layer 20 and the second conductive region 12 have good insulation and prevent breakdown between the conductive layer 20 and the second conductive region 12 when voltage is applied.

[0045] The source 31 is electrically connected to the first conductive region 11, the drain 32 is electrically connected to the second conductive region 12, and the gate 33 is disposed on the other side of the active layer 10. An insulating layer 34 can be disposed between the gate 33 and the active layer 10, thereby insulating the gate 33 from the active layer 10. A first via and a second via can be disposed on the insulating layer 34. The source 31 and the first conductive region 11 can be electrically connected through the first via, and the drain 32 and the second conductive region 12 can be electrically connected through the second via. The insulating layer 34 can be selected from at least one of aluminum nitride, silicon nitride, silicon oxide, aluminum oxide, zirconium nitride, hafnium nitride, tantalum nitride, titanium oxide, titanium nitride, tin oxide, cerium oxide, silicon oxynitride (SiON), and lithium fluoride. For example, the insulating layer 34 can be selected from aluminum nitride, silicon nitride, silicon oxide, or aluminum oxide. The insulating layer 34 can include aluminum nitride and silicon nitride. The specific material and thickness of the insulating layer 34 can be selected according to the actual situation. The insulating layer 34 may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin and dinaphthalene-containing resin. For example, the insulating layer 34 may include acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin or cellulose resin. The insulating layer 34 may include acrylic resin, methacrylic resin and polyisoprene. The specific material of the insulating layer 34 can be selected according to the actual situation.

[0046] The active layer 10 may include at least one of indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), zinc tin indium oxide (IZTO), and indium gallium tin oxide (IGTO). For example, the active layer 10 may include indium gallium zinc oxide, indium gallium zinc tin oxide, or indium gallium tin oxide. The active layer 10 may include indium gallium tin oxide (IGTO) and indium zinc oxide (IZO). The specific type of oxide semiconductor material in the active layer 10 can be selected according to the actual situation. The conductive layer 20 may be a metal layer. The material of the conductive layer 20 may be made of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, or Cr and their mixtures, or it may be made of metal oxide materials with equivalent conductivity such as ITO, IZO, or IGZO. For example, the material of the conductive layer 20 may be Ag, Mg, or Al, or it may be a mixture of Ag, Al, and Ni. The specific material of the conductive layer 20 can be reasonably selected according to actual needs.

[0047] In the transistor of this embodiment, the active layer 10 has a first conductive region 11, a second conductive region 12, and a semiconductor region 13 located between the first conductive region 11 and the second conductive region 12. A conductive layer 20 is disposed on one side surface of the active layer 10, with the conductive layer 20 and the first conductive region 11 spaced apart, and the conductive layer 20 and the second conductive region 12 spaced apart. By disposing of the conductive layer 20 on one side surface of the active layer 10, a depletion layer capacitance can be formed, which can increase the subthreshold swing of the metal oxide TFT, reduce the sensitivity of OLED luminous brightness to voltage fluctuations, improve display uniformity, and enhance display effect.

[0048] In some embodiments, the orthographic projection of the conductive layer 20 onto the active layer 10 is spaced apart from the first conductive region 11, and the orthographic projection of the conductive layer 20 onto the active layer 10 is spaced apart from the second conductive region 12. In a direction parallel to the active layer 10, the conductive layer 20 is spaced apart from the first conductive region 11, and the conductive layer 20 is spaced apart from the second conductive region 12. This spaced-apart arrangement of the conductive layer 20 from the first conductive region 11 and the second conductive region 12 increases insulation, preventing breakdown between the conductive layer 20 and the conductive regions 11 and 12 when a voltage is applied. In a direction parallel to the active layer 10, the spacing between the conductive layer 20 and the first conductive region 11 and the spacing between the conductive layer 20 and the second conductive region 12 can be the same or different; for example, in a direction parallel to the active layer 10, the spacing between the conductive layer 20 and the first conductive region 11 and the spacing between the conductive layer 20 and the second conductive region 12 can be the same. In the direction parallel to the active layer 10, the spacing between the conductive layer 20 and the first conductive region 11 can be smaller than the spacing between the conductive layer 20 and the second conductive region 12. The specific spacing can be reasonably selected according to the actual situation.

[0049] In other embodiments, the orthographic projection of the conductive layer 20 onto the active layer 10 may be located within the semiconductor region 13, and the edge of the orthographic projection of the conductive layer 20 onto the active layer 10 may be spaced apart from the outer edge of the semiconductor region 13 to form a depletion layer capacitance in the semiconductor region 13 near the conductive layer 20, thereby increasing the subthreshold swing.

[0050] In an embodiment of the present invention, the first conductive region 11 and the second conductive region 12 may be symmetrically arranged about the conductive layer 20 to form a relatively uniform depletion layer capacitance, thereby increasing the subthreshold swing.

[0051] In some embodiments, one side surface of the active layer 10 may have a first surface, the conductive layer 20 may be disposed on the first surface, and the side surface of the conductive layer 20 near the active layer 10 may be a second surface. The first surface and the second surface may be disposed in parallel, both of which may be planar, and the first surface and the second surface may be in close contact to form a relatively uniform and stable depletion layer capacitance, thereby increasing the subthreshold swing.

[0052] According to some embodiments, there can be multiple conductive layers 20. These multiple conductive layers 20 can be spaced apart on one side surface of the active layer 10, or they can be uniformly spaced apart. The shapes and sizes of the multiple conductive layers 20 can be the same or different. For example, the shapes and sizes of the multiple conductive layers 20 can be the same, and all of them can be rectangular, circular, or elliptical. At least two of the multiple conductive layers 20 can have different shapes and sizes. For example, the shapes and sizes of the multiple conductive layers 20 can all be different. The shapes of the multiple conductive layers 20 can be selected from rectangular, triangular, circular, or elliptical, with at least one conductive layer 20 being rectangular and at least one conductive layer 20 being circular. By setting conductive layers 20 of different shapes and sizes in different regions, different depletion layer capacitances can be formed in different regions, allowing for the increase or adjustment of the subthreshold swing as needed.

[0053] In some embodiments of the present invention, the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the first conductive region 11 can be 2-6 μm. For example, the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the first conductive region 11 can be 2 μm, 4 μm, or 6 μm. The smaller the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the first conductive region 11, the lower the insulation between the conductive layer 20 and the first conductive region 11, and the easier it is for the conductive layer 20 and the first conductive region 11 to break down when voltage is applied. Conversely, the larger the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the first conductive region 11, the better the insulation between the conductive layer 20 and the first conductive region 11, and the less likely it is to break down when voltage is applied, ensuring a better insulation effect. However, this results in a larger space occupation. Therefore, the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the first conductive region 11 can be selected as 2-6 μm, which can ensure a good insulation effect without occupying too much space. The specific spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the first conductive region 11 can be reasonably selected according to the actual situation.

[0054] The spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the second conductive region 12 is 2-6 μm. For example, the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the second conductive region 12 can be 2 μm, 4 μm, or 6 μm. The smaller the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the second conductive region 12, the lower the insulation between the conductive layer 20 and the second conductive region 12, and the easier it is for the conductive layer 20 and the second conductive region 12 to break down when voltage is applied. Conversely, the larger the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the second conductive region 12, the better the insulation between the conductive layer 20 and the second conductive region 12, and the less likely it is to break down when voltage is applied, ensuring a good insulation effect. However, this can lead to a larger space requirement. Therefore, the spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the second conductive region 12 can be selected as 2-6 μm, which can ensure a good insulation effect without occupying too much space. The specific spacing between the orthographic projection of the conductive layer 20 on the active layer 10 and the second conductive region 12 can be reasonably selected according to the actual situation.

[0055] The conductive layer 20 can be disposed on one side surface of the active layer 10. The conductive layer 20 and the first conductive region 11 can be disposed at intervals. The conductive layer 20 and the first conductive region 11 can be disposed at intervals in the direction perpendicular to the active layer 10. The spacing between the conductive layer 20 and the first conductive region 11 in the direction perpendicular to the active layer 10 can be greater than or equal to 2 μm. For example, the spacing between the conductive layer 20 and the first conductive region 11 in the direction perpendicular to the active layer 10 can be 3 μm. The spacing between the conductive layer 20 and the first conductive region 11 in the direction perpendicular to the active layer 10 can be selected according to the actual situation. The conductive layer 20 can be disposed on one side surface of the active layer 10. The conductive layer 20 and the second conductive region 12 can be disposed alternately. The conductive layer 20 and the second conductive region 12 can be disposed alternately in the direction perpendicular to the active layer 10. The spacing between the conductive layer 20 and the second conductive region 12 in the direction perpendicular to the active layer 10 can be greater than or equal to 2 μm. For example, the spacing between the conductive layer 20 and the second conductive region 12 in the direction perpendicular to the active layer 10 can be 3 μm. The spacing between the conductive layer 20 and the second conductive region 12 in the direction perpendicular to the active layer 10 can be selected according to the actual situation.

[0056] The spacing between the conductive layer 20 and the first conductive region 11 can be the same as or different from the spacing between the conductive layer 20 and the second conductive region 12. For example, the spacing between the conductive layer 20 and the first conductive region 11 can be the same as the spacing between the conductive layer 20 and the second conductive region 12, and the first conductive region 11 and the second conductive region 12 can be symmetrically arranged about the conductive layer 20. The spacing between the conductive layer 20 and the first conductive region 11 can be smaller than the spacing between the conductive layer 20 and the second conductive region 12, and the specific spacing can be selected according to the actual situation.

[0057] In some embodiments, the thickness of the conductive layer 20 can be 50-100 nm. For example, the thickness of the conductive layer 20 can be 50 nm, 80 nm or 100 nm, and the thickness of the conductive layer 20 can be reasonably selected according to the actual situation.

[0058] Optionally, the thickness of the active layer 10 can be 100-400 nm. For example, the thickness of the active layer 10 can be 100 nm, 230 nm or 400 nm, and the thickness of the active layer 10 can be reasonably selected according to the actual situation.

[0059] In some embodiments, the active layer 10 may include an oxide semiconductor material layer. The oxide semiconductor material may include at least one of indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), zinc tin indium oxide (IZTO), indium gallium tin oxide (IGTO), and indium zinc oxide (IZO). For example, the oxide semiconductor material may be indium gallium zinc oxide, indium gallium zinc tin oxide, or indium gallium tin oxide. The oxide semiconductor material may be indium gallium tin oxide (IGTO) or indium zinc oxide (IZO). The specific type of oxide semiconductor material may be selected according to the actual situation.

[0060] In embodiments of the present invention, such as Figures 1 to 3 As shown, a conductive layer 20 is disposed on one side surface of the active layer 10. An accumulation layer a can be formed on the side away from the conductive layer 20, and a depletion layer capacitor b can be formed on the side closer to the conductive layer 20. Figure 4 As shown, the active layer in the transistor does not have a conductive layer. Only an accumulation layer a is formed on the upper surface of the active layer 10, and no depletion layer capacitor b is formed.

[0061] like Figure 4 As shown, when the transistor is turned on, an accumulation layer a is formed, but a depletion layer capacitance cannot be formed.

[0062] The subthreshold swing (ss) of a metal oxide TFT can be expressed as:

[0063]

[0064] Where k represents Boltzmann constant, T represents Kelvin temperature, q represents the charge of an electron, CD represents depletion layer capacitance, Cit represents the equivalent capacitance of interface defects, and Cox represents the capacitance per unit area of ​​gate insulating layer. Figure 4 In the transistor shown, CD is essentially 0. Figures 1 to 3 In the transistor shown, since a conductive layer 20 is disposed on one side of the active layer 10, a depletion layer capacitance b can be formed on the side near the conductive layer 20. The depletion layer capacitance b can increase CD, thereby increasing the subthreshold swing, reducing the sensitivity of the OLED's luminous intensity to voltage fluctuations, improving display uniformity, and enhancing the display effect. Figure 5 As shown, when a positive voltage is applied to the conductive layer in a transistor, the width of the depletion layer capacitance is narrower, and the depletion layer capacitance is smaller. For example... Figure 6 As shown, when a negative voltage is applied to the conductive layer in the transistor, the width of the depletion layer capacitance increases, and there is no conduction between the source 31, drain 32 and the conductive layer 20. The larger depletion layer capacitance can increase CD and increase the subthreshold swing.

[0065] The display module of this invention includes the transistor described in the above embodiments. The display module having the transistor described in the above embodiments can form a depletion layer capacitor by forming a conductive layer 20 on one side surface of the active layer 10, which can increase the subthreshold swing of the metal oxide TFT, reduce the sensitivity of OLED brightness to voltage fluctuations, improve display uniformity, and enhance display performance.

[0066] In some embodiments, the display module may further include a light-emitting unit, wherein the transistor is used to drive the light-emitting unit to emit light. By driving the light-emitting unit to emit light with a transistor, the sensitivity of OLED brightness to voltage fluctuations can be reduced, the uniformity of the display can be improved, and the display effect can be enhanced.

[0067] The display panel of this invention includes the display module described in the above embodiments. The display panel having the display module described in the above embodiments, by driving the light-emitting unit to emit light through transistors, can reduce the sensitivity of OLED brightness to voltage fluctuations, improve display uniformity, and enhance display performance.

[0068] The display device of this invention includes the display panel described in the above embodiments. The display device having the display panel described in the above embodiments can improve display uniformity and display effect.

[0069] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A transistor, characterized in that, include: An active layer having a first conductive region and a second conductive region and a semiconductor region located between the first conductive region and the second conductive region; A conductive layer is disposed on one side surface of the active layer, the conductive layer and the first conductive region are spaced apart, and the conductive layer and the second conductive region are spaced apart; the conductive layer is disposed on one side surface of the active layer to form a depletion layer capacitor; The source electrode electrically connected to the first conductive region; The drain electrode electrically connected to the second conductive region; A gate, wherein the gate is disposed on the other side of the active layer; The orthographic projection of the conductive layer on the active layer is spaced apart from the first conductive region, and the orthographic projection of the conductive layer on the active layer is spaced apart from the second conductive region.

2. The transistor according to claim 1, characterized in that, The orthogonal projection of the conductive layer onto the active layer lies within the semiconductor region.

3. The transistor according to claim 2, characterized in that, The first conductive region and the second conductive region are symmetrically arranged about the conductive layer.

4. The transistor according to claim 3, characterized in that, The active layer has a first surface on one side, the conductive layer is disposed on the first surface, and the conductive layer has a second surface on the side of the active layer closer to the active layer. The first surface and the second surface are arranged parallel to each other.

5. The transistor according to claim 1, characterized in that, The number of conductive layers is multiple, and the multiple conductive layers are disposed at intervals on one side surface of the active layer.

6. The transistor according to claim 1, characterized in that, The spacing between the orthographic projection of the conductive layer onto the active layer and the first conductive region is 2-6 μm; and / or The spacing between the orthographic projection of the conductive layer onto the active layer and the second conductive region is 2-6 μm; and / or The thickness of the conductive layer is 50-100 nm; and / or The thickness of the active layer is 100-400 nm; and / or The active layer includes an oxide semiconductor material layer.

7. A display module, characterized in that, include: The transistor according to any one of claims 1-6.

8. A display panel, characterized in that, include: The display module as described in claim 7.

9. A display device, characterized in that, Includes the display panel as described in claim 8.

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