High-efficiency and safe modulation method, modulator and system for low-cost three-level inverter

Abstract

The present disclosure relates to the technical field of power electronic power conversion, and proposes an efficient and safe modulation method, modulator and system for a low-cost three-level inverter. When the reference voltage vector is located in the outer area of ​​each sector, the basic voltage vector switch state combination is limited, and a seven-segment clamped P-type and N-type switch sequence is designed; when the reference voltage vector is located in the inner area of ​​each sector, the basic voltage vector switch state combination is limited, and a five-segment clamped P-type and N-type switch sequence is designed; the voltage deviation of the two capacitors at the DC side is sent to the hysteresis comparator, the output value of the hysteresis comparator is set, and the switch sequence is further optimized to realize the midpoint voltage balance control function. The method of the present invention can effectively reduce the switching loss of the power device of the low-cost three-level inverter system, and when the midpoint voltage is offset due to abnormal factors, the midpoint voltage balance recovery can be realized, thereby improving the system operation efficiency and safety.

Description

Technical Field

[0001] The present disclosure relates to the technical field related to power electronic power conversion, and in particular to an efficient and safe modulation method, a modulator and a system for a low-cost three-level inverter. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.

[0003] The three-level inverter has significant advantages such as low voltage stress of power devices, good output waveform quality, low harmonic content, and small filter size. It is widely used in renewable energy generation, battery energy storage, power quality management and other fields. Diode clamped and T-type three-level inverters are the two most commonly used three-level inverter topologies, but both require a large number of power devices, which inevitably increases system cost and size.

[0004] In order to further reduce the number of power devices, reduce system size and cost, T. Ngo and other scholars from Auckland University of Technology in New Zealand proposed a low-cost (Reduced Switch Count, RSC) three-level inverter topology, which contains ten power devices and can obtain multi-level output waveforms without the use of clamping diodes.

[0005] The inventor found in the study that, on the one hand, the input end of the three-level inverter system is connected to new energy power generation components such as photovoltaic arrays, which has inherent limitations such as randomness, intermittency, and volatility, resulting in large power fluctuations and a wide range of input voltage variations. Therefore, reducing the loss of the power devices of the three-level inverter system itself is the key to improving the power generation efficiency and power generation of the system. On the other hand, due to the characteristics of the topological structure itself, the three-phase output voltage of the low-cost three-level inverter can only contain two types of states at most. In other words, the circuit topology cannot generate a neutral vector, which makes the traditional space vector modulation method used for diode clamped and T-type three-level inverters unable to be directly applied. At present, domestic and foreign scholars have proposed space vector modulation methods suitable for low-cost three-level inverters, but they are essentially continuous pulse width modulation methods, with a large number of switching times, which increases the switching loss of power devices and reduces the operating efficiency of the system. Therefore, an efficient and safe modulation method suitable for low-cost three-level inverters is urgently needed. Summary of the invention

[0006] In order to solve the above problems, the present disclosure proposes a low-cost three-level inverter with efficient and safe modulation method, modulator and system, which can effectively reduce the switching loss of power devices, improve the system operation efficiency, ensure the balance of midpoint voltage, and significantly improve the system operation safety.

[0007] In order to achieve the above objectives, the present disclosure adopts the following technical solutions:

[0008] One or more embodiments provide a high-efficiency and safe modulation method for a low-cost three-level inverter, comprising the following steps:

[0009] Determine the sector and region where the reference voltage vector is located, select basic voltage vectors to synthesize the reference voltage vector, and solve to obtain the duty cycle of each basic voltage vector;

[0010] In order to achieve switching loss suppression and midpoint voltage balance control, the switch state corresponding to the small vector is limited to obtain the basic voltage vector switch state combination;

[0011] According to the obtained basic voltage vector switch state combination, a symmetrical clamped P-type switch sequence and a symmetrical clamped N-type switch sequence are designed respectively;

[0012] According to the voltage difference between the two ends of the DC side capacitor, the output value of the hysteresis comparator is determined;

[0013] According to the region where the reference voltage vector is located and the output of the hysteresis comparator, the clamping switching sequence is optimally selected;

[0014] The corresponding PWM drive signal is generated according to the optimized switching sequence to control the opening and closing of the power switch tube.

[0015] One or more embodiments provide a high efficiency and safety modulator for a low cost three-level inverter, including:

[0016] Basic voltage vector selection and duty cycle calculation module: configured to determine the sector and region where the reference voltage vector is located, select the basic voltage vector to synthesize the reference voltage vector, and solve to obtain the duty cycle of each basic voltage vector;

[0017] A basic voltage vector switch state combination limiting module is configured to limit the switch state corresponding to the small vector to obtain a basic voltage vector switch state combination for the purpose of achieving switch loss suppression and midpoint voltage balance control;

[0018] A clamped switch sequence determination module: configured to design a symmetrical clamped P-type switch sequence and a clamped N-type switch sequence according to the obtained basic voltage vector switch state combination;

[0019] A hysteresis comparator control module: configured to determine an output value of a set hysteresis comparator according to a voltage difference across the DC link capacitor;

[0020] A switch sequence optimization selection module: configured to optimize and select a clamped switch sequence according to the region where the reference voltage vector is located and the output of the hysteresis comparator;

[0021] PWM drive signal conversion module: configured to generate corresponding PWM drive signals according to the optimized switching sequence to control the on and off of the power switch tube.

[0022] One or more embodiments provide a high-efficiency and safe modulation system for a three-level inverter, using the high-efficiency and safe modulator for the low-cost three-level inverter described above.

[0023] An electronic device comprises a memory and a processor, and computer instructions stored in the memory and executed on the processor. When the computer instructions are executed by the processor, the steps described in the above method are completed.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] (1) The disclosed method can obtain a multi-level output voltage waveform and improve the quality of the output voltage and current waveforms.

[0026] (2) The clamping switch sequence designed by the disclosed method has a symmetrical characteristic and can reduce the harmonic content in the output waveform.

[0027] (3) The disclosed method can effectively reduce the switching loss of power devices in a low-cost three-level inverter system and improve the system operation efficiency through the clamped switching sequence design.

[0028] (4) The method disclosed in the present invention realizes the active control function of the midpoint balance through the hysteresis comparator. When abnormal factors cause the midpoint voltage to shift, the method disclosed in the present invention can restore the balance of the midpoint voltage, thereby improving the safety of system operation.

[0029] The advantages of the present disclosure and the advantages of additional aspects will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings constituting a part of the present disclosure are used to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and the description thereof are used to explain the present disclosure but do not constitute a limitation of the present disclosure.

[0031] Figure 1 is a circuit topology diagram of a low-cost three-level inverter according to Embodiment 1 of the present disclosure;

[0032] Figure 2is a spatial vector diagram of a low-cost three-level inverter according to Embodiment 1 of the present disclosure;

[0033] Figure 3 is a control block diagram of a modulation method according to Embodiment 1 of the present disclosure;

[0034] FIG4( a ) is a waveform diagram of a system output using the modulation method of the present disclosure under the first simulation condition of the embodiment 1 of the present disclosure;

[0035] FIG4( b ) is a driving signal waveform diagram of a power device using the modulation method of the present disclosure under the first simulation condition of Example 1 of the present disclosure;

[0036] FIG5( a ) is a waveform diagram of a system output using a conventional modulation method under the first simulation condition of Embodiment 1 of the present disclosure;

[0037] FIG5( b ) is a driving signal waveform diagram of a power device using a conventional modulation method under the first simulation condition of Example 1 of the present disclosure;

[0038] FIG6( a ) is a waveform diagram of a system output using the modulation method of the present disclosure under the second simulation condition of Example 1 of the present disclosure;

[0039] FIG6( b ) is a driving signal waveform diagram of a power device using the modulation method of the present disclosure under the second simulation condition of Example 1 of the present disclosure;

[0040] FIG. 7( a ) is a waveform diagram of a system output using a conventional modulation method under the second simulation condition of Embodiment 1 of the present disclosure;

[0041] FIG. 7( b ) is a driving signal waveform diagram of a power device using a conventional modulation method under the second simulation condition of Example 1 of the present disclosure;

[0042] Figure 8 is a waveform diagram of a dynamic process of midpoint voltage balance control using the modulation method of the present disclosure under the first simulation condition of the embodiment 1 of the present disclosure;

[0043] Fig. 9 It is a waveform diagram of the dynamic process of midpoint voltage balance control using the modulation method of the present disclosure under the second simulation condition of Example 1 of the present disclosure. DETAILED DESCRIPTION

[0044] The present disclosure is further described below in conjunction with the accompanying drawings and embodiments.

[0045] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present disclosure belongs.

[0046] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof. It should be noted that, in the absence of conflict, the various embodiments in the present disclosure and the features in the embodiments can be combined with each other. The embodiments will be described in detail below in conjunction with the accompanying drawings.

[0047] Example 1

[0048] In the technical solutions disclosed in one or more embodiments, Figure 1-Figure 9 As shown, an efficient and safe modulation method for a low-cost three-level inverter is applicable to a low-cost three-level inverter, can obtain a multi-level output voltage waveform, and improve the quality of the output voltage and current waveforms.

[0049] Figure 1 The circuit topology diagram of the low-cost three-level inverter includes the following components: photovoltaic array (PV), two DC side support capacitors (C 1 and C 2 ), ten power switch tubes (S 1 , S 2 , …, S 10 ), output side filter. Among them, the values ​​of the two DC side support capacitors are equal, and the connection point of the two is used as the DC side neutral point (i.e. point O 1 ). 1 , S 2 , S 3 , S 4 The four power switch tubes are connected in series to form a common switch unit. 5 , S 6 The first group of independent switch units is formed by connecting them in series, S 7 , S 8 By connecting in series to form a second group of independent switch units, S 9 , S 10 The third group of independent switch units is formed by connecting in series. 2 and S 3 The connection point is connected to the neutral point of the DC side. The inductor is used as the output side filter. The pulse width modulation (PWM) method can be used to control the opening and closing of each power switch tube.

[0050] Optionally, the power switch tube can be implemented by any controllable power electronic switch tube, specifically, an insulated gate bipolar transistor (IGBT) can be used; other forms of transistors can also be used to implement it.

[0051] The low-cost three-level inverter includes three switching states: [P], [O] and [N]. Select the DC side neutral point (i.e. Figure 1 Point O 1 ) as the reference point. When the switch state is [P], the bridge arm output voltage is +V dc / 2; when the switch state is [O], the bridge arm output voltage is 0; when the switch state is [N], the bridge arm output voltage is -V dc / 2.

[0052] The basic voltage vector, switch state and the switch tube turned on of the low-cost three-level inverter are shown in Table 1. The space vector diagram is shown in Figure 2 As shown, it can be seen that the entire space vector diagram is divided into six sectors (sector 1-sector 6). Each sector is further divided into two small areas (area A and area B), where the outer area is defined as area A and the inner area is defined as area B.

[0053] Figure 3 The control block diagram of the method of this embodiment. A vector control strategy based on grid voltage orientation is adopted to realize the grid-connected control function of a low-cost three-level inverter system. Among them, the phase-locked loop (PLL) is used to obtain the grid voltage phase, and the proportional integral (PI) regulator in the synchronous rotating coordinate system is used to realize the grid-connected current control function. The output of the active current and reactive current PI regulators is sent to the efficient and safe modulation method system of this embodiment after dq / abc coordinate transformation.

[0054] Table 1 Basic voltage vectors and switching states of low-cost three-level inverter

[0055]

[0056] The embodiment of the present disclosure provides a high-efficiency and safe modulation method for a low-cost three-level inverter, comprising the following steps:

[0057] (1) Selection of basic voltage vectors and calculation of duty cycle: Determine the sector and region where the reference voltage vector is located, select the basic voltage vectors to synthesize the reference voltage vector, and solve for the duty cycle of each basic voltage vector;

[0058] In a specific example, the basic voltage vector selection and duty cycle calculation steps are as follows:

[0059] When the reference voltage vector is located in the outer area of ​​each sector, the four closest basic voltage vectors are selected to synthesize the reference voltage vector, and an indirect calculation method is designed to solve the duty cycle of each basic voltage vector. When the reference voltage vector is located in the inner area of ​​each sector, the three closest basic voltage vectors are selected to synthesize the reference voltage vector, and a direct calculation method is designed to solve the duty cycle of each basic voltage vector.

[0060] An optional, indirect calculation method uses the gh coordinate system to set the small vector duty cycle distribution factor, and uses the small vector duty cycle distribution factor to represent the duty cycles of the four selected basic voltage vectors. According to the duty cycle values ​​of the four basic voltage vectors must be greater than 0 and less than 1, the upper and lower limits of the small vector duty cycle distribution factor are obtained, and the small vector duty cycle distribution factor is taken as the arithmetic mean of its upper and lower limits, and substituted into the duty cycle expression of the four basic voltage vectors to obtain the duty cycle of each basic voltage vector.

[0061] Among them, the gh coordinate system is a non-orthogonal coordinate system. In the gh coordinate system, the g axis coincides with the α axis in the α-β coordinate system, and the h axis is obtained by rotating the g axis counterclockwise by 60°.

[0062] Alternatively, a direct calculation method uses the GH coordinate system to directly obtain the duty cycle of the three basic voltage vectors by solving the volt-second balance equation.

[0063] Without loss of generality, the following takes sector 1 as an example to explain in detail the basic voltage vector selection and duty cycle calculation method.

[0064] 1) When the reference voltage vector is located in the outer region (i.e., region A) within sector 1, see Figure 2 , select the large vector V L1 , Large Vector V L2 , small vector V S1 , small vector V S2 The synthetic reference voltage vector, volt-second balance equation is:

[0065]

[0066] Among them, V r is the reference voltage vector, d L1 ,d L2 ,d S1 and d S2 They are large vectors V L1 , Large Vector V L2 , small vector V S1 , small vector V S2 duty cycle.

[0067] To avoid complex trigonometric calculations, the gh coordinate system (see Figure 2 ), design an indirect calculation method, and solve the duty cycle of each basic voltage vector as:

[0068]

[0069] Among them, V rg and V rh are the g-axis and h-axis components of the reference voltage vector, V dc is the DC bus voltage, β is the small vector duty cycle allocation factor, d s12 is a small vector V S1 and V S2 The sum of the duty cycles can be expressed as:

[0070]

[0071] The small vector duty cycle allocation factor β can be taken as the arithmetic average of its upper and lower limits:

[0072]

[0073] Among them, the upper limit value and the lower limit value of the small vector duty cycle allocation factor β are expressed as formula (5) and formula (6) respectively.

[0074]

[0075]

[0076] Substituting the small vector duty cycle allocation factor given by equation (4) into equation (2), we can get the large vector V L1 , Large Vector V L2 , small vector V S1 , small vector V S2 duty cycle.

[0077] 2) When the reference voltage vector is located in the outer region (i.e., region B) within sector 1, see Figure 2 , select the three closest basic voltage vectors (including the small vector V S1 , small vector V S2 , zero vector V Z ) synthesizes the reference voltage vector, and the volt-second balance equation is:

[0078]

[0079] To avoid complex trigonometric calculations, the gh coordinate system (see Figure 2 ). A direct calculation method is designed to solve the duty cycle of each basic voltage vector as:

[0080]

[0081] When the reference voltage vector is located in sectors other than sector 1, the basic voltage vector selection and duty cycle calculation steps can be obtained by utilizing the symmetry of the space vector diagram, which will not be repeated here.

[0082] (2) Basic voltage vector switch state combination limitation: According to the sector and region where the reference voltage vector is located, the switch state corresponding to the small vector is limited to obtain the basic voltage vector switch state combination for the purpose of achieving switching loss suppression and midpoint voltage balance control;

[0083] Specifically, when the reference voltage vector is located in the outer area of ​​each sector, the two small vectors used to synthesize the reference voltage vector are defined as P-type small vectors, which together with the two large vectors constitute a P-type switch state combination; the two small vectors used to synthesize the reference voltage vector are defined as N-type small vectors, which together with the two large vectors constitute an N-type switch state combination;

[0084] When the reference voltage vector is located in the inner area of ​​each sector, the two small vectors used to synthesize the reference voltage vector are limited to P-type small vectors, and the zero vector used to synthesize the reference voltage vector is limited to [PPP], which together constitute a P-type switching state combination; the two small vectors used to synthesize the reference voltage vector are limited to N-type small vectors, and the zero vector used to synthesize the reference voltage vector is limited to [NNN], which together constitute an N-type switching state combination.

[0085] like Figure 2 The sector numbering method shown in the figure, the basic voltage vector switch state combination limitation rules in different sectors and regions are as follows:

[0086] When the reference voltage vector is located in the outer region of sector 1, the P-type switch state combinations are: POO, PPO, PPN, PNN, and the N-type switch state combinations are: OON, ONN, PNN, PPN;

[0087] When the reference voltage vector is located in the inner region of sector 1, the P-type switch state combinations are: POO, PPO, PPP, and the N-type switch state combinations are: OON, ONN, NNN;

[0088] When the reference voltage vector is located in the outer region of sector 2, the P-type switch state combinations are: OPO, PPO, PPN, NPN, and the N-type switch state combinations are: OON, NON, NPN, PPN;

[0089] When the reference voltage vector is located in the inner region of sector 2, the P-type switch state combinations are: OPO, PPO, PPP, and the N-type switch state combinations are: OON, NON, NNN;

[0090] When the reference voltage vector is located in the outer region of sector 3, the P-type switch state combinations are: OPO, OPP, NPP, NPN, and the N-type switch state combinations are: NOO, NON, NPN, NPP;

[0091] When the reference voltage vector is located in the inner region of sector 3, the P-type switch state combinations are: OPO, OPP, PPP, and the N-type switch state combinations are: NOO, NON, NNN;

[0092] When the reference voltage vector is located in the outer region of sector 4, the P-type switch state combinations are: OOP, OPP, NPP, NNP, and the N-type switch state combinations are: NOO, NNO, NNP, NPP;

[0093] When the reference voltage vector is located in the inner region of sector 4, the P-type switch state combinations are: OOP, OPP, PPP, and the N-type switch state combinations are: NOO, NNO, NNN;

[0094] When the reference voltage vector is located in the outer region of sector 5, the P-type switch state combinations are: OOP, POP, PNP, NNP, and the N-type switch state combinations are: ONO, NNO, NNP, PNP;

[0095] When the reference voltage vector is located in the inner region of sector 5, the P-type switch state combinations are: OOP, POP, PPP, and the N-type switch state combinations are: ONO, NNO, NNN;

[0096] When the reference voltage vector is located in the outer region of sector 6, the P-type switch state combinations are: POO, POP, PNP, PNN, and the N-type switch state combinations are: ONO, ONN, PNN, PNP;

[0097] When the reference voltage vector is located in the inner region of sector 6, the P-type switch state combinations are: POO, POP, PPP, and the N-type switch state combinations are: ONO, ONN, NNN.

[0098] (3) Clamped switch sequence design: Based on the obtained basic voltage vector switch state combination, a symmetrical clamped P-type switch sequence and a clamped N-type switch sequence are designed respectively;

[0099] Specifically, in the clamped P-type switch sequence, there is one phase that is clamped to the P state within the switching cycle; in the clamped N-type switch sequence, there is one phase that is clamped to the N state within the switching cycle.

[0100] Specifically, a clamped switch sequence is designed based on the basic voltage vector switch state combination in step (2). When the reference voltage vector is located in the outer region of each sector, a seven-segment clamped P-type switch sequence and a seven-segment clamped N-type switch sequence are designed to reduce the switching loss of the power device; when the reference voltage vector is located in the inner region of each sector, a five-segment clamped P-type switch sequence and a five-segment clamped N-type switch sequence are designed to reduce the switching loss of the power device. Among them, in the seven-segment clamped P-type switch sequence and the five-segment clamped P-type switch sequence, there is a phase that is clamped to the P state within the switching cycle; in the seven-segment clamped N-type switch sequence and the five-segment clamped N-type switch sequence, there is a phase that is clamped to the N state within the switching cycle.

[0101] The clamping switch sequence design in different sectors and regions is as follows:

[0102] When the reference voltage vector is located in the outer region of sector 1, the seven-segment clamped P-type switch sequence is designed as: POO-PPO-PPN-PNN-PPN-PPO-POO, and the seven-segment clamped N-type switch sequence is designed as: OON-ONN-PNN-PPN-PNN-ONN-OON;

[0103] When the reference voltage vector is located in the inner region of sector 1, the five-stage clamped P-type switch sequence is designed as: POO-PPO-PPP-PPO-POO, and the five-stage clamped N-type switch sequence is designed as: OON-ONN-NNN-ONN-OON;

[0104] When the reference voltage vector is located in the outer region of sector 2, the seven-segment clamped P-type switch sequence is designed as: OPO-PPO-PPN-NPN-PPN-PPO-OPO, and the seven-segment clamped N-type switch sequence is designed as: OON-NON-NPN-PPN-NPN-NON-OON;

[0105] When the reference voltage vector is located in the inner region of sector 2, the five-stage clamped P-type switch sequence is designed as: OPO-PPO-PPP-PPO-OPO, and the five-stage clamped N-type switch sequence is designed as: OON-NON-NNN-NON-OON;

[0106] When the reference voltage vector is located in the outer region of sector 3, the seven-segment clamped P-type switch sequence is designed as: OPO-OPP-NPP-NPN-NPP-OPP-OPO, and the seven-segment clamped N-type switch sequence is designed as: NOO-NON-NPN-NPP-NPN-NON-NOO;

[0107] When the reference voltage vector is located in the inner region of sector 3, the five-stage clamped P-type switch sequence is designed as: OPO-OPP-PPP-OPP-OPO, and the five-stage clamped N-type switch sequence is designed as: NOO-NON-NNN-NON-NOO;

[0108] When the reference voltage vector is located in the outer region of sector 4, the seven-segment clamped P-type switch sequence is designed as: OOP-OPP-NPP-NNP-NPP-OPP-OOP, and the seven-segment clamped N-type switch sequence is designed as: NOO-NNO-NNP-NPP-NNP-NNO-NOO;

[0109] When the reference voltage vector is located in the inner region of sector 4, the five-stage clamped P-type switch sequence is designed as: OOP-OPP-PPP-OPP-OOP, and the five-stage clamped N-type switch sequence is designed as: NOO-NNO-NNN-NNO-NOO;

[0110] When the reference voltage vector is located in the outer region of sector 5, the seven-segment clamped P-type switch sequence is designed as: OOP-POP-PNP-NNP-PNP-POP-OOP, and the seven-segment clamped N-type switch sequence is designed as: ONO-NNO-NNP-PNP-NNP-NNO-ONO;

[0111] When the reference voltage vector is located in the inner region of sector 5, the five-stage clamped P-type switch sequence is designed as: OOP-POP-PPP-POP-OOP, and the five-stage clamped N-type switch sequence is designed as: ONO-NNO-NNN-NNO-ONO;

[0112] When the reference voltage vector is located in the outer region of sector 6, the seven-segment clamped P-type switch sequence is designed as: POO-POP-PNP-PNN-PNP-POP-POO, and the seven-segment clamped N-type switch sequence is designed as: ONO-ONN-PNN-PNP-PNN-ONN-ONO;

[0113] When the reference voltage vector is located in the inner area of ​​sector 6, the five-stage clamped P-type switch sequence is designed to be: POO-POP-PPP-POP-POO, and the five-stage clamped N-type switch sequence is designed to be: ONO-ONN-NNN-ONN-ONO.

[0114] The clamping switch sequence designed by the method of this embodiment has a symmetrical characteristic and can reduce the harmonic content in the output waveform.

[0115] (4) Hysteresis comparator output value setting: According to the DC side capacitor C 1 and C 2 The voltage difference between the two ends determines the output value of the hysteresis comparator.

[0116] In order to realize the midpoint voltage balance control function, the DC side capacitor C is sampled. 1 and C 2 The voltage across the two capacitors is used to calculate the voltage deviation between the two capacitors.

[0117] ΔV NP =V C1 -V C2 (9)

[0118] Among them, V C1 and V C2 They are the DC side capacitors C 1 and C 2 The voltage across both ends.

[0119] The capacitor voltage deviation (ΔV NP ) is sent to a hysteresis comparator, and the method for setting the output value of the hysteresis comparator is: when the capacitor voltage deviation is greater than the upper threshold of the hysteresis comparator, the output value of the hysteresis comparator is 1; when the capacitor voltage deviation is less than the lower threshold of the hysteresis comparator, the output value of the hysteresis comparator is 0; when the capacitor voltage deviation is between the lower threshold and the upper threshold of the hysteresis comparator, the output value of the hysteresis comparator remains unchanged.

[0120] (5) Optimal selection of switching sequence: The switching sequence is optimized based on the region where the reference voltage vector is located and the output of the hysteresis comparator.

[0121] Select the corresponding switch sequence according to the output value of the hysteresis comparator. The specific optimization selection method is:

[0122] 1) When the reference voltage vector is located in the outer region of each sector and the output value of the hysteresis comparator is 1, a seven-segment clamped P-type switch sequence is selected;

[0123] 2) When the reference voltage vector is located in the inner region of each sector and the output value of the hysteresis comparator is 1, a five-stage clamped P-type switch sequence is selected;

[0124] 3) When the reference voltage vector is located in the outer region of each sector and the output value of the hysteresis comparator is 0, a seven-segment clamped N-type switch sequence is selected;

[0125] 4) When the reference voltage vector is located in the inner region of each sector and the output value of the hysteresis comparator is 0, a five-stage clamped N-type switch sequence is selected.

[0126] The method of this embodiment optimizes the switching sequence by setting a hysteresis comparator, thereby realizing the active control function of the midpoint balance. When an abnormal factor causes the midpoint voltage to shift, the midpoint voltage balance can be restored, thereby improving the safety of system operation.

[0127] (6) PWM drive signal conversion: Generate the corresponding PWM drive signal according to the optimized switching sequence to control the opening and closing of the power switch tube.

[0128] Specifically, the optimized selected switching sequence is converted into a PWM drive signal of a power device to control the operation of a low-cost three-level inverter system.

[0129] The method of the present embodiment described above can obtain a multi-level output voltage waveform, thereby improving the quality of the output voltage and current waveforms; and can effectively reduce the switching losses of power devices in a low-cost three-level inverter system, thereby improving the operating efficiency of the system.

[0130] In order to illustrate the effect of the method of this embodiment, a simulation experiment was carried out, as follows:

[0131] FIG4(a) is a waveform diagram of the system output when the DC voltage is 340V and the effective value of the grid voltage is 110V using the modulation method of this embodiment, including the phase voltage (v ao )、Line voltage(v ab )、three-phase current (i a 、i b 、i c ) and the DC link capacitor voltage (V C1 、V C2 4(b) is a waveform diagram of the driving signal of the power device when the modulation method of this embodiment is adopted, the DC voltage is 340V, and the effective value of the grid voltage is 110V, including the power device S 1 The driving signal (PWM-1), S 2 The driving signal (PWM-2) and S 5 The driving signal (PWM-5) of the power device S 1 , S 2 and S 5 The driving signal has a partial clamping interval and no switching action occurs, so that the phase voltage waveform has a clamping characteristic, thereby reducing the switching loss of the power device; the line voltage is a five-level waveform, which shows that the proposed method can realize the multi-level output function; the output current is a three-phase symmetrical sinusoidal waveform; the voltages across the two capacitors on the DC side are equal, and the fluctuation value is very small, which shows that the proposed method can effectively control the midpoint voltage balance.

[0132] Figure 5(a) shows the system output waveform when the traditional method is used, the DC voltage is 340V, and the effective value of the grid voltage is 110V, including the phase voltage (v ao )、Line voltage(v ab )、three-phase current (i a 、i b 、i c ) and the DC link capacitor voltage (VC1 、V C2 ). Figure 5(b) shows the driving signal waveform of the power device when the traditional method is used, the DC voltage is 340V, and the effective value of the grid voltage is 110V, including the power device S 1 The driving signal (PWM-1), S 2 The driving signal (PWM-2) and S 5 The driving signal (PWM-5) of the power device S 1 and S 2 There is no clamping interval for the driving signal and switching action occurs continuously, which increases the switching loss of the power device and reduces the system operation efficiency.

[0133] FIG6(a) is a waveform diagram of the system output when the modulation method of this embodiment is used, the DC voltage is 340V, and the effective value of the grid voltage is 55V, including the phase voltage (v ao )、Line voltage(v ab )、three-phase current (i a 、i b 、i c ) and the DC link capacitor voltage (V C1 、V C2 6(b) is a waveform diagram of the driving signal of the power device when the modulation method of this embodiment is adopted, the DC voltage is 340V, and the effective value of the grid voltage is 55V, including the power device S 1 The driving signal (PWM-1), S 2 The driving signal (PWM-2) and S 5 It can be seen that when the DC power supply remains unchanged and the grid voltage decreases, the system operation modulation degree decreases. At this time, the modulation method of this embodiment can still achieve the function of suppressing the switching loss of the power device. Specifically, the power device S 1 , S 2 and S 5 There is a partial clamping interval in the driving signal without switching action, and the phase voltage waveform has a clamping characteristic, thereby reducing the switching loss of the power device.

[0134] Figure 7(a) shows the system output waveform when the traditional method is used, the DC voltage is 340V, and the effective value of the grid voltage is 55V, including the phase voltage (v ao )、Line voltage(v ab )、three-phase current (i a 、i b 、i c ) and the DC link capacitor voltage (V C1 、V C2). Figure 7(b) shows the driving signal waveform of the power device when the DC voltage is 340V and the effective value of the grid voltage is 55V using the traditional method, including the power device S 1 The driving signal (PWM-1), S 2 The driving signal (PWM-2) and S 5 Obviously, the power device S 1 and S 2 There is no clamping interval for the driving signal, and switching action continues to occur, making it impossible to suppress switching losses.

[0135] Figure 8 The waveform diagram of the dynamic process of the midpoint voltage balance control when the modulation method of this embodiment is used, the DC voltage is 340V, and the effective value of the grid voltage is 110V, including the phase voltage (v ao )、Line voltage(v ab )、three-phase current (i a 、i b 、i c ) and the DC link capacitor voltage (V C1 、V C2 ). When the running time is between 0.6s and 0.61s, the midpoint voltage balance control function is disabled; when the running time is before 0.6s and after 0.61s, the midpoint voltage balance control function is enabled. It can be seen that: when the midpoint voltage balance control function is disabled, the DC side capacitor voltage is significantly offset; when the midpoint voltage balance control function is enabled, the voltages across the two capacitors on the DC side are equal again, which shows that the method of the present invention can achieve midpoint voltage balance recovery.

[0136] Fig. 9 The waveform diagram of the dynamic process of the midpoint voltage balance control when the modulation method of this embodiment is used, the DC voltage is 340V, and the effective value of the grid voltage is 55V, including the phase voltage (v ao )、Line voltage(v ab )、three-phase current (i a 、i b 、i c ) and the DC link capacitor voltage (V C1 、V C2 ). When the running time is between 0.6s and 0.61s, the midpoint voltage balance control function is disabled; when the running time is before 0.6s and after 0.61s, the midpoint voltage balance control function is enabled. It is obvious that when the system operation modulation is reduced, the method of this embodiment can still effectively control the midpoint voltage balance, thereby improving the safety of system operation.

[0137] Example 2

[0138] Based on Embodiment 1, this embodiment provides a high-efficiency and safe modulator for a low-cost three-level inverter, including:

[0139] Basic voltage vector selection and duty cycle calculation module: configured to determine the sector and region where the reference voltage vector is located, select the basic voltage vector to synthesize the reference voltage vector, and solve to obtain the duty cycle of each basic voltage vector;

[0140] A basic voltage vector switch state combination limiting module is configured to limit the switch state corresponding to the small vector to obtain a basic voltage vector switch state combination for the purpose of achieving switch loss suppression and midpoint voltage balance control;

[0141] A clamped switch sequence determination module: configured to design a symmetrical clamped P-type switch sequence and a clamped N-type switch sequence according to the obtained basic voltage vector switch state combination;

[0142] A hysteresis comparator control module: configured to determine an output value of a set hysteresis comparator according to a voltage difference across the DC side capacitor;

[0143] A switch sequence optimization selection module: configured to optimize and select a clamped switch sequence according to the region where the reference voltage vector is located and the output of the hysteresis comparator;

[0144] PWM drive signal conversion module: configured to generate corresponding PWM drive signals according to the optimized switching sequence to control the on and off of the power switch tube.

[0145] It should be noted here that the various modules in this embodiment correspond one-to-one to the various steps in Example 1, and the specific implementation process is the same, which will not be repeated here.

[0146] Example 3

[0147] Based on the first embodiment, this embodiment provides a high-efficiency and safe modulation system for a three-level inverter, including the high-efficiency and safe modulator for the low-cost three-level inverter described in the second embodiment.

[0148] In a specific implementation, the modulation system also includes a driving circuit, a protection circuit, and a signal sampling and conditioning circuit.

[0149] The modulator is connected to the drive circuit, and the PWM signal output by the modulator is sent to the gate of the power switch tube through the drive circuit to control Figure 1 The output signal of the three-level inverter is connected to the modulator through the signal sampling and conditioning circuit, and the protection circuit realizes the functions of over-current and over-voltage protection.

[0150] Among them, the signal sampling and conditioning circuit samples the two supporting capacitors (C1 and C 2 ) voltage, the three-phase current of the three-level inverter (i a 、i b 、i c ) and three-phase grid voltage value (e a 、e b 、e c ).

[0151] Example 4

[0152] This embodiment provides an electronic device, including a memory and a processor, and computer instructions stored in the memory and running on the processor. When the computer instructions are run by the processor, the steps described in the method of Embodiment 1 are completed.

[0153] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

[0154] Although the above describes the specific implementation methods of the present disclosure in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present disclosure. Technical personnel in the relevant field should understand that on the basis of the technical solution of the present disclosure, various modifications or variations that can be made by those skilled in the art without creative work are still within the scope of protection of the present disclosure.

Claims

1. An efficient and safe modulation method for a low-cost three-level inverter, characterized in that: The steps include: Determine the sector and region where the reference voltage vector is located, select basic voltage vectors to synthesize the reference voltage vector, and solve to obtain the duty cycle of each basic voltage vector; In order to achieve switching loss suppression and midpoint voltage balance control, the switch state corresponding to the small vector is limited to obtain the basic voltage vector switch state combination; According to the obtained basic voltage vector switch state combination, a symmetrical clamped P-type switch sequence and a symmetrical clamped N-type switch sequence are designed respectively; According to the voltage difference between the two ends of the DC side capacitor, the output value of the hysteresis comparator is determined; According to the region where the reference voltage vector is located and the output of the hysteresis comparator, the clamping switching sequence is optimally selected; Generate corresponding PWM drive signals according to the optimized switching sequence to control the on and off of the power switch tube; In the step of designing a clamped switching sequence of basic voltage vector switch state combinations, when the reference voltage vector is located in the outer region of each sector, a seven-segment clamped switching sequence is designed; when the reference voltage vector is located in the inner region of each sector, a five-segment clamped switching sequence is designed; The clamping switch sequence design in different sectors and regions is as follows: When the reference voltage vector is located in the outer region of sector 1, the seven-segment clamped P-type switching sequence is: POO-PPO-PPN-PNN-PPN-PPO-POO, and the seven-segment clamped N-type switching sequence is: OON-ONN-PNN-PPN-PNN-ONN-OON; When the reference voltage vector is located in the inner region of sector 1, the five-stage clamped P-type switching sequence is: POO-PPO-PPP-PPO-POO, and the five-stage clamped N-type switching sequence is: OON-ONN-NNN-ONN-OON; When the reference voltage vector is located in the outer region of sector 2, the seven-segment clamped P-type switching sequence is: OPO-PPO-PPN-NPN-PPN-PPO-OPO, and the seven-segment clamped N-type switching sequence is: OON-NON-NPN-PPN-NPN-NON-OON; When the reference voltage vector is located in the inner region of sector 2, the five-stage clamped P-type switching sequence is: OPO-PPO-PPP-PPO-OPO, and the five-stage clamped N-type switching sequence is: OON-NON-NNN-NON-OON; When the reference voltage vector is located in the outer region of sector 3, the seven-segment clamped P-type switch sequence is: OPO-OPP-NPP-NPN-NPP-OPP-OPO, and the seven-segment clamped N-type switch sequence is: NOO-NON-NPN-NPP-NPN-NON-NOO; When the reference voltage vector is located in the inner region of sector 3, the five-stage clamped P-type switching sequence is: OPO-OPP-PPP-OPP-OPO, and the five-stage clamped N-type switching sequence is: NOO-NON-NNN-NON-NOO; When the reference voltage vector is located in the outer region of sector 4, the seven-segment clamped P-type switching sequence is: OOP-OPP-NPP-NNP-NPP-OPP-OOP, and the seven-segment clamped N-type switching sequence is: NOO-NNO-NNP-NPP-NNP-NNO-NOO; When the reference voltage vector is located in the inner region of sector 4, the five-stage clamped P-type switching sequence is: OOP-OPP-PPP-OPP-OOP, and the five-stage clamped N-type switching sequence is: NOO-NNO-NNN-NNO-NOO; When the reference voltage vector is located in the outer region of sector 5, the seven-segment clamped P-type switch sequence is: OOP-POP-PNP-NNP-PNP-POP-OOP, and the seven-segment clamped N-type switch sequence is: ONO-NNO-NNP-PNP-NNP-NNO-ONO; When the reference voltage vector is located in the inner region of sector 5, the five-stage clamped P-type switching sequence is: OOP-POP-PPP-POP-OOP, and the five-stage clamped N-type switching sequence is: ONO-NNO-NNN-NNO-ONO; When the reference voltage vector is located in the outer region of sector 6, the seven-segment clamped P-type switch sequence is: POO-POP-PNP-PNN-PNP-POP-POO, and the seven-segment clamped N-type switch sequence is: ONO-ONN-PNN-PNP-PNN-ONN-ONO; When the reference voltage vector is located in the inner region of sector 6, the five-stage clamped P-type switch sequence is: POO-POP-PPP-POP-POO, and the five-stage clamped N-type switch sequence is: ONO-ONN-NNN-ONN-ONO; The basic voltage vector switch state combination is determined as follows: When the reference voltage vector is located in the outer region of each sector, the two small vectors used to synthesize the reference voltage vector are defined as P-type small vectors, which together with the two large vectors form a P-type switch state combination; the two small vectors used to synthesize the reference voltage vector are defined as N-type small vectors, which together with the two large vectors form an N-type switch state combination; When the reference voltage vector is located in the inner area of ​​each sector, the two small vectors used to synthesize the reference voltage vector are defined as P-type small vectors, and the zero vector used to synthesize the reference voltage vector is defined as [PPP], which together constitute a P-type switch state combination; the two small vectors used to synthesize the reference voltage vector are defined as N-type small vectors, and the zero vector used to synthesize the reference voltage vector is defined as [NNN], which together constitute an N-type switch state combination; The basic voltage vector switch state combination is determined as follows: The basic voltage vector switch state combination limits in different sectors and regions are as follows: When the reference voltage vector is located in the outer region of sector 1, the P-type switch state combinations are: POO, PPO, PPN, PNN, and the N-type switch state combinations are: OON, ONN, PNN, PPN; When the reference voltage vector is located in the inner region of sector 1, the P-type switch state combinations are: POO, PPO, PPP, and the N-type switch state combinations are: OON, ONN, NNN; When the reference voltage vector is located in the outer region of sector 2, the P-type switch state combinations are: OPO, PPO, PPN, NPN, and the N-type switch state combinations are: OON, NON, NPN, PPN; When the reference voltage vector is located in the inner region of sector 2, the P-type switch state combinations are: OPO, PPO, PPP, and the N-type switch state combinations are: OON, NON, NNN; When the reference voltage vector is located in the outer region of sector 3, the P-type switch state combinations are: OPO, OPP, NPP, NPN, and the N-type switch state combinations are: NOO, NON, NPN, NPP; When the reference voltage vector is located in the inner region of sector 3, the P-type switch state combinations are: OPO, OPP, PPP, and the N-type switch state combinations are: NOO, NON, NNN; When the reference voltage vector is located in the outer region of sector 4, the P-type switch state combinations are: OOP, OPP, NPP, NNP, and the N-type switch state combinations are: NOO, NNO, NNP, NPP; When the reference voltage vector is located in the inner region of sector 4, the P-type switch state combinations are: OOP, OPP, PPP, and the N-type switch state combinations are: NOO, NNO, NNN; When the reference voltage vector is located in the outer region of sector 5, the P-type switch state combinations are: OOP, POP, PNP, NNP, and the N-type switch state combinations are: ONO, NNO, NNP, PNP; When the reference voltage vector is located in the inner region of sector 5, the P-type switch state combinations are: OOP, POP, PPP, and the N-type switch state combinations are: ONO, NNO, NNN; When the reference voltage vector is located in the outer region of sector 6, the P-type switch state combinations are: POO, POP, PNP, PNN, and the N-type switch state combinations are: ONO, ONN, PNN, PNP; When the reference voltage vector is located in the inner region of sector 6, the P-type switch state combinations are: POO, POP, PPP, and the N-type switch state combinations are: ONO, ONN, NNN.

2. The efficient and safe modulation method for a low-cost three-level inverter according to claim 1, characterized in that: In the basic voltage vector selection and duty cycle calculation steps, when the reference voltage vector is located in the outer area of ​​each sector, the four closest basic voltage vectors are selected to synthesize the reference voltage vector, and an indirect calculation method is designed to solve the duty cycle of each basic voltage vector; when the reference voltage vector is located in the inner area of ​​each sector, the three closest basic voltage vectors are selected to synthesize the reference voltage vector, and a direct calculation method is designed to solve the duty cycle of each basic voltage vector.

3. The efficient and safe modulation method for a low-cost three-level inverter according to claim 1, characterized in that: In the clamped P-type switching sequence, there is one phase that is clamped to the P state within the switching cycle; in the clamped N-type switching sequence, there is one phase that is clamped to the N state within the switching cycle.

4. The efficient and safe modulation method for a low-cost three-level inverter according to claim 1, characterized in that: The output value of the hysteresis comparator is determined as follows: when the capacitor voltage deviation is greater than the upper threshold of the hysteresis comparator, the output value of the hysteresis comparator is 1; when the capacitor voltage deviation is less than the lower threshold of the hysteresis comparator, the output value of the hysteresis comparator is 0; when the capacitor voltage deviation is between the lower threshold and the upper threshold of the hysteresis comparator, the output value of the hysteresis comparator remains unchanged.

5. The efficient and safe modulation method for a low-cost three-level inverter according to claim 1, characterized in that: The specific method for optimizing the selection of switch sequences is: When the reference voltage vector is located in the outer region of each sector and the output value of the hysteresis comparator is 1, a seven-segment clamped P-type switch sequence is selected; When the reference voltage vector is located in the inner region of each sector and the output value of the hysteresis comparator is 1, a five-stage clamped P-type switch sequence is selected; When the reference voltage vector is located in the outer region of each sector and the output value of the hysteresis comparator is 0, a seven-segment clamped N-type switch sequence is selected; When the reference voltage vector is located in the inner region of each sector and the output value of the hysteresis comparator is 0, a five-stage clamping N-type switch sequence is selected.

6. An efficient and safe modulator for low-cost three-level inverters, characterized in that: include: Basic voltage vector selection and duty cycle calculation module: configured to determine the sector and region where the reference voltage vector is located, select the basic voltage vector to synthesize the reference voltage vector, and solve to obtain the duty cycle of each basic voltage vector; A basic voltage vector switch state combination limiting module is configured to limit the switch state corresponding to the small vector to obtain a basic voltage vector switch state combination for the purpose of achieving switch loss suppression and midpoint voltage balance control; A clamped switch sequence determination module: configured to design a symmetrical clamped P-type switch sequence and a clamped N-type switch sequence according to the obtained basic voltage vector switch state combination; A hysteresis comparator control module: configured to determine an output value of a set hysteresis comparator according to a voltage difference across the DC link capacitor; A switch sequence optimization selection module: configured to optimize and select a clamped switch sequence according to the region where the reference voltage vector is located and the output of the hysteresis comparator; PWM drive signal conversion module: configured to generate a corresponding PWM drive signal according to the optimized switch sequence to control the on and off of the power switch tube; In the step of designing a clamped switching sequence of basic voltage vector switch state combinations, when the reference voltage vector is located in the outer region of each sector, a seven-segment clamped switching sequence is designed; when the reference voltage vector is located in the inner region of each sector, a five-segment clamped switching sequence is designed; The clamping switch sequence design in different sectors and regions is as follows: When the reference voltage vector is located in the outer region of sector 1, the seven-segment clamped P-type switching sequence is: POO-PPO-PPN-PNN-PPN-PPO-POO, and the seven-segment clamped N-type switching sequence is: OON-ONN-PNN-PPN-PNN-ONN-OON; When the reference voltage vector is located in the inner region of sector 1, the five-stage clamped P-type switching sequence is: POO-PPO-PPP-PPO-POO, and the five-stage clamped N-type switching sequence is: OON-ONN-NNN-ONN-OON; When the reference voltage vector is located in the outer region of sector 2, the seven-segment clamped P-type switching sequence is: OPO-PPO-PPN-NPN-PPN-PPO-OPO, and the seven-segment clamped N-type switching sequence is: OON-NON-NPN-PPN-NPN-NON-OON; When the reference voltage vector is located in the inner region of sector 2, the five-stage clamped P-type switching sequence is: OPO-PPO-PPP-PPO-OPO, and the five-stage clamped N-type switching sequence is: OON-NON-NNN-NON-OON; When the reference voltage vector is located in the outer region of sector 3, the seven-segment clamped P-type switch sequence is: OPO-OPP-NPP-NPN-NPP-OPP-OPO, and the seven-segment clamped N-type switch sequence is: NOO-NON-NPN-NPP-NPN-NON-NOO; When the reference voltage vector is located in the inner region of sector 3, the five-stage clamped P-type switching sequence is: OPO-OPP-PPP-OPP-OPO, and the five-stage clamped N-type switching sequence is: NOO-NON-NNN-NON-NOO; When the reference voltage vector is located in the outer region of sector 4, the seven-segment clamped P-type switching sequence is: OOP-OPP-NPP-NNP-NPP-OPP-OOP, and the seven-segment clamped N-type switching sequence is: NOO-NNO-NNP-NPP-NNP-NNO-NOO; When the reference voltage vector is located in the inner region of sector 4, the five-stage clamped P-type switching sequence is: OOP-OPP-PPP-OPP-OOP, and the five-stage clamped N-type switching sequence is: NOO-NNO-NNN-NNO-NOO; When the reference voltage vector is located in the outer region of sector 5, the seven-segment clamped P-type switch sequence is: OOP-POP-PNP-NNP-PNP-POP-OOP, and the seven-segment clamped N-type switch sequence is: ONO-NNO-NNP-PNP-NNP-NNO-ONO; When the reference voltage vector is located in the inner region of sector 5, the five-stage clamped P-type switching sequence is: OOP-POP-PPP-POP-OOP, and the five-stage clamped N-type switching sequence is: ONO-NNO-NNN-NNO-ONO; When the reference voltage vector is located in the outer region of sector 6, the seven-segment clamped P-type switch sequence is: POO-POP-PNP-PNN-PNP-POP-POO, and the seven-segment clamped N-type switch sequence is: ONO-ONN-PNN-PNP-PNN-ONN-ONO; When the reference voltage vector is located in the inner region of sector 6, the five-stage clamped P-type switch sequence is: POO-POP-PPP-POP-POO, and the five-stage clamped N-type switch sequence is: ONO-ONN-NNN-ONN-ONO; The basic voltage vector switch state combination is determined as follows: When the reference voltage vector is located in the outer region of each sector, the two small vectors used to synthesize the reference voltage vector are defined as P-type small vectors, which together with the two large vectors form a P-type switch state combination; the two small vectors used to synthesize the reference voltage vector are defined as N-type small vectors, which together with the two large vectors form an N-type switch state combination; When the reference voltage vector is located in the inner area of ​​each sector, the two small vectors used to synthesize the reference voltage vector are defined as P-type small vectors, and the zero vector used to synthesize the reference voltage vector is defined as [PPP], which together constitute a P-type switch state combination; the two small vectors used to synthesize the reference voltage vector are defined as N-type small vectors, and the zero vector used to synthesize the reference voltage vector is defined as [NNN], which together constitute an N-type switch state combination; The basic voltage vector switch state combination is determined as follows: The basic voltage vector switch state combination limits in different sectors and regions are as follows: When the reference voltage vector is located in the outer region of sector 1, the P-type switch state combinations are: POO, PPO, PPN, PNN, and the N-type switch state combinations are: OON, ONN, PNN, PPN; When the reference voltage vector is located in the inner region of sector 1, the P-type switch state combinations are: POO, PPO, PPP, and the N-type switch state combinations are: OON, ONN, NNN; When the reference voltage vector is located in the outer region of sector 2, the P-type switch state combinations are: OPO, PPO, PPN, NPN, and the N-type switch state combinations are: OON, NON, NPN, PPN; When the reference voltage vector is located in the inner region of sector 2, the P-type switch state combinations are: OPO, PPO, PPP, and the N-type switch state combinations are: OON, NON, NNN; When the reference voltage vector is located in the outer region of sector 3, the P-type switch state combinations are: OPO, OPP, NPP, NPN, and the N-type switch state combinations are: NOO, NON, NPN, NPP; When the reference voltage vector is located in the inner region of sector 3, the P-type switch state combinations are: OPO, OPP, PPP, and the N-type switch state combinations are: NOO, NON, NNN; When the reference voltage vector is located in the outer region of sector 4, the P-type switch state combinations are: OOP, OPP, NPP, NNP, and the N-type switch state combinations are: NOO, NNO, NNP, NPP; When the reference voltage vector is located in the inner region of sector 4, the P-type switch state combinations are: OOP, OPP, PPP, and the N-type switch state combinations are: NOO, NNO, NNN; When the reference voltage vector is located in the outer region of sector 5, the P-type switch state combinations are: OOP, POP, PNP, NNP, and the N-type switch state combinations are: ONO, NNO, NNP, PNP; When the reference voltage vector is located in the inner region of sector 5, the P-type switch state combinations are: OOP, POP, PPP, and the N-type switch state combinations are: ONO, NNO, NNN; When the reference voltage vector is located in the outer region of sector 6, the P-type switch state combinations are: POO, POP, PNP, PNN, and the N-type switch state combinations are: ONO, ONN, PNN, PNP; When the reference voltage vector is located in the inner region of sector 6, the P-type switch state combinations are: POO, POP, PPP, and the N-type switch state combinations are: ONO, ONN, NNN.

7. An efficient and safe modulation system for a three-level inverter, characterized in that: An efficient and safe modulator using the low-cost three-level inverter as claimed in claim 6.

8. An electronic device, characterized in that: The method comprises a memory and a processor and computer instructions stored in the memory and executed on the processor, wherein when the computer instructions are executed by the processor, the steps described in any one of the methods of claims 1 to 5 are completed.

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