A C-band power amplifier with gain compensation network design

Abstract

This invention discloses a C-band power amplifier with a gain compensation network design, belonging to the field of microwave integrated circuit technology. This invention is a two-stage push-pull circuit, in which the matching networks and transistors of each stage are arranged completely symmetrically. The first stage has two transistors with a total gate width of 1.04mm each, which mainly provide gain; the final stage is an eight-way synthesis, and each tube has the same specifications as the first-stage tube, with a drive ratio of 1:4. In order to make the tubes work efficiently and improve the long-term reliability of the chip, the eight tubes of the final stage are arranged in parallel with large spacing. The matching network of the circuit includes input, inter-stage and output matching networks. By adding a gain compensation network to the input stage, the gain can be adjusted and the gain flatness can be improved. The input standing wave coefficient is improved through the clever design of the gain compensation network.

Description

Technical Field

[0001] The invention belongs to the technical field of microwave integrated circuits, and in particular relates to a C-band power amplifier with a gain compensation network design. Background Art

[0002] RF power amplifiers are widely used in communications, radar, and electronic warfare. Their gain flatness directly impacts the transmitter's in-band power fluctuations. Therefore, under normal operating conditions, differences in gain at different frequencies can affect the quality of the resulting broadband signal. GaN transistors exhibit varying gain responses at different frequencies, generally exhibiting higher gain at low frequencies. Common methods for improving gain flatness include negative feedback and the addition of interstage attenuators.

[0003] In 2017, Zhang Zhe and others from the School of Electronic Engineering at the University of Electronic Science and Technology of China used an output power equalization network topology to design a power amplifier operating at 3-4 GHz with a gain flatness of ±1 dB and an output power of 10 W. See [ZHANG Zhe; CHEN Bo; YANG Wei; ZHU Hantao; PU Xingyue,"Design of S-Band Broadband Solid-State Power Amplifier using GaN Power HEMTs," in Proceedings of 2017 National Conference on Microwave and Millimeter Waves (NCMMW2017)].

[0004] In 2021, Jun Hu et al. from Fudan University in China proposed a modular technology to design a two-stage broadband power amplifier operating in the 0.03 GHz to 2.7 GHz frequency range. The amplifier achieved a saturated output power of 38.8 dBm, a small-signal gain of 37.35 dB, and a gain flatness of ±2.35 dB. See [JUN HU, XIAOJUAN CHEN, ZHI JIN, and HONGTAOXU, "Design of 35-dB 0.03-to-2.7 GHz Two-Stage Broadband Power Amplifier With 37.2 dBm Psat Using Modular Technology," in IEEE Access, vol. 9, pp. 142328–142339, 2021, doi: 10.1109 / ACCESS.2021.3120992].

[0005] Qorvo's QPA1019 uses a GaN HEMT process, operates at 4.5 to 7 GHz, offers 30 dB small-signal gain, and has a small-signal gain flatness of ±1 dB. However, its output power is only 40 dBm. See [https: / / www.qorvo.com / products / p / QPA1019].

[0006] The 13th Institute's product NC11634C-408P25 uses GaN HEMT technology, has an operating frequency of 4-8GHz, an output power of 45dBm, and a small signal gain of 23dB, but the gain flatness is only ±3dB.

[0007] As can be seen, current sub-C-band GaN MMIC gain flatness is mostly ±2dB or above, and the saturated output power is not high. Therefore, there are few C-band power amplifier monolithic products that achieve both high power output and good gain flatness. Summary of the Invention

[0008] In order to solve the problem of poor gain flatness of microwave amplifiers, the present invention proposes a circuit design method, which can enable the microwave amplifier to achieve good gain flatness while ensuring high power output and improve input standing wave.

[0009] The technical solutions adopted in the present invention are as follows:

[0010] A C-band power amplifier with a gain compensation network design includes: an input gain compensation network, a mid-range gain compensation network, and an output matching network. The following characters "C" represent a capacitor, "R" represents a resistor, "L" represents an inductor, and "MLIN" represents a bias microstrip line. The input gain compensation network includes R1, R2, and L1. The input end of the amplifier is one end of R1, and the other end of R1 is divided into two paths. One path is connected to the input end of the mid-range gain compensation network, and the other path is connected in sequence to R2 and L1 and then to ground.

[0011] The mid-section gain compensation network includes two parallel circuits M1 and M2, where the two circuits have identical structures and share an input and an output. The input of one of M1 or M2 is sequentially connected to C1, L2, R3, and the gate of transistor Q1. One end of C2 is connected to the common point of C1 and L2, and the other end of C2 is grounded. C3 is connected in parallel with R. The common point of R3 and transistor Q1 is sequentially connected to ground through R4, MLIN1, and C4. The common point of MLIN1 and C4 is input with a voltage Vg, which is a negative voltage and provides a gate bias for the transistor. The source of transistor Q1 is grounded, and the drain is sequentially connected to one end of L1 and C5. The common point of L1 and C5 is sequentially connected to L4, MLIN2, and C8, and then grounded. The common point of MLIN2 and C8 is Vd, which is +28V and provides a drain bias voltage for the transistor.

[0012] The other end of C5 is divided into two parallel circuits M3 and M4. M3 and M4 have the same structure and share an input and an output. The input end of M3 or M4 is connected to one end of L5 and one end of C6. The other end of C6 is grounded. The other end of L5 is grounded through C7. The common point of L5 and C7 is connected to the input ends of the two circuits M5 and M6. One circuit M5 is connected to L6, R6, and the gate of Q2 in sequence from the input end. The source of Q2 is connected to Ground, the drain of Q2 is connected to the input of MLIN7 after passing through MLIN5; another circuit M6 is connected to L7, R7, and the gate of Q3 in sequence starting from the input end, the source of Q3 is grounded, and the drain of Q3 is connected to the input of MLIN7 after passing through MLIN6; the common point of R6 and Q2 is J1, the common point of R7 and Q3 is J2, J1 and J2 are connected together and then pass through R5, MLIN3, C9 in sequence before being grounded, and the common point of MLIN3 and C9 is the input voltage Vg;

[0013] The output of MLIN7 passes through MLIN8 and serves as the output of M3 or M4. The common point of MLIN7 and MLIN8 passes through MLIN4, C 10 Then ground, MLIN4 and C 10 The common point is connected to the input voltage Vd;

[0014] The output ends of M3 and M4 serve as the output ends of M1 or M2 after passing through MLIN9, and the output ends of M1 and M2 serve as the output ends of the power amplifier after passing through the output matching network;

[0015] The input signal of the output matching network is sequentially transmitted through the MLIN 10 、C 13 The two ends of MLIN9 are connected through C 11 and C 12 Ground.

[0016] This invention proposes a C-band power amplifier with a gain compensation network design. The overall scheme is a two-stage push-pull circuit, with the matching networks and transistors in each stage arranged symmetrically. The first stage features two transistors, each with a total gate width of 1.04 mm, primarily providing gain. The final stage is an eight-way synthesizer, with each transistor matching the specifications of the first-stage transistors and a drive-to-displacement ratio of 1:4. To ensure high transistor efficiency and improve the long-term reliability of the chip, the eight transistors in the final stage are arranged in parallel with large spacing. The circuit's matching network includes input, interstage, and output matching networks. The addition of a gain compensation network in the input stage allows for adjustable gain and improved gain flatness. The ingenious design of the gain compensation network also improves the input standing wave coefficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of an embodiment of the present invention;

[0018] Figure 2 This is a simulation diagram of the input stage gain according to an embodiment of the present invention;

[0019] Figure 3 This is a simulation diagram of the second-stage gain of an embodiment of the present invention;

[0020] Figure 4 This is a simulation diagram of the overall gain of an embodiment of the present invention;

[0021] Figure 5 This is a diagram of the measured results of an embodiment of the present invention;

[0022] Figure 6 This is a diagram of the measured results of an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in conjunction with the following specific embodiments and with reference to the accompanying drawings.

[0024] The present invention includes: DC blocking capacitors C1, C5, C 13 , decoupling capacitors C4, C8, C9, C 10 , bias microstrip lines MLIN1, MLIN2, MLIN3, MLIN4, stabilizing resistors R1, R3, R4, R6, R7, C3 and R3 form an RC parallel stabilizing network, input gain compensation network R1, R2 and L1, where R2 and L1 are connected in series to ground, input matching capacitors C1, C2, input matching inductor L2; inter-stage matching inductors L3, L5, L6, L7, inter-stage matching capacitors C5, C6, C7;

[0025] One end of the blocking capacitor C1 is used as the input of the previous stage system or the RF input source of this stage, and the other end is connected to the input matching circuit and the gate; one end of the blocking capacitor C5 is connected to the drain of the previous stage transistor, and the other end is connected to the input matching network and the gate of the final stage transistor; the blocking capacitor C 13 One end is connected to the drain of the final transistor, and the other end is connected to the output (i.e., the input of the next system); one end of the decoupling capacitor C4 is grounded, and the other end is connected in sequence to the bias microstrip line MLIN1, the isolation resistor R4 to the gate of the transistor Q1; one end of the decoupling capacitor C8 is grounded, and the other end is connected in sequence to the bias microstrip lines MLIN2, L4, and L3 to the drain of Q1; one end of the decoupling capacitor C9 is grounded, and the other end is connected in sequence to the bias microstrip line MLIN4, the isolation resistor R5 to the gates of the transistors Q2 and Q3; the decoupling capacitor C 10 One end is grounded, and the other end is connected to the bias microstrip line MLIN4, microstrip line MLIN7, microstrip line MLIN5 to the drain of Q3. The output matching uses microstrip lines MLIN5, MLIN6, MLIN7, MLIN8, MLIN9, MLIN 10 And grounding capacitor C 11 、C 12 、C 13 .

[0026] Example:

[0027] This example provides a C-band power amplifier circuit structure with a gain compensation network design, including a power supply, transistors, matching inductors, matching capacitors, stabilizing resistors, DC-blocking capacitors, matching microstrip lines, AC-blocking resistors, and decoupling capacitors. Inductors, capacitors, and microstrip lines are used to match the transistor impedance, while a combination of resistors and inductors is used in the input stage to reduce the gain in the low-frequency band, achieving a relatively flat overall gain within the band. Tests show that the power amplifier operates from 3.6 to 6.2 GHz, with an output power greater than 45 dBm, a power-added efficiency greater than 39%, a saturated power gain greater than 20 dB, and a small-signal gain of 27.7 ± 1 dB.

[0028] like Figure 1 It is a C-band power amplifier circuit structure with a gain compensation network design. The RF signal is from RF inAt the input port, the RF signal is attenuated after passing through R1. Simultaneously, since reflected signals also pass through R1, the input return loss and standing wave coefficient are improved. A larger R1 value increases the effect, but at the expense of some gain. R2 and L1 are connected in series to ground. At low frequencies, the signal flows through R2 and L1 to ground, with some energy dissipated by R2. Therefore, the energy entering the transistor gate is further reduced. Furthermore, this structure increases the loss at lower frequencies, directly contradicting the transistor's gain characteristic. This improves gain flatness for this stage and suppresses low-frequency self-oscillation. C1, C2, and L2 primarily match the input impedance, matching the input port impedance to the gate impedance of transistor Q1. Interstage matching utilizes a T-type matching network, consisting of L3, L4, and C5. This is followed by two L-type matching networks to broaden the bandwidth. C6 forms two pairs of LC low-pass filters with L5, and C7 forms two pairs of LC low-pass filters with L7 / L6.

[0029] The gain compensation network is implemented using three networks, including an RL series network, an RC parallel network, and an RCL series network. This circuit includes two stages of amplification, each stage contains an RCL series network, and the first stage gate terminal contains three balanced gain networks to adjust the in-band gain flatness. Figure 1 As shown in the figure, R4, MLIN1, and C4 form a first-stage RLC series network, also known as a bias circuit. One end of the gain compensation resistor R4 is connected to the transistor's gate bias voltage Vgs, and the other end is connected to MLIN1. A parallel bypass capacitor C4 is connected between the transmission line MLIN1 and Vgs, with the other end of capacitor C4 grounded. One end of the parallel connection of resistor R3 and capacitor C3 is connected to the transistor's gate. One end of the series connection of resistor R2 and capacitor L1 is grounded, and the other end is connected to the circuit in parallel. Figure 2 The small signal gain change of the first stage before and after adding the gain compensation network is shown (S21-GCN is the small signal gain after adding the compensation network, and S21-NO GCN is the small signal gain before adding the compensation network). The gain suppression in the low-frequency band of the network is mainly played by the RL series structure and the RLC bias structure, and the gain compensation in the high-frequency band is mainly played by the RC parallel structure and the RLC bias structure. The parameter values of each component of the gain compensation network are reasonably adjusted, and the out-of-band low frequency is finally stabilized to prevent transistor self-excitation, and the in-band gain flatness is adjusted to a reasonable state, and the low-frequency gain is kept lower than the high-frequency gain. Based on the need for good overall gain flatness, the second stage considers that the low-frequency gain is higher than the high-frequency gain. Since the output end should have the minimum loss, the gain compensation network is added to the input end of the second stage to rationally design the gain, and the output end is designed according to the minimum loss principle.

[0030] The second stage has high DC power consumption. If multiple gain compensation networks are used, the high losses will directly affect efficiency. Therefore, if the low-frequency gain of the first stage is suppressed low enough, the low-frequency output power of the first stage output power will be reduced compared to the high-frequency output power. On this basis, we connect an RLC series network and a small resistor of about 1ohm in series with the gate to form a stable network with the resistor on the bias line. However, since the final stage tube still has the characteristic of high low-frequency gain, the final output within the total frequency band maintains a relatively good flatness. Figure 3 The small-signal gain change of the second stage before and after the gain compensation network is added is shown. After adding the gain compensation network and properly adjusting the component parameters, the gain flatness trend of this stage is exactly complementary to that of the first stage, and the maximum difference in the in-band gain of the two stages remains close, so the final gain flatness becomes relatively good.

[0031] The final stage is designed with maximum power output in mind and uses a compact cascaded L-shaped broadband matching network. Figure 4 The gain of each stage after adding the gain compensation network and the overall gain before and after adding the gain compensation network are shown. It is obvious that the gains of the input stage (IMN) and the second stage (ISMN) are complementary, and the final overall circuit gain (S21-GCN) maintains good flatness, with a flatness of ±1dB. When the gain compensation network is not added (S21-NO GCN), the flatness is ±2.5dB.

[0032] Example In the DC power supply V g =-2V, V d =28V, the small signal gain measured results are as follows Figure 5 The actual measurement results of large signals with an input power of 25dBm are as follows: Figure 6 .

[0033] In summary, the present invention proposes a C-band power amplifier circuit structure with a gain compensation network design. The structure mainly changes the size of the gate signal injection of the input stage by increasing the difference in signal loss of the gain compensation network at different frequencies, thereby lowering the low-frequency gain of the first stage and reducing the low-frequency signal of the intermediate stage. However, since the final stage tube still has the low-frequency and high-gain characteristics, the final gain is relatively flat. At the same time, the loss of the final stage matching network is small, which not only meets the high-efficiency operation of the power amplifier during power output, but also solves the problem of poor gain flatness in the communication system.

Claims

1. A C-band power amplifier with a gain compensation network design, the amplifier comprising: Input gain compensation network, mid-stage gain compensation network, and output matching network. The following characters "C" represent capacitors, "R" represent resistors, "L" represent inductors, and "MLIN" represents bias microstrip lines. The input gain compensation network includes R1, R2, and L1. The input end of the amplifier is one end of R1, and the other end of R1 is divided into two paths. One path is connected to the input end of the mid-stage gain compensation network, and the other path is connected to R2 and L1 in sequence and then grounded. The mid-stage gain compensation network includes two parallel circuits M1 and M2, which have identical structures and share an input and an output. The input of one circuit, M1 or M2, is sequentially connected to C1, L2, R3, and the gate of transistor Q1. One end of C2 is connected to the common point of C1 and L2, and the other end of C2 is grounded. C3 and R3 are connected in parallel. The common point of R3 and transistor Q1 is sequentially connected to ground through R4, MLIN1, and C4. The common point of MLIN1 and C4 is connected to an input voltage Vg, which is a negative voltage and provides a gate bias for transistor Q1. The source of transistor Q1 is grounded, and the drain is sequentially connected to one end of L3 and C5. The common point of L3 and C5 is sequentially connected to L4, MLIN2, and C8, and then grounded. The common point of MLIN2 and C8 is connected to an input voltage Vd, Vd = +28V, which provides a drain bias voltage for transistor Q1. The other end of C5 is divided into two parallel circuits M3 and M4. M3 and M4 have exactly the same structure. M3 and M4 share an input end and an output end. The input end of M3 or M4 is connected to one end of L5 and one end of C6. The other end of C6 is grounded. The other end of L5 is grounded through C7. The common point of L5 and C7 is then connected to the input ends of the two circuits M5 and M6. One circuit M5 is connected to L6, R6, and the gate of transistor Q2 in sequence from the input end. The source of transistor Q2 is grounded. The drain of 2 is connected to the input of MLIN7 after passing through MLIN5; another circuit M6 is connected to L7, R7, and the gate of transistor Q3 in sequence starting from the input end. The source of transistor Q3 is grounded, and the drain of transistor Q3 is connected to the input of MLIN7 after passing through MLIN6; the common point of R6 and transistor Q2 is J1, and the common point of R7 and transistor Q3 is J2. J1 and J2 are connected together and then pass through R5, MLIN3, and C9 in sequence before being grounded. The common point of MLIN3 and C9 is the input voltage Vg; The output of MLIN7 passes through MLIN8 and serves as the output of M3 or M4. The common point of MLIN7 and MLIN8 passes through MLIN4, C 10 Then ground, MLIN4 and C 10 The common point is connected to the input voltage Vd; The output ends of M3 and M4 serve as the output ends of M1 or M2 after passing through MLIN9, and the output ends of M1 and M2 serve as the output ends of the power amplifier after passing through the output matching network; The input signal of the output matching network is sequentially transmitted through the MLIN 10 、C 13 The two ends of MLIN9 are connected through C 11 and C 12 Ground.

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