Single-ended to differential circuit and method thereof, continuous-time sigma-delta analog-to-digital converter

Abstract

A single-ended to differential circuit and method, and a successive approximation analog-to-digital converter are disclosed. A method for converting a single-ended signal to a differential signal includes providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; controlling the first end to receive a single-ended signal, the second end to receive a reference voltage, the third end to receive a mid voltage value of a swing of the reference voltage or the single-ended signal, and the fourth end to receive the single-ended signal at a first time point; and controlling the second end and the fourth end to receive the reference voltage at a second time point. The first end and the third end output a differential signal after the second time point, and the second time point is later than the first time point.

Description

TECHNICAL FIELD

[0001] The present application relates to single-ended signals and differential-ended signals (or differential signals), and more particularly, to a circuit and method for converting a single-ended signal to a differential-ended signal, and an analog-to-digital converter using the single-ended to differential-ended circuit. BACKGROUND

[0002] Most of the electronic components use differential signals, but there are still some single-ended signals. The swing of the single-ended signal is only half of the differential signal, and the single-ended signal has poor noise immunity. Converting the single-ended signal to the differential signal helps to improve the performance of the electronic components, and thus becomes an important issue in the field. SUMMARY

[0003] In view of the deficiencies of the prior art, one object of the present application is to provide a single-ended to differential-ended circuit and a method for converting a single-ended signal to a differential-ended signal to improve the deficiencies of the prior art.

[0004] One embodiment of the present application provides a single-ended to differential-ended circuit for receiving a single-ended signal and outputting a differential-ended signal at a first output node and a second output node. The single-ended to differential-ended circuit includes a first sampling capacitor, a second sampling capacitor, and a switch group. The first sampling capacitor has a first end and a second end, the first end is coupled to the first output node, and the second end receives a reference voltage. The second sampling capacitor has a third end and a fourth end, the third end is coupled to the second output node. The switch group is coupled to the first output node, the second output node, and the fourth end. At a first time point, the switch group couples the first output node and the first end to the single-ended signal, couples the second output node and the third end to the reference voltage or a mid voltage value of a swing of the single-ended signal, and couples the fourth end to the single-ended signal. At a second time point, the switch group couples the fourth end to the reference voltage. The differential-ended signal is outputted after the second time point, and the second time point is later than the first time point.

[0005] Another embodiment of the present application provides a continuous-time sigma-delta analog-to-digital converter, comprising a comparator, a continuous-time sigma-delta register, a first sampling capacitor, a second sampling capacitor, a first capacitor group, a first switch group, a second capacitor group, a second switch group, a control circuit, and a third switch group. The comparator has a first input and a second input for generating a comparison result. The continuous-time sigma-delta register is coupled to the comparator for storing the comparison result. The first sampling capacitor has a first terminal coupled to the first input and a second terminal for receiving a reference voltage. The second sampling capacitor has a third terminal coupled to the second input and a fourth terminal. The first capacitor group includes a plurality of first capacitors having one terminal coupled to the first input. The first switch group is coupled to the other terminal of the first capacitors. The second capacitor group includes a plurality of second capacitors having one terminal coupled to the second input. The second switch group is coupled to the other terminal of the second capacitors. The control circuit is coupled to the continuous-time sigma-delta register for controlling the first switch group and the second switch group according to the comparison result. The third switch group is coupled to the first input, the second input, and the fourth terminal. At a first time point, the third switch group couples the first input and the first terminal to a single-ended signal, couples the second input and the third terminal to the reference voltage or a mid voltage value of a swing of the single-ended signal, and couples the fourth terminal to the single-ended signal. At a second time point, the third switch group couples the fourth terminal to the reference voltage, and the second time point is later than the first time point.

[0006] Another embodiment of the present application provides a method for converting a single-ended signal to a differential signal, comprising providing a first sampling capacitor having a first terminal and a second terminal, providing a second sampling capacitor having a third terminal and a fourth terminal, at a first time point, controlling the first terminal to receive the single-ended signal, controlling the second terminal to receive a reference voltage, controlling the third terminal to receive the reference voltage or a mid voltage value of a swing of the single-ended signal, and controlling the fourth terminal to receive the single-ended signal, and at a second time point, controlling the second terminal to receive the reference voltage and controlling the fourth terminal to receive the reference voltage. The first terminal and the third terminal output the differential signal after the second time point, and the second time point is later than the first time point.

[0007] The single-ended to differential circuit and the method for converting a single-ended signal to a differential signal of the present application convert a single-ended signal to a differential signal to increase a swing of the signal, thereby increasing a signal-to-noise ratio (SNR) of the signal, and further improving performance of an electronic component, such as a continuous-time sigma-delta analog-to-digital converter.

[0008] The present application will be described in detail below with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1A Figure 1B is a circuit diagram of one embodiment of the single-ended to differential circuit of the present application;

[0010] Figure 2A Figure 2B is a circuit diagram of another embodiment of the single-ended to differential circuit of the present application;

[0011] Figure 3A Figure 3B is one embodiment of the display clock CLK;

[0012] Figure 4A Figure 4B is a circuit diagram of another embodiment of the single-ended to differential circuit of the present application;

[0013] Figure 5 is a circuit diagram of another embodiment of the single-ended to differential circuit of the present application;

[0014] Figure 6 is a circuit diagram of one embodiment of the continuous ramp analog-to-digital converter of the present application;

[0015] Figure 7 is a circuit diagram of another embodiment of the continuous ramp analog-to-digital converter of the present application;

[0016] Figure 8 is a flow chart of one embodiment of the method of converting a single-ended signal to a differential signal of the present application; and

[0017] Figure 9 is a flow chart of another embodiment of the method of converting a single-ended signal to a differential signal of the present application. DETAILED DESCRIPTION

[0018] The following description of background, embodiments, advantages, and effects is provided to assist in understanding the present application. It should be understood that the present application can be carried out without some or all of the described advantages and / or effects.

[0019] ​​​​The present disclosure includes a single-ended to differential circuit, a successive approximation analog-to-digital converter using the same, and a method of converting a single-ended signal to a differential signal. Since the components included in the single-ended to differential circuit and the successive approximation analog-to-digital converter using the same of the present disclosure can be known components individually, the following description will omit the details of the known components without affecting the sufficient disclosure and the implementability of the device invention. In addition, the method of converting a single-ended signal to a differential signal of the present disclosure can be performed by the single-ended to differential circuit of the present disclosure or its equivalent device, and the following description of the method invention will focus on the contents of the steps rather than the hardware without affecting the sufficient disclosure and the implementability of the method invention.

[0020] Figure 1A and Figure 1B is a circuit diagram of an embodiment of the single-ended to differential circuit of the present disclosure. The single-ended to differential circuit 100 receives a single-ended signal VIP and a reference voltage Vrefn in a sampling phase ( Figure 1A ) and outputs a signal VOP and a signal VON (collectively, a differential signal VO) from output nodes N_a and N_b, respectively, in a holding phase ( Figure 1B ). In other words, the single-ended to differential circuit 100 converts the single-ended signal VIP to the differential signal VO. The single-ended to differential circuit 100 includes a sampling capacitor C_Ra, a sampling capacitor C_Rb, a switch group 110, and a logic circuit 120. The switch group 110 includes a switch 110_a, a switch 110_b, and a switch 110_c. One end of the sampling capacitor C_Ra is coupled or electrically connected to the output node N_a, and the other end of the sampling capacitor C_Ra receives (i.e., is coupled to) the reference voltage Vrefn. One end of the sampling capacitor C_Rb is coupled or electrically connected to the output node N_b, and the other end of the sampling capacitor C_Rb receives the single-ended signal VIP or the reference voltage Vrefn through the switch group 110 (more specifically, through the switch 110_c). The logic circuit 120 generates a control signal CS (including a control signal CS1 and a control signal CS2) according to a clock CLK. The switch 110_a and the switch 110_b are controlled by the control signal CS1, and the switch 110_c is controlled by the control signal CS2.

[0021] As shown in Figure 1A , in the sampling phase, the logic circuit 120 controls the switch 110_a and the switch 110_b to be turned on and controls the switch 110_c to be switched to the single-ended signal VIP. In other words, in the sampling phase, the voltage of the output node N_a and the voltage of one end of the sampling capacitor C_Ra are equal to the single-ended signal VIP, the voltage of the output node N_b and the voltage of one end of the sampling capacitor C_Rb are equal to the reference voltage Vrefn, and the voltage of the other end of the sampling capacitor C_Rb is equal to the single-ended signal VIP.

[0022] like Figure 1B As shown, during the hold phase, logic circuit 120 controls switches 110_a and 110_b to be off, and controls switch 110_c to switch to the reference voltage Vrefn. In other words, during the hold phase, signal VOP is equal to the voltage of output node N_a (i.e., the voltage at one end of sampling capacitor C_Ra), signal VON is equal to the voltage of output node N_b (i.e., the voltage at one end of sampling capacitor C_Rb), and the voltage at the other end of sampling capacitor C_Rb is equal to the reference voltage Vrefn.

[0023] Assuming the single-ended signal VIP = VCM + DELTA_V and the reference voltage Vrefn = VCM + VCMdelta, the differential signal VO is as shown in equation (1).

[0024]

[0025] Wherein, VCM represents the common-mode voltage of the single-ended signal VIP (i.e., the midpoint voltage value of the swing of the single-ended signal VIP), DELTA_V represents the signal component of VIP, and VCMdelta represents the difference between the common-mode voltage of VIP and the common-mode voltage of the reference voltage Vrefn.

[0026] In equation (1), “2*VCMdelta” represents the conversion error of the single-ended to double-ended circuit 100. As shown in equation (1), the differential signal VO is a differential signal (i.e., both signals VOP and VON contain the signal component DELTA_V), representing that the single-ended to double-ended circuit 100 converts the single-ended signal (VIP) into a differential signal (VO). Furthermore, because the signal component of the differential signal VO (i.e., the difference between signals VOP and VON = 2*DELTA_V - 2*VCMdelta) contains 2*DELTA_V, the single-ended to double-ended circuit 100 has the function of amplifying the single-ended signal VIP.

[0027] Figure 2A and Figure 2B This is a circuit diagram of another embodiment of the single-ended to double-ended circuit of the present invention. The single-ended to double-ended circuit 200 is similar to the single-ended to double-ended circuit 100, except that in the single-ended to double-ended circuit 200, the switch 110_b couples the output node N_b to the common-mode voltage VCM of the single-ended signal VIP instead of the reference voltage Vrefn. Therefore, the above equation (1) becomes the following equation (2).

[0028]

[0029] In equation (2), “VCMdelta” represents the conversion error of the single-ended to double-ended circuit 200, which is less than that of the single-ended to double-ended circuit 100. As shown in equation (2), similar to the single-ended to double-ended circuit 100, the single-ended to double-ended circuit 200 can convert the single-ended signal VIP into a differential signal VO and also has the function of amplifying the single-ended signal VIP.

[0030] Figure 3A and Figure 3B An embodiment of the clock CLK. The period of the clock CLK is T, "Φs" represents the sampling phase, and "Φh" represents the holding phase. The sampling phase Φs can correspond to the high level of the clock CLK ( Figure 3A The holding phase Φh corresponds to the low level of the clock CLK. Figure 3A Alternatively, the sampling phase Φs can correspond to the low level of the clock CLK. Figure 3B The holding phase Φh can correspond to the high level of the clock CLK. Figure 3B In other words, in some embodiments, the single-ended to dual-ended circuit 100 and the single-ended to dual-ended circuit 200 operate alternately in the sampling phase Φs and the holding phase Φh according to the clock CLK.

[0031] right Figure 3A For example, at the rising edge of clock CLK (time point t1, time point t3, ...), logic circuit 120 controls switches 110_a and 110_b to conduct, and controls switch 110_c to switch to single-ended signal VIP; at the falling edge of clock CLK (time point t2, time point t4, ...), logic circuit 120 controls switches 110_a and 110_b to deconduct, and controls switch 110_c to switch to reference voltage Vrefn.

[0032] right Figure 3B For example, at the falling edge of clock CLK (time point t1, time point t3, ...), logic circuit 120 controls switches 110_a and 110_b to conduct, and controls switch 110_c to switch to single-ended signal VIP; at the rising edge of clock CLK (time point t2, time point t4, ...), logic circuit 120 controls switches 110_a and 110_b to deconduct, and controls switch 110_c to switch to reference voltage Vrefn.

[0033] Those skilled in the art can design the logic circuit 120 based on the above disclosure. That is, the logic circuit 120 can be an application-specific integrated circuit (ASIC) or implemented by circuits or hardware such as a programmable logic device (PLD).

[0034] Figure 4A and Figure 4B This is a circuit diagram of another embodiment of the single-ended to double-ended circuit of the present invention. The single-ended to double-ended circuit 400 is similar to the single-ended to double-ended circuits 100 and 200, except that the single-ended to double-ended circuit 400 further includes capacitors C_1a and C_1b. The voltage Vx can be a reference voltage Vrefn or a common-mode voltage VCM. One end of capacitor C_1a is coupled or electrically connected to output node N_a, and the other end of capacitor C_1a receives the reference voltage Vrefn. One end of capacitor C_1b is coupled or electrically connected to output node N_b, and the other end of capacitor C_1b receives the reference voltage Vrefn. In this embodiment, the differential signal VO can be adjusted by adjusting the ratio of the capacitance values ​​of sampling capacitor C_Ra (or sampling capacitor C_Rb) to those of capacitor C_1a (or capacitor C_1b). For example, when the capacitance values ​​of sampling capacitors C_Ra and C_Rb are both X units and the capacitance values ​​of capacitors C_1a and C_1b are both Y units, the signal component of the differential signal VO of the single-ended to double-ended circuit 400 is X / (X+Y) times the signal component of the differential signal VO of the single-ended to double-ended circuit 100 (or the single-ended to double-ended circuit 200).

[0035] Figure 5 This is a circuit diagram of another embodiment of the single-ended to double-ended circuit of the present invention. The single-ended to double-ended circuit 500 is similar to the single-ended to double-ended circuit 100 (please note that...). Figure 5 (Only the holding phase is shown). The difference lies in that the single-ended to double-ended circuit 500 further includes capacitor groups 520_a and 520_b. Capacitor group 520_a contains m first capacitors (C_1a, C_2a, ..., C_ma, where m is an integer greater than 1, and some are omitted in the figure), and capacitor group 520_b contains m second capacitors (C_1b, C_2b, ..., C_mb, where m is an integer greater than 1, and some are omitted in the figure). One end of the first capacitor is coupled or electrically connected to the output node N_a, and the other end receives the reference voltage Vrefn. One end of the second capacitor is coupled or electrically connected to the output node N_b, and the other end receives the reference voltage Vrefn. Similar to the single-ended to double-ended circuit 400, the single-ended to double-ended circuit 500 can adjust the magnitude of the differential signal VO by adjusting the equivalent capacitance values ​​of capacitor groups 520_a and 520_b.

[0036] In some embodiments, the capacitance values ​​of the m first capacitors and the m second capacitors increase or decrease in a power of two. For example, the capacitance values ​​of C_1a (C_1b), C_2a (C_2b), ..., C_ma (C_mb) are 1C, 2C, 4C, ..., 2m-1C, respectively (C is the unit capacitance value).

[0037] Figure 6 This is a circuit diagram of one embodiment of the successive-approximation register analog-to-digital converter (SAR ADC) of the present invention. The SAR ADC 600 uses the previously described single-ended to dual-ended circuit 100 or single-ended to dual-ended circuit 200, and further includes a comparator 610, a successive-approximation register (SAR) 620, a control circuit 630, switch groups 640_a and 640_b, and capacitor groups 650_a and 650_b.

[0038] Switch group 640_a contains m first switches (S_1a, S_2a, ..., S_ma, where m is an integer greater than 1, and some are omitted in the figure), and switch group 640_b contains m second switches (S_1b, S_2b, ..., S_mb, where m is an integer greater than 1, and some are omitted in the figure). Capacitor group 650_a (or capacitor group 650_b) contains m first capacitors (or second capacitors). One end of each first capacitor (or second capacitor) is coupled or electrically connected to output node N_a (or output node N_b), and the other end of each first capacitor (or second capacitor) is coupled to reference voltage VRP or reference voltage VRN through a corresponding first switch (or second switch). In some embodiments, reference voltage VRP is a high voltage, reference voltage VRN is a low voltage, and reference voltage Vrefn is not equal to reference voltage VRP and reference voltage VRN.

[0039] Comparator 610 has a first input terminal (electrically connected to output node N_a) and a second input terminal (electrically connected to output node N_b). Comparator 610 compares the voltage at output node N_a with the voltage at output node N_b and generates a comparison result Dk. A successive asymptotic register 620 is coupled to comparator 610 and control circuit 630 and is used to store the comparison result Dk. Control circuit 630 controls switch groups 640_a and 640_b according to the registered value of successive asymptotic register 620 and clock CLK. The details of control circuit 630 controlling switch groups 640_a and 640_b are well known to those skilled in the art and will not be described further.

[0040] Similarly, in some embodiments, the capacitance values ​​of the m first capacitors and the m second capacitors increase or decrease in powers of two.

[0041] Since the single-ended to double-ended circuit 100 and the single-ended to double-ended circuit 200 have the function of amplifying the single-ended signal VIP, the continuous asymptotic analog-to-digital converter 600 of the present invention has better performance (e.g., better signal-to-noise ratio) compared to a continuous asymptotic analog-to-digital converter that does not implement single-ended to double-ended conversion.

[0042] Figure 7 This is a circuit diagram of another embodiment of the continuous asymptotic analog-to-digital converter of the present invention. The continuous asymptotic analog-to-digital converter 700 is similar to the continuous asymptotic analog-to-digital converter 600, the difference being that... Figure 7 In one embodiment, logic circuit 120 is integrated into control circuit 730, so control circuit 730 generates control signal CS based on clock CLK.

[0043] Figure 8 This is a flowchart of one embodiment of the method for converting a single-ended signal to a dual-ended signal according to the present invention, which is used to convert a single-ended signal VIP into a differential signal VO, and includes the following steps.

[0044] Step S810: Provide a first sampling capacitor C_Ra, which has a first terminal (i.e., one of the terminals coupled to or electrically connected to the output node N_a) and a second terminal.

[0045] Step S820: Provide a second sampling capacitor C_Rb, which has a third terminal (i.e., one of the output nodes N_b coupled or electrically connected) and a fourth terminal.

[0046] Step S830: At the first time point t1, control the first terminal to receive the single-ended signal VIP, control the second terminal to receive the reference voltage Vrefn, and control the third terminal to receive the reference voltage Vrefn (corresponding to...). Figure 1A and Figure 1B ) or the midpoint voltage value of the swing of a single-ended signal VIP (corresponding to Figure 2A and Figure 2B ), and control the fourth terminal to receive the single-ended signal VIP.

[0047] Step S840: At the second time point t2, control the second terminal to receive the reference voltage Vrefn and control the fourth terminal to receive the reference voltage Vrefn.

[0048] The second time point t2 mentioned above is later than the first time point t1 (e.g., Figure 3A and Figure 3BAs shown), the converted differential signal VO is output from the first terminal and the second terminal after the second time point t2.

[0049] Figure 9 This is a flowchart of another embodiment of the method for converting a single-ended signal to a dual-ended signal according to the present invention, used to convert a single-ended signal VIP into a differential signal VO, including steps S810 to S820, S910 to S920, and S830 to S840. Since steps S810 to S820 and S830 to S840 are related to... Figure 8 Since they are the same, I will not repeat them here.

[0050] Step S910: Provide a first capacitor C_1a, which has a fifth terminal and a sixth terminal. The fifth terminal is coupled to or electrically connected to the first terminal, and the sixth terminal receives a reference voltage Vrefn.

[0051] Step S920: Provide a second capacitor C_1b, which has a seventh terminal and an eighth terminal. The seventh terminal is coupled to or electrically connected to the third terminal, and the eighth terminal receives a reference voltage Vrefn.

[0052] Since those skilled in the art can understand the implementation details and variations of the method invention through the disclosure of the apparatus invention in this case, to avoid redundancy, repeated descriptions are omitted here without affecting the disclosure requirements and implementability of the method invention. Please note that the shapes, sizes, and proportions of the elements in the aforementioned figures are merely illustrative and are intended for those skilled in the art to understand the invention, and are not intended to limit the invention. Furthermore, in some embodiments, the order of the steps mentioned in the aforementioned flowchart may be adjusted according to actual operation, and they may even be performed simultaneously or partially simultaneously.

[0053] Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

[0054] [Symbol Explanation]

[0055] 100, 200, 400, 500: Single-ended to double-ended circuit

[0056] N_a, N_b: Output nodes

[0057] VOP, VON: Signals

[0058] VIP: Single-ended signal

[0059] VO: Differential signal

[0060] C_Ra, C_Rb: Sampling capacitors

[0061] 110,640_a,640_b: Switch groups

[0062] 120: Logic Circuits

[0063] 110_a, 110_b, 110_c: Switches

[0064] Vrefn, VRP, VRN: Reference voltage

[0065] CLK: Clock

[0066] CS, CS1, CS2: Control signals

[0067] VCM: Common-mode voltage

[0068] T: Period

[0069] Φs: Sampling stage

[0070] Φh: Holding phase

[0071] t1, t2, t3, t4: Time points

[0072] S_1a,S_1b,S_2a,S_2b,S_ma,S_mb: Switches

[0073] C_1a,C_1b,C_2a,C_2b,C_ma,C_mb: Capacitors

[0074] Vx: Voltage

[0075] 520_a, 520_b, 650_a, 650_b: Capacitor groups

[0076] 600, 700: Continuous Asymptotic Analog-to-Digital Converter

[0077] 610: Comparator

[0078] 620: Successive Asymptotic Register

[0079] 630, 730: Control circuit

[0080] Dk: Comparison results

[0081] S810, S820, S830, S840, S910, S920: Steps.

Claims

1. A single-ended to double-ended circuit for receiving a single-ended signal and outputting a differential signal at a first output node and a second output node, the single-ended to double-ended circuit comprising: A first sampling capacitor has a first terminal and a second terminal, the first terminal being coupled to the first output node, and the second terminal receiving a reference voltage. A second sampling capacitor having a third terminal and a fourth terminal, the third terminal being coupled to the second output node; and A switch group is coupled to the first output node, the second output node and the fourth terminal; in, At a first time point, the switch group couples the first output node and the first terminal to the single-ended signal, couples the second output node and the third terminal to the reference voltage or an intermediate voltage value of the swing of the single-ended signal, and couples the fourth terminal to the single-ended signal. At a second time point, the switch group couples the fourth terminal to the reference voltage; and The differential signal is output after the second time point, and the second time point is later than the first time point.

2. The single-ended to double-ended circuit according to claim 1, wherein, This switch group contains: A first switch is coupled to the first output node and the first terminal; A second switch is coupled to the second output node and the third terminal; as well as A third switch is coupled to the fourth terminal; At the first time point, the first switch is turned on to couple the first output node and the first terminal to the single-ended signal; the second switch is turned on to couple the second output node and the third terminal to the reference voltage or the intermediate voltage value of the swing of the single-ended signal; and the third switch couples the fourth terminal to the single-ended signal. At the second time point, the first switch and the second switch are not conducting, and the third switch couples the fourth terminal to the reference voltage.

3. The single-ended to double-ended circuit according to claim 1 further comprises: A first capacitor has a fifth terminal and a sixth terminal, the fifth terminal being coupled to the first output node, and the sixth terminal receiving the reference voltage; and A second capacitor has a seventh terminal and an eighth terminal, the seventh terminal being coupled to the second output node, and the eighth terminal receiving the reference voltage.

4. The single-ended to double-ended circuit according to claim 1 further comprises: A first capacitor group, comprising a plurality of first capacitors, one end of each first capacitor being coupled to the first output node, and the other end of each first capacitor being coupled to the reference voltage; and A second capacitor group, comprising multiple second capacitors, one end of which is coupled to the second output node, and the other end of which is coupled to the reference voltage.

5. The single-ended to double-ended circuit according to claim 4, wherein, The capacitance value of the first capacitor increases in powers of two, and the capacitance value of the second capacitor also increases in powers of two.

6. The single-ended to double-ended circuit according to claim 1 further comprises: A logic circuit, coupled to the switch group, is used to control the switch group according to a clock cycle; in, The first time point corresponds to one of the rising edge and the falling edge of the clock, while the second time point corresponds to the other of the rising edge and the falling edge of the clock.

7. A continuous asymptotic analog-to-digital converter, comprising: A comparator having a first input and a second input is used to generate a comparison result; A successive asymptotic register, coupled to the comparator, is used to store the comparison result; A first sampling capacitor has a first terminal and a second terminal, the first terminal being coupled to the first input terminal, and the second terminal receiving a reference voltage. A second sampling capacitor has a third terminal and a fourth terminal, the third terminal being coupled to the second input terminal; A first capacitor group, comprising a plurality of first capacitors, one end of each first capacitor being coupled to the first input terminal; A first switch group is coupled to the other end of the first capacitor; A second capacitor group, comprising a plurality of second capacitors, one end of each second capacitor being coupled to the second input terminal; A second switch group is coupled to the other end of the second capacitor; A control circuit, coupled to the successive asymptotic register, is used to control the first switch group and the second switch group based on the comparison result; as well as A third switch group is coupled to the first input terminal, the second input terminal and the fourth terminal; At a first time point, the third switch group couples the first input terminal and the first terminal to a single-ended signal, couples the second input terminal and the third terminal to an intermediate voltage value of the reference voltage or the swing of the single-ended signal, and couples the fourth terminal to the single-ended signal. At a second time point, the third switch group couples the fourth terminal to the reference voltage, the second time point being later than the first time point.

8. The continuous asymptotic analog-to-digital converter according to claim 7, wherein, This third switch group includes: A first switch is coupled to the first input terminal and the first terminal; A second switch is coupled to the second input terminal and the third terminal; as well as A third switch is coupled to the fourth terminal; At the first time point, the first switch is turned on to couple the first input terminal and the first terminal to the single-ended signal; the second switch is turned on to couple the second input terminal and the third terminal to the reference voltage or the intermediate voltage value of the swing of the single-ended signal; and the third switch couples the fourth terminal to the single-ended signal. At the second time point, the first switch and the second switch are not conducting, and the third switch couples the fourth terminal to the reference voltage.

9. A method for converting a single-ended signal to a double-ended signal, used to convert a single-ended signal into a differential signal, comprising: A first sampling capacitor is provided, the first sampling capacitor having a first terminal and a second terminal; A second sampling capacitor is provided, the second sampling capacitor having a third terminal and a fourth terminal; At a first time point, control the first terminal to receive the single-ended signal, control the second terminal to receive a reference voltage, control the third terminal to receive an intermediate voltage value of the swing of the reference voltage or the single-ended signal, and control the fourth terminal to receive the single-ended signal; and At a second time point, control the second terminal to receive the reference voltage and control the fourth terminal to receive the reference voltage; in, The first terminal and the third terminal output the differential signal after the second time point, and the second time point is later than the first time point.

10. The method of claim 9, further comprising: A first capacitor is provided, the first capacitor having a fifth terminal and a sixth terminal, the fifth terminal being coupled to the first terminal, and the sixth terminal receiving the reference voltage; and A second capacitor is provided, the second capacitor having a seventh terminal and an eighth terminal, the seventh terminal being coupled to the third terminal, and the eighth terminal receiving the reference voltage.

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