Error code testing equipment and signal rise / fall time correction method used therefor

Abstract

The present invention belongs to the technical field of signal rise / fall time correction, and specifically discloses a bit error test device and a signal rise / fall time correction method for the same. The signal rise / fall time correction method comprises: step S1: setting an input clock on a clock source according to the actual desired output signal; step S2: sequentially inputting the input clock in multiple channels into a pattern generator, a slope filter group, and an oscilloscope, wherein the oscilloscope displays and records the data of the rise / fall times of the multiple output signals; and step S3: using an enumeration method to compare the multiple channels of data one by one, determining a result for each channel so that the deviation between the channels is minimized, recording the parameters of the slope filter group corresponding to the minimum deviation, and setting the parameters in the corresponding slope filter group to achieve correction of the output signal rise / fall time. The present invention can solve the problem of difficulty in achieving consistency in signal rise / fall times between multiple transmission channels of a bit error test device.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal rise / fall time correction, and in particular relates to a bit error test device and a signal rise / fall time correction method used therefor. Background Art

[0002] Bit error test equipment measures the bit error rate of digital communication systems. Its primary function is to provide a test code source for transmission on the data link, receive downlink data from the data link, compare it with the test codebook, and display the system's bit error status in real time. Currently, most bit error test equipment on the market uses a multi-channel design to test the product under test.

[0003] The multi-channel signal quality of bit error rate test equipment generally includes numerous parameters such as rise / fall time, jitter, amplitude, rate accuracy and stability, and de-emphasis. The signal's rise time is the time it takes for a low-level signal to transition from a high-level state, while the signal's fall time is the time it takes for a high-level signal to transition from a low-level state. This is typically measured between 20% and 80% of the amplitude threshold. The rise / fall time of the output signal can affect the eye opening and closing of the device under test, thereby altering the bit error rate test results. Therefore, it is crucial to ensure that the rise / fall time of the signals across multiple transmit channels is strictly consistent. Summary of the Invention

[0004] The purpose of the present invention is to provide a bit error test device and a signal rise / fall time correction method therefor, so as to solve the problem that the rise / fall time of signals between multiple transmission channels of the bit error test device is difficult to reach consistency.

[0005] To achieve the above objectives, according to one aspect of the present application, a signal rise / fall time correction method for a bit error test device is provided, the signal rise / fall time correction method comprising:

[0006] Step S1: setting the input clock on the clock source according to the actual required output signal;

[0007] Step S2: inputting the input clocks in a multi-channel form into a pattern generator, a slope filter bank, and an oscilloscope in sequence, wherein the oscilloscope displays and records data of the rise / fall time of the multi-channel output signals;

[0008] Step S3: using an enumeration method to compare the multiple channels of data one by one, determining a result for each channel so that the deviation between the channels is minimized, recording the parameters of the slope filter group corresponding to the minimum deviation, and setting the parameters in the corresponding slope filter group to achieve correction of the rise / fall time of the output signal.

[0009] Furthermore, in step S3, the step of using the enumeration method to compare the multiple channels of data one by one and determining a result for each channel so as to minimize the deviation between the channels includes:

[0010] Calculate the variance of each data channel;

[0011] Compare the variances of each path;

[0012] The group with the smallest variance is determined as the group with the smallest deviation.

[0013] Further, in step S1, if the output signal is F, then the clock source is set to F / 2 of the output signal.

[0014] Furthermore, the output signal has a rate of 500Mb / s to 60Gb / s.

[0015] Furthermore, the output signal is four-way.

[0016] On the other hand, the present invention further provides a bit error test device, which is used to perform the above-mentioned signal rise / fall time correction method, and the bit error test device includes:

[0017] A clock source, the clock source being used to set an input clock according to an actual desired output signal;

[0018] A signal processing device, wherein there are multiple signal processing devices, each of which includes a graph generator, a slope filter group, and an oscilloscope, the graph generator is electrically connected to the slope filter group, the slope filter group is electrically connected to the oscilloscope, the signal processing device is used to receive the input clock, and the oscilloscope is used to display and record the rise / fall time of the output signal.

[0019] Furthermore, the bit error test equipment further includes a power distributor, which is used to distribute the input clock to the signal processing device in a multi-channel form.

[0020] Furthermore, the slope filter group includes 10 slope filters, the 10 slope filters are arranged in parallel, and each of the slope filters is selectively electrically connected to the pattern generator.

[0021] Furthermore, the slope filter is a low-pass filter.

[0022] Furthermore, the graphic generator includes an FPGA and a serializer electrically connected to each other, the FPGA is used to receive the input clock, process the input clock and transmit it to the serializer, and the serializer is used to process the signal transmitted by the FPGA and output the signal at a predetermined rate.

[0023] Applying the technical solution of the present invention, first, step S1 is performed: an input clock is set on a clock source according to the actual desired output signal. Then, step S2 is performed: the input clock is sequentially input in multiple channels to a pattern generator, a slope filter bank, and an oscilloscope, and the oscilloscope displays and records the data of the rise / fall times of the multiple output signals. Then, the 10 slope filters in the slope filter bank 22 are sequentially switched to obtain the rise / fall time of the signal passing through each slope filter. The data of the rise / fall time of the output signal is then displayed and recorded using an oscilloscope 23. Then, step S3 is performed: an enumeration method is used to compare the multiple channels of data one by one, a result is determined for each channel to minimize the deviation between the channels, the parameters of the slope filter bank corresponding to the minimum deviation are recorded, and the parameters are set in the corresponding slope filter bank to achieve correction of the output signal rise / fall time. Correction of the output signal rise / fall time to the actual desired output signal rise / fall time is achieved.

[0024] In other words, the bit rate test equipment can use 10 slope filters to independently correct the rise / fall time of the output signal of each channel, adapting to the signal rate range of 500Mb / s to 60Gb / s. It can achieve that the relative deviation of the signal rise / fall time between each channel after passing through the slope filter group output does not exceed 0.5 picoseconds. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 This is a flow chart of a signal rise and fall time correction method for a bit error test device disclosed in an embodiment of the present application;

[0027] Figure 2 It is a structural diagram of the bit error test equipment disclosed in the embodiment of this application.

[0028] Description of reference numerals:

[0029] 10. Clock source; 20. Signal processing device; 21. Graphics generator; 211. FPGA; 212. Serializer; 22. Slope filter bank; 30. Power divider. DETAILED DESCRIPTION

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are all in a very simplified form and are not to exact scale. They are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0031] It should be noted that, in order to clearly illustrate the contents of the present invention, the present invention specifically provides multiple embodiments to further illustrate different implementations of the present invention. These multiple embodiments are provided in an enumerated manner rather than an exhaustive manner. Furthermore, for the sake of brevity, the contents mentioned in the previous embodiments are often omitted in the subsequent embodiments. Therefore, for the contents not mentioned in the subsequent embodiments, reference may be made to the previous embodiments accordingly.

[0032] See also Figure 1 and Figure 2 As shown, according to an embodiment of the present application, a signal rise / fall time correction method for a bit error test device is provided, and the signal rise / fall time correction method includes:

[0033] Step S1: setting an input clock on the clock source 10 according to the actual required output signal.

[0034] In this step, the frequency of the input clock is set based on the output signal rate. If the output signal rate is F, the frequency of the input clock on clock source 10 is F / 2 of the output signal. This is set based on the type of clock source 10. Of course, other types of clock sources 10 can also be selected to set the input clock frequency. For example, for one type of clock source 10: if the desired output signal rate is F, the frequency of the input clock on clock source 10 is F. Any device that can provide an input clock is within the scope of protection of this application.

[0035] Specifically, the output signal rate described in this embodiment is 500Mb / s to 60Gb / s, for example, 500Mb / s, 600Mb / s, 2Gb / s, 20Gb / s, and 60Gb / s, which greatly increases the selection range of output signals.

[0036] Specifically, clock source 10 is used to provide a frequency-stable, level-matched square wave clock pulse signal to the ring pulse generator. This application utilizes clock source 10 to provide the processing clock, i.e., the input clock. This simple structure facilitates implementation and reduces the cost of implementing a signal rise / fall time correction method for error testing equipment.

[0037] Step S2: Multiple input clocks are sequentially input to the pattern generator 21, the slope filter bank 22, and the oscilloscope. After being processed by the pattern generator 21 and the slope filter bank 22, the input clocks are displayed and recorded on the oscilloscope (not shown) to obtain data on the rise and fall times of the multiple output signals.

[0038] In this step, the input clock is fed into pattern generator 21 in multiplexed form. Pattern generator 21 receives the clock and transmits it as a signal to slope filter bank 22. Slope filter bank 22 receives the signal and sequentially switches the slope filters in the bank to obtain the rise and fall times of the signal passing through each slope filter. The rise and fall time data of the output signal is then displayed and recorded using an oscilloscope.

[0039] Taking the example of obtaining four output signals with an output signal rate of F, the specific operations are as follows:

[0040] First, set the input clock of clock source 10 to F / 2 and distribute it to pattern generator 21 in four paths via a four-way power divider. Pattern generator 21 in the first path now generates an output signal at a rate of F, which is then transmitted to slope filter bank 22 in the first path. The ten slope filters in slope filter bank 22 are switched sequentially and connected to an oscilloscope. The rise and fall times of the signal passing through each slope filter are recorded.

[0041] The pattern generator 21 in the second path generates an output signal at a rate F. This output signal at a rate F is transmitted to the slope filter bank 22 in the second path. The ten slope filters in this slope filter bank 22 are switched sequentially and connected to an oscilloscope. The rise and fall times of the signal passing through each slope filter are recorded.

[0042] The pattern generator 21 in the third path generates an output signal at a rate F. This output signal at a rate F is transmitted to the slope filter bank 22 in the third path. The ten slope filters in this slope filter bank 22 are switched sequentially and connected to an oscilloscope. The rise and fall times of the signals passing through each slope filter are recorded.

[0043] Pattern generator 21 in the fourth path generates an output signal at a rate F. This output signal at a rate F is transmitted to slope filter bank 22 in the fourth path. The ten slope filters in slope filter bank 22 are switched sequentially and connected to an oscilloscope. The rise and fall times of the signal passing through each slope filter are recorded.

[0044] Step S3: Use the enumeration method to compare multiple channels of data one by one, determine a result for each channel so that the deviation between the channels is minimized, record the parameters of the slope filter group 22 corresponding to the minimum deviation, and set the parameters in the corresponding slope filter group 22 to achieve correction of the output signal rise / fall time.

[0045] In step S3, the steps of comparing multiple channels of data one by one using an enumeration method and determining a result for each channel so as to minimize the deviation between the channels include:

[0046] Calculate the variance of each data channel;

[0047] Compare the variances of each path;

[0048] The group with the smallest variance is determined to have the smallest deviation.

[0049] Taking the data in step S2 as an example, the specific operations are as follows:

[0050] According to step S2, data of four output signals can be obtained. Each channel has ten data of output signal rise / fall time, so the four channels have a total of forty data of output signal rise / fall time.

[0051] There are 10 possible choices for any data in the first path, 10 possible choices for any data in the second path, 10 possible choices for any data in the third path, and 10 possible choices for any data in the fourth path. There are a total of 10,000 combinations of the four paths.

[0052] For example, select the first data point in the first channel, the first data point in the second channel, the first data point in the third channel, and the first data point in the fourth channel, and calculate the variance of these four data points. Select the second data point in the first channel, the first data point in the second channel, the first data point in the third channel, and the first data point in the fourth channel, and so on. Using the enumeration method, we need to calculate 10,000 variances. Compare these 10,000 variances one by one, and the group with the smallest variance is determined to have the smallest deviation.

[0053] At this time, the parameters of the slope filter group 22 corresponding to the group with the smallest variance are recorded and then set in the corresponding slope filter group, so as to achieve the correction of the rise / fall time of the output signal with a rate of F.

[0054] Specifically, the enumeration method uses the characteristics of computer's fast computing speed and high precision to test all possible situations to solve the problem without missing any one, and find the answer that meets the requirements. Therefore, the result obtained by the enumeration method is definitely correct.

[0055] In this embodiment, the output signal is set to four channels. If it is set to two or three channels, the data is too little and the final measurement result may not be very accurate. If it is set to eight or even sixteen channels, according to the enumeration method mentioned above, it can be seen that there is too much data, the operation is too troublesome, and unnecessary time is wasted.

[0056] From the above description we can know:

[0057] Using the signal rise / fall time correction method for bit error rate test equipment disclosed herein, the bit error rate test equipment can use a clock source 10 to set an input clock based on the actual desired output signal. This input clock is sequentially input in multiple channels to a pattern generator 21, a slope filter bank 22, and an oscilloscope. The 10 slope filters in the slope filter bank 22 are then switched sequentially to obtain the rise / fall time of the signal passing through each slope filter. The oscilloscope then displays and records the rise / fall time data of the output signal. An enumeration method is then used to compare the multiple channels of data one by one, determining a result for each channel that minimizes the deviation between the channels. The parameters of the slope filter bank 22 corresponding to the minimum deviation are recorded and set in the corresponding slope filter bank 22 to achieve correction of the output signal rise / fall time.

[0058] In other words, the bit error test equipment can use 10 slope filters to independently correct the rise / fall time of each output signal, adapting to the signal rate range of 500Mb / s to 60Gb / s. After passing through the slope filter group, the relative deviation of the signal rise / fall time between each channel can be reduced to no more than 0.5 picosecond.

[0059] Combine Figure 1 and Figure 2 As shown, an embodiment of the present application further provides a bit error test device, which is used to perform the signal rise / fall time correction method in the above embodiment. The bit error test device includes a clock source 10 and a signal processing device 20. The clock source 10 is used to set the input clock according to the actual required output signal; there are multiple signal processing devices 20, each of which includes a pattern generator 21 and a slope filter group 22; the pattern generator 21 is electrically connected to the slope filter group 22, and the slope filter group 22 is electrically connected to an oscilloscope. The signal processing device 20 is used to receive the input clock, and the oscilloscope (not shown in the figure) is used to display and record the output signal rise / fall time.

[0060] In actual operation, an input clock is first set on clock source 10 based on the desired output signal, and this input clock is then received by signal processing device 20. Since signal processing device 20 includes a pattern generator 21 and a slope filter bank 22, after the input clock passes through pattern generator 21 and the filter bank, an output signal is generated, and the rise / fall time of the signal is obtained. At this point, an oscilloscope can be used to display and record the rise / fall time of the signal. Furthermore, in this embodiment, multiple signal processing devices 20 are provided, meaning that the signal processing device 20 can receive input clocks in a multi-channel manner.

[0061] In other words, the present application utilizes clock source 10 to set an input clock based on the desired output signal and transmits this input clock to multiple pattern generators 21 and slope filter bank 22. After passing through these multiple pattern generators 21 and slope filter bank 22, the input clock outputs a signal, and the signal's rise / fall time is obtained. At this point, the signal's rise / fall time can be displayed and recorded using an oscilloscope, thereby obtaining the desired output signal rise / fall time.

[0062] Specifically, to distribute the input clock to the signal processing devices 20 in multiple channels, this embodiment also includes a power divider 30. This device splits the energy of one input signal into two or more output channels of equal or unequal energy. In this embodiment, the power divider 30 distributes the input clock to the signal processing devices 20 in multiple channels with equal energy. This ensures that the input clock frequencies received by the multiple signal processing devices 20 are the same, ultimately resulting in the same rate for the multiple output signals.

[0063] Specifically, slope filter bank 22 includes 10 slope filters, each of which is arranged in parallel, and each of which is selectively electrically connected to pattern generator 21. The 10 slope filters are arranged in parallel to facilitate independent switching of the slope filters. Each slope filter is selectively electrically connected to pattern generator 21. In actual use, the 10 slope filters are switched sequentially to obtain the rise / fall time of the signal passing through each slope filter. This facilitates recording using an oscilloscope and reduces confusion.

[0064] Furthermore, the oscilloscope can be selected to be single-channel, dual-channel or multi-channel. The specific selection is made according to actual use and is not specifically limited in this application.

[0065] Optionally, the oscilloscope may be a high-speed oscilloscope.

[0066] Specifically, the slope filters are low-pass filters. Each low-pass filter has a bandwidth of 50 GHz, resulting in a passband loss step of 0.1 dB for the entire slope filter bank. After a signal passes through the low-pass filters and is output, the relative deviation of the output signal's rise / fall time does not exceed 0.5 picoseconds.

[0067] Specifically, the pattern generator 21 includes an FPGA 211 and a serializer 212 electrically connected to each other. The FPGA 211 is configured to receive and process the input clock from the clock source 10, and transmit the processed input clock as a signal to the serializer 212. The serializer 212 is configured to process the signal transmitted by the FPGA 211 so that the signal is output at a predetermined rate.

[0068] Furthermore, multiple serializers 212 can be provided. FPGA 211 is electrically connected to multiple serializers 212, and multiple serializers are electrically connected to each other, to convert multiple signals into a single, higher-speed signal through parallel-to-serial conversion. This allows output signals to be selected within the range of 500 Mb / s to 60 Gb / s, for example, 500 Mb / s, 600 Mb / s, 2 Gb / s, 20 Gb / s, and 60 Gb / s, thus increasing the range of output signal options.

[0069] Furthermore, FPGA 211, or Field Programmable Logic Array, is a new type of high-performance programmable logic device developed based on CPLD. It generally utilizes an SRAM process, though some specialized devices utilize Flash or anti-fuse processes. FPGA 211 has a high level of integration, with device densities ranging from tens of thousands to tens of millions of system gates. It can perform extremely complex sequential and combinational logic circuit functions and is suitable for high-speed, high-density, high-end digital logic circuit design. This application utilizes FPGA 211 to receive an input clock and output a signal.

[0070] Furthermore, the serializer 212 is an interface circuit in high-speed data communication. The serializer 212 is very common in the field of high-speed data communication and is used to perform parallel-to-serial conversion on multiple input signals to synthesize a higher-speed signal.

[0071] From the above description we can know:

[0072] With the bit error test equipment of the present application, an input clock can be set at the clock source 10 according to the actual required output signal. This input clock is distributed in multiple channels to the signal processing device 20 using a power divider 30. The FPGA 211 in the signal processing device 20 receives the input clock from the clock source 10 and processes it. The processed input clock is transmitted as a signal to the serializer 212. The serializer 212 processes the signal transmitted by the FPGA 211 so that the signal is transmitted to the slope filter bank 22 at the actual required rate.

[0073] When the slope filter bank 22 receives a signal, the slope filter bank in this embodiment includes 10 slope filters, each of which is connected in parallel, allowing for easy and independent switching of the slope filters. Each slope filter can also be selectively electrically connected to the pattern generator 21. In actual use, the 10 slope filters can be switched sequentially to obtain the rise / fall time of the signal passing through each slope filter. This facilitates recording and reduces confusion.

[0074] Thereafter, the rise / fall time of the signal passing through each slope filter is shown and recorded using an oscilloscope.

[0075] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0076] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.

[0077] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A signal rise / fall time correction method for a bit error test device, characterized in that: include: Step S1: using a clock source to set an input clock on a clock source (10) according to an actual required output signal; Step S2: using a power distributor (30) to distribute the input clock to a signal processing device (20) in a multi-channel form, using the signal processing device (20) to receive the input clock, and allowing the input clock to be sequentially input in a multi-channel form to a pattern generator (21), a slope filter group (22), and an oscilloscope, wherein the pattern generator (21) is electrically connected to the slope filter group (22), the slope filter group (22) is electrically connected to the oscilloscope, and the oscilloscope displays and records data on the rise / fall time of the multi-channel output signals; Step S3: using a computer to compare the multiple channels of data one by one using an enumeration method, determining a result for each channel so that the deviation between the channels is minimized, recording the parameters of the slope filter group (22) corresponding to the minimum deviation, and setting the parameters in the corresponding slope filter group (22) to achieve correction of the rise / fall time of the output signal.

2. The signal rise / fall time correction method according to claim 1, characterized in that: In step S3, the step of using the enumeration method to compare the multiple channels of data one by one and determining a result for each channel so as to minimize the deviation between the channels includes: Calculate the variance of each data channel; Compare the variances of each path; The group with the smallest variance is determined as the group with the smallest deviation.

3. The signal rise / fall time correction method according to claim 1, wherein: In the step S1, if the output signal is F, the clock source (10) is set to F / 2 of the output signal.

4. The signal rise / fall time correction method according to claim 3, wherein: The output signal has a rate of 500Mb / s to 60Gb / s.

5. The signal rise / fall time correction method according to claim 1, wherein: There are four output signals.

6. A bit error test device, characterized in that: The bit error test device is used to perform the signal rise / fall time correction method according to any one of claims 1 to 5, and the bit error test device includes: A clock source (10), the clock source (10) being used to set an input clock according to an actual required output signal; A signal processing device (20), wherein there are a plurality of signal processing devices (20), each of the signal processing devices (20) comprises a pattern generator (21) and a slope filter group (22), wherein the pattern generator (21) is electrically connected to the slope filter group, and the slope filter group (22) is electrically connected to an oscilloscope, wherein the signal processing device (20) is used to receive the input clock, and the oscilloscope is used to display and record the rise / fall time of the output signal.

7. The bit error test equipment according to claim 6, characterized in that: The error code testing device further comprises a power distributor (30), and the power distributor (30) is used to distribute the input clock to the signal processing device (20) in a multi-channel form.

8. The bit error test equipment according to claim 6, characterized in that: The slope filter group (22) includes 10 slope filters, the 10 slope filters are arranged in parallel, and each of the slope filters is selectively electrically connected to the pattern generator (21).

9. The bit error test equipment according to claim 8, characterized in that: The slope filter is a low-pass filter.

10. The bit error test equipment according to claim 6, characterized in that: The graphic generator (21) includes an FPGA (211) and a serializer (212) electrically connected to each other. The FPGA (211) is used to receive the input clock, process the input clock, and transmit the clock to the serializer (212). The serializer (212) is used to process the signal transmitted by the FPGA (211) and output the signal at a predetermined rate.

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