Linear array image sensor chip and image sensor

Abstract

The application provides a linear array image sensor chip, which comprises a photosensitive unit, a signal storage unit, a signal transmission unit and a timing control unit, wherein the photosensitive unit comprises N photosensitive pixel subunits; the signal storage unit comprises N signal storage subunits, and the N photosensitive pixel subunits are connected with the N signal storage subunits respectively; the signal transmission unit comprises a first signal transmission subunit and N first transmission switches, and the N signal storage subunits are connected with the first signal transmission subunit through the N first transmission switches respectively; the timing control unit is connected with the signal transmission unit, and the timing control unit comprises a row start signal pin, a clock signal pin, a transmission control signal pin, a cascade start input signal pin and a cascade start output signal pin, so that the parasitic capacitance on the line during signal transmission can be reduced, and the technical effect of improving the strength of effective signals can be achieved.

Description

Technical Field

[0001] This invention relates to the field of image sensing, and more specifically, to a linear array image sensor chip and an image sensor. Background Technology

[0002] Linear image sensors are widely used in modern industrial inspection. Their core component is the linear image sensor chip, which has linearly arranged photosensitive pixels. After the photosensitive pixels sense light, they convert the light signal into an electrical signal, amplify it initially, and store it. Then, the timing control circuit controls all the pixels to be connected to a common signal line in sequence through shift switches. Finally, the signal is amplified by the final stage amplifier and output serially.

[0003] With the development of technology, the industrial inspection field demands increasingly higher accuracy and speed from image sensors, meaning higher resolution and faster scanning speeds. Increased resolution means a greater number of photosensitive pixels arranged on a linear image sensor chip of the same length. This leads to two problems: Firstly, the increased number of shift switches connected to the common signal lines increases the parasitic capacitance on these lines, reducing the strength of the effective signal. Secondly, increased parasitic capacitance also affects the fastest signal transmission speed. Summary of the Invention

[0004] The main objective of this invention is to provide a linear image sensor chip 1 to solve the problem of excessive parasitic capacitance on the common signal line in the prior art, which reduces the strength of the effective signal.

[0005] To achieve the above objectives, according to one aspect of the present invention, a linear array image sensor chip 1 is provided, comprising: a photosensitive unit 101, a signal storage unit 102, a signal transmission unit 103, and a timing control unit 104, wherein the photosensitive unit 101 includes N photosensitive pixel sub-units; the signal storage unit 102 includes N signal storage sub-units, and the N photosensitive pixel sub-units are respectively connected to the N signal storage sub-units; the signal transmission unit 103 includes a first signal transmission sub-unit and N first transmission switches, and the N signal storage sub-units are respectively connected to the first signal transmission sub-unit through the N first transmission switches; the timing control unit 104 is connected to the signal transmission unit, and the timing control unit 104 includes a row start signal pin FS, a clock signal pin CLK, a transmission control signal pin MODE, a cascade start input signal pin SI, and a cascade start output signal pin SO.

[0006] Furthermore, the signal transmission unit 103 also includes N-1 second signal transmission sub-units and N-1 second transmission switches. The N-1 signal storage sub-units are respectively connected to one end of the N-1 second transmission switches, and the other end of the N-1 second transmission switches are respectively connected to the N-1 second signal transmission sub-units. The N-1 signal storage sub-units are any N-1 signal storage sub-units among the N signal storage sub-units.

[0007] Furthermore, the signal transmission subunit includes an amplifier and a signal transmission pin, wherein the signal transmission subunit includes a first signal transmission subunit and a second signal transmission subunit.

[0008] According to another aspect of the present invention, an image sensor is provided, comprising any of the above-described linear image sensor chips 1.

[0009] Furthermore, the image sensor also includes: a substrate, a frame, an optical lens, a light source, and a socket interface; wherein, the optical lens is disposed above the photosensitive window of the linear image sensor chip 1; the light source is disposed on the side of the optical lens; and the socket interface is connected to the linear image sensor chip 1 and the light source.

[0010] Furthermore, the image sensor includes multiple linear image sensor chips 1.

[0011] Furthermore, multiple linear image sensor chips 1 are arranged linearly.

[0012] Furthermore, multiple linear image sensor chips 1 are connected in parallel.

[0013] Furthermore, multiple linear array image sensor chips 1 are cascaded in a linear arrangement, and the cascade start output signal pin SO of the previous stage chip in the multiple linear array image sensor chips 1 is connected to the cascade start input signal pin SI of the next stage chip.

[0014] Furthermore, each of the multiple linear array image sensor chips 1 includes multiple signal transmission pins, and each of the multiple signal transmission pins of the multiple linear array image sensor chips 1 independently outputs a signal.

[0015] Applying the technical solution of this invention, the linear array image sensor chip 1 of this invention includes a photosensitive unit 101, a signal storage unit 102, a signal transmission unit 103, and a timing control unit 104. The photosensitive unit 101 includes N photosensitive pixel sub-units; the signal storage unit 102 includes N signal storage sub-units, and the N photosensitive pixel sub-units are respectively connected to the N signal storage sub-units; the signal transmission unit 103 includes a first signal transmission sub-unit and N first transmission switches, and the N signal storage sub-units are respectively connected to the first signal transmission sub-unit through the N first transmission switches; the timing control unit 104 is connected to the signal transmission unit and includes a row start signal pin FS, a clock signal pin CLK, a transmission control signal pin MODE, a cascade start input signal pin SI, and a cascade start output signal pin SO. This reduces parasitic capacitance on the lines during signal transmission, thereby achieving the technical effect of improving the strength of the effective signal. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0017] Figure 1 A schematic diagram of the overall structure of a linear image sensor chip provided according to an embodiment of the present invention is shown;

[0018] Figure 2 A schematic diagram of a linear image sensor chip according to an optional embodiment of the present invention is shown;

[0019] Figure 3 A timing diagram of dual-channel serial output of a linear image sensor chip according to an optional embodiment of the present invention is shown;

[0020] Figure 4 A timing diagram of a single-channel serial output of a linear image sensor chip according to an optional embodiment of the present invention is shown;

[0021] Figure 5 A schematic diagram of an image sensor structure constructed by cascading linear array image sensor chips according to an optional embodiment of the present invention is shown.

[0022] Figure 6 A schematic diagram of an image sensor structure consisting of parallel linear array image sensor chips provided by an optional embodiment of the present invention is shown.

[0023] The above figures include the following reference numerals:

[0024] 1. Linear image sensor chip; 101. Photosensitive unit; 102. Signal storage unit; 103. Signal transmission unit; 104. Timing control unit; PD. Photodiode; AMP. Amplifier; Ct. Storage capacitor; FS. Horizontal start signal pin; CLK. Clock signal pin; MODE. Transmission control signal pin; SI. Cascade start input signal pin; SO. Cascade start output signal pin; SIG. Transmission signal pin. Detailed Implementation

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0028] Figure 1 A schematic diagram of the overall structure of an embodiment of the linear array image sensor chip according to the present invention is shown, as follows. Figure 1As shown, the present invention provides a linear array image sensor chip, comprising:

[0029] The linear array image sensor chip of the present invention includes a photosensitive unit 101, a signal storage unit 102, a signal transmission unit 103, and a timing control unit 104. The photosensitive unit 101 includes N photosensitive pixel sub-units; the signal storage unit 102 includes N signal storage sub-units, and the N photosensitive pixel sub-units are respectively connected to the N signal storage sub-units; the signal transmission unit 103 includes a first signal transmission sub-unit and N first transmission switches, and the N signal storage sub-units are respectively connected to the first signal transmission sub-unit through the N first transmission switches; the timing control unit 104 is connected to the signal transmission unit and includes a row start signal pin FS, a clock signal pin CLK, a transmission control signal pin MODE, a cascade start input signal pin SI, and a cascade start output signal pin SO. This reduces parasitic capacitance on the lines during signal transmission, thereby improving the strength of the effective signal.

[0030] Specifically, in existing technologies, all electrical signals generated by photosensitive pixels converge into a single common line and are output from the same signal transmission subunit. In this case, the parasitic capacitance on the common line affects the strength of the effective signal of each signal flowing through it. The linear array image sensor chip provided in this solution divides the input signal transmission unit's lines into N lines. Each line can connect to one photosensitive pixel subunit and one signal storage subunit. Each photosensitive pixel subunit can include one or more photosensitive pixels. Each line has a first transmission switch, with its two ends connected to the signal storage subunit and the first signal transmission unit on that line, respectively. Therefore, by opening and closing the first transmission switch, a line can be controlled to only establish an electrical connection with the first signal transmission subunit when transmitting a signal. When no signal is being transmitted on a line, its connection to the first signal transmission subunit is disconnected. Thus, for each transmitting electrical signal, the parasitic capacitance affecting its effective signal is only the parasitic capacitance of one line. Compared to existing technologies, this solution effectively reduces the parasitic capacitance on the lines during signal transmission, thereby improving the strength of the effective signal. It should be noted that, as... Figure 1 In the illustrated scheme, N is 2, and the photosensitive unit is divided into two sub-units. Photosensitive pixels PIX1-PIX432 form one photosensitive pixel sub-unit, and PIX433-PIX854 form the other photosensitive pixel sub-unit. The signal storage unit and the signal transmission unit are also divided into two sub-units. The two photosensitive pixel sub-units are connected to the two signal storage sub-units, and the two signal storage sub-units are connected to the two signal transmission sub-units. This is only one specific implementation of the present invention and does not limit N to other values.

[0031] Furthermore, the signal transmission unit 103 also includes N-1 second signal transmission sub-units and N-1 second transmission switches. The N-1 signal storage sub-units are respectively connected to one end of the N-1 second transmission switches, and the other end of the N-1 second transmission switches are respectively connected to the N-1 second signal transmission sub-units. The N-1 signal storage sub-units are any N-1 signal storage sub-units among the N signal storage sub-units.

[0032] Furthermore, the signal transmission subunit includes an amplifier and a signal transmission pin, wherein the signal transmission subunit includes a first signal transmission subunit and a second signal transmission subunit.

[0033] Specifically, the signal transmission unit of the linear array image sensor chip provided by this invention may include multiple signal transmission subunits, each of which may include an amplifier and a signal transmission pin. The linear array image sensor chip provided in this optional embodiment can provide a mode where multiple lines simultaneously output signals. Among the N signal transmission subunits, one signal transmission subunit may be special. This signal transmission subunit establishes a circuit connection with each of the N signal storage subunits. Each of the circuits established between this signal transmission subunit and each of the N signal storage subunits has a second transmission switch. This special signal transmission subunit is the first signal transmission subunit. Simultaneously, among the N signal storage subunits, there is also a special signal storage subunit, namely the one that is not connected to any of the N-1 second signal transmission subunits. Of the N signal transmission subunits, all except the first signal transmission subunit are second signal transmission subunits. N-1 second signal transmission subunits are connected one-to-one with N-1 signal storage subunits via N-1 second transmission switches. Simultaneously, each of the N signal storage subunits is connected to the first signal transmission subunit via N first transmission switches. In summary, among the N signal storage subunits, there is one special signal storage subunit that is connected to the first signal transmission subunit only via one first transmission switch and not to any other signal transmission subunits. The other N-1 signal storage subunits are connected one-to-one with the N-1 second signal transmission subunits via N-1 second transmission switches, and simultaneously, the other N-1 signal storage subunits are connected to the first signal transmission subunit via corresponding N-1 first transmission switches.

[0034] In the mode where the linear array image sensor chip outputs signals simultaneously through multiple lines, N-1 second transmission switches are closed, and the special first transmission switch connecting the special signal storage subunit and the first signal transmission subunit among the N first transmission switches is closed, while the remaining N-1 first transmission switches are open. This connects the circuits of the N-1 second signal transmission subunits and the N-1 signal storage subunits, and disconnects the circuits of the N-1 second signal storage subunits and the first signal transmission subunits. At this time, data from the N signal storage units can be output simultaneously through the N signal transmission subunits, significantly increasing the signal transmission rate compared to existing technologies. In the mode where the linear array image sensor chip outputs signals sequentially through a single line, N-1 second transmission switches are open, and the N first transmission switches are closed sequentially. This connects the N signal storage units sequentially to the first signal transmission subunits. Compared to existing technologies, when each signal storage subunit transmits data to the first signal transmission subunit, the parasitic capacitance in the circuit is significantly reduced, effectively improving signal strength and enhancing the sensitivity of the linear array image sensor chip.

[0035] As a specific implementation, N can be 2. Figure 1 A schematic diagram of the overall structure of a linear image sensor chip according to an embodiment of the present invention is shown, as follows. Figure 1 The diagram shows a functional block diagram of a linear array image sensor chip, including a photosensitive unit 101 for converting light signals into electrical signals and performing preliminary amplification; the photosensitive unit has 864 photosensitive pixels spaced at 1200 DPI resolution within an 18.3 mm length range, each photosensitive pixel being 20*20 μm in size; a signal storage unit 102 for storing the preliminary amplified voltage signals of each pixel; and a signal transmission unit 103 for sequentially amplifying and outputting the voltage signals corresponding to each pixel in the storage unit, including two output ports: a transmission signal pin SIG1 and a transmission signal pin SIG2. Signal pin SIG2; Timing control unit 104, used to receive external clock signals and generate internal switch control timing. The input signal pins of the timing control unit include: cascade start input signal pin SI, line start signal pin FS, clock signal pin CLK, single / dual output selection signal pin MODE. The output signal pins of the timing control unit include cascade start output signal pin SO, and various switch signals used for internal timing. Here, a photodiode can also be called a photosensitive pixel, because the signal output by a photodiode is the pixel value of a pixel in the image.

[0036] Figure 2 A schematic diagram of a linear image sensor chip according to an optional embodiment of the present invention is shown, such as... Figure 2As shown, N can be 2. PD1 to PD864 are photodiodes in the photosensitive unit, and AMP1 to AMP864 are the initial amplifiers in the photosensitive unit. The photodiodes in the photosensitive unit are connected to the initial amplifiers respectively. The photodiodes and the initial amplifiers can be connected to the reference voltage Vref through the reset switch Sr. PD1 to PD432 are connected to AMP1 to AMP432 respectively to form a photosensitive pixel sub-unit. PD433 to PD864 are connected to AMP433 to AMP864 respectively to form another photosensitive pixel sub-unit. Ct1 to Ct864 are storage capacitors in the signal storage unit. The initial amplifier is connected to the storage capacitors through the storage switch St. The storage capacitors Ct1 to Ct432 and the shift switches sch_1 to sch_432 form a signal storage sub-unit. In this unit, storage capacitors Ct1 to Ct432 are connected to the front common signal line L1 via shift switches sch_1 to sch_432, respectively. Storage capacitors Ct433 to Ct864 and shift switches sch_433 to sch_864 constitute another signal storage sub-unit. Storage capacitors Ct433 to Ct864 are connected to the rear common signal line L2 via shift switches sch_433 to sch_864, respectively. The front and rear common signal lines are independent of each other. The parasitic capacitance of each common signal line is reduced by half compared to the parasitic capacitance of the common signal line when using the same common signal line. The final stage amplifier AMP_1 and the transmission signal pin SIG1 constitute a signal transmission sub-unit, and the final stage amplifier AMP_2 and the transmission signal pin SIG2 constitute another signal transmission sub-unit.The front-end common signal line is connected to the final stage amplifier AMP_1 via switch K1. The single-pole double-throw switch K1 can be considered a regular switch, i.e., a first transmission switch. When this first transmission switch is closed, the front-end common signal line is connected to the final stage amplifier AMP_1, meaning the first signal storage subunit is connected to the first signal transmission subunit. When this first transmission switch is open, the front-end common signal line is disconnected from the final stage amplifier AMP_1, meaning the first signal storage subunit is disconnected from the first signal transmission subunit. The rear-end common signal line can be connected to either the final stage amplifier AMP_1 or the final stage amplifier AMP_2 via switch K2. The single-pole double-throw switch K2 can... Consider these as two ordinary switches: one is a first transmission switch connecting the front-end common signal line to the final stage amplifier AMP_1, and the other is a second transmission switch connecting the rear-end common signal line to the final stage amplifier AMP_2. When the first transmission switch is closed and the second transmission switch is open, the rear-end common signal line is connected to the final stage amplifier AMP_1 and disconnected from the final stage amplifier AMP_2. In other words, the second signal storage subunit is connected to the first signal transmission subunit. When the first transmission switch is open and the second transmission switch is closed, the rear-end common signal line is connected to the final stage amplifier AMP_2 and disconnected from the final stage amplifier AMP_1. In other words, the second signal storage subunit is connected to the second signal transmission subunit. By combining switching switches K1 and K2, the output can be configured to either be a single-channel serial output through the final stage amplifier AMP_1 or a dual-channel serial output through both final stage amplifiers AMP_1 and AMP_2. The switching sequence of the reset switch Sr, storage switch St, shift switches sch_1 to sch_864, and switching switches K1 and K2 is generated by the timing control unit based on the input signals FS, SI, CLK, and MODE.

[0037] Figure 3A timing diagram of a dual-channel serial output linear array image sensor chip according to an optional embodiment of the present invention is shown. The operation of the linear array image sensor chip is as follows: After the pulse of the signal in the row start signal pin FS arrives, the timing control unit controls the reset switch Sr to close, initializes each photodiode, and then opens the reset switch Sr. The photodiodes begin to receive external light for exposure and perform primary amplification. After a period of exposure, the timing control unit controls the storage switch St to close, storing the initially amplified voltage of each photosensitive pixel in its corresponding capacitor. Then the storage switch St is opened. The timing control unit determines whether the output is a dual-channel serial output or a single-channel serial output based on the high or low level of the signal in the transmission control signal pin MODE. When the signal in the MODE pin is high, the chip can be set to dual-channel serial output. Switch K1 connects to the final stage amplifier AMP_1, and switch K2 connects to the final stage amplifier AMP_2. At this time, the timing control unit controls shift switches sch_1 and sch_433 to close and then open simultaneously. The voltage stored in Ct1 is amplified and output by the final stage amplifier AMP_1 after passing through the front common signal line L1, and the voltage stored in Ct433 is amplified and output by the final stage amplifier AMP_2 after passing through the rear common signal line L2. Then, the timing control unit controls the shift switches... After shift switches sch_2 and sch_434 are simultaneously closed and then opened, the voltage stored in Ct2 is amplified and output by the final stage amplifier AMP_1 after passing through the front common signal line L1. Simultaneously, the voltage stored in Ct434 is amplified and output by the final stage amplifier AMP_2 after passing through the rear common signal line L2. The timing control unit sequentially controls the two shift switches to close and then open simultaneously until the last two shift switches sch_432 and sch_864 are closed and then opened, completing the signal output for all 864 photosensitive pixels. The dual-channel serial output timing is as follows: Figure 3 As shown, where l = 432 and m = 648. In this embodiment, the common signal line is divided into two equal parts, a front segment and a rear segment. The parasitic capacitance on each segment of the common signal line is reduced to half of its original value, which can increase the highest frequency of signal transmission. Furthermore, when the shift switch is activated to turn on the storage capacitor for final stage amplification, the charge loss of the storage capacitor on the common signal line is halved, thus improving the strength of the effective signal. All photosensitive pixels are simultaneously serially output through two channels. At the same clock frequency, the output time of all photosensitive pixels is halved, improving the scanning speed.

[0038] Figure 4This diagram illustrates a single-channel serial output timing diagram for a linear array image sensor chip according to an optional embodiment of the present invention. Optionally, when it is not necessary to increase the chip scanning speed, to reduce the number of channels in the subsequent parallel analog-to-digital converter, the signal in the transmission control signal pin MODE can be set to a low level, and the chip is in single-channel serial output mode. Switch K1 is turned on by the final stage amplifier AMP_1, and switch K2 is turned on by the final stage amplifier AMP_2. The timing control unit controls the shift switch sch_1 to close and then open, so that the voltage stored in Ct1 is amplified and output by the final stage amplifier AMP_1 after passing through the front common signal line L1. Then, the shift switch sch_2 is controlled to close and then open, so that the voltage stored in Ct2 is amplified and output by the final stage amplifier AMP_1 after passing through the front common signal line L1. The shift switches are controlled sequentially until the shift switch sch_432 is controlled to close and then open, so that Ct1 is amplified and output by the final stage amplifier AMP_1. The voltage stored in t432 is amplified and output by the final stage amplifier AMP_1 after passing through the front-end common signal line L1, completing the output of the first half of the photosensitive pixels. At this time, the timing control unit controls the switch K1 to be floating, and K2 to be connected to the final stage amplifier AMP_1. Simultaneously, it controls the shift switch sch_433 to close and then open, allowing the voltage stored in t433 to pass through the rear-end common signal line L2 and be amplified and output by the final stage amplifier AMP_1. Then, it controls the shift switch sch_434 to close and then open, allowing the voltage stored in t434 to pass through the rear-end common signal line L2 and be amplified and output by the final stage amplifier AMP_1. This process continues until finally controlling the shift switch sch_864 to close and then open, allowing the voltage stored in t864 to pass through the rear-end common signal line L2 and be amplified and output by the final stage amplifier AMP_1, completing the output of all 864 photosensitive pixels. The single-channel serial output timing is as follows: Figure 4 As shown, where n = 864. This single-channel serial output mode also divides the common signal line into two equal parts, the front and the back. The parasitic capacitance on each common signal line is reduced to half of its original value, which can increase the highest frequency of signal transmission. Furthermore, when the shift switch is turned on to activate the storage capacitor for final stage amplification, the charge loss of the storage capacitor on the common signal line is halved, thus improving the strength of the effective signal.

[0039] According to another aspect of the present invention, an image sensor is provided, comprising any of the above-described linear array image sensor chips. Further, the image sensor further includes: a substrate, a frame, an optical lens, a light source, and a socket interface; wherein the optical lens is disposed above the photosensitive window of the linear array image sensor chip; the light source is disposed on the side of the optical lens; and the socket interface is connected to the linear array image sensor chip and the light source.

[0040] Furthermore, the image sensor includes multiple linear image sensor chips. These chips are arranged linearly. They are also connected in parallel. Finally, they are cascaded in a linear arrangement, with the cascade start output signal pin SO of the preceding chip connected to the cascade start input signal pin SI of the following chip.

[0041] Figure 5 A schematic diagram of an image sensor structure constructed by cascading linear image sensor chips according to an optional embodiment of the present invention is shown, as follows: Figure 5As shown, this invention provides an image sensor, including a PCB substrate 2. Three linear array image sensor chips 1 are disposed on the PCB substrate. The image sensor chips are linearly arranged, and the row start signal pin FS, clock signal pin CLK, transmission signal control pin MODE, transmission signal pin SIG1, and transmission signal pin SIG2 of the three chips are respectively connected. The cascade start input signal pin SI of the first chip is left floating, and the cascade start output signal pin SO is connected to the cascade start input signal pin SI of the second chip. The cascade start output signal pin SO of the second chip is connected to the cascade start input signal pin SI of the third chip, and the cascade start output signal pin SO of the third chip is left floating. In this embodiment, after each photosensitive pixel of the three chips simultaneously senses light, performs preliminary amplification, and stores the image, the signal output mode of each photosensitive pixel is set according to the high or low level of the signal in the transmission signal control pin MODE. When the signal in the transmission signal control pin MODE is high, all chips are set to dual-channel serial output. The signals corresponding to photosensitive pixels 1 to 432 of the first chip are sequentially output to the transmission signal pin SIG1, and the signals corresponding to photosensitive pixels 433 to 864 of the first chip are sequentially output to the transmission signal pin SIG2. Then, the signals corresponding to photosensitive pixels 1 to 432 of the second chip are sequentially output to the transmission signal pin SIG1, and the signals corresponding to photosensitive pixels 433 to 864 of the second chip are sequentially output to the transmission signal pin SIG2. Finally, the signals corresponding to photosensitive pixels 1 to 432 of the third chip are sequentially output to the transmission signal pin SIG1, and the signals corresponding to photosensitive pixels 433 to 864 of the third chip are sequentially output to the transmission signal pin SIG2. In this way, the signals corresponding to the first half of the photosensitive pixels of each of the three chips are sequentially output serially through the transmission signal pin SIG1, and the signals corresponding to the second half of the photosensitive pixels of each of the three chips are sequentially output serially through the transmission signal pin SIG2. When the MODE signal on the transmission signal control pin is low, all chips are set to single-channel serial output. The signals corresponding to photosensitive pixels 1 to 864 of the first chip are sequentially output to the transmission signal pin SIG1. Then, the signals corresponding to photosensitive pixels 1 to 864 of the second chip are sequentially output to the transmission signal pin SIG1. Finally, the signals corresponding to photosensitive pixels 1 to 864 of the third chip are sequentially output to the transmission signal pin SIG1. In this way, the signals corresponding to all photosensitive pixels of the three chips are sequentially output serially through SIG1.In this embodiment, multiple image sensor chips are electrically cascaded, mainly to reduce the number of subsequent analog conversion channels. The image sensor can be set to single-channel serial output or dual-channel serial output by controlling the signal in the MODE pin, so as to meet the scanning speed requirements of different occasions. Since the common signal line inside all chips is divided into two parts in the two transmission modes, the parasitic capacitance is halved, which improves the strength of the effective signal.

[0042] Furthermore, each of the multiple linear image sensor chips includes multiple signal transmission pins, and each of the multiple signal transmission pins in the multiple linear image sensor chips outputs a signal independently.

[0043] Figure 6 A schematic diagram of an image sensor structure composed of parallel linear array image sensor chips according to an optional embodiment of the present invention is shown, as follows: Figure 6 As shown, this invention provides another image sensor, including a PCB substrate 2. Three linear array image sensor chips 1 (as in Embodiment 1) are mounted on the PCB substrate. The linear array image sensor chips are linearly arranged, and the row start signal pin FS, clock signal pin CLK, and transmission signal control pin MODE of the three chips are respectively connected. The cascade start input signal pin SI and cascade start output signal pin SO of the three chips are both floating. The transmission signal pins SIG1 and SIG2 of the three chips are output independently. In this embodiment, after each photosensitive pixel of the three chips simultaneously senses light, performs preliminary amplification, and stores the data, the signal output mode of each photosensitive pixel is set according to the high or low level of the signal in the transmission signal control pin MODE. When the signal in the transmission signal control pin MODE is high, all chips are set to dual-channel serial output. The signals corresponding to photosensitive pixels 1 to 432 of the three chips are sequentially output to their respective transmission signal pins SIG1, and the signals corresponding to photosensitive pixels 433 to 864 of the three chips are sequentially output to their respective transmission signal pins SIG2, completing the output of all photosensitive pixels. When the signal in the transmission signal control pin MODE is low, all chips are set to single-channel serial output. The signals corresponding to photosensitive pixels 1 to 864 of the three chips are sequentially output to their respective transmission signal pin SIG1, completing the output of all photosensitive pixels. In this embodiment, multiple image sensor chips are electrically connected in parallel, mainly to improve the scanning speed. The signal in the transmission signal control pin MODE can be used to set the image sensor to 6-channel serial output or 3-channel serial output to meet the scanning speed requirements of different occasions. Similarly, in both transmission modes, the common signal lines inside all chips are divided into two parts, the parasitic capacitance is halved, and the strength of the effective signal is improved.

[0044] The linear array image sensor chip of the present invention includes a photosensitive unit 101, a signal storage unit 102, a signal transmission unit 103, and a timing control unit 104. The photosensitive unit 101 includes N photosensitive pixel sub-units; the signal storage unit 102 includes N signal storage sub-units, and the N photosensitive pixel sub-units are respectively connected to the N signal storage sub-units; the signal transmission unit 103 includes a first signal transmission sub-unit and N first transmission switches, and the N signal storage sub-units are respectively connected to the first signal transmission sub-unit through the N first transmission switches; the timing control unit 104 is connected to the signal transmission unit and includes a row start signal pin FS, a clock signal pin CLK, a transmission control signal pin MODE, a cascade start input signal pin SI, and a cascade start output signal pin SO. This reduces parasitic capacitance on the lines during signal transmission, thereby improving the strength of the effective signal.

[0045] In the description of this invention, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this invention; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0046] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0047] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this invention.

[0048] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A linear array image sensor chip (1), characterized in that, include: The system comprises a photosensitive unit (101), a signal storage unit (102), a signal transmission unit (103), and a timing control unit (104), wherein... The photosensitive unit (101) includes N photosensitive pixel subunits; The signal storage unit (102) includes N signal storage sub-units, and the N photosensitive pixel sub-units are respectively connected to the N signal storage sub-units. Each signal storage sub-unit is connected to an independent common signal line that is independent of each other. The signal transmission unit (103) includes a first signal transmission subunit and N first transmission switches. The independent common signal lines connected to the N signal storage subunits are respectively connected to the first signal transmission subunit through the N first transmission switches. The timing control unit (104) is connected to the signal transmission unit (103). The timing control unit (104) includes a row start signal pin (FS), a clock signal pin (CLK), a transmission control signal pin (MODE), a cascade start input signal pin (SI), and a cascade start output signal pin (SO). The signal transmission unit (103) further includes N-1 second signal transmission subunits and N-1 second transmission switches. The N-1 signal storage subunits are respectively connected to one end of the N-1 second transmission switches, and the other end of the N-1 second transmission switches are respectively connected to the N-1 second signal transmission subunits. The N-1 signal storage subunits are any N-1 signal storage subunits among the N signal storage subunits. The signal transmission unit (103) further includes an amplifier and a signal transmission pin.

2. The linear array image sensor chip (1) according to claim 1, characterized in that, The signal transmission unit includes the first signal transmission subunit and the second signal transmission subunit.

3. An image sensor, characterized in that, The linear image sensor chip (1) includes any one of claims 1 to 2.

4. The image sensor according to claim 3, characterized in that, Also includes: The substrate, frame, optical lens, light source, and socket interface; among which, The optical lens is positioned above the photosensitive window of the linear image sensor chip (1); The light source is disposed on the side of the optical lens; The socket interface is connected to the linear image sensor chip (1) and the light source.

5. The image sensor according to claim 3, characterized in that, The image sensor includes multiple linear image sensor chips (1).

6. The image sensor according to claim 5, characterized in that, Multiple linear array image sensor chips (1) are arranged linearly.

7. The image sensor according to claim 5, characterized in that, Multiple linear image sensor chips (1) are connected in parallel.

8. The image sensor according to claim 6, characterized in that, Multiple linear image sensor chips (1) are cascaded in a linear arrangement, and the cascade start output signal pin (SO) of the previous stage chip in the multiple linear image sensor chips (1) is connected to the cascade start input signal pin (SI) of the next stage chip.

9. The image sensor according to claim 7, characterized in that, Each of the multiple linear array image sensor chips (1) includes multiple signal transmission pins, and each of the multiple signal transmission pins of the multiple linear array image sensor chips (1) independently outputs a signal.

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