Semiconductor structure and method for forming the same

Abstract

The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. The method for forming a semiconductor structure provided in the present application includes the following steps: forming a substrate, the substrate including a main body and a protrusion located on the surface of the main body; forming a gate electrode located on the main body and distributed around the sidewalls of the protrusion; forming a first doping region and a second doping region located in the main body and distributed on opposite sides of the gate electrode. Some embodiments of the present application increase the channel length in a MOS device having the gate electrode, the first doping region, and the second doping region, reduce the short channel effect, reduce the leakage current, and improve the electrical performance and yield of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor structure commonly used in electronic devices such as computers. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to a capacitor. The word line voltage on the word line can control the on and off of the transistor, thereby allowing data stored in the capacitor to be read or written through the bit line.

[0003] Dynamic random access memory typically includes an array region and a core region located outside the array region. The array region has multiple memory cells arranged in a row, and the core region has multiple control devices for applying control signals to the memory cells in the array region. The area of ​​the core region accounts for approximately 20% of the entire chip area. To reduce chip size and increase integration, the MOS devices in the core region are usually manufactured to be very small. They are segmented channel devices, which have large short channel current effects and severe leakage problems.

[0004] Therefore, how to reduce the short channel effect of MOS devices in semiconductor structures and reduce leakage, thereby improving the electrical performance and yield of the semiconductor structure, is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present application provide a semiconductor structure and a method for forming the same, which are used to solve the problem of severe leakage of MOS devices in the semiconductor structure, thereby improving the electrical performance and yield of the semiconductor structure.

[0006] According to some embodiments of the present application, the present application provides a method for forming a semiconductor structure, comprising the following steps:

[0007] forming a substrate, the substrate comprising a main body and a protrusion located on a surface of the main body;

[0008] forming a gate electrode located on the body portion and surrounding a sidewall of the protrusion;

[0009] A first doping region and a second doping region are formed in the body portion and distributed on opposite sides of the gate electrode.

[0010] In some embodiments, the steps of forming the substrate include:

[0011] Providing an initial substrate, wherein the initial substrate includes a first lightly doped region;

[0012] forming an initial insulating layer covering the surface of the initial substrate;

[0013] The initial insulating layer and the initial substrate are etched to form a substrate including a main body and a protrusion located on the surface of the main body, and an insulating layer located on the surface of the protrusion, wherein the protrusion includes the first lightly doped region and the main body does not have the first lightly doped region.

[0014] In some embodiments, the specific steps of forming the gate electrode located on the body portion and surrounding the sidewall of the protrusion portion include:

[0015] forming a gate dielectric layer covering the sidewalls of the protrusion and a portion of the surface of the body;

[0016] A gate electrode is formed on the surface of the gate dielectric layer and surrounds the sidewall of the protrusion.

[0017] In some embodiments, the specific steps of forming a gate electrode located on the surface of the gate dielectric layer and surrounding the sidewall of the protrusion include:

[0018] Depositing a gate material layer on the surface of the gate dielectric layer and the surface of the insulating layer;

[0019] The entire gate material layer on the surface of the insulating layer and a portion of the gate material layer above the main body are removed, and the gate material layer remaining on the surface of the gate dielectric layer and surrounding the sidewall of the protrusion serves as the gate electrode.

[0020] In some embodiments, before forming the first doped region and the second doped region located in the body portion and distributed on opposite sides of the gate electrode, the following steps are further included:

[0021] forming a first dielectric layer covering the gate electrode;

[0022] First doping ions are implanted into the main body at two opposite sides of the protrusion to form a second lightly doped region.

[0023] In some embodiments, the specific steps of forming the first doped region and the second doped region located in the body portion and distributed on opposite sides of the gate electrode include:

[0024] Second doping ions are implanted into the body portion at opposite sides of the protrusion to form the first doping region and the second doping region in the body portion at opposite sides of the gate electrode, respectively.

[0025] In some embodiments, in a direction perpendicular to the surface of the body portion, a projection of the second lightly doped region partially overlaps with a projection of the first doped region and a projection of the second doped region.

[0026] In some embodiments, after forming the first doping region and the second doping region located in the body portion and distributed on opposite sides of the gate electrode, the method further includes the following steps:

[0027] forming a second dielectric layer covering the surface of the main body, the surface of the first dielectric layer, and the surface of the insulating layer;

[0028] Etching the second dielectric layer, the first dielectric layer, and the insulating layer to form a first through hole exposing the first lightly doped region in the protrusion, a second through hole exposing the first doped region in the body, a third through hole exposing the second doped region in the body, and a fourth through hole exposing the gate electrode;

[0029] Filling the first through hole, the second through hole, and the third through hole with conductive material to form a first plug electrically connected to the first lightly doped region, a second plug electrically connected to the first doped region, a third plug electrically connected to the second doped region, and a fourth plug electrically connected to the gate electrode.

[0030] In some embodiments, the specific steps of forming a first plug electrically connected to the first lightly doped region, a second plug electrically connected to the first doped region, a third plug electrically connected to the second doped region, and a fourth plug electrically connected to the gate electrode include:

[0031] forming a first contact layer at the bottom of the first through hole, forming a second contact layer at the bottom of the second through hole, forming a third contact layer at the bottom of the third through hole, and forming a fourth contact layer at the bottom of the fourth through hole;

[0032] forming a first diffusion barrier layer on the surface of the first contact layer and the inner wall of the first through-hole, forming a second diffusion barrier layer on the surface of the second contact layer and the inner wall of the second through-hole, forming a third diffusion barrier layer on the surface of the third contact layer and the inner wall of the third through-hole, and forming a fourth diffusion barrier layer on the surface of the fourth contact layer and the inner wall of the fourth through-hole;

[0033] Filling the first through-hole, the second through-hole, the third through-hole and the fourth through-hole with conductive material to form the first plug on the first diffusion barrier layer, the second plug on the second diffusion barrier layer, the third plug on the third diffusion barrier layer, and the fourth plug on the fourth diffusion barrier layer.

[0034] In some embodiments, the plurality of fourth plugs are distributed around the periphery of the same gate electrode and are electrically connected to the same gate electrode.

[0035] In some embodiments, a height of the gate electrode along a direction perpendicular to a surface of the body portion is smaller than a height of the protrusion portion.

[0036] In some embodiments, the height of the protrusion is 30 nm to 100 nm.

[0037] According to some embodiments of the present application, the present application provides a semiconductor structure, including:

[0038] A substrate comprising a main body and a protrusion located on a surface of the main body;

[0039] a gate electrode, located on the main body and distributed around the sidewall of the protrusion;

[0040] a first doped region, located in the body portion;

[0041] The second doping region is located in the body portion, and the first doping region and the second doping region are distributed on two opposite sides of the gate electrode.

[0042] In some embodiments, further comprising:

[0043] a first lightly doped region located in the protrusion;

[0044] The second lightly doped region is located in the main body at two opposite sides of the protrusion.

[0045] In some embodiments, in a direction perpendicular to the surface of the body portion, a projection of the second lightly doped region partially overlaps with a projection of the first doped region and a projection of the second doped region.

[0046] In some embodiments, further comprising:

[0047] a first plug extending in a direction perpendicular to a surface of the body portion and electrically connected to the first lightly doped region;

[0048] a second plug extending in a direction perpendicular to the surface of the body portion and electrically connected to the first doped region;

[0049] a third plug extending in a direction perpendicular to the surface of the body portion and electrically connected to the second doped region;

[0050] The fourth plug extends in a direction perpendicular to the surface of the body portion and is electrically connected to the gate electrode.

[0051] In some embodiments, the plurality of fourth plugs are distributed around the periphery of the same gate electrode and are electrically connected to the same gate electrode.

[0052] In some embodiments, further comprising:

[0053] a first contact layer, located between the first lightly doped region and the first plug;

[0054] a second contact layer located between the first doped region and the second plug;

[0055] a third contact layer, located between the second doped region and the third plug;

[0056] A fourth contact layer is located between the gate electrode and the fourth plug.

[0057] In some embodiments, the substrate is made of silicon, and the gate electrode is made of polysilicon.

[0058] Materials of the first contact layer, the second contact layer, the third contact layer, and the fourth contact layer are all metal silicide.

[0059] In some embodiments, further comprising:

[0060] An insulating layer covers the top surface of the protrusion, and the first plug penetrates the insulating layer along a direction perpendicular to the surface of the main body.

[0061] In some embodiments, further comprising:

[0062] a first dielectric layer covering the surface of the gate electrode;

[0063] a second dielectric layer covering a surface of the main body, a surface of the first dielectric layer, and a surface of the insulating layer; the second plug and the third plug both penetrate the second dielectric layer in a direction perpendicular to the surface of the main body; and the fourth plug penetrates the first dielectric layer in a direction perpendicular to the surface of the main body.

[0064] In some embodiments, a height of the protrusion along a direction perpendicular to a surface of the body portion is greater than a width of the protrusion along a direction parallel to the surface of the body portion.

[0065] In some embodiments, a height of the gate electrode along a direction perpendicular to a surface of the body portion is smaller than a height of the protrusion portion.

[0066] In some embodiments, the height of the protrusion is 30 nm to 100 nm.

[0067] The semiconductor structure and its formation method provided in some embodiments of the present application increase the channel length of a MOS device having the gate electrode, the first doped region, and the second doped region, thereby reducing the short channel effect and leakage current, thereby improving the electrical performance and yield of the semiconductor structure. Furthermore, the channel area of ​​the MOS device is increased, the threshold voltage shift of the MOS device caused by process variations is reduced, and the size of the MOS device is further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Attachment Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;

[0069] Attachment Figures 2A-2Z It is a schematic cross-sectional view of the main processes in forming a semiconductor structure according to a specific embodiment of the present invention;

[0070] Attachment Figures 3A-3C Schematic diagram of a semiconductor structure in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0071] The specific embodiments of the semiconductor structure and the method for forming the same provided by the present invention are described in detail below with reference to the accompanying drawings.

[0072] This embodiment provides a semiconductor structure. Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention, Figures 2A-2Z FIG. 1 is a schematic cross-sectional view of the main process in forming a semiconductor structure according to a specific embodiment of the present invention. Figure 1 、 Figure 2A-2Z As shown, the method for forming a semiconductor structure provided in this embodiment includes the following steps:

[0073] Step S11, forming a substrate, the substrate comprising a main body 201 and a protrusion 202 located on the surface of the main body 201, as shown in FIG. Figure 2C shown.

[0074] In some embodiments, the steps of forming the substrate include:

[0075] Provide an initial substrate 20, the initial substrate including a first lightly doped region 501, such as Figure 2A As shown;

[0076] forming an initial insulating layer covering the surface of the initial substrate 20;

[0077] The initial insulating layer and the initial substrate 20 are etched to form a substrate including a main body 201 and a protrusion 202 located on the surface of the main body 201, and an insulating layer located on the surface of the protrusion 202, wherein the protrusion 202 includes the first lightly doped region 501, and the main body 201 does not have the first lightly doped region 501.

[0078] Specifically, the initial substrate 20 can be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the initial substrate 20 as a silicon substrate as an example. In other examples, the initial substrate 20 can be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The initial substrate 20 has multiple active areas inside, and adjacent active areas are isolated from each other by shallow trench isolation structures 21. The surface of the initial substrate 20 is also covered with a substrate isolation layer 53, such as Figure 2A As shown. After the initial substrate 20 is subjected to surface activation treatment, ion implantation is performed into the active area in the initial substrate 20 to form a well region. After the well region is formed, first doping ions may be implanted into the initial substrate 20 to form a first lightly doped region 501. The first lightly doped region 501 is located at least where the protrusion 202 is preformed. In order to reduce the number of masks, in one example, the first doping ions may be implanted into the entire initial substrate 20, thereby forming the first lightly doped region 501 in the entire initial substrate 20. The materials of the substrate isolation layer 53 and the shallow trench isolation structure 21 may both be oxide materials, such as silicon dioxide.

[0079] The initial insulating layer can be a single-layer structure or a multi-layer structure. This specific embodiment is described by taking the initial insulating layer as a multi-layer structure as an example. After the well region is formed in the initial substrate 20, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process can be used to deposit the first sub-initial insulating layer 221, the second sub-initial insulating layer 222 and the third sub-initial insulating layer 223 on the surface of the initial substrate 20 at one time. The material of the first sub-initial insulating layer 221 can be a nitride (such as silicon nitride) or a nitride oxide (such as silicon oxynitride). The material of the second sub-initial insulating layer 222 can be an oxide material (such as silicon dioxide). The material of the third sub-initial insulating layer 223 can be a nitride material (such as silicon nitride). Afterwards, a first sub-mask layer 231 is deposited on the surface of the third sub-initial insulating layer 223, a second sub-mask layer 232 is deposited on the surface of the first sub-mask layer 231, and a patterned first photoresist layer 24 is formed on the surface of the second sub-mask layer 232, as shown in FIG. Figure 2BAfterwards, the pattern in the first photoresist layer 24 is transferred downward, and a portion of the second sub-mask layer 232, the first sub-mask layer 231, the third sub-insulating layer 223, the second sub-insulating layer 222, the first sub-insulating layer 221, the substrate isolation layer 53 and the initial substrate 20 is etched away, and the remaining second sub-mask layer 232 and the remaining first sub-mask layer 231 are stripped off to obtain the following: Figure 2C The structure shown in FIG. The remaining first sub-initial insulating layer 221 forms a first sub-insulating layer 2511, the remaining second sub-initial insulating layer 222 forms a second sub-insulating layer 2512, the remaining third sub-initial insulating layer 223 forms a third sub-insulating layer 253, and the remaining substrate isolation layer 53 forms a fourth sub-insulating layer 254. The height of the etched initial substrate 20 is greater than the depth of the first lightly doped region 501, so that the first lightly doped region 501 is not included in the main body 201 formed after etching, while the first lightly doped region 501 remains in the protrusion 202.

[0080] The specific height of the protrusion 202 can be set by those skilled in the art according to actual needs. The height of the protrusion 202 should not be too high, otherwise it will increase the overall size of the semiconductor structure; the height of the protrusion 202 should not be too low, otherwise it will not effectively increase the channel length. In some embodiments, the height of the protrusion 202 is 30nm to 100nm. In this specific embodiment, the height of the protrusion 202 refers to the height of the protrusion 202 in a direction perpendicular to the surface of the main body 201.

[0081] This embodiment is described by taking the cross-sectional shape of the protrusion 202 as an example. In other embodiments, those skilled in the art may also adjust the shape of the protrusion 202 according to actual needs.

[0082] Step S12: forming a gate electrode 28 on the main body 201 and surrounding the sidewall of the protrusion 202. Figure 2F shown.

[0083] In some embodiments, the specific steps of forming the gate electrode 28 located on the body portion 201 and surrounding the sidewall of the protrusion 202 include:

[0084] A gate dielectric layer 26 is formed to cover the sidewalls of the protrusion 202 and a portion of the surface of the body 201, such as Figure 2D As shown;

[0085] A gate electrode 28 is formed on the surface of the gate dielectric layer 26 and surrounds the sidewall of the protrusion 202 .

[0086] In some embodiments, the specific steps of forming the gate electrode 28 located on the surface of the gate dielectric layer 26 and surrounding the sidewall of the protrusion 202 include:

[0087] A gate material layer 27 is deposited on the surface of the gate dielectric layer 26 and the surface of the insulating layer. Figure 2E As shown;

[0088] The entire gate material layer 27 on the surface of the insulating layer and a portion of the gate material layer 27 above the main body 201 are removed, and the gate material layer 27 remaining on the surface of the gate dielectric layer 26 and surrounding the sidewall of the protrusion 202 is used as the gate electrode 28. Figure 2F shown.

[0089] Specifically, after forming the protrusion 202, an in-situ vapor growth process (ISSG) can be used to grow an oxide layer on the surface of the main body 201 and the sidewall of the protrusion 202 to serve as the gate dielectric layer 26. Figure 2D Afterwards, polysilicon and other materials are deposited on the surface of the gate dielectric layer 26 and the surface of the insulating layer to form a gate material layer 27, as shown. Figure 2E Next, ion implantation is performed on the gate material layer 27, and all of the gate material layer 27 on the surface of the insulating layer and a portion of the gate material layer 27 above the main body 201 are removed. The gate material layer 27 remaining on the surface of the gate dielectric layer 26 and surrounding the sidewall of the protrusion 202 serves as the gate electrode 28, as shown. Figure 2F shown.

[0090] In some embodiments, in a direction perpendicular to the surface of the body portion 201 , a height of the gate electrode 28 is smaller than a height of the protrusion 202 .

[0091] The height of the gate electrode 28 refers to the height of the gate electrode 28 in a direction perpendicular to the surface of the main body 201. Making the height of the gate electrode 28 smaller than the height of the protrusion 202 helps reduce the internal resistance of the gate electrode 28 and also facilitates isolation of the gate electrode 28 from other device structures.

[0092] Step S13, forming a first doping region 511 and a second doping region 512 located in the body portion 201 and distributed on opposite sides of the gate electrode 28, as shown in FIG. Figure 2M shown.

[0093] Specifically, if Figure 2MAs shown, the gate electrode 28 is arranged around the periphery of the protrusion 202, and the first doping region 511 and the second doping region 512 are distributed inside the body portion 201 on opposite sides of the gate electrode 28, so that the length of the channel is Figure 2M As shown by the double-headed arrows in the figure, the channel length is increased, which reduces leakage current. Moreover, the increase in channel length will increase the area of ​​the channel region, reducing the threshold voltage mismatch problem caused by process deviation.

[0094] In some embodiments, before forming the first doping region 511 and the second doping region 512 located in the body portion 201 and distributed on opposite sides of the gate electrode 28 , the following steps are further included:

[0095] A first dielectric layer 30 is formed covering the gate electrode 28, as shown in FIG. Figure 2H As shown;

[0096] The first doping ions are implanted into the main body 201 on opposite sides of the protrusion 202 to form a second lightly doped region 502. Figure 2K shown.

[0097] Specifically, after forming the gate electrode 28, an oxide material (such as silicon dioxide) is deposited on the surface of the body portion 201, the surface of the gate electrode 28 and the surface of the insulating layer to form a Figure 2G Next, the first initial dielectric layer 29 is etched to remove the top surface and part of the sidewall surface of the insulating layer and part of the first initial dielectric layer 29 on the surface of the body portion 201. The first initial dielectric layer 29 remaining on the surface of the gate electrode 28 forms the first dielectric layer 30. Figure 2H When the material of the first initial dielectric layer 29 is the same as that of the shallow trench isolation structure 21, a portion of the shallow trench isolation structure 21 will also be removed during the process of removing the first initial dielectric layer 29. Next, a nitride material (such as silicon nitride) is deposited on the surface of the first dielectric layer 30, the surface of the insulating layer, the surface of the main body 201, and the surface of the shallow trench isolation structure 21 to form a first isolation layer 31, as shown in FIG. Figure 2I Then, the first isolation layer 31 covering the surface of the insulating layer and the surface of the main body 201, as well as a portion of the first isolation layer 31 on the surface of the first dielectric layer 30, is removed by an etching process, and a portion of the first isolation layer 31 remains on the surface of the first dielectric layer 30, as shown. Figure 2J shown.

[0098] Then, first doping ions are implanted into the main body 201 on opposite sides of the protrusion 202 to form a second lightly doped region 502, as shown in FIG. Figure 2K shown.

[0099] In some embodiments, the specific steps of forming the first doping region 511 and the second doping region 512 located in the body portion 201 and distributed on opposite sides of the gate electrode 28 include:

[0100] Second doping ions are implanted into the main body 201 on opposite sides of the protrusion 202 to form the first doping region and the second doping region in the main body 201 on opposite sides of the gate electrode 28 .

[0101] In some embodiments, in a direction perpendicular to the surface of the body portion 201 , a projection of the second lightly doped region 502 partially overlaps with a projection of the first doped region 511 and a projection of the second doped region 512 .

[0102] Specifically, after forming the second lightly doped region 502, oxide and other materials are deposited on the surface of the main body, the surface of the insulating layer, the surface of the first dielectric layer 30 and the surface of the first isolation layer 31 to form a second initial isolation layer 32. Figure 2L Next, the second initial isolation layer 32 is partially etched away from the surface of the main body 201, the surface of the first dielectric layer 30, and the surface of the first isolation layer 31, and the second initial isolation layer 32 remaining on the surface of the first isolation layer 31 and the sidewall of the insulating layer forms a second isolation layer 33, as shown. Figure 2M Afterwards, second doping ions are injected into the main body 201 on opposite sides of the protrusion 202 to form the first doping region 511 and the second doping region 512, as shown. Figure 2M The first doping region 511 is a source region, and correspondingly, the second doping region 512 is a drain region; or the first doping region 511 is a drain region, and correspondingly, the second doping region 512 is a source region.

[0103] In some embodiments, after forming the first doping region 511 and the second doping region 512 located in the body portion 201 and distributed on opposite sides of the gate electrode 28 , the following steps are further included:

[0104] forming a second dielectric layer 35 covering the surface of the main body 201, the surface of the first dielectric layer 30, and the surface of the insulating layer;

[0105] The second dielectric layer 35, the first dielectric layer 30, and the insulating layer are etched to form a first through hole 391 exposing the first lightly doped region 501 in the protrusion 202, a second through hole 392 exposing the first doped region 511 in the body 201, a third through hole 393 exposing the second doped region 512 in the body, and a fourth through hole (not shown) exposing the gate electrode 28, as shown in FIG. Figure 2R As shown;

[0106] Fill the first through hole 391, the second through hole 392 and the third through hole 393 with conductive material to form a first plug 451 electrically connected to the first lightly doped region 501, a second plug 452 electrically connected to the first doped region 511, a third plug 453 electrically connected to the second doped region 512, and a fourth plug 454 electrically connected to the gate electrode 28. Figure 2X and Figure 2Z shown.

[0107] In some embodiments, the specific steps of forming the first plug 451 electrically connected to the first lightly doped region 501 , the second plug 452 electrically connected to the first doped region 511 , the third plug 453 electrically connected to the second doped region 512 , and the fourth plug 454 electrically connected to the gate electrode 28 include:

[0108] forming a first contact layer 411 at the bottom of the first through hole 391 , forming a second contact layer 412 at the bottom of the second through hole 392 , forming a third contact layer 413 at the bottom of the third through hole 393 , and forming a fourth contact layer 414 at the bottom of the fourth through hole;

[0109] forming a first diffusion barrier layer on the surface of the first contact layer 411 and the inner wall of the first through hole 391, forming a second diffusion barrier layer on the surface of the second contact layer 412 and the inner wall of the second through hole 392, forming a third diffusion barrier layer on the surface of the third contact layer 413 and the inner wall of the third through hole 393, and forming a fourth diffusion barrier layer on the surface of the fourth contact layer 414 and the inner wall of the fourth through hole;

[0110] Conductive material is filled into the first through hole 391, the second through hole 392, the third through hole 393 and the fourth through hole to form the first plug 451 located on the first diffusion barrier layer, the second plug 452 located on the second diffusion barrier layer, the third plug 453 located on the third diffusion barrier layer, and the fourth plug 454 located on the fourth diffusion barrier layer.

[0111] Specifically, after forming the first doping region 511 and the second doping region 512, a nitride material (such as silicon nitride) is deposited on the surface of the insulating layer, the surface of the body portion 201, the surface of the second isolation layer 33 and the surface of the first dielectric layer 30 to form a third isolation layer 34. Figure 2N Then, an oxide material (such as silicon dioxide) is deposited on the surface of the third isolation layer 34 to form a Figure 2O The second dielectric layer 35 is planarized by chemical mechanical polishing process to expose the third isolation layer 34. Figure 2P Then, a third sub-mask layer 36 is formed on the surface of the second dielectric layer 35 and the exposed surface of the third isolation layer 34, a fourth sub-mask layer 37 is formed on the surface of the third sub-mask layer 36, and a patterned second photoresist layer 38 is formed on the surface of the fourth sub-mask layer 37. The second photoresist layer 38 has a first etching window 381, a second etching window 382, ​​a third etching window 383 and a fourth etching window ( Figure 2Q Not shown), such as Figure 2Q Etching is performed downward along the first etching window 381, the second etching window 382, ​​the third etching window 383 and the fourth etching window to form a first through hole 391 exposing the first lightly doped region 501 in the protrusion 202, a second through hole 392 exposing the first doped region 511 in the body 201, a third through hole 393 exposing the second doped region 512 in the body, and a fourth through hole exposing the gate electrode 28. After removing the second photoresist layer 38, the third sub-mask layer 36 and the fourth sub-mask layer 37, the following is obtained: Figure 2R The structure shown.

[0112] Deposit metal material 40 (eg, cobalt) in the first through hole 391, the second through hole 392, the third through hole 393, and the fourth through hole, as shown in FIG. Figure 2S As shown. The metal material 40 reacts with the substrate material (such as silicon) to generate metal silicide, forming a first contact layer 411 at the bottom of the first through hole 391, a second contact layer 412 at the bottom of the second through hole 392, a third contact layer 413 at the bottom of the third through hole 393, and a fourth contact layer 414 at the bottom of the fourth through hole. Using metal silicide as a contact layer can reduce the contact resistance inside the through hole. After stripping off the remaining metal material, the following is obtained: Figure 2T The structure shown.

[0113] Then, a metal Ti material layer 42 is deposited on the inner wall of the first through hole 391, the inner wall of the second through hole 392, the inner wall of the third through hole 393, the inner wall of the fourth through hole and the surface of the second dielectric layer 35 to form a first adhesion layer covering the inner wall of the first through hole 391, a second adhesion layer covering the inner wall of the second through hole 392, a third adhesion layer covering the inner wall of the third through hole 393 and a fourth adhesion layer covering the inner wall of the fourth through hole ( Figure 2U Not shown), such as Figure 2U shown.

[0114] Next, a TiN material layer 43 is deposited on the surface of the metal Ti material layer 42 to form a first diffusion barrier layer covering the surface of the first adhesion layer, a second diffusion barrier layer covering the surface of the second adhesion layer, a third diffusion barrier layer covering the surface of the third adhesion layer, and a fourth diffusion barrier layer covering the surface of the fourth adhesion layer, as shown in FIG. Figure 2V shown.

[0115] Afterwards, a metal material layer 44 such as tungsten is deposited in the first through hole 391, the second through hole 392, the third through hole 393, the fourth through hole, and on the surface of the TiN material layer 43. The metal material layer 44 in the first through hole 391 serves as the first plug 451, the metal material layer 44 in the second through hole 392 serves as the second plug 452, and the metal material layer 44 in the third through hole 393 serves as the third plug 453. Figure 2W As shown, the metal material layer 44 in the fourth through hole is used as the fourth plug 454. Figure 2Z Next, the metal material layer 44 located on the surface of the second dielectric layer 35 is etched to form a first metal interconnection layer 471 for transmitting electrical signals to the first lightly doped region 501, a second metal interconnection layer 472 for transmitting electrical signals to the first doped region 511, a third metal interconnection layer 473 for transmitting electrical signals to the second doped region 512, and a fourth metal interconnection layer 474 for transmitting electrical signals to the gate electrode 28. The first metal interconnection layer 471, the second metal interconnection layer 472, the third metal interconnection layer 473, and the fourth metal interconnection layer 474 are electrically isolated from each other by a spacer layer 46, as shown. Figure 2X shown. Figure 2Y yes Figure 2X Schematic diagram of the top view of the structure, Figure 2Z yes Figure 2Y Schematic diagram of the cross section along the AB direction.

[0116] In some embodiments, the plurality of fourth plugs 454 are distributed around the periphery of the same gate electrode 28 and are electrically connected to the same gate electrode 28 .

[0117] Specifically, by providing a plurality of fourth plugs 454 electrically connected to the same gate electrode 28 , while ensuring stable connection between the fourth plugs 454 and the gate electrode 28 , the parasitic capacitance effect between the fourth plugs 454 and the gate electrode 28 can be improved.

[0118] According to some embodiments of the present application, another aspect of the present application provides a semiconductor structure. Figures 3A-3C is a schematic diagram of a semiconductor structure in a specific embodiment of the present invention, Figure 3B yes Figure 3A Schematic diagram of the cross section along the CD direction, Figure 3C yes Figure 3A The semiconductor structure provided in this embodiment can be used as follows: Figure 1 、 Figure 2A-2Z The semiconductor structure is formed by the method shown in FIG. Figure 2A-2Z and Figure 3A-3C As shown, the semiconductor structure includes:

[0119] A substrate comprising a main body 201 and a protrusion 202 located on a surface of the main body 201;

[0120] a gate electrode 28 , located on the main body 201 and distributed around the sidewall of the protrusion 202 ;

[0121] A first doped region 511 is located in the main body 201;

[0122] The second doping region 512 is located in the main body 201 . The first doping region 511 and the second doping region 512 are located on opposite sides of the gate electrode 28 .

[0123] In some embodiments, the semiconductor structure further comprises:

[0124] A first lightly doped region 501 is located in the protrusion 202;

[0125] The second lightly doped regions 502 are located in the main body 201 on two opposite sides of the protrusion 202 .

[0126] In some embodiments, in a direction perpendicular to the surface of the body portion 201 , a projection of the second lightly doped region 502 partially overlaps with a projection of the first doped region 511 and a projection of the second doped region 512 .

[0127] In some embodiments, further comprising:

[0128] a first plug 451 extending in a direction perpendicular to the surface of the body portion 201 and electrically connected to the lightly doped region 50;

[0129] a second plug 452 extending in a direction perpendicular to the surface of the body portion 201 and electrically connected to the first doped region 511;

[0130] a third plug 453 extending in a direction perpendicular to the surface of the body portion 201 and electrically connected to the second doped region 512;

[0131] The fourth plug 454 extends in a direction perpendicular to the surface of the body portion 201 and is electrically connected to the gate electrode 28 .

[0132] In some embodiments, the plurality of fourth plugs 454 are distributed around the periphery of the same gate electrode 28 and are electrically connected to the same gate electrode 28 .

[0133] In some embodiments, the semiconductor structure further comprises:

[0134] A first contact layer 411 is located between the first lightly doped region 501 and the first plug 451 ;

[0135] A second contact layer 412 is located between the first doped region 511 and the second plug 452 ;

[0136] A third contact layer 413 is located between the second doped region 512 and the third plug 453 ;

[0137] The fourth contact layer 414 is located between the gate electrode 28 and the fourth plug 454 .

[0138] In some embodiments, the substrate is made of silicon, and the gate electrode 28 is made of polysilicon.

[0139] Materials of the first contact layer 411 , the second contact layer 412 , the third contact layer 413 , and the fourth contact layer 414 are all metal silicide.

[0140] In some embodiments, the semiconductor structure further comprises:

[0141] The insulating layer covers the top surface of the protrusion 202 , and the first plug 451 penetrates the insulating layer in a direction perpendicular to the surface of the main body 201 .

[0142] In some embodiments, the semiconductor structure further comprises:

[0143] A first dielectric layer 30 covering the surface of the gate electrode 28;

[0144] The second dielectric layer 35 covers the surface of the main body 201, the surface of the first dielectric layer 30, and the surface of the insulating layer. The second plug 452 and the third plug 453 both penetrate the second dielectric layer 35 in a direction perpendicular to the surface of the main body 201. The fourth plug 454 penetrates the first dielectric layer 30 in a direction perpendicular to the surface of the main body 201.

[0145] In some embodiments, the height of the protrusion 201 along a direction perpendicular to the surface of the main body 201 is greater than the width of the protrusion 202 along a direction parallel to the surface of the main body 201 .

[0146] In some embodiments, in a direction perpendicular to the surface of the body portion 201 , a height of the gate electrode 28 is smaller than a height of the protrusion 202 .

[0147] In some embodiments, the height of the protrusion 202 is 30 nm to 100 nm.

[0148] The semiconductor structure and method for forming the same provided in this embodiment form a substrate comprising a body portion and a protrusion portion, with a gate electrode distributed around the periphery of the protrusion portion, and first and second doped regions distributed within the body portion on either side of the gate electrode. This increases the channel length of a MOS device comprising the gate electrode, the first doped region, and the second doped region, reduces short channel effects and leakage current, and improves the electrical performance and yield of the semiconductor structure. Furthermore, the channel area of ​​the MOS device is increased, reducing the threshold voltage shift of the MOS device caused by process variations, thereby further reducing the size of the MOS device.

[0149] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: The steps include: Forming a substrate, the substrate including a main body and a protrusion located on a surface of the main body, comprising: providing an initial substrate, the initial substrate including a first lightly doped region; forming an initial insulating layer covering the surface of the initial substrate; etching the initial insulating layer and the initial substrate to form a substrate including a main body and a protrusion located on a surface of the main body, and an insulating layer located on a surface of the protrusion, wherein the protrusion includes the first lightly doped region and the main body does not include the first lightly doped region; forming a gate electrode located on the body portion and surrounding a sidewall of the protrusion; A first doping region and a second doping region are formed in the body portion and distributed on opposite sides of the gate electrode.

2. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming a gate electrode located on the main body and surrounding the sidewall of the protrusion include: forming a gate dielectric layer covering the sidewalls of the protrusion and a portion of the surface of the body; A gate electrode is formed on the surface of the gate dielectric layer and surrounds the sidewall of the protrusion.

3. The method for forming a semiconductor structure according to claim 2, wherein: The specific steps of forming a gate electrode located on the surface of the gate dielectric layer and surrounding the sidewall of the protrusion include: Depositing a gate material layer on the surface of the gate dielectric layer and the surface of the insulating layer; The entire gate material layer on the surface of the insulating layer and a portion of the gate material layer above the main body are removed, and the gate material layer remaining on the surface of the gate dielectric layer and surrounding the sidewall of the protrusion serves as the gate electrode.

4. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first doping region and the second doping region located in the body portion and distributed on opposite sides of the gate electrode, the following steps are further included: forming a first dielectric layer covering the gate electrode; First doping ions are implanted into the main body at two opposite sides of the protrusion to form a second lightly doped region.

5. The method for forming a semiconductor structure according to claim 4, wherein: The specific steps of forming a first doping region and a second doping region located in the body portion and distributed on opposite sides of the gate electrode include: Second doping ions are implanted into the body portion at opposite sides of the protrusion to form the first doping region and the second doping region in the body portion at opposite sides of the gate electrode, respectively.

6. The method for forming a semiconductor structure according to claim 4, wherein: In a direction perpendicular to the surface of the body portion, a projection of the second lightly doped region partially overlaps with a projection of the first doped region and a projection of the second doped region.

7. The method for forming a semiconductor structure according to claim 4, wherein: After forming the first doping region and the second doping region located in the body portion and distributed on opposite sides of the gate electrode, the following steps are further included: forming a second dielectric layer covering the surface of the main body, the surface of the first dielectric layer, and the surface of the insulating layer; Etching the second dielectric layer, the first dielectric layer, and the insulating layer to form a first through hole exposing the first lightly doped region in the protrusion, a second through hole exposing the first doped region in the body, a third through hole exposing the second doped region in the body, and a fourth through hole exposing the gate electrode; Filling the first through hole, the second through hole, and the third through hole with conductive material to form a first plug electrically connected to the first lightly doped region, a second plug electrically connected to the first doped region, a third plug electrically connected to the second doped region, and a fourth plug electrically connected to the gate electrode.

8. The method for forming a semiconductor structure according to claim 7, wherein: The specific steps of forming a first plug electrically connected to the first lightly doped region, a second plug electrically connected to the first doped region, a third plug electrically connected to the second doped region, and a fourth plug electrically connected to the gate electrode include: forming a first contact layer at the bottom of the first through hole, forming a second contact layer at the bottom of the second through hole, forming a third contact layer at the bottom of the third through hole, and forming a fourth contact layer at the bottom of the fourth through hole; forming a first diffusion barrier layer on the surface of the first contact layer and the inner wall of the first through-hole, forming a second diffusion barrier layer on the surface of the second contact layer and the inner wall of the second through-hole, forming a third diffusion barrier layer on the surface of the third contact layer and the inner wall of the third through-hole, and forming a fourth diffusion barrier layer on the surface of the fourth contact layer and the inner wall of the fourth through-hole; Filling the first through-hole, the second through-hole, the third through-hole and the fourth through-hole with conductive material to form the first plug on the first diffusion barrier layer, the second plug on the second diffusion barrier layer, the third plug on the third diffusion barrier layer, and the fourth plug on the fourth diffusion barrier layer.

9. The method for forming a semiconductor structure according to claim 7, wherein: The plurality of fourth plugs are distributed around the periphery of the same gate electrode and are electrically connected to the same gate electrode.

10. The method for forming a semiconductor structure according to claim 1, wherein: A height of the gate electrode is smaller than a height of the protrusion in a direction perpendicular to a surface of the body portion.

11. The method for forming a semiconductor structure according to claim 1, wherein: The height of the protrusion is 30nm~100nm.

12. A semiconductor structure, characterized in that: include: A substrate comprising a main body and a protrusion located on a surface of the main body; a gate electrode, located on the main body and distributed around the sidewall of the protrusion; a first doped region, located in the body portion; a second doped region located in the body portion, wherein the first doped region and the second doped region are distributed on opposite sides of the gate electrode; a first lightly doped region located in the protrusion; The second lightly doped region is located in the main body at two opposite sides of the protrusion.

13. The semiconductor structure according to claim 12, wherein: In a direction perpendicular to the surface of the body portion, a projection of the second lightly doped region partially overlaps with a projection of the first doped region and a projection of the second doped region.

14. The semiconductor structure according to claim 13, wherein: Also includes: a first plug extending in a direction perpendicular to a surface of the body portion and electrically connected to the first lightly doped region; a second plug extending in a direction perpendicular to the surface of the body portion and electrically connected to the first doped region; a third plug extending in a direction perpendicular to the surface of the body portion and electrically connected to the second doped region; The fourth plug extends in a direction perpendicular to the surface of the body portion and is electrically connected to the gate electrode.

15. The semiconductor structure according to claim 14, wherein: The plurality of fourth plugs are distributed around the periphery of the same gate electrode and are electrically connected to the same gate electrode.

16. The semiconductor structure according to claim 14, wherein: Also includes: a first contact layer, located between the first lightly doped region and the first plug; a second contact layer located between the first doped region and the second plug; a third contact layer, located between the second doped region and the third plug; A fourth contact layer is located between the gate electrode and the fourth plug.

17. The semiconductor structure according to claim 16, wherein: The material of the substrate is silicon, and the material of the gate electrode is polysilicon; Materials of the first contact layer, the second contact layer, the third contact layer, and the fourth contact layer are all metal silicide.

18. The semiconductor structure according to claim 14, wherein: Also includes: An insulating layer covers the top surface of the protrusion, and the first plug penetrates the insulating layer along a direction perpendicular to the surface of the main body.

19. The semiconductor structure according to claim 18, wherein: Also includes: a first dielectric layer covering the surface of the gate electrode; a second dielectric layer covering a surface of the main body, a surface of the first dielectric layer, and a surface of the insulating layer; the second plug and the third plug both penetrate the second dielectric layer in a direction perpendicular to the surface of the main body; and the fourth plug penetrates the first dielectric layer in a direction perpendicular to the surface of the main body.

20. The semiconductor structure according to claim 12, wherein: The height of the protrusion along a direction perpendicular to the surface of the body portion is greater than the width of the protrusion along a direction parallel to the surface of the body portion.

21. The semiconductor structure according to claim 12, wherein: A height of the gate electrode is smaller than a height of the protrusion in a direction perpendicular to a surface of the body portion.

22. The semiconductor structure according to claim 12, wherein: The height of the protrusion is 30nm~100nm.

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