Semiconductor structure and preparation method thereof

Abstract

The present application provides a semiconductor structure and a method for preparing the same. The semiconductor structure includes an N-type semiconductor layer arranged on a substrate in a vertical direction; at least one multi-quantum well structure is formed on the N-type semiconductor layer in a horizontal direction, and a P-type semiconductor layer is formed above and on at least part of the side of each multi-quantum well structure; each multi-quantum well structure includes a plurality of semiconductor layers stacked in sequence in a vertical direction, and a multi-quantum well unit formed between two adjacent semiconductor layers; the P-type semiconductor layer is in contact with each semiconductor layer of the multi-quantum well structure in a vertical direction. The preparation method is used to prepare the semiconductor structure. The present application can realize the injection of carriers provided by the P-type semiconductor layer by lateral injection of carriers into the active region (light-emitting region) of each designed multi-quantum well structure, thereby ultimately forming a GaN-based LED structural material with multiple emission wavelengths.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Conventional GaN (gallium nitride)-based LEDs are widely used in various lighting products, such as indoor lighting. Conventional white LED lighting is achieved by growing GaN-based LED epitaxial wafers in the blue wavelength band. The blue light excites specific phosphors to produce a mixture of blue and yellow light. Similarly, conventional LCD displays use blue LEDs and phosphors to create white LEDs, which are then used as backlight sources for display applications.

[0003] However, how to simplify the structure to directly produce white light LEDs is a difficult problem that needs to be solved urgently in this technical field. Summary of the Invention

[0004] The present application provides a semiconductor structure and a preparation method thereof, which can realize the injection of carriers provided by the P-type semiconductor layer by lateral injection of carriers into the active area (light-emitting area) of each designed multi-quantum well structure, thereby ultimately forming a GaN-based LED structural material with multiple emission wavelengths.

[0005] To achieve the above objectives, according to an embodiment of the present application, a semiconductor structure is provided, comprising:

[0006] substrate;

[0007] An N-type semiconductor layer, wherein the N-type semiconductor layer is provided on the substrate;

[0008] A multi-quantum well structure, wherein the multi-quantum well structure is provided on the N-type semiconductor layer, the multi-quantum well structure comprising a plurality of semiconductor layers stacked in sequence, and a multi-quantum well unit formed between two adjacent semiconductor layers;

[0009] A P-type semiconductor layer is disposed above the multi-quantum well structure and on at least a portion of the side surfaces thereof, and the P-type semiconductor layer is in contact with each semiconductor layer of the multi-quantum well structure.

[0010] Optionally, a groove penetrating the N-type semiconductor layer is provided on the N-type semiconductor layer, and a multi-quantum well structure is formed in the groove.

[0011] Optionally, the number of the multi-quantum well structures is one or more;

[0012] When there are multiple multi-quantum well structures, the multiple multi-quantum well structures are arranged regularly or irregularly along the horizontal direction.

[0013] Optionally, the molar content of indium in each of the multiple semiconductor layers of the multi-quantum well structure is different.

[0014] Optionally, each semiconductor layer of the multi-quantum well structure includes a first sub-semiconductor layer and a second sub-semiconductor layer that are periodically stacked, and the multi-quantum well unit is formed between the first sub-semiconductor layer and the second sub-semiconductor layer, wherein the first sub-semiconductor layer contains indium.

[0015] Optionally, along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the molar content of indium in the first sub-semiconductor layer in each of the semiconductor layers increases successively.

[0016] Optionally, the material of the first sub-semiconductor layer of the semiconductor layer is InGaN, and the material of the second sub-semiconductor layer of the semiconductor layer is GaN;

[0017] The material of the N-type semiconductor layer is a group III nitride;

[0018] The material of the P-type semiconductor layer is group III nitride.

[0019] Optionally, the semiconductor structure further includes:

[0020] An intrinsic semiconductor layer is located between the substrate and the N-type semiconductor layer.

[0021] Optionally, the semiconductor structure further includes:

[0022] A stress release layer is located between the N-type semiconductor layer and the multi-quantum well structure.

[0023] Optionally, the material of the stress release layer includes GaN, InGaN, or a combination of the two.

[0024] Optionally, the semiconductor structure further includes a dielectric layer, the dielectric layer is located between the N-type semiconductor layer and the P-type semiconductor layer, the dielectric layer is formed with a hollow region, and the multi-quantum well structure is formed in the hollow region.

[0025] Optionally, along a direction from the N-type semiconductor layer to the P-type semiconductor layer, a side surface of the multi-quantum well structure extends obliquely inward, and the side surface is a slope or a curved surface.

[0026] Optionally, each of the multiple semiconductor layers in the multi-quantum well structure emits light at a different wavelength, the light emission closest to the N-type semiconductor layer is the shortest, and the light emission farthest from the N-type semiconductor layer is the longest.

[0027] Optionally, the preparation method comprises the following steps:

[0028] S1: forming an N-type semiconductor layer on the substrate in a vertical direction to form an intermediate semiconductor structure;

[0029] S2: forming a multi-quantum well structure on the intermediate semiconductor structure, wherein the multi-quantum well structure includes a plurality of semiconductor layers stacked in sequence and a multi-quantum well unit formed between two adjacent semiconductor layers;

[0030] S3: forming a P-type semiconductor layer above the multi-quantum well structure and on at least part of the side surfaces thereof, wherein the P-type semiconductor layer is in contact with each semiconductor layer of the multi-quantum well structure along a vertical direction.

[0031] Optionally, step S2 includes the following steps:

[0032] S21: forming a multi-quantum well layer on the intermediate semiconductor structure;

[0033] S22: forming a mask on the multi-quantum well layer;

[0034] S23: Etching or corroding the multi-quantum well layer through the mask to form the multi-quantum well structure;

[0035] S24: removing the mask.

[0036] Optionally, step S2 includes the following steps:

[0037] S21: forming a mask on the intermediate semiconductor structure;

[0038] S22: forming the multi-quantum well structure in the hollow region of the mask;

[0039] S23: removing the mask.

[0040] Optionally, step S2 includes the following steps:

[0041] S21: forming a stacked dielectric layer and a mask on the intermediate semiconductor structure;

[0042] S22: forming the multi-quantum well structure in the hollow regions of the mask and the dielectric layer, wherein the hollow regions of the mask are formed corresponding to the hollow regions of the dielectric layer;

[0043] S23: removing the mask.

[0044] Optionally, step S2 includes the following steps:

[0045] S21: forming a groove on the intermediate semiconductor structure;

[0046] S22: forming a multi-quantum well structure in the intermediate semiconductor structure and the groove.

[0047] Optionally, step S1 includes the following steps:

[0048] S11: forming an intrinsic semiconductor layer on the substrate;

[0049] S12: forming the N-type semiconductor layer on the intrinsic semiconductor layer;

[0050] S13: forming a stress release layer on the N-type semiconductor layer to form the intermediate semiconductor structure.

[0051] Optionally, in step S23 , the multi-quantum well layer is etched or corroded, and the depth of the etching or corrosion is equal to or less than the thickness of the multi-quantum well layer.

[0052] In the semiconductor structure and preparation method of the above-mentioned embodiment, a multi-quantum well structure is provided, and the P-type semiconductor layer is provided above the multi-quantum well structure and on at least part of the side surface. The P-type semiconductor layer is in contact with each semiconductor layer of the multi-quantum well structure in a vertical direction, thereby realizing that the injection method of carriers provided by the P-type semiconductor layer is different from the injection method of the vertical epitaxial material surface of the traditional LED, but rather the carriers are laterally injected into the active area (light-emitting area) of each designed multi-quantum well structure, thereby finally forming a GaN-based LED structural material with multiple emission wavelengths.

[0053] The semiconductor structure of the present application can be used in:

[0054] 1. No need to use phosphor or other color mixing methods to achieve white light LED;

[0055] 2. No need to add phosphors, directly encapsulate to replace traditional LCD backlight sources;

[0056] 3. Cooperate with bandpass filter to directly realize full-color display and other applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a structural schematic diagram of the semiconductor structure of Example 1 of the present application.

[0058] Figure 2 It is a structural schematic diagram of another implementation of the semiconductor structure of Example 1 of the present application.

[0059] Figure 3(a)-Figure 3(f) It is a process flow chart of the method for preparing the semiconductor structure of Example 1 of the present application.

[0060] Figure 4It is a structural schematic diagram of the semiconductor structure of Example 2 of the present application.

[0061] Figure 5(a)-Figure 5(d) It is a method for preparing a semiconductor structure of Example 2 of the present application and a process flow chart of the method for preparing a semiconductor structure.

[0062] Figure 6 It is a structural schematic diagram of the semiconductor structure of Example 3 of the present application.

[0063] Figure 7(a)-Figure 7(d) It is a method for preparing a semiconductor structure of Example 3 of the present application and a process flow chart of the method for preparing a semiconductor structure.

[0064] Figure 8 It is a structural schematic diagram of the semiconductor structure of Example 4 of the present application.

[0065] Figure 9(a)-Figure 9(d) It is a method for preparing a semiconductor structure of Example 4 of the present application and a process flow chart of the method for preparing a semiconductor structure.

[0066] Figure 10 It is a structural schematic diagram of the semiconductor structure of Example 5 of the present application.

[0067] Figure 11 It is a structural schematic diagram of another implementation of the semiconductor structure of Example 5 of the present application. DETAILED DESCRIPTION

[0068] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0069] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit this application. Unless otherwise defined, technical or scientific terms used in this application should have the same ordinary meaning as understood by persons of ordinary skill in the art to which this invention belongs. The use of "a," "an," and similar terms in this specification and claims does not indicate a limitation of quantity, but rather indicates the presence of at least one. "Include," "comprising," and similar terms mean that the elements or objects preceding "include" or "comprise" include the elements or objects listed after "include" or "comprise," and their equivalents, and do not exclude other elements or objects. "Connected," "connected," and similar terms are not limited to physical or mechanical connections and may include electrical connections, whether direct or indirect. "A plurality" includes two and is equivalent to at least two. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0070] Example 1

[0071] like Figure 1 As shown, this embodiment provides a semiconductor structure. The semiconductor structure includes: a substrate 10, an N-type semiconductor layer 30, a plurality of multi-quantum well structures 50, and a P-type semiconductor layer 60. In this embodiment, the number of multi-quantum well structures 50 is three, but this is not limited to this. It can also be set to two or other numbers according to design requirements.

[0072] The N-type semiconductor layer 30 is disposed along the vertical direction Y on the substrate 10 .

[0073] Three multi-quantum well structures 50 are spaced apart on the N-type semiconductor layer 30 along the horizontal direction X. Each multi-quantum well structure 50 includes a plurality of semiconductor layers stacked in sequence along the vertical direction Y, and a multi-quantum well unit 55 formed between two adjacent semiconductor layers.

[0074] The molar content of indium in each of the plurality of semiconductor layers is different, that is, the composition of indium in each of the plurality of semiconductor layers is different. In this embodiment, there is no limitation on how the composition of indium in each semiconductor layer varies. Along the direction from the N-type semiconductor layer 30 to the P-type semiconductor layer 60, the molar content of indium in each semiconductor layer may increase, decrease, change periodically, or change irregularly.

[0075] Specifically, such as Figure 1As shown in FIG, there are four semiconductor layers, which are sequentially recorded as a first semiconductor layer 51, a second semiconductor layer 52, a third semiconductor layer 53, and a fourth semiconductor layer 54 along the vertical direction Y. The molar content of indium in the first semiconductor layer 51, the second semiconductor layer 52, the third semiconductor layer 53, and the fourth semiconductor layer 54 is different. However, this is not limited to the above, and the number of semiconductor layers can be other values ​​according to design requirements. A multi-quantum well unit 55 is provided between the first semiconductor layer 51 and the second semiconductor layer 52, between the second semiconductor layer 52 and the third semiconductor layer 53, and between the third semiconductor layer 53 and the fourth semiconductor layer 54.

[0076] The P-type semiconductor layer 60 is disposed above each multi-quantum well structure 50 and at least partially on the side surfaces thereof. The P-type semiconductor layer 60 contacts each semiconductor layer of each multi-quantum well structure 50 along the vertical direction Y. In the present embodiment, the P-type semiconductor layer 60 is located above each multi-quantum well structure 50 and is disposed around the side surfaces of each multi-quantum well structure 50.

[0077] In this way, by setting up multiple multi-quantum well structures 50, and the P-type semiconductor layer 60 is set above each multi-quantum well structure 50 and around the side of each multi-quantum well structure 50, the P-type semiconductor layer 60 is in contact with each semiconductor layer of each multi-quantum well structure 50 along the vertical direction Y, thereby achieving the injection method of carriers provided by the P-type semiconductor layer 60 being different from the vertical epitaxial material surface injection method of traditional LEDs, but rather injecting carriers laterally into the active area (light-emitting area) of each designed multi-quantum well structure 50, ultimately forming a GaN-based LED structural material with multiple light-emitting wavelengths.

[0078] The material of the N-type semiconductor layer 30 is Group III nitride; the material of the P-type semiconductor layer 60 is Group III nitride.

[0079] Along the vertical direction Y, the semiconductor structure further includes: an intrinsic semiconductor layer 20 and a stress release layer 40 .

[0080] The intrinsic semiconductor layer 20 is located between the substrate 10 and the N-type semiconductor layer 30. It serves as a material buffer layer, improving material quality. The stress relief layer 40 is located between the N-type semiconductor layer 30 and the multi-quantum well structure 50. It relieves built-in stress in the material.

[0081] The material of the intrinsic semiconductor layer 20 is undoped GaN. The material of the stress release layer 40 includes one or a combination of GaN and InGaN.

[0082] Another embodiment of the present application is as follows Figure 2As shown, each semiconductor layer 51 includes a first sub-semiconductor layer 511 and a second sub-semiconductor layer 512 stacked along a vertical direction Y. A multi-quantum well unit 55 is also formed between the first sub-semiconductor layer 511 and the second sub-semiconductor layer 512. The first sub-semiconductor layer 511 contains indium. The molar content of indium in the first sub-semiconductor layer 511 in each semiconductor layer 51 increases in the direction from the N-type semiconductor layer 30 toward the P-type semiconductor layer 60. That is, the semiconductor layer 51 near the N-type semiconductor layer 30 has a multi-quantum well structure with a shorter wavelength, while the semiconductor layer 51 near the P-type semiconductor layer 60 has a multi-quantum well structure with a longer wavelength, thereby forming a multi-wavelength light-emitting structure.

[0083] The material of the first sub-semiconductor layer 511 of the semiconductor layer 51 is InGaN, and the material of the second sub-semiconductor layer 512 of the semiconductor layer 51 is GaN. In other words, the multi-quantum well structure 50 is a material structure in which InGaN material and GaN material are alternately stacked.

[0084] like Figure 3(a) to Figure 3(f) As shown, another aspect of this embodiment further provides a method for preparing a semiconductor structure, which is used to prepare the above-mentioned semiconductor structure. The preparation method includes the following steps:

[0085] S100: forming an N-type semiconductor layer 30 on the substrate 10 along a vertical direction Y to form an intermediate semiconductor structure;

[0086] S200: forming at least one multi-quantum well structure 50 on the intermediate semiconductor structure along a horizontal direction X, each multi-quantum well structure 50 including a plurality of semiconductor layers stacked in sequence along a vertical direction Y;

[0087] S300 : forming a P-type semiconductor layer 60 above each multi-quantum well structure 50 and at least partially on the side surfaces thereof. The P-type semiconductor layer 60 is in contact with each semiconductor layer of each multi-quantum well structure 50 along a vertical direction Y.

[0088] In step S100, specifically, as shown in FIG3(a), the following steps are included:

[0089] S110: forming an intrinsic semiconductor layer 20 on the substrate 10;

[0090] S120: forming an N-type semiconductor layer 30 on the intrinsic semiconductor layer 20;

[0091] S130 : forming a stress release layer 40 on the N-type semiconductor layer 30 to form an intermediate semiconductor structure.

[0092] In step S200, specifically, the following steps are included:

[0093] S210: As shown in FIG3(b), a multi-quantum well layer 90 is formed on the intermediate semiconductor structure. The multi-quantum well layer 90 includes a plurality of semiconductor layers stacked in sequence along a vertical direction Y, and a multi-quantum well unit formed between two adjacent semiconductor layers. The molar content of indium in each of the plurality of semiconductor layers is different. Specifically, in this embodiment, the number of semiconductor layers is four, and the four semiconductor layers are sequentially recorded as a first semiconductor layer 51, a second semiconductor layer 52, a third semiconductor layer 53, and a fourth semiconductor layer 54 along the vertical direction Y. The molar content of indium in the first semiconductor layer 51, the second semiconductor layer 52, the third semiconductor layer 53, and the fourth semiconductor layer 54 is different, but the present invention is not limited thereto. The number of semiconductor layers may be other values ​​according to design requirements. A multi-quantum well unit 55 is provided between the first semiconductor layer 51 and the second semiconductor layer 52, between the second semiconductor layer 52 and the third semiconductor layer 53, and between the third semiconductor layer 53 and the fourth semiconductor layer 54.

[0094] S220: As shown in FIG3( c ), a mask 80 is formed on the multi-quantum well layer 90 , and the mask 80 is patterned to form a hollow region 81 on the mask 80 ;

[0095] S230: As shown in FIG3(d), the multi-quantum well layer 90 is etched or corroded through the patterned mask 80. Specifically, a plurality of first grooves 91 are formed on the multi-quantum well layer 90 by combining external physical bombardment etching or chemical etching. The etching or corrosion depth (the depth of the first grooves 91) is the bottommost semiconductor layer (the first semiconductor layer 51), so as to form at least one multi-quantum well structure 50. Optionally, the etching depth is equal to or less than the thickness of the multi-quantum well layer 90.

[0096] S240: As shown in FIG3(e), the mask 80 is removed.

[0097] Next, in step S300, as shown in FIG3(f), the process returns to the vapor phase epitaxy apparatus, and a P-type semiconductor layer 60 is formed above each multi-quantum well structure 50 and around the sides of each multi-quantum well structure 50, and the P-type semiconductor layer 60 is in contact with each semiconductor layer of each multi-quantum well structure 50 along the vertical direction Y, thereby completing the preparation of the LED structural material having multiple emission wavelengths.

[0098] Example 2

[0099] like Figure 4As shown, this embodiment also provides a semiconductor structure, which is basically the same as the structure of the semiconductor structure in Example 1, except that: the number of multi-quantum well structures 50 is one, and the P-type semiconductor layer 60 is located above the multi-quantum well structure 50 and is arranged around the side of the multi-quantum well structure 50.

[0100] like Figure 5(a) to Figure 5(d) As shown, another aspect of this embodiment further provides a method for preparing a semiconductor structure, which is used to prepare the above-mentioned semiconductor structure. The preparation method is basically the same as the preparation method of Example 1, except that:

[0101] Step S200 includes the following steps:

[0102] S210: As shown in FIG5(a), a mask 80 is formed on the intermediate semiconductor structure, and the mask 80 is patterned to form a hollow region 81 on the mask 80;

[0103] S220: As shown in FIG5(b), forming a multi-quantum well structure 50 in the hollow region 81 of the mask 80;

[0104] S230: As shown in FIG5(c), the mask 80 is removed.

[0105] Next, in step S300, as shown in Figure 5(d), a P-type semiconductor layer 60 is formed above the multi-quantum well structure 50 and around the side of the multi-quantum well structure 50, and the P-type semiconductor layer 60 is in contact with each semiconductor layer of each multi-quantum well structure 50 along the vertical direction Y to complete the preparation of this LED structural material with multiple emission wavelengths.

[0106] It should be noted that the preparation method in this embodiment is also applicable to the preparation of the semiconductor structure in Example 1.

[0107] Example 3

[0108] like Figure 6 As shown, this embodiment further provides a semiconductor structure, which is substantially the same as the semiconductor structure in Example 2, except that:

[0109] The semiconductor structure also includes a dielectric layer 90, which is positioned between the N-type semiconductor layer 30 and the P-type semiconductor layer 60. The dielectric layer 90 includes a hollow region, within which the multi-quantum well structure 50 is formed. The dielectric layer 90 is used to prevent carrier recombination between the N-type semiconductor layer 30 and the P-type semiconductor layer 60, thereby preventing a decrease in the device's luminous efficiency. The dielectric layer 90 is made of silicon nitride.

[0110] like Figure 7(a) to Figure 7(d)As shown, another aspect of this embodiment further provides a method for preparing a semiconductor structure, which is used to prepare the above-mentioned semiconductor structure. This preparation method is basically the same as the preparation method of Example 2, except that:

[0111] Step S200 includes the following steps:

[0112] S210: As shown in FIG7( a ), a dielectric layer 90 and a mask 80 are stacked on the intermediate semiconductor structure, and the dielectric layer 90 and the mask 80 are patterned to form a hollow region 81 in the mask 80 and a hollow region 91 in the dielectric layer 900 ;

[0113] S220: As shown in FIG7( b ), a multi-quantum well structure 50 is formed in the hollow region 81 of the mask 80 and the hollow region 91 of the dielectric layer 90 , wherein the hollow region 81 of the mask 80 is formed corresponding to the hollow region 91 of the dielectric layer 90 ;

[0114] S230: As shown in FIG7(c), the mask 80 is removed.

[0115] Next, in step S300, as shown in FIG7(d), a P-type semiconductor layer 60 is formed above the dielectric layer 90, above the multi-quantum well structure 50, and around the side of the multi-quantum well structure 50, and the P-type semiconductor layer 60 is in contact with each semiconductor layer of each multi-quantum well structure 50 along the vertical direction Y to complete the preparation of this LED structural material with multiple emission wavelengths.

[0116] In this embodiment, the number of the multi-quantum well structure 50 is one, but the present invention is not limited thereto. The number of the multi-quantum well structures 50 may also be set to two or other numbers according to design requirements.

[0117] It should be noted that the preparation method in this embodiment is also applicable to the preparation of the semiconductor structure in Example 1.

[0118] Example 4

[0119] like Figure 8 As shown, this embodiment further provides a semiconductor structure, which is basically the same as the semiconductor structure in Example 1, except that: there are multiple multi-quantum well structures 50, and when the outer side of the outermost multi-quantum well structure 50 is flush with the outer side of the underlying N-type semiconductor layer 30, the multiple multi-quantum well structures 50 are arranged at intervals, and the P-type semiconductor layer 60 is located above all the multi-quantum well structures 50 and between two adjacent multi-quantum well structures 50; and, a groove 70 is provided on the N-type semiconductor layer 30 to penetrate the N-type semiconductor layer 30, and a multi-quantum well structure 90' ​​is also formed in the groove 70.

[0120] In this embodiment, the number of the multi-quantum well structures 50 is two, but the present invention is not limited thereto.

[0121] like Figure 9(a) to Figure 9(d) As shown, another aspect of this embodiment further provides a method for preparing a semiconductor structure, which is used to prepare the above-mentioned semiconductor structure. The preparation method is basically the same as the preparation method of Example 1, except that:

[0122] Step S200 includes the following steps:

[0123] S210: forming a groove 70 on the intermediate semiconductor structure;

[0124] S220 : forming a multi-quantum well structure 50 on the intermediate semiconductor structure, and also forming a multi-quantum well structure 90 ′ in the groove 70 .

[0125] In step S210, as shown in FIG9(a), after forming the N-type semiconductor layer 30 of the intermediate semiconductor structure, the N-type semiconductor layer 30 is etched to form a second groove 71. Then, as shown in FIG9(b), a stress relief layer 40 is formed on the unetched N-type semiconductor layer 30, and a third groove 72 is formed above the second groove 71 in the same layer as the N-type semiconductor layer 30. In this way, the final groove 70 is formed by stacking the second groove 71 and the third groove 72. Alternatively, the groove 70 can be formed directly by etching on the final intermediate semiconductor structure.

[0126] In step S220, as shown in FIG9(c), since a groove 70 is formed in the intermediate semiconductor structure, when the multi-quantum well structure is subsequently formed, the multi-quantum well layer located on the intermediate semiconductor structure naturally forms a multi-quantum well structure 50 with a partition 56 in the middle, and a multi-quantum well structure 90' ​​is also formed in the groove 70. The multi-quantum well structure 90' ​​formed in the groove 70 can prevent carriers from the P-type semiconductor layer 60 from being directly injected into the N-type semiconductor layer 30.

[0127] In step 300 , as shown in FIG9( d ), since the outer side of the outermost multi-quantum well structure 50 is flush with the outer side of the underlying N-type semiconductor layer 30 , the P-type semiconductor layer 60 is located above all the multi-quantum well structures 50 and between two adjacent multi-quantum well structures 50 .

[0128] It should be noted that the preparation method in this embodiment is also applicable to the preparation of the semiconductor structures in Embodiment 1 and Embodiment 2.

[0129] Example 5

[0130] like Figure 10As shown, this embodiment further provides a semiconductor structure, which is substantially the same as the semiconductor structure in Example 1, except that:

[0131] Along the direction from the N-type semiconductor layer 30 to the P-type semiconductor layer 60, the side surface 50a of the multi-quantum well structure 50 extends obliquely inward, and the side surface is an inclined surface, that is, the cross section of the multi-quantum well structure 50 is formed as follows: Figure 10 The trapezoid shown in .

[0132] like Figure 11 As shown, in another embodiment, the side surface 50a of the multi-quantum well structure 50 is a curved surface.

[0133] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor structure, characterized in that It includes: substrate; An N-type semiconductor layer, wherein the N-type semiconductor layer is provided on the substrate; A multi-quantum well structure, the multi-quantum well structure being disposed on the N-type semiconductor layer, the multi-quantum well structure comprising a plurality of semiconductor layers stacked in sequence, and a multi-quantum well unit formed between two adjacent semiconductor layers; the semiconductor layers of the multi-quantum well structure comprising a first sub-semiconductor layer and a second sub-semiconductor layer periodically stacked, the multi-quantum well unit being formed between the first sub-semiconductor layer and the second sub-semiconductor layer, wherein the first sub-semiconductor layer contains indium; and the molar content of indium in each of the plurality of semiconductor layers of the multi-quantum well structure is different; A P-type semiconductor layer is disposed above the multi-quantum well structure and on at least a portion of the side surfaces thereof, and the P-type semiconductor layer is in contact with each semiconductor layer of the multi-quantum well structure.

2. The semiconductor structure according to claim 1, wherein A groove penetrating the N-type semiconductor layer is provided on the N-type semiconductor layer, and a multi-quantum well structure is formed in the groove.

3. The semiconductor structure according to claim 1, wherein: The number of the multi-quantum well structures is one or more; When there are multiple multi-quantum well structures, the multiple multi-quantum well structures are arranged regularly or irregularly along the horizontal direction.

4. The semiconductor structure according to claim 1, wherein Along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the molar content of indium in the first sub-semiconductor layer in the semiconductor layer increases successively.

5. The semiconductor structure according to claim 4, wherein: The material of the first sub-semiconductor layer of the semiconductor layer is InGaN, and the material of the second sub-semiconductor layer of the semiconductor layer is GaN; The material of the N-type semiconductor layer is a group III nitride; The material of the P-type semiconductor layer is group III nitride.

6. The semiconductor structure according to claim 1, wherein The semiconductor structure further comprises: An intrinsic semiconductor layer is located between the substrate and the N-type semiconductor layer.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: A stress release layer is located between the N-type semiconductor layer and the multi-quantum well structure.

8. The semiconductor structure according to claim 7, wherein: The material of the stress release layer includes one of GaN and InGaN or a combination of the two.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a dielectric layer, the dielectric layer is located between the N-type semiconductor layer and the P-type semiconductor layer, the dielectric layer is formed with a hollow region, and the multi-quantum well structure is formed in the hollow region.

10. The semiconductor structure according to claim 1, wherein: Along the direction from the N-type semiconductor layer to the P-type semiconductor layer, the side surface of the multi-quantum well structure extends inwardly at an angle, and the side surface is a slope or a curved surface.

11. The semiconductor structure according to claim 1, wherein: Each of the plurality of semiconductor layers in the multi-quantum well structure emits light at a different wavelength. The light emission wavelength of the layer closest to the N-type semiconductor layer is the shortest, and the light emission wavelength of the layer farthest from the N-type semiconductor layer is the longest.

12. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises the following steps: S1: forming an N-type semiconductor layer on the substrate in a vertical direction to form an intermediate semiconductor structure; S2: forming a multi-quantum well structure on the intermediate semiconductor structure, the multi-quantum well structure comprising a plurality of semiconductor layers stacked in sequence, and a multi-quantum well unit formed between two adjacent semiconductor layers; the semiconductor layers of the multi-quantum well structure comprising a first sub-semiconductor layer and a second sub-semiconductor layer periodically stacked, the multi-quantum well unit being formed between the first sub-semiconductor layer and the second sub-semiconductor layer, wherein the first sub-semiconductor layer contains indium; and the molar content of indium in each of the plurality of semiconductor layers of the multi-quantum well structure is different; S3: forming a P-type semiconductor layer above the multi-quantum well structure and on at least a portion of the side surfaces thereof, wherein the P-type semiconductor layer is in contact with each of the semiconductor layers along a vertical direction.

13. The method for preparing a semiconductor structure according to claim 12, wherein: Step S2 includes the following steps: S21: forming a multi-quantum well layer on the intermediate semiconductor structure; S22: forming a mask on the multi-quantum well layer; S23: Etching or corroding the multi-quantum well layer through the mask to form the multi-quantum well structure; S24: removing the mask.

14. The method for preparing a semiconductor structure according to claim 12, wherein: Step S2 includes the following steps: S21: forming a mask on the intermediate semiconductor structure; S22: forming the multi-quantum well structure in the hollow region of the mask; S23: removing the mask.

15. The method for preparing a semiconductor structure according to claim 12, wherein: Step S2 includes the following steps: S21: forming a stacked dielectric layer and a mask on the intermediate semiconductor structure; S22: forming the multi-quantum well structure in the hollow regions of the mask and the dielectric layer, wherein the hollow regions of the mask are formed corresponding to the hollow regions of the dielectric layer; S23: removing the mask.

16. The method for preparing a semiconductor structure according to claim 12, wherein: Step S2 includes the following steps: S21: forming a groove on the intermediate semiconductor structure; S22: forming a multi-quantum well structure in the intermediate semiconductor structure and the groove.

17. The method for preparing a semiconductor structure according to claim 12, wherein: Step S1 includes the following steps: S11: forming an intrinsic semiconductor layer on the substrate; S12: forming the N-type semiconductor layer on the intrinsic semiconductor layer; S13: forming a stress release layer on the N-type semiconductor layer to form the intermediate semiconductor structure.

18. The method for preparing a semiconductor structure according to claim 13, wherein: In step S23, the multi-quantum well layer is etched or corroded, and the depth of the etching or corrosion is equal to or less than the thickness of the multi-quantum well layer.

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