Methods of manufacturing 3D NAND using nickel or cobalt alloys

Abstract

This invention relates to a process for metallizing a semiconductor substrate, particularly for manufacturing 3D NAND memories. The metallization process includes activating the surface of a dielectric material with a noble metal such as palladium, followed by depositing a nickel or cobalt alloy using an electroless process with a solution containing metal ions.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to three-dimensional devices, such as three-dimensional vertical NAND memory. Background Technology

[0002] 3D NAND memory devices consist of a semiconductor substrate and an insulating material layer made of inorganic dielectric. Alternating stacks of conductive material layers, called "word lines," are arranged on the semiconductor substrate and are essentially metallic. On the sides of the device, this stack can be etched into a "staircase" pattern, where the length and number of layers decrease from one level to the next in the upward direction.

[0003] In the region with the highest number of layers, the conductor / insulator stack is pierced with polycrystalline silicon semiconductor channels across its entire height. Pads consisting of tunnel dielectric (typically SiO2), charge storage materials (such as silicon nitride), and inorganic oxide barrier dielectrics are inserted between each semiconductor channel and the conductor / insulator stack to create a three-dimensional array of memory cells, with each cell located at the intersection of a channel and a word line.

[0004] NAND flash memory manufacturers are seeking to increase the storage capacity of NAND flash memory by increasing the number of word lines and memory cells. However, significant challenges arise as the stacking height increases. In fact, as the number of layers increases, their thickness must decrease.

[0005] In current manufacturing processes, word lines are created by simultaneously filling several rows of thin, horizontal cavities separated by insulating layers, with tungsten being the most commonly used conductive material. Tungsten is typically deposited in two steps: atomic layer deposition (ALD) to create a thin adhesion layer, followed by chemical vapor deposition (PECVD) to completely fill the cavities. However, the deeper the stack, the more difficult it becomes to completely fill them. This problem is amplified when the word lines to be manufactured are thinner and the cavity openings are smaller. As a result, material voids form in the tungsten deposit, leading to loss of conductivity and storage failures. This filling technique has shown its limitations, especially for stacks containing 96 or 128 word lines.

[0006] Furthermore, existing vapor deposition processes often deform silicon samples, causing them to bend after annealing at the end of the process. To avoid this deformation, it has been suggested to deposit a layer on the back side of the wafer (with the front side stacked and covered) using plasma-enhanced chemical vapor deposition (PECVD) followed by EOS. Etching. However, the disadvantage of this method is that it adds at least two steps to the manufacturing process of the memory device, and the back side processing needs to be controlled in subsequent steps to avoid damaging the front side.

[0007] Therefore, there is a need to provide an improved 3D NAND memory, particularly to manufacture a 3D NAND memory whose word lines have higher conductivity than those of the same level in the prior art. The increase in conductivity is achieved by adjusting at least one of the following two parameters: reducing material voids in the lines and / or optimizing the conductor volume available for creating the lines.

[0008] In existing technologies, particularly when word lines are based on tungsten, it is necessary to insert a thin layer, known as a "barrier" material, between the metal line and the barrier dielectric (typically SiO2, optionally combined with alumina Al2O3). This barrier material prevents elements contained in the metal from migrating into the dielectric. The barrier material layer reduces the space available for the metal, imposing a height requirement on the space to be filled. An example of existing material combinations inserted between a polysilicon channel and a tungsten line is polySi / SiO / SiN / SiO2 / Al2O3 / TiN / W. The increasing number of successive layers deposited to create the word lines significantly limits the volume of the tungsten conductor. Furthermore, the deposition of additional material increases the number of steps required to manufacture the memory device.

[0009] Therefore, there is still a need for a method for manufacturing semiconductor devices such as 3D NAND memories that includes fewer steps, particularly fewer steps for depositing material between the semiconductor channel and the conductive metal.

[0010] In 3D NAND memory devices, there are also contact points between the polysilicon channel and the copper bit lines. Similar to the word lines mentioned above, the contacts are typically made of tungsten, and a thin layer of so-called "barrier material" needs to be inserted between the contacts and the polysilicon. A barrier material also needs to be inserted between the copper bit lines and the tungsten contacts. Therefore, the issues associated with fabricating word lines also apply to fabricating contacts and bit lines. Thus, it remains necessary to manufacture a 3D NAND memory where the conductivity between the word lines and bit lines is improved by limiting or eliminating the use of barrier materials such as titanium nitride and tantalum nitride. Summary of the Invention

[0011] This invention addresses these different needs by replacing the metals used in the prior art for manufacturing 3D NAND devices, such as tungsten, with nickel or cobalt alloys containing elements selected from boron, phosphorus, tungsten, or mixtures thereof.

[0012] This invention also responds to these diverse needs by providing a process for manufacturing 3D NAND memory, wherein the step of depositing conductive metal in the stage of creating word lines, bit lines, or contacts between semiconductor channels and bit lines uses a wet process, whereas prior art can only achieve this through a dry process. Specifically, the conductive metal deposition step is performed in two steps: the first step includes surface activation of the inorganic oxide with a noble metal, and then the second step includes depositing metal on the activated inorganic oxide by contacting the surface without polarization with an electroless solution containing metal ions and a reducing agent of the metal ions.

[0013] This process involves depositing nickel and boron alloys via an electroless process (electrodeization without a substrate). The method of this invention has the unique characteristic of producing metal deposits using a wet process with an aqueous electrolyte, rather than a dry process as in the prior art. The method of this invention enables the creation of numerous line-filled structures. The specific filling kinetics observed in this process allow the metal growth rate to adapt to these new dimensions. This result is particularly achieved through the nature of the chemical composition of the electrolyte.

[0014] The method of this invention allows for the direct deposition of a metal layer onto an inorganic dielectric material. This method also avoids the deposition of a barrier layer, typically titanium nitride or tantalum nitride, with titanium nitride being more common. Eliminating the barrier material has two advantages: it eliminates a step in the process without reducing the conductivity of the metal wire. The inventors discovered that nickel-boron alloys do not diffuse into the dielectric. Nickel-boron alloys, used instead of tungsten as conductors, not only possess barrier properties but also exhibit higher conductivity than tungsten.

[0015] Detailed description

[0016] Therefore, the present invention provides a method for manufacturing 3D NAND memory, the method comprising at least one process of selectively metallizing an inorganic oxide surface in a solvent phase, the metallization being performed by depositing an alloy of nickel or cobalt with an element selected from boron, phosphorus, and tungsten, said metallization process comprising:

[0017] - The step of activating the surface of an inorganic oxide with a noble metal, followed by the activation step is

[0018] - The step of contacting the surface with an electroless solution without polarization, the electroless solution containing nickel or cobalt metal ions, at least one reducing agent for the metal ions containing at least one element selected from boron, phosphorus and tungsten, and a polyamine, to form a nickel or cobalt alloy deposit.

[0019] An "alloy" is a solid solution in which elements are uniformly dispersed in nickel or cobalt.

[0020] The alloy deposition step can advantageously be performed by subjecting the inorganic oxide surface to ultrasonic waves. Elements selected from boron, phosphorus, and tungsten preferably constitute 1 to 10 atomic percent of the alloy. The metal deposit preferably consists of an alloy of nickel and at least one element selected from boron, phosphorus, and tungsten, wherein the element can be 1 atomic percent to 10 atomic percent. According to one embodiment of the invention, the metal consists of a nickel-boron alloy containing 6 atomic percent boron.

[0021] The inorganic oxide that comes into contact with the non-electrolyte solution can be SiO2 or Al2O3.

[0022] Nickel or cobalt alloy deposits can be formed at various stages of the 3D NAND memory manufacturing process. For example, alloys are deposited to form word lines, contacts between polysilicon channels and bit lines, or barrier layers for bit lines.

[0023] The noble metal can be ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). In one particular embodiment, the noble metal used to activate the inorganic oxide surface is palladium.

[0024] Another object of the present invention is a 3D NAND device comprising an alloy of nickel or cobalt with at least one element selected from boron, phosphorus and tungsten, which can be manufactured by any of the methods described above.

[0025] This application also describes a process for metallizing a semiconductor substrate, the substrate including at least one horizontal cavity opening onto a vertical cavity, the horizontal cavity having an opening size smaller than the vertical cavity, the cavities defining a surface comprising at least one region of inorganic oxide, the metallization process including a step of selectively activating the inorganic oxide surface, followed by a step of depositing metal on the activated inorganic oxide surface by contacting the surface with an electroless solution without polarization, the electroless solution comprising metal ions, a reducing agent for such ions, an inhibitor suitable for the horizontal cavity, and an inhibitor suitable for the vertical cavity.

[0026] The present invention also provides an electrolyte for filling cavities with opening sizes of less than 1 micrometer or even 100 nm.

[0027] The present invention also provides an electrolyte for manufacturing 3D NAND memory. This electrolyte can form metal deposits on substrates with very different morphologies in terms of size and bump. Therefore, it is not necessary to use different metallization techniques depending on the starting substrate to be covered: this simplifies the manufacturing process of memory devices. In particular, the electrolyte allows complex substrates containing multiple cavities of different sizes—especially those with different widths (or dimensions) at the openings—to simultaneously fill all cavities, and to deposit metal in the cavities using a single solution of ions containing metal ions and a reducing agent for the metal ions. This process can yield metal deposits without material defects on surfaces with highly irregular morphological bumps.

[0028] This invention results in a dielectric / metal multilayer structure with excellent interlayer adhesion.

[0029] The electrolyte and metallization process of this invention can also form metal deposits of uniform quality over complex geometries. Because the barrier layer necessary in the prior art to ensure proper device operation is eliminated between the conductive metal and the dielectric, the conductivity of the wire network in the device is improved. Attached Figure Description

[0030] Figure 1 A schematic portion of a 3D NAND memory according to the prior art is shown.

[0031] Figure 2A A substrate is shown for implementing a metallization process of the prior art or a metallization process according to the present invention to produce word lines.

[0032] Figure 2B Etching was shown Figure 2A The steps of substrate preparation.

[0033] Figure 2C A substrate covered with a nickel or cobalt alloy obtained by performing a metallization process according to the invention is shown.

[0034] Figure 2D The image shows nickel or cobalt alloy word lines of a 3D NAND device obtained by implementing the metallization process according to the invention.

[0035] Figure 3 This demonstrates 3D NAND devices along the existing technology. Figure 1 The cross section of axis B-B'.

[0036] Figure 4A The substrate to be metallized with a nickel or cobalt alloy using the process of the present invention is shown.

[0037] Figure 4B Showing Figure 4AThe substrate has been metallized according to the process of the present invention to obtain a deposit of nickel or cobalt alloy that fills the cavity to form word lines.

[0038] Figure 5 Showing Figure 4A The substrate has been metallized according to the process of the present invention to obtain a deposit of nickel or cobalt alloy covering the cavity walls without filling the cavity.

[0039] Figure 6 The illustration shows a substrate used for manufacturing peripheral contacts according to the process of the present invention or according to a prior art process.

[0040] Figure 7 Showing Figure 6 The substrate, which has been etched upstream of the metallization.

[0041] Figure 8 The process according to the invention demonstrates metallization using nickel or cobalt alloys. Figure 7 The substrate.

[0042] Figure 9 This demonstrates the metallization process using barrier materials and tungsten according to existing technologies. Figure 7 The substrate.

[0043] Figure 10 The illustration shows a substrate used in the fabrication of contacts between semiconductor channels and bit lines using a process according to the present invention or a prior art process.

[0044] Figure 11 Showing Figure 10 The substrate has been etched to define cavities for filling metal using the process according to the invention or a prior art process.

[0045] Figure 12 The process according to the invention demonstrates metallization using nickel or cobalt alloys. Figure 11 The substrate.

[0046] Figure 13 This demonstrates the metallization process using barrier materials and tungsten according to existing technologies. Figure 11 The substrate.

[0047] Figure 14 Schematic details of a 3D NAND device including bit lines of a nickel or cobalt alloy obtained according to the method of the present invention are shown.

[0048] Figure 15 The illustration shows schematic details of a 3D NAND device including copper-based bit lines according to the prior art.

[0049] Figure 16The process according to the present invention shows that the silicon metallized substrate obtained is free from bending compared to prior art silicon metallized substrates.

[0050] Figure 17 The EELS curves of the nickel-boron alloy obtained according to the process of the present invention are shown. Detailed Implementation

[0051] The first objective of this invention is a method for manufacturing 3D NAND memory, comprising a process of selectively metallizing an inorganic oxide surface in a solvent phase with an alloy of nickel or cobalt with elements selected from boron, phosphorus, and tungsten or mixtures thereof, the metallization process comprising:

[0052] - The step of activating the surface of the inorganic oxide with a noble metal, followed by the activation step is

[0053] - The step of contacting the surface with an electroless solution without polarization, the electroless solution containing nickel or cobalt metal ions, a reducing agent for the metal ions containing at least one element selected from boron, phosphorus and tungsten, and a polyamine, to form a nickel or cobalt alloy deposit.

[0054] The manufacturing method of the present invention can be part of a more globally integrated scheme for 3D NAND memory, wherein conductive and dielectric materials are assembled and deposited according to specific geometries, enabling the creation of functional elements, including word lines, contacts between polysilicon channels and bit lines, peripheral contacts between word lines and source lines, and bit lines themselves. Therefore, in the manufacturing method of the present invention, nickel or cobalt alloys can be used in the composition of various functional elements and deposited at various stages of the 3D NAND memory integration scheme.

[0055] In a first embodiment of the first objective of the present invention, a nickel or cobalt alloy deposit is included in the composition of the word lines of the 3D NAND memory.

[0056] In this context, alloy deposition can therefore be achieved through a solvent-phase metallization process for a semiconductor substrate intended for fabrication of 3D NAND memory, the substrate defining a horizontal plane and having at least two series of horizontal cavities opening onto vertical cavities, these cavities defining a surface comprising at least one region of inorganic oxide, the metallization process comprising:

[0057] - The step of activating the region of the inorganic oxide by contacting the surface with an activation solution comprising at least one palladium complex, at least one organosilane compound and at least one solvent, followed by

[0058] - A step of depositing metal on an activated region of an inorganic oxide by contacting the surface of a cavity with an electroless solution containing metal ions and at least one reducing agent for the metal ions without polarization. The electroless solution may also contain at least one first inhibitor suitable for horizontal cavities and at least one second inhibitor suitable for vertical cavities.

[0059] The first inhibitor can be an aliphatic polyamine with a number-average molecular weight of less than 500 g / mol, such as dipropylenetriamine. The second inhibitor can be polyethyleneimine with a number-average molecular weight greater than or equal to 500 g / mol. The reducing agent can be hypophosphite, and the electroless solution can contain at least two reducing agents, with hypophosphite as the first reducing agent and dimethylaminoborane as the second reducing agent.

[0060] According to one embodiment, the concentration of metal ions is 10. -3 The concentrations of the first inhibitor are in the range of 5 mg / L to 100 mg / L, from M to 1 M.

[0061] The horizontal cavity, for example, has an average diameter at the opening in the range of 10 nm to 50 nm and a depth in the range of 30 nm to 80 nm. Furthermore, the inorganic oxide consists of SiO2 and / or Al2O3.

[0062] The present invention also provides a process for manufacturing 3D NAND memory, comprising:

[0063] - The step of preparing a semiconductor substrate defining a horizontal plane and comprising at least one surface of an inorganic oxide, the inorganic oxide surface comprising at least two sets of horizontal cavities leading to vertical cavities.

[0064] - The step of activating the inorganic oxide surface using an activation solution containing at least one palladium complex, an organosilane compound, and a solvent.

[0065] - By subjecting the surface to a mixture containing metal ions, at least one reducing agent for the metal ions, at least one first aliphatic polyamine with a molecular weight of 500 g / mol to 25000 g / mol, and at least one second aliphatic polyamine with a molecular weight lower than that of the first polyamine without polarization.

[0066] Finally, the present invention provides a solvent phase and electroless metallization process for a semiconductor substrate, the semiconductor substrate including a cavity with an average width of less than 1 micrometer at its opening, the cavity defining a surface comprising at least one region of insulating material, the metallization process comprising:

[0067] - The step of activating the surface of the insulating material by contacting the surface with an activation solution comprising at least one palladium complex, at least one bifunctional adhesive and at least one solvent, followed by

[0068] - A step of depositing metal on an activated surface by contacting the metal with a solution containing metal ions such as Ni(II) or Co(II) ions, hypophosphite, and dipropylenetriamine without polarization.

[0069] The molar ratio of metal ions to dipropyltriamine is preferably greater than 10:1.

[0070] In this process, the width of the cavity opening is preferably less than 500 nm, for example less than a value selected from 400 nm, 300 nm, 200 nm, 100 nm and 50 nm.

[0071] The process of the present invention, in all its particular forms and embodiments, includes the step of activating the surface of an inorganic dielectric material, on which a metal is subsequently deposited.

[0072] The dielectric material can be an inorganic oxide, preferably selected from silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide, zirconium oxide and their silicates.

[0073] According to a specific embodiment of the invention, the substrate includes a cavity, and the available surface area of ​​the cavity includes insulating regions, all of which are composed of silicon oxide and / or aluminum oxide. All insulating regions have either a silicon oxide surface or an aluminum oxide surface. Alternatively, some insulating regions have a silicon oxide surface while others have an aluminum oxide surface.

[0074] The surface of dielectric materials, especially inorganic oxides, can be activated in the solvent phase in a step prior to being covered by metal deposited by an electroless method.

[0075] Surface activation can be achieved, for example, by grafting a noble metal such as palladium, as taught in documents FR2950063-A1 or FR2950634-A1. The principle of grafting is to introduce palladium into solution as a complex in the presence of a bifunctional ligand. The properties of the ligand used depend on the properties of the dielectric material to be activated.

[0076] Surface activation of the insulating layer can also be achieved by depositing metal nanoparticles, such as nickel-boron nanoparticles as described in WO2010 / 001054.

[0077] According to one embodiment, when the dielectric is an inorganic oxide, particularly SiO2 or Al2O3, surface activation is carried out by an activation solution containing a solvent, a palladium complex used as an activator, and a bifunctional binder, such as an organosilane compound, which functions as an adhesion promoter.

[0078] Therefore, the activator can be composed of one or more palladium complexes, such as (NH4)2(PdCl4); Pd(NH3)4 or complex of formula (I).

[0079]

[0080] in:

[0081] -R1 and R2 are the same, representing H; CH2CH2NH2; CH2CH2OH; or R1 represents H, and R2 represents CH2CH2NH2; or R1 represents CH2CH2NH2, and R2 represents CH2CH2NHCH2CH2NH2; or R1 represents H, and R2 represents CH2CH2NHCH2CH2NHCH2CH2NH2.

[0082] -X is selected from Cl - ;Br - ;I - H2O, NO3 - CH3SO3 - CF3SO3 - CH3-Ph-SO3 - CH3COO - ligands;

[0083] According to a specific feature of the invention, the solution contains a concentration of 10 -6 M to 10 -2 M, Preferred 10 -5 M to 10 -3 M, more preferably 5.10 -5 M to 5.10 -4 The above-mentioned activator of M.

[0084] An adhesion promoter composed of one or more organosilanes in an activated solution ensures adhesion between the metal top layer and the inorganic oxide.

[0085] According to a specific feature of the present invention, the organosilane compound conforms to the general formula (Va):

[0086] {X-(L)} 3-n Si(OR) n (Va)

[0087] -where X represents a functional group selected from thiols, pyridyl, epoxy (oxetyl), glycidyl, primary amines and capable of reacting with simple palladium compounds or formula (I);

[0088] -L represents a spacer arm selected from CH2; CH2CH2; CH2CH2CH2-; CH2CH2CH2CH2-; CH2CH2NHCH2CH2; CH2CH2CH2NHCH2CH2; CH2CH2CH2NHCH2CH2NHCH2CH2; CH2CH2CH2NHCH2CH2CH2CH2CH2CH2; Ph; Ph-CH2; and CH2CH2-Ph-CH2; (Ph represents the benzene ring).

[0089] -R represents a group selected from CH3, CH3CH2, CH3CH2CH2, and (CH3)2CH; and

[0090] -n is an integer equal to 2 or 3.

[0091] Organosilanes can also conform to formula (Vb):

[0092] (OR)3Si-(L)-Si(OR)3 (Vb)

[0093] -Where L represents a spacer arm selected from CH2CH2CH2NHCH2CH2NHCH2CH2CH2 and CH2CH2CH2-SS-CH2CH2CH2.

[0094] -R represents a group selected from CH3, CH3CH2, CH3CH2CH2, and (CH3)2CH.

[0095] Compounds of formula (Va) or (Vb) are selected, for example, from the following compounds: (3-aminopropyl)triethoxysilane; (3-aminopropyl)trimethoxysilane; m-aminophenyltrimethoxysilane; p-aminophenyltrimethoxysilane; p, m-aminophenyltrimethoxysilane; 4-aminobutyltriethoxysilane; m, p-(aminoethylaminomethyl)phenethyltrimethoxysilane; N-(2-aminoethyl)-3-aminopropyltriethoxysilane; N-(2-aminoethyl)-3-aminopropyltrimethoxysilane; 2-(4-pyridylethyl)triethoxysilane; bis(3-trimethoxysilylpropyl)ethylenediamine; (3-tri... N-(3-trimethoxysilylpropyl)diethylenetriamine; N-(6-aminohexyl)aminopropyltrimethoxysilane; (3-glycidoxypropyl)trimethoxysilane; (3-glycidoxypropyl)triethoxysilane; 5,6-epoxyhexyltriethoxysilane; (3-mercaptopropyl)trimethoxysilane; (3-mercaptopropyl)triethoxysilane; bis[3-(triethoxysilyl)propyl]disulfide; 3-chloropropyltrimethoxysilane; 3-chloropropyltriethoxysilane; (p-chloromethyl)phenyltrimethoxysilane; m, p-((chloromethyl)phenylethyl)trimethoxysilane.

[0096] As preferred organosilane compounds applicable in the context of this invention, compounds of formula (Va) are particularly mentioned, wherein: X represents an NH2 group and L represents CH2CH2CH2- and R represents CH3 (a compound named (3-aminopropyl)trimethoxysilane or APTMS); or L represents CH2CH2CH2- and R represents CH3CH2 (a compound named (3-aminopropyl)triethoxysilane or APTES); or L represents CH2CH2NHCH2CH2 and R represents CH3 (a compound named [3-(2-aminoethyl)aminopropyl]trimethoxysilane or DATMS or DAMO). X represents SH; L represents CH2CH2CH2- and R represents CH2-CH3 (a compound named (3-mercaptopropyl)trimethoxysilane or MPTES); or X represents C6H5N; L represents CH2CH2- and R represents CH2-CH3 (a compound named 2-(4-pyridylethyl)triethoxysilane or PETES); or X represents CHCH2O; L represents CH2CH2CH2 and R represents CH3 (a compound named (3-glycidoxypropyl)trimethoxysilane or EPTMS); or X represents Cl; L represents CH2CH2CH2 and R represents CH3 (a compound named 3-chloropropyltrimethoxysilane or CPTMS).

[0097] In the context of this invention, a particularly preferred organosilane compound is (3-aminopropyl)trimethoxysilane (APTMS).

[0098] Advantageously, the concentration of the organosilane compound is 10. -5 M to 10 -1 M, preferably 10 -4 M to 10 -2 M, more preferably 5.10 -4 M to 5.10 -3 M.

[0099] According to a particularly advantageous feature, the above-mentioned activation solution contains a very small amount of water. Therefore, water can be present at a concentration of less than 1 vol%, preferably less than 0.5 vol%, and even more preferably less than 0.2 vol%.

[0100] The solvent of the solution must be able to dissolve the activator and binder defined above. The solvent system may consist of one or more solvents selected from: N-methylpyrrolidone (NMP), dimethyl sulfoxide (DMSO), alcohols, ethylene glycol ethers such as monoethyl diethylene glycol (EDEG), propylene glycol ethers, dioxane, and toluene. Typically, the solvent system advantageously consists of a mixture of a solvent capable of dissolving palladium compounds and a solvent such as ethylene glycol ether or propylene glycol ether. In the context of this invention, a particularly preferred solvent system is dimethyl sulfoxide (DMSO) alone or a mixture of dimethyl sulfoxide (DMSO) and diethylene glycol monoethyl ether (EDEG), especially because of its very low toxicity. These compounds can be used in volume ratios of 1:200 to 1:5, preferably about 1:10.

[0101] According to one particular embodiment, the surface of an insulating substrate comprising silica or alumina can be activated with a palladium complex, such as palladium-diethylenetriamine complex, using aminopropyl-trimethoxy-silane as a bifunctional organic binder.

[0102] The process of this invention includes a step of metallizing an inorganic oxide substrate. This step is performed after a step of activating the substrate using a bifunctional palladium / ligand complex system or by depositing metal nanoparticles.

[0103] Preferably, a metal selected from noble metals and transition metals and their alloys will be used. Palladium is a specific example of the present invention.

[0104] The metal ions are, for example, nickel(II) ions or cobalt(II) ions.

[0105] Metals can be alloyed with at least one other element selected from phosphorus and boron. A particular embodiment of the invention uses nickel alloyed with boron.

[0106] In the context of this invention, the coating of the surface activated in the previous steps may optionally be performed by contacting the surface with a liquid solution, preferably an aqueous solution, containing:

[0107] - At least one metal salt, preferably with a concentration of 10 -3 M to 1M;

[0108] -A mixture of multiple reducing agents, preferably in an amount of 10. -6 M to 1M;

[0109] - A reagent used to adjust and maintain the pH value at 6 to 11, preferably 8 to 10;

[0110] - A reagent with vertical cavity suppression effect, preferably at a concentration of 0.5 ppm to 100 ppm, and

[0111] - A reagent or mixture of reagents having a horizontal cavity suppression effect, preferably at a concentration of 0.5 ppm to 100 ppm.

[0112] The electrolyte may optionally contain at least one stabilizer for metal ions, preferably in an amount of 10. -3 M to 1M.

[0113] Contact between the electroless solution and the surface is carried out, for example, under conditions that allow the formation of a metal film with a thickness of at least 5 nanometers, such as under conditions that allow the formation of a metal film with a thickness of at least 30 nanometers, preferably 30 to 100 nanometers, more preferably 30 to 200 nanometers. According to one embodiment, the thickness of the film is at least equal to the depth of the cavity, preferably 30 to 100 nanometers. When the substrate includes a horizontal cavity opening onto the vertical cavity, the thickness of the metal film is advantageously at least equal to the depth of the horizontal cavity and less than half the diameter of the vertical cavity, such that the vertical cavity is not completely filled.

[0114] The metal salts of the aforementioned metals are preferably water-soluble and selected from acetates, acetylacetonates, hexafluorophosphates, nitrates, perchlorates, sulfates, or tetrafluoroborates of the metal. In the context of this invention, nickel sulfate hexahydrate is a preferred metal salt.

[0115] Advantageously, the reducing agent described above can be selected from phosphorus derivatives and borane derivatives. The phosphorus derivative can be hypophosphite or a salt thereof, while the borane derivative can be selected from dimethylaminoborane, pyridineborane, morpholineborane, or tert-butylamineborane.

[0116] In the context of this invention, the preferred reducing agent mixture comprises borane derivatives, such as, in particular, dimethylaminoborane (DMAB), and phosphorus derivatives, such as, in particular, hypophosphoric acid.

[0117] When a stabilizer is present, its properties and amount are chosen to complex metal ions in solution. Preferably, the electroless solution contains a complex of the metal ions and ligands, also referred to as a stabilizer. Stabilizers for metal ions can be selected from ethylenediamine, citric acid, acetic acid, succinic acid, malonic acid, glycine, malic acid, or alkali metal salts of these compounds. In the context of this invention, citric acid is a preferred stabilizer, and it forms a complex with the metal ions in solution.

[0118] Electroless aqueous solutions may include reagents to adjust the pH to 6 to 11. When the solution contains amines that do not complex with metal ions, the pH of the solution is preferably chosen such that not all amine functional groups of these amines are protonated. When the solution contains polyamines, such as poly(ethyleneimine), which can be used as inhibitors suitable for horizontal cavities, the pH of the aqueous solution is preferably in the range of 8 to 10. In particular, it can be in the range of 9.0 to 9.5. The pH adjuster may be selected from aminoethanol, N-methylaminoethanol, and N,N-dimethylaminoethanol. The preferred pH adjuster is N-methylaminoethanol.

[0119] According to one embodiment of the invention, the electroless solution comprises a poly(ethyleneimine) homopolymer or copolymer that functions as an inhibitor, capable of adsorbing onto nickel or cobalt alloys, and is particularly selectively applicable to vertical cavities. "Selectively applicable" means that it is not applicable to inhibitors of horizontal cavities. The inhibitory agent for vertical cavities can also be selected from polymers and copolymers derived from chitosan, poly(allylamine), poly(vinylamine), poly(vinylpyridine), poly(aminostyrene), poly(L-lysine), and acidic (or protonated) forms of these polymers.

[0120] For example, straight-chain poly(ethyleneimine) containing -(CH2-CH2-NH)- units with a number-average molecular weight Mn of 500 g / mol to 25000 g / mol, or branched polyethyleneimine containing primary, secondary and tertiary amine units with a number-average molecular weight Mn of 500 g / mol to 70000 g / mol.

[0121] Poly(ethyleneimine) can be poly(ethyleneimine) with CAS number 25987-06-8, having a number-average molecular weight Mn of, for example, 500 to 700 g / mol, product code 408719, sold by Sigma-Aldrich, or poly(ethyleneimine) with CAS number 9002-98-6, having a number-average molecular weight Mn of, for example, 500 to 700 g / mol, product code 02371, sold by Polysciences, Inc.

[0122] The preferred reagent for inhibiting vertical cavities is branched poly(ethyleneimine) with a mass Mn of about 600 g / mol.

[0123] Aliphatic polyamines with a molecular weight less than 500 g / mol can be used in electroless solutions. They can function as inhibitors that adsorb onto nickel or cobalt alloys, and are particularly selectively adapted to horizontal cavities, or to cavities with an average opening size less than 100 nm. "Selectively adapted" means not suitable for inhibitors of cavities with an average opening size greater than 100 nm.

[0124] The reagent or mixture of reagents that inhibits horizontal cavities may be selected from the aliphatic polyamines listed above. Examples include ethylenediamine, diethylenetriamine, triethylenetetramine, dipropylenetriamine, 1,3-diaminopropane, 2-(aminomethyl)-2-methyl-1,3-propanediamine, and N,N,N,N-tetramethyl-1,3-butanediamine. The following can also be used as inhibitors of horizontal cavities: 1,4,8,11-tetraazacyclotetradecane; aliphatic alcohols, such as ethylene glycol, diethylene glycol, triethylene glycol, tetraethylene glycol, propylene glycol, dipropylene glycol, tripropylene glycol, and tetrapropylene glycol; or amino acids (alanine; arginine; asparagine; aspartate; cysteine; glutamate; glutamine; glycine; histidine; isoleucine; leucine; lysine; methionine; phenylalanine; proline; pyrrolidone; serine; threonine; tryptophan; tyrosine; valine). A specific agent that inhibits horizontal cavities is dipropyltriamine.

[0125] Typically, the substrate can be brought into contact with the electroless solution for 30 seconds to 20 minutes by immersing it in the solution at a temperature of 40°C to 90°C, preferably 70°C, depending on the required layer thickness.

[0126] According to an advantageous embodiment, the layer can be annealed in an inert or reducing atmosphere (4% hydrogen in nitrogen) at a temperature of 200°C to 400°C, preferably 250°C, for 1 minute to 30 minutes, preferably about 10 minutes.

[0127] The deposition of alloy metal layers can be performed under various conditions. For example, the substrate to be coated can be rotated. Recirculation of the electroless solution can be applied in a reactor. The substrate can be brought into contact with the electroless solution by spraying the solution under high pressure. Other means can be used in a complementary manner, such as agitating the substrate and / or solution with ultrasound or an ultrasonic gun. In any case, contact can be performed under vacuum.

[0128] In addition to selective metallization processes, the method for manufacturing 3D NAND memory according to the present invention may include other steps necessary to provide a functional memory device. Alternatively, the method of the present invention may include steps other than those described above to provide only a portion of the memory device.

[0129] A first example of a 3D NAND memory obtained according to the method of the present invention includes a semiconductor substrate defining a horizontal plane, at least one semiconductor channel disposed along a vertical axis, and a plurality of word lines comprising a nickel or cobalt alloy.

[0130] In addition to the metallization process, the method for manufacturing such a memory may include at least one other step. For example, prior to the activation and chemical deposition steps of the nickel or cobalt alloy, the method of the present invention may include the following steps:

[0131] - The step of fabricating or providing a stack of parallel layers arranged on a semiconductor substrate and comprising at least two layers of sacrificial material such as SiN or polycrystalline silicon, separated by a first insulating material such as SiO2, wherein the vertical surface opening of the stack is in a cavity with the largest dimension along the vertical axis.

[0132] - The step of selectively etching sacrificial material to form at least two horizontal cavities, the at least two horizontal cavities opening on cavities where the axis is vertical.

[0133] These two steps are followed by the selective deposition of nickel or cobalt alloy in the horizontal cavity using the aforementioned electrical-free process. This selective deposition ensures that the vertical cavity is not filled with nickel or cobalt alloy after this step.

[0134] The average opening diameter of the vertical cavity ranges from 80 nm to 150 nm, and the depth is greater than 1 micrometer. The average width of the horizontal cavity along the vertical axis is smaller than the average opening diameter of the vertical cavity.

[0135] The method of the present invention provides a particularly advantageous alternative for manufacturing 3D NAND comprising more than 90 word lines of tungsten or other physically deposited metals. The substrate used to manufacture such 3D NAND in contact with the aforementioned electroless solution (also known as an electrolyte) may comprise a number of layers greater than or equal to the following values: 32, 48, 64, 96, 128, 192, 256, preferably 96 or 128.

[0136] In this substrate, the vertical cavities have an average diameter at the opening that is particularly less than 1 micrometer, for example, ranging from 50 nanometers to 150 nanometers, and a depth greater than 1 micrometer, and the horizontal cavities have an average width of less than 100 nanometers along the vertical axis and an average depth of less than 100 nanometers along the horizontal axis.

[0137] In a second example of the method according to the invention, a nickel or cobalt alloy deposit forms at least a portion of electrical contacts between different functional conductive elements of a 3D NAND device. These contacts may be located between bit lines and semiconductor channels (referred to as "contacts" in this specification). These contacts may also be located between power lines and word lines (referred to as "peripheral contacts" in this specification).

[0138] According to a third example, the 3D NAND memory obtained by the method according to the invention includes a semiconductor substrate defining a horizontal plane, at least one semiconductor channel arranged along a vertical axis, and at least one bit line comprising a nickel or cobalt alloy deposited by the metallization process according to the invention.

[0139] The features of the above-described metallization process, including the steps of activation with noble metals and contacting the activated substrate with an electroless solution, are applicable to all three embodiments of the method according to the present invention.

[0140] In addition to the metallization process, the manufacturing method according to the invention may include at least one other step. For example, the method of the invention may include a step of depositing a dielectric material layer prior to an activation and electroless deposition step of nickel or cobalt alloy, followed by a step of etching cavities in the dielectric material by photolithography. The walls of the dielectric cavity are then activated with a noble metal and metallized with a nickel or boron alloy as described above.

[0141] Detailed description of the attached figures

[0142] Reproducing 3D NAND memory based on existing technology Figure 1 It includes:

[0143] - A silicon substrate 4, on which a dielectric coating 6b is applied and a multilayer stack located on a horizontal plane, wherein layers of silicon dioxide 1 alternate with conductive metal layers constituting word lines 23 containing tungsten.

[0144] - At least one polysilicon channel 5, which perpendicularly penetrates the stack of the multilayers, and

[0145] - At least one copper bit line 406, which is located in a plane parallel to the stack of the multi-layer and above the stack.

[0146] The polysilicon channel 5 and the copper base line 406 are electrically connected via tungsten metal contact 305b.

[0147] The polysilicon channel 5 and word line 23 are separated by the ONO charge storage region, and

[0148] The copper contact line 406 is separated from the metal contact 305b by a copper diffusion barrier material 404, which typically includes tantalum nitride or titanium nitride.

[0149] The metal contact 305b is separated from the polysilicon channel 5 by a barrier material layer 304a, typically comprising tantalum nitride or titanium nitride, and

[0150] The word line 23 is separated from the silicon dioxide 1 by a barrier material layer 21, which typically includes tantalum nitride or titanium nitride.

[0151] Figures 2A to 2D , Figures 4A to 4B and Figure 5 The first example of a 3D NAND memory manufacturing method according to the present invention is described, which produces word lines containing a nickel or cobalt alloy by metallizing the surface of a silicon dioxide structure.

[0152] These diagrams only represent a few stages of dielectric / conductor stacking. Please remember that the 3D NAND memory of this invention can include dozens, particularly 96, 128, or 196. Figures 2A to 2D Only eight layers are displayed.

[0153] According to the method of the invention, a substrate is provided, which is etched to form horizontal cavities and then metallized with a nickel or cobalt alloy. Figure 2A The substrate includes a semiconductor substrate 4 and a semiconductor channel 5 (only a portion of which is shown). In two layers stacked parallel to the substrate 4, a sacrificial material layer 1, such as silicon nitride, alternates with an insulating material layer 2, such as SiO2, and is separated by a vertical cavity 30. The sacrificial layer 1 at the bottom is separated from the semiconductor channel 5 by a dielectric ring 6a and from the substrate 4 by a dielectric coating 6b.

[0154] The so-called “ONO” charge storage region separates the semiconductor channel 5 from the layer stack. The ONO region includes charge storage material 8, which is isolated from the semiconductor channel 5 and the stack by an insulating region including a barrier dielectric layer 7 and a tunnel dielectric layer 9.

[0155] The barrier dielectric layer 7 may comprise a single layer of dielectric material or a set of dielectric material layers. In one embodiment, the barrier dielectric layer 7 comprises aluminum oxide, silicon oxide, silicon oxynitride, or combinations thereof. The thickness of the dielectric layer 7 may range from 1 nm to 20 nm. The charge storage region 8 may be a continuous layer or an collection of discrete portions. Figure 2A In this embodiment, the charge storage region 8 is shown as a continuous layer comprising a dielectric charge trapping material, such as silicon nitride. In an embodiment not shown, the sacrificial material layer 1 may be laterally recessed from the sidewalls of the insulating layer 2, and the charge storage layer 8 may be in the form of multiple spaced-apart portions. The charge storage layer 8 may be formed from a single material or comprise a stack of several charge storage materials. The thickness of the charge storage layer 8 may range from 2 nm to 20 nm. It may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In particular, the charge storage layer 8 may comprise metals such as ruthenium, metal silicides such as nickel silicide, and / or semiconductor materials. The tunnel dielectric layer 9 comprises at least one dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In one embodiment, the tunnel dielectric layer 9 may comprise a silicon dioxide / silicon oxynitride / silicon dioxide stack. The thickness of the tunnel dielectric layer 9 may range from 2 nm to 20 nm.

[0156] Will Figure 2A Etching of the substrate sacrificial material 1 to obtain Figure 2BThe structure is shown. A large amount of sacrificial material 1 is selectively etched to create cavity 3. When the sacrificial material layer 1 contains silicon nitride, the etching process can be performed by wet etching by immersing the structure in a bath containing phosphoric acid. Cavity 3 is a horizontal cavity. A horizontal cavity in the sense of this invention is... Figure 2B The cavity 3 has a smaller size in the plane and a larger size in the plane perpendicular to it. The ratio of the maximum size to the minimum size of the cavity 3 is greater than 1, and can be as high as 10 or even 100. Each cavity 3 is bounded by the upper horizontal plane of the lower insulating layer 2, the lower horizontal plane of the lower insulating layer 2, and the transverse vertical surface of the dielectric material (preferably the material that blocks the dielectric layer 7).

[0157] In the context of this invention, cavity 3 is filled with a nickel or cobalt alloy using an electrical-free process to create word lines for a monolithic three-dimensional NAND device. Figure 2C In the image, a nickel or cobalt alloy metal deposit 20 can be seen filling the horizontal cavity 3 and covering it with an insulating material 2. The metal deposit is formed by continuously applying [the material] without polarization. Figure 2B The substrate is contacted with an activation solution containing noble metal to obtain an activated silicon dioxide surface, and then the activated surface is contacted with an electrolyte as described above. The deposited metal 20 fills the entire volume of the horizontal cavity 3, and may also cover all or part of the sidewalls of the insulating layer 2. This structure is obtained by etching the excess metal 20 located outside the cavity 3 and covering the dielectric block 2, as shown below. Figure 2D As shown. The structure includes word lines 20a made of nickel or cobalt alloy.

[0158] Figure 3 An intermediate structure for manufacturing tungsten word lines 23 in 3D NAND memory, obtained using existing technology, is described. This structure is derived from... Figure 2B The substrate shown is obtained from the same substrate, which includes a cavity 3 and an insulating layer 2. The insulating layer 2 defines a free dielectric surface, which includes a surface blocking the dielectric layer 7, the bottom and walls of the cavity 3, and a flush surface of the dielectric layer 2. According to prior art processes, a tungsten diffusion barrier layer 21 is deposited on the dielectric surface via CVD or ALD processes. This barrier layer comprises a metal nitride, such as TiN or TaN. Examples of prior art barrier layers consist of a stack of three consecutive layers: titanium nitride / tungsten / titanium nitride, each of which can have a thickness ranging from 1 nm to 3 nm. After the barrier layer 21 is deposited, the hollow volume of the cavity covered by the barrier layer is filled with tungsten via CVD or ALD to form a metal deposit 23. In prior art 3D NAND memories obtained by this process, material voids 22 are observed in the metal layer, the frequency of which is inversely proportional to the size of the opening at the cavity 3.

[0159] Figure 4A , Figure 4B and Figure 5 Variations of the process of the present invention shown include metallizing aluminum oxide (Al2O3) instead of silicon dioxide. In this embodiment, in the final device, a thin aluminum oxide layer may be intermediate between the insulating layer 2 and the nickel or cobalt alloy 20. Its thickness can be in the range of 1 nm to 15 nm, for example, 2 nm to 6 nm. The process then includes the further step of: conforming to Figure 2B A thin aluminum oxide layer 10 is deposited on the surface of the substrate defined by the cavity 3 and the protruding insulating layer 2 to obtain a conformal... Figure 4A The pattern is then applied. The surface of the alumina layer 10 is then contacted with an activation solution containing a noble metal to obtain an activated alumina surface, which, without polarization, is then contacted with an electrolyte as described above to induce the deposition of a nickel or cobalt alloy. The result of this process is as follows: Figure 4B or Figure 5 The substrate shown.

[0160] According to a preferred embodiment of the invention, the device of the invention is obtained by activating the surface of the insulating layer 2 and / or the thin alumina layer 10 using an aqueous solution containing a noble metal such as palladium. Following this activation, the structure containing the cavity 3 is immersed in a solution containing nickel ions and a reducing agent for the nickel ions, preferably borane, more preferably dimethylaminoborane, to deposit a nickel-boron alloy as a metal on the bottom and walls of the cavity 3. The alloy can completely fill the cavity and form a deposit 20b. Figure 4B ), or cover the walls and bottom of the cavity without completely filling them to form deposits 20c ( Figure 5 ).

[0161] In the method of the present invention, it is advantageous to fill all the horizontal cavities 3, rather than completely filling the vertical cavity 30.

[0162] In particular, Figure 4A and Figure 4B An embodiment of the present invention for forming a nickel-boron alloy deposit 20b from a silicon substrate is shown. The silicon substrate includes i) a vertical cavity 30 with an opening of about 100 nm and a height of about 4 μm, ii) a horizontal cavity 3 with a height of 30 nm (dimension c) and a depth of 50 nm (dimension a), and protrusions of silicon dioxide corresponding to an insulating layer 2. The surface of the horizontal cavity 3 and the silicon dioxide are covered with an aluminum oxide layer 10 with a thickness of about 5 nm (dimension b). The nickel-boron alloy deposit 20b fills the horizontal cavity 3 and covers the aluminum oxide layer 10.

[0163] exist Figure 5 In the middle, the nickel-boron alloy deposit 20c is in the form of a thin layer covering the entire surface of the alumina layer 10 and does not fill the horizontal cavity 3.

[0164] In Figures 2 and 4, and Figure 5 In the illustrated embodiment of the invention, a barrier material can be inserted between the barrier dielectric 7 and the nickel or cobalt alloy 20, or between the alumina layer 10 and the nickel or cobalt alloy 20b. However, this embodiment of the invention is not preferred because the process of the invention has the advantage of avoiding this step. This is advantageous because barrier materials such as metal nitrides have lower conductivity than metals, and the addition of the barrier layer reduces the cavity space available for filling the metal. Not depositing a barrier layer allows for the creation of a conductive line with conductivity at least equal to or even higher than that of prior art lines. Furthermore, depositing a barrier material implies performance improvements in the additional steps of the 3D NAND manufacturing process.

[0165] Therefore, according to a variation of the process according to the present invention, it is possible to Figure 2C In the intermediate step between the step of forming cavity 3 and the step of depositing nickel or cobalt alloy 20 shown, according to processes known to those skilled in the art, in Figure 2B A barrier material is inserted between the surface of the barrier dielectric layer 7 and the nickel or cobalt alloy layer 20a. In another variation of the process according to the invention, a diffusion barrier material layer known to those skilled in the art can be inserted... Figure 4B The alumina layer 10 is shown between the surface and the metal layer 20b. In both variations, the barrier material can be deposited in one or more steps. The barrier layer can be a monolayer of metal nitride or a stack of multiple layers of different materials comprising at least one layer of metal nitride. The metal nitride can be TiN, TaN, or WN. For example, a continuous tantalum nitride or titanium nitride layer with a thickness of 1 nm to 6 nm is deposited.

[0166] A second example of the method for manufacturing 3D NAND memory according to the present invention includes creating peripheral contacts containing a nickel or cobalt alloy. This embodiment is provided by... Figures 6 to 8 Explanation. This variant of the invention, achieved by implementing the metallization process of the invention, involves creating vertical lines connecting word lines and power lines, these vertical lines comprising a nickel or cobalt alloy.

[0167] Figures 6 to 8 A second example of the manufacturing method of the present invention is illustrated, by which a 3D NAND memory is obtained, comprising a semiconductor substrate defining a horizontal plane, a multilayer stack deposited on the semiconductor substrate (where insulating layer 1 and word lines 24 alternate), a vertical semiconductor channel 5, and peripheral contacts 203 connecting power lines to the word lines. A nickel or cobalt alloy deposit forms at least a portion of the peripheral contacts 203, i.e., a contact located at the device periphery 200 and with the device center occupied by the vertical semiconductor channel 5. The peripheral contacts 203 connect the word lines 24 to conductive power lines (not shown).

[0168] To create these peripheral contacts 203, it is possible to manufacture or obtain, for example... Figure 6 The substrate shown includes a horizontally stacked insulating layer 1 and word lines 24, and a vertical semiconductor channel 5 surrounded by ONO components. This substrate may be prior art and include tungsten-based word lines 24.

[0169] Alternatively, the substrate can be obtained by a metallization process incorporating the present invention, and the word line 24 comprises a nickel or cobalt alloy. The stack of insulating layer 1 and word line 24 is covered on its upper part by an insulating capping layer 1a (which may be made of silicon dioxide), and on its sides by dielectric blocks 1b covering all steps of the stepped stack. Dielectric blocks 1b may be made of silicon dioxide and optionally doped with elements such as boron, phosphorus, or fluorine. The capping layer 1a and dielectric blocks 1b are coplanar and covered by a contact dielectric layer 1c. Two regions can be defined: a central region 100 comprising the vertical semiconductor channel 5, and a peripheral region 200 comprising the word line 24 and dielectric blocks 1b. Two types of contacts can be created on this substrate: a first series of contacts located on the central region 100, arranged in a block shape on the upper part of the semiconductor channel 5, and a second series of contacts located on the peripheral region 200, arranged in the form of vertical lines, intended to connect the word line 24 to... Figure 6 The power supply is not shown and is located on the upper part of the substrate.

[0170] like Figure 7 As shown, in Figure 6 A photolithographic mask 201 is deposited on the substrate shown to etch contact cavities 202 in dielectric block 1b. Etching is performed using an etch solution with high selectivity for the metal constituting word lines 24, such that etching stops once the etch solution contacts the word lines 24. This etching step results in the formation of vertical contact cavities 202, the depth of which increases from the top to the bottom of dielectric block 1b, i.e., from the top of the stair-like stack to the case. After removing the polymer deposited by photolithography and cleaning the substrate, the substrate is contacted with an activation solution to selectively graft noble metals onto the walls of the contact cavities 202, which constitute the dielectric surface of the etched dielectric block 1b. The dielectric surface activated by the noble metal is then contacted with an electroless solution containing nickel or cobalt ions to form a nickel or cobalt alloy deposit according to the process of the invention. Chemical mechanical polishing removes excess alloy deposited outside the contact cavities 202 and provides peripheral contacts 203 made of nickel or cobalt alloy, such as… Figure 8 As shown.

[0171] according to Figure 9 The prior art process shown for creating the peripheral tungsten contact 205 uses photolithography in a process similar to... Figure 6 and Figure 7The previously described substrate has a vertical contact cavity 202 etched on it, except that it includes tungsten letter lines 23. After cleaning the substrate and the photolithographically deposited polymer, the surface of the etched substrate is covered with a TiN or TaN barrier layer 204, and then the cavity is filled with tungsten. Excess metal deposited outside the vertical contact cavity 202 is then removed by chemical mechanical polishing to obtain peripheral tungsten contacts 205. The process of the present invention advantageously eliminates the step of depositing the TiN or TaN barrier layer 204, which must be deposited between the tungsten and the dielectric block 1b.

[0172] Figures 10 to 12 A third example of an embodiment of the process of the present invention is shown, which enables the production of a 3D NAND memory having contacts between semiconductor channels and bit lines, comprising a nickel or cobalt alloy. Manufacturing or obtaining Figure 10 The substrate shown includes a horizontally stacked insulating layer 1 and word lines 25. The substrate may be prior art and includes tungsten word lines 25 and tungsten-based peripheral contacts 206. When the word lines and peripheral contacts are tungsten, a titanium nitride or tantalum nitride barrier layer is inserted between the tungsten and the dielectric block 1b and dielectric layer 1a. Alternatively, the substrate may include word lines 25 containing a nickel or cobalt alloy, or vertical peripheral contacts 206 containing a nickel or cobalt alloy, or both, wherein the nickel or cobalt alloy has been formed by performing the previously described metallization process. The contact dielectric layer 1c is covered by another dielectric layer 1d.

[0173] like Figure 11 As shown, the photolithography mask 301 has been deposited on Figure 10 On the substrate shown, contact cavities 302a and 302b are etched into the dielectric layer 1d. Etching is performed using an etching solution that is highly selective for the metal of the peripheral contact 206 and the semiconductor channel 5.

[0174] After cleaning the polymer that has been deposited by photolithography, the substrate is contacted with an activation solution to selectively graft noble metals onto the walls of contact cavities 302a and 302b and the surface of layer Id, forming a dielectric surface. According to the process of the present invention, the dielectric surface activated by the noble metal is then contacted with an electroless solution containing nickel or cobalt ions to form a nickel or cobalt alloy deposit. Chemical mechanical polishing removes excess alloy deposited on the exterior of contact cavities 302a and 302b, such as… Figure 12 As shown, a block-shaped peripheral contact 303a is formed on the peripheral contact 206, and a block-shaped contact 303b is formed on the semiconductor channel 5. Contacts 303a and 303b comprise a nickel or cobalt alloy. Contact 303a, thus manufactured, will connect the peripheral contact 206 to a power line formed later, while contact 303b will connect the semiconductor channel 5 to a bit line formed in a later step.

[0175] According to the generation Figure 13 The tungsten contacts 305a and 305b shown are manufactured using a prior art process, employing photolithography in a process similar to... Figure 10 Vertical contact cavities, including tungsten word lines 23, are etched onto the previously described substrate, along with tungsten peripheral contacts 206. The tungsten of the word lines and peripheral contacts is insulated from the adjacent dielectric material by a barrier material. Cavities are formed by etching at the top of the semiconductor channel 5 and the top of the peripheral contacts 206. After cleaning the substrate and the photolithographically deposited polymer, the etched substrate surface is covered with barrier layers 304a and 304b of tantalum nitride or titanium nitride, and the cavities with barrier material on the walls are then filled with tungsten. Excess metal deposited outside the contact cavities is then removed by chemical mechanical polishing to obtain peripheral tungsten contacts 305a and 305b. The process of the present invention advantageously eliminates the step of depositing barrier layers 304a, 304b that must be inserted between the tungsten and the dielectric material of elements 1c and 1d.

[0176] Figure 14 The structure obtained according to the process of the present invention includes bit line 403 based on a nickel or cobalt alloy. Obtained from the process of the present invention... Figure 12 Starting with a substrate, or from existing technologies. Figure 13 Starting with a substrate, a dielectric layer is deposited, which is etched by photolithography to form cavities. The bottom of the cavities reaches the surface of the top contact 306, which can be made of tungsten or a nickel or cobalt alloy, depending on the starting substrate used. According to the process of the invention, a portion of the flush-mounted etched substrate is activated with a noble metal and then contacted with an electroless solution containing nickel or cobalt ions to form a bit line 403 based on a nickel or cobalt alloy.

[0177] according to Figure 15 The process of the prior art shown is based on Figure 13 The substrate is covered with a dielectric material layer 1e, which is etched by photolithography to form a cavity reaching the upper surface of the tungsten contact 305b. A thin layer of barrier material 404, followed by a thin layer of copper 405, covers the cavity walls flush with the dielectric material 1e (the bottom being the top surface of the contact 305b) and the dielectric material surface outside the cavity. The remaining cavity volume is then filled with copper 406. Advantageously, the process of the present invention can omit the steps of depositing the barrier layer 404 and the copper seed layer 405.

[0178] electrolytes

[0179] The electrolyte according to the present invention is an electrolyte for manufacturing 3D NAND memory devices, comprising:

[0180] - Nickel or cobalt ions as metal ions, preferably at a concentration of 10. -3 M to 1M;

[0181] - At least two reducing agents for the metal ion, preferably in a total amount of 10. -4 M to 1M;

[0182] - A reagent used to adjust and maintain the pH value at 6 to 11, preferably 8 to 10;

[0183] - At least one polyamine reagent, preferably in an amount of 1 to 100 mg / L.

[0184] The characteristics already given for describing the metallization process are applicable to this electrolyte.

[0185] In this embodiment, the electrolyte contains two reducing agents. The two reducing agents can be hypophosphite and dimethylaminoborane.

[0186] EP2705172A1 proposes depositing nickel-boron alloys in vertical wells with opening diameters on the order of 1 to 5 micrometers and depths up to approximately 30 micrometers. However, the inventors have demonstrated that the electrolyte of this prior art does not allow for the simultaneous filling of different geometries, such as those used in the fabrication of 3D NAND flash memory. In particular, as shown in the comparative examples below, the electrolyte according to EP2705172A1 cannot achieve conformal deposition at the bottom of structures where openings can be as small as 100 nm and depths can be as large as 4 micrometers.

[0187] Existing DMAB reducing agents are not fast enough to initiate reduction at the bottom and sides of pores and steps. Unexpectedly, the inventors discovered that adding a second reducing agent can accelerate alloy growth in inaccessible structures and achieve conformal deposition without affecting alloy quality.

[0188] The electrolyte may contain two polyamine reagents, a first polyamine reagent and a second polyamine reagent, preferably an aliphatic polyamine.

[0189] The concentration of the first polyamine reagent can be from 0.5 ppm to 100 ppm, and the concentration of the second polyamine reagent can also be from 0.5 ppm to 100 ppm. Preferably, the molecular weight of the first polyamine reagent is lower than that of the second polyamine. The molecular weight of the second polyamine reagent can be in the range of 500 g / mol to 25000 g / mol, and the molecular weight of the first polyamine reagent can be in the range of 50 g / mol to 500 g / mol, excluding values ​​of 50 g / mol and 500 g / mol.

[0190] A particular electrolyte contains:

[0191] -10 -2 At least one nickel or cobalt ion metal salt from M to 1M;

[0192] -10-4 At least one first reducing agent from M to 1M for nickel or cobalt ions;

[0193] -10 to 100 mg / L of at least one second reducing agent for nickel or cobalt ions, different from the first reducing agent;

[0194] At least one primary polyamine with a concentration of -1 to 5 mg / L;

[0195] -1 to 100 mg / L, preferably 1 to 10 mg / L, of at least one second aliphatic polyamine with a molecular weight lower than that of the first polyamine.

[0196] The first and second reducing agents can be selected from the reducing agents mentioned above.

[0197] This application also discloses an electrolyte for fabricating 3D NAND memory devices, the electrolyte comprising:

[0198] - At least one metal salt, preferably with a concentration of 10 -3 M to 1M;

[0199] - At least one reducing agent for the metal salt, preferably in an amount of 10. -4 M to 1M;

[0200] - A reagent used to adjust and maintain the pH value at 6 to 11, preferably 8 to 10;

[0201] - A first polyamine reagent and a second polyamine reagent that is different from the first polyamine reagent.

[0202] This application discloses an electrolyte for coating the surface of a dielectric material, the electrolyte comprising:

[0203] - At least one metal salt, preferably with a concentration of 10 -3 M to 1M;

[0204] - A mixture of reducing agents, preferably comprising 10 -4 Amounts from M to 1M;

[0205] - A reagent used to adjust and maintain the pH value at 6 to 11, preferably 8 to 10;

[0206] - At least two reagents capable of adsorbing onto metal oxides, particularly a first reagent having an inhibitory effect and preferably a concentration of 0.5 ppm to 100 ppm, and a second reagent having an inhibitory effect and preferably a concentration of 0.5 ppm to 100 ppm.

[0207] This application also discloses an electrolyte for manufacturing 3D NAND memory devices, comprising:

[0208] - At least one metal salt, preferably with a concentration of 10 -3 M to 1M;

[0209] - A mixture of at least two reducing agents, preferably comprising 10% of the mixture. -4 Amounts from M to 1M;

[0210] - A reagent used to adjust and maintain the pH value at 6 to 11, preferably 8 to 10;

[0211] - At least two reagents capable of adsorbing onto metal oxides, particularly a first reagent optionally having an inhibitory effect and preferably having a concentration of 0.5 ppm to 100 ppm, and a second reagent optionally having an inhibitory effect and preferably having a concentration of 0.5 ppm to 100 ppm.

[0212] The first reagent can be dipropylenetriamine and the second reagent can be polyethyleneimine. The electrolyte may contain two reducing agents, namely hypophosphite and dimethylaminoborane.

[0213] The ratio of metal ions to the second polyamine reagent is preferably greater than 1.

[0214] The specific electrolyte of the present invention contains 10 -2 Nickel ions from M to 1M, 10 -4 DMAB of M to 1M, H2PO3 of 10 to 100 mg / L, PEI of 1 to 5 mg / L, and dipropyltriamine of 1 to 100 mg / L (preferably 1 to 10 mg / L)

[0215] In a specific embodiment of the present invention, the first reducing agent is preferably dimethylaminoborane, and the second reducing agent is preferably hypophosphoric acid.

[0216] The first and second polyamines may be selected from the aforementioned polyamines. In a particular embodiment, the first polyamine is polyethyleneimine with a molecular weight of 500 g / mol to 25000 g / mol, and the second aliphatic polyamine may be dipropylenetriamine.

[0217] To facilitate filling horizontal cavities in stepped sections above main trenches or apertures within 3D NAND structures, this specific combination of two aliphatic polyamines is preferred. As demonstrated in the comparative example below, the metal deposits formed at the bottom of cavities without dipropylenetriamine are non-conformal, which can cause problems in subsequent etching steps involving over-deposited metal, particularly at the level of vertical cavities. Without being bound by any theory, it is believed that the combination of the two polyamines promotes lateral metal growth in 30 nm high stepped sections without affecting the conformability of deposits in vertical structures with openings of approximately 100 nm. When used alone, polyamines with molecular weights greater than 500 g / mol appear to preclude selective filling, likely due to their hydrodynamic volume and low diffusion rate into the stepped sections.

[0218] In one particular implementation, the electrolyte comprises:

[0219] - At least one nickel metal salt (II) with a concentration of 100 mM to 200 mM;

[0220] - At least one reducing agent for nickel ions, in an amount of 400 mM to 550 mM;

[0221] - Stabilizer, preferably citric acid, in an amount sufficient to complex nickel ions;

[0222] - Poly(ethyleneimine) with a number-average molecular weight (Mn) of approximately 600 g / mol, in amounts ranging from 1 mg / L to 5 mg / L.

[0223] - Aliphatic polyamines with a molecular weight less than 500 g / mol, in amounts ranging from 1 mg / L to 100 mg / L, and

[0224] - A reagent used to adjust the pH value to 9.0 to 9.5.

[0225] In this particular embodiment, two reducing agents may be used, including dimethylaminoborane at a concentration of 450 mM to 500 mM and hypophosphoric acid at a concentration of 10 mg / L to 100 mg / L.

[0226] The electrolyte is prepared upstream of the metallization step. If it is necessary to store certain components constituting the electrolyte, it is preferable to prepare and store at least two different solutions, which are mixed only before the electroless solution comes into contact with the substrate. A first solution containing metal ions and a second solution containing a reducing agent can be prepared and optionally stored, and these two solutions together contain all the compounds in the electrolyte composition. In this case, the second solution containing the reducing agent preferably also contains one or more polyamines, if multiple are present. The metal ions and the reducing agent are preferably packaged separately to be present in the electroless solution, just before contact with the substrate. The electrolyte of the present invention is preferably prepared temporarily by mixing the two solutions described above.

[0227] A third objective of the present invention is a 3D NAND device in which the metal used to manufacture the word lines comprises primarily nickel and an alloy of at least one element selected from boron, phosphorus, and tungsten, wherein the element may comprise 1 to 10 atoms.

[0228] In a particular embodiment of the 3D NAND device according to the present invention, all semiconductor channels are vertical (vertical channels) and the gates of the memory cells are horizontal (horizontal gates): thus each channel is surrounded by a vertical stack formed by a plurality of memory cells, and the control gate (also called a word line) is in the form of a horizontal line. In this vertical integration mode, the memory cells surround the channels and are in a so-called gate all-around (GAA) configuration.

[0229] Various types of vertically integrated 3D NAND memories are known to those skilled in the art. Without limiting the invention to these categories, reference commercial memories may be mentioned. (Bit-Cost (abbreviation) P- (Pipe-shape Bit-Cost The abbreviation for Terabit Cell Array Transistor (TCAT) and 3D V-NAND (Vertical NAND) are used, where information storage is achieved through charge storage materials, typically silicon nitride. Another type of memory is 3D V-FG (3D Vertical Floating Gate), where charge storage is provided by a floating gate.

[0230] In TCAT and V-NAND technologies, the control gate is deposited last (last gate or gate replacement), which requires sacrificial nickel silicide, which is replaced by the control gate (thin metal layer), followed by metal filling. In p-BICS and 3D V-FG technologies, the metal gate is deposited first (gate-first).

[0231] In a particular embodiment of the present invention, the 3D NAND device is a 3D V-NAND memory.

[0232] The NAND devices of the present invention, particularly in the case of 3D V-NAND, can include a material with a high dielectric constant, such as aluminum oxide instead of silicon dioxide, in the gate dielectric to optimize charge transfer.

[0233] The device can be manufactured according to various processes known to those skilled in the art, wherein, according to the process of the present invention described above, at least one tungsten deposition step is replaced by a nickel deposition step.

[0234] The present invention is illustrated by the following embodiments.

[0235] Example 1: Creation of a letter line with a nickel-boron alloy

[0236] In this embodiment, the substrate used is a silicon sample with a side length of 4cm x 4cm and a thickness of 750μm. It has a vertical cavity with an opening of about 100nm and a height of about 4μm, and a horizontal cavity with a height of 30nm and a depth of 50nm, all of which are covered with a layer of aluminum oxide (Al2O3) with a thickness of about 5nm.

[0237] a) Cleaning of the cavity surface:

[0238] The sample was cleaned according to the chemical properties of the substrate. After this cleaning step, the sample was thoroughly rinsed with deionized water, immersed in a beaker filled with deionized water, and subjected to ultrasonic treatment (40 kHz) for 2 minutes. The sample was then removed from the beaker, thoroughly rinsed with deionized water, and dried in an oven at 100°C for 10 minutes.

[0239] b) Activation of the cavity surface:

[0240] b1) Preparation of activation solution:

[0241] In a beaker, 350 μL of (3-aminopropyl)-trimethoxysilane (APTMS) and 15 mg of Pd(En)Cl2 were dissolved in 80 mL of anhydrous DMSO (maximum 50 ppm H2O).

[0242] b2) Activation treatment of substrate surface:

[0243] The sample prepared in step a1) is immersed in a beaker containing the activation solution prepared in step b1) and subjected to a rapid vacuum sufficient to purge the air trapped within the structural cavity. For this purpose, the beaker is placed in a desiccator connected to a vane pump, and the entire mixture is brought under vacuum for approximately 2 minutes. After returning to ambient pressure, the liquid mixture containing the sample is heated to 65°C and maintained for 20 minutes. The sample is removed from the solution, thoroughly rinsed with deionized water, and then immersed in a beaker filled with deionized water for 30 seconds of ultrasonic treatment (40 kHz). The sample is then removed from the beaker and thoroughly rinsed with deionized water.

[0244] c) Deposition of NiB metal layers via an electrical-free method:

[0245] c1) Preliminary preparation of the electroless solution:

[0246] In a 1-liter container, add the following in sequence: minimum amount of deionized water, 31.11 g nickel sulfate hexahydrate (0.118 mol), 44.67 g citric acid (0.232 mol), 52.26 g N-methylaminoethanol (0.700 mol), 2.5 ppm polyethyleneimine (PEI) with Mn = 600 g / mol, 55 ppm hypophosphite, and 6 ppm dipropylenetriamine. Adjust the final pH to 9.3 with N-methylaminoethanol and adjust the total volume to 1 liter with deionized water.

[0247] Just before the next step, add one volume of reducing solution to the nine volumes of the previous solution. The latter contains 28 g / L of dimethylaminoborane (DMAB; 0.475 mol) and 60.00 g of N-methylaminoethanol (0.798 mol).

[0248] c2) Formation of the NiB alloy layer on the alumina layer:

[0249] A nickel-boron alloy layer is deposited on the surface of the substrate treated in step b) by first immersing the substrate in a beaker of deionized water. The beaker is rapidly evacuated to a vacuum sufficient to remove air trapped in the structural cavities. For this purpose, the beaker is placed in a desiccator connected to a vane pump, and the entire system is kept under vacuum for approximately 2 minutes. After returning to ambient pressure, depending on the desired final thickness and the dimensions of the treated structure, the sample is rapidly immersed in a pre-prepared electroless solution and heated to 65°C for 30 seconds to 9 minutes. A shiny gray metallic coating can then be observed on the sample. The sample is removed from the solution, thoroughly rinsed with deionized water, immersed in a beaker filled with deionized water, and ultrasonically treated (40 kHz) for 30 seconds. The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream. The sample is then subjected to rapid thermal annealing (RTA) at 250°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen). This operation can be performed using a tube furnace or hot plate.

[0250] d) Characteristics of metal deposits filling cavities

[0251] After hot annealing the sample obtained in step c2), it was observed that all horizontal cavities were filled with nickel-boron alloy without material voids, while the vertical cavities were not completely filled. The pattern of the resulting alloy deposit is as follows: Figure 5 As shown.

[0252] e) Constructing EELS curves: Barrier properties of metals

[0253] The sample obtained at the end of step c2) was subjected to a new thermal annealing at 800°C for one minute in a reducing atmosphere (4% hydrogen in nitrogen) to simulate the transformations that industrial-grade 3D NAND memory may undergo in all manufacturing steps. EELS curves (e.g.) Figure 17As shown, the nickel-boron alloy did not diffuse into the SiO2. The metal deposited by the process according to the present invention eliminates the step of depositing a barrier layer of several nanometers, which must be inserted between the dielectric and the metal filling the cavity in order to manufacture prior art 3D NAND memories.

[0254] f) Evaluation of wafer bending induced by metal film

[0255] In the context of this invention, the bending caused by a 50 nm NiB deposit annealed at 400°C for 2 hours does not affect the wafer flatness. The stress applied to the NiB layer is estimated at 825 MPa, while for a W layer of equivalent thickness obtained by tungsten-CVD, the stress is greater than 2 GPa. This is in... Figure 16 This was explained in the text.

[0256] Example 2: Deposition of a thin layer of nickel-boron alloy on the cavity wall intended to form word lines

[0257] Example 1 was repeated, except that 55 ppm of hypophosphoric acid was not added in step c1). A thin layer of NiB alloy was placed over the horizontal cavity, and a schematic diagram of the resulting substrate is shown below. Figure 6 As shown.

[0258] Example 3: Creation of a contact between a bit line with a nickel-boron alloy and a polysilicon channel

[0259] The purpose of this embodiment is to activate a substrate coated with a mixed structure of silicon dioxide (SiO2) and polycrystalline silicon (pSi) from a solution containing silane and palladium complexes, so as to fill the "contact" structure located between the "bit lines" and "channels" of the NAND substrate using a NiB-type alloy.

[0260] In this embodiment, the substrate consists of a 4x4cm silicon sample with a thickness of 750μm, covered with a structured silicon oxide layer containing vias (grooves) with an opening of approximately 100nm and a height of approximately 300nm. The bottom of the cavity is recessed and in direct contact with polysilicon (pSi). These structures mimic the contacts in NAND devices.

[0261] Clean the surface of the cavity:

[0262] The sample was immersed in solution SC1 at 70°C and subjected to ultrasonic treatment (40 kHz). After this cleaning step, the sample was thoroughly rinsed with deionized water, immersed in a beaker filled with deionized water, and subjected to ultrasonic treatment (40 kHz) for 2 minutes. The sample was then removed from the beaker, thoroughly rinsed with deionized water, and dried in an oven at 100°C for 10 minutes.

[0263] Activation of cavity surface:

[0264] b1) Preparation of activation solution:

[0265] In a dry beaker, 350 μL of (3-aminopropyl)-trimethoxysilane (APTMS) and 15 mg of Pd(En)Cl2 were dissolved in 80 mL of anhydrous DMSO (maximum 50 ppm H2O).

[0266] b2) Activation treatment of substrate surface:

[0267] The sample prepared in step a) is immersed in a beaker containing the activation solution prepared in step b1) and subjected to a rapid vacuum sufficient to purge the air trapped within the structural cavity. For this purpose, the beaker is placed in a desiccator connected to a vane pump, and the entire mixture is brought under vacuum for approximately 2 minutes. After returning to ambient pressure, the liquid mixture containing the sample is heated to 65°C and maintained for 10 minutes. The sample is removed from the solution, thoroughly rinsed with deionized water, and then immersed in a beaker filled with deionized water for 30 seconds of ultrasonic treatment (40 kHz). The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream.

[0268] Deposition of NiB metal layers via an electroless method:

[0269] c1) Preliminary preparation of the electroless solution:

[0270] In a 1-liter container, add the following in sequence: a minimum amount of deionized water, 31.11 g of nickel sulfate hexahydrate (0.118 mol), 44.67 g of citric acid (0.232 mol), 52.26 g of N-methylaminoethanol (0.700 mol), 2.5 ppm of polyethyleneimine (PEI) with Mn = 600 g / mol, 55 ppm of hypophosphite, and 6 ppm of dipropylenetriamine. Adjust the final pH to 9.3 with N-methylaminoethanol and bring the total volume to 1 liter with deionized water. Just before proceeding to the next step, add one volume of reducing solution to the nine volumes of the previous solution. The latter contains 28 g / L of dimethylaminoborane (DMAB; 0.475 mol) and 60.00 g of N-methylaminoethanol (0.798 mol). 100 ml of this mixture is required for a 4 x 4 cm sample.

[0271] c2) Filling the hybrid structure with a NiB alloy layer:

[0272] A nickel-boron alloy layer is deposited on the surface of the substrate treated in step b) by first immersing the substrate in a beaker of deionized water. The beaker is rapidly evacuated to a vacuum sufficient to remove air trapped in the structural cavity. For this purpose, the beaker is placed in a desiccator connected to a vane pump, and the entire system is kept under vacuum for approximately 2 minutes. After returning to ambient pressure, the sample is rapidly immersed in a previously prepared electroless solution (c1) and heated to 65°C for 2 to 9 minutes, depending on the desired final thickness and the dimensions of the treated structure. The solution is then subjected to 40 kHz ultrasound with 3-second pulses every 15 seconds in a purge mode for 2 minutes. Ultrasound is then applied continuously for the next 7 minutes. Thus, this step lasts for 9 minutes. A shiny gray metallic coating is then observed on the sample. The sample is removed from the solution, thoroughly rinsed with deionized water, and then immersed in a beaker filled with deionized water for 30 seconds of ultrasound treatment (40 kHz). The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream. The sample was subjected to rapid thermal annealing (RTA) at 400°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen). This operation can be performed using a tube furnace or a hot plate.

[0273] Characteristics of metal deposits filling contacts

[0274] After heat annealing the specimens obtained at the end of step c2), it was observed that all vias were uniformly filled with a nickel-boron alloy. The adhesion was 16 / 16, measured according to standard ASTM 3359. Therefore, this electroless solution can be used to create letter lines (as shown in Examples 1 and 2) as well as to create contacts below the letter lines.

[0275] Example 4: Creation of bit lines with nickel-boron alloy

[0276] The purpose of this embodiment is to activate a substrate coated with a mixture of silicon dioxide (SiO2) and NiB alloy from a solution containing silane and palladium complex, so as to fill the bit line structure above the NiB contacts of the NAND substrate with NiB alloy, the contacts being manufactured, for example, according to Example 3.

[0277] The substrate used in this embodiment consists of a 4x4 cm square silicon sample with a thickness of 750 μm, covered with a structured silicon oxide layer having vias (or trenches) with an opening of approximately 300 nm and a height of approximately 500 nm. The bottom of the cavity is recessed and in direct contact with the NiB alloy or tungsten of the NAND structure "contact" portion. These structures mimic the bit lines in a NAND chip.

[0278] Pretreatment of cavity surface:

[0279] The sample was treated with reducing plasma using hydrogen. After this surface pretreatment step, the sample was stored in a nitrogen atmosphere until the next step.

[0280] Activation of cavity surface:

[0281] b1) Preparation of activation solution:

[0282] In a dry beaker, 350 μL of (3-aminopropyl)-trimethoxysilane (APTMS) and 15 mg of Pd(En)Cl2 were dissolved in 80 mL of anhydrous DMSO (maximum 50 ppm H2O).

[0283] b2) Activation treatment of substrate surface:

[0284] The sample prepared in step a) is immersed in a beaker containing the activation solution prepared in step b1) and subjected to a rapid vacuum sufficient to purge the air trapped within the structural cavity. For this purpose, the beaker is placed in a desiccator connected to a vane pump, and the entire mixture is brought under vacuum for approximately 2 minutes. After returning to ambient pressure, the liquid mixture containing the sample is heated to 65°C and maintained for 10 minutes. The sample is removed from the solution, thoroughly rinsed with deionized water, and then immersed in a beaker filled with deionized water for 30 seconds of ultrasonic treatment (40 kHz). The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream.

[0285] c) Deposition of NiB metal layers via an electrical-free method:

[0286] c1) Preliminary preparation of the electroless solution:

[0287] In a 1-liter container, add the minimum amount of deionized water, 31.11 g of nickel sulfate hexahydrate (0.118 mol), 44.67 g of citric acid (0.232 mol), 52.26 g of N-methylaminoethanol (0.700 mol), and 2.5 ppm of polyethyleneimine (PEI) with Mn = 600 g / mol. Adjust the final pH to 9.3 with N-methylaminoethanol and bring the total volume to 1 liter with deionized water. Just before the next step, add one volume of reducing solution to the nine volumes of the previous solution. The latter contains 28 g / L of dimethylaminoborane (DMAB; 0.475 mol) and 60.00 g of N-methylaminoethanol (0.798 mol).

[0288] c2) Forming a NiB alloy layer on the hybrid structure:

[0289] A nickel-boron alloy layer is deposited on the surface of the substrate treated in step b) by first immersing the substrate in a beaker of deionized water. The beaker is rapidly evacuated to a vacuum sufficient to remove air trapped in the structural cavities. For this purpose, the beaker is placed in a desiccator connected to a vane pump, and the entire system is kept under vacuum for approximately 2 minutes. After returning to ambient pressure, the sample is rapidly immersed in a previously prepared electroless plating solution (cl) and heated to 65°C for 2 to 9 minutes, depending on the desired final thickness and the size of the structure being treated. The solution is then subjected to 40 kHz ultrasound, experiencing 3-second pulses every 15 seconds in a purge mode for 2 minutes. Ultrasound is then applied continuously for the next 7 minutes. Therefore, this step lasts for 9 minutes. A shiny gray metallic coating is then observed on the sample. The sample is removed from the solution, thoroughly rinsed with deionized water, and then immersed in a beaker filled with deionized water for 30 seconds of ultrasound treatment (40 kHz). The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen stream. The sample was subjected to rapid thermal annealing (RTA) at 400°C for ten minutes in a reducing atmosphere (4% hydrogen in nitrogen). This operation can be performed using a tube furnace or a hot plate.

[0290] Characteristics of metal deposits filling cavities

[0291] After hot annealing of the specimens obtained at the end of step c2), it was observed that all the vias were uniformly filled with the same thickness of nickel-boron alloy. The adhesion was measured to be 16 / 16 according to standard ASTM 3359.

[0292] Example 5: Creation of bit lines with nickel-boron alloy and copper

[0293] The substrate is the same as in Example 4.

[0294] Pretreatment of cavity surface:

[0295] The substrate was treated in the same manner as in Part a) of Example 4.

[0296] Activation of cavity surface:

[0297] b1) Preparation of activation solution:

[0298] The solution is the same as that prepared in Example 4b).

[0299] b2) Activation treatment of substrate surface:

[0300] The surface treatment is the same as in Example 4 (b2).

[0301] Deposition of NiB metal layers via an electricity-free method:

[0302] c1) Preliminary preparation of the electroless solution:

[0303] The solution is the same as that prepared in c1) of Example 4.

[0304] c2) Forming a NiB alloy layer on the hybrid structure:

[0305] The surface treatment was performed in the same manner as in c2) of Example 4. However, according to those skilled in the art, by reducing the processing time or adjusting the concentration of the additives, the treatment was incomplete, resulting in incomplete filling of the NiB alloy bit lines. The remaining cavities were filled with copper in the following steps.

[0306] The remaining cavity was filled with copper using an electrodeposition process.

[0307] d1) Electrodeposition solution:

[0308] In this solution, Cu 2+ The concentration was equal to 15 g / L obtained from CuSO4(H2O)5. The stoichiometric ratio of ethylenediamine to copper was 2:1. The pH of the solution was adjusted to pH 7.0 by adding tetraethylammonium hydroxide. Then 50 ppm of thiodiglycolic acid was introduced.

[0309] d2) Equipment:

[0310] In this embodiment, an electrodeposition apparatus consisting of two parts is used: a cell for containing the electrodeposition solution, equipped with a fluid recirculation system to control the system's hydrodynamics, and a rotating electrode equipped with a sample holder suitable for the size of the sample used (4cm x 4cm). The electrodeposition cell has two electrodes:

[0311] Copper anode

[0312] A silicon sample coated with the layer described in c) above constitutes a cathode.

[0313] The reference electrode is connected to the anode.

[0314] The connector allows for electrical contact between electrodes, which are connected via wires to a potentiostat that provides up to 20V or 2A.

[0315] d3) Experimental design:

[0316] Preparatory steps:

[0317] If the substrate obtained in step c) is fresh, no special treatment is required. The sample prepared in step c) may optionally be first immersed in a deionized water beaker. The beaker is rapidly evacuated to a vacuum sufficient to remove air trapped in the structural cavities. For this purpose, the beaker is placed in a desiccator connected to a vane pump, and the entire assembly is kept under vacuum for approximately 2 minutes. After restoring to ambient pressure, the sample is quickly mounted in a deposition tank immersed in the solution prepared in step d1), and the assembly then undergoes an electrical process with a cold inlet.

[0318] Electrical process:

[0319] The process is carried out as follows: At a current range of 5mA (or 2mA / cm²)... 2 ) to 50mA (or 20mA / cm) 2 For example, 20mA (or 8mA / cm). 2 The cathode is biased in a pulsed current mode, with a cathode bias pulse duration of 5 to 1000 milliseconds and a zero bias between two cathode pulses of 5 to 1000 milliseconds. This step is performed for 10 minutes at 60 rpm. Contact between the electrolyte and the substrate is established before energizing, with a 30-second delay. The sample is removed from the solution, thoroughly rinsed with deionized water, and then immersed in a beaker filled with deionized water for 30 seconds of ultrasonic treatment (40 kHz). The sample is then removed from the beaker, thoroughly rinsed with deionized water, and dried under a nitrogen flow.

[0320] d4) Annealing:

[0321] The sample is subjected to rapid thermal annealing (RTA) at 250°C for ten minutes in a reducing atmosphere (nitrogen with 4% hydrogen). This operation can be performed using a tube furnace or a hot plate.

[0322] Results obtained:

[0323] Scanning electron microscopy analysis (Mag=100k, EHT=2kV) revealed copper filler without interface or porosity defects. Adhesion strength was measured to be 16 / 16 according to standard ASTM 3359.

Claims

1. A method of manufacturing a 3D NAND memory comprising at least one metallization process of selective metallization of an inorganic oxide surface in a solvent phase, the metallization process being carried out by forming a metallic alloy deposit of nickel or cobalt with an element selected from the group consisting of boron, phosphorus and tungsten, and the metallization process comprising: - a step of activation of the inorganic oxide surface with a noble metal, the activation step being followed by - a step of contacting the inorganic oxide surface with an electroless solution to form a metallic alloy deposit, in the absence of polarization, the electroless solution comprising: metal ions, the metal ions being nickel ions or cobalt ions; at least two reducing agents for the metal ions, comprising boron, phosphorus, tungsten or mixtures thereof; a stabilizer in an amount sufficient to complex the metal ions; a polyethyleneimine having a number average molecular weight Mn of 500 to 700 g / mol; and an aliphatic polyamine having a Mn of less than 500 g / mol.

2. The method of claim 1, wherein, The step of contacting the inorganic oxide surface with an electroless solution is carried out by subjecting the inorganic oxide surface to ultrasound.

3. The method according to claim 1 or 2, characterized in that, The element selected from the group consisting of boron, phosphorus and tungsten is present in the metallic alloy in an atomic percentage of 1 to 10.

4. The method according to claim 1 or 2, characterized in that, The inorganic oxide is SiO2 or AI2O3.

5. The method according to claim 1 or 2, characterized in that, The noble metal is palladium.

6. The method according to claim 1, wherein the metal ions comprise nickel ions.

7. The method according to claim 1, wherein the stabilizer comprises citric acid.

8. The method according to claim 1, wherein the aliphatic polyamine comprises dipropylene triamine.

9. A 3D NAND memory device comprising word lines, bit lines, poly-silicon channels, contacts between the poly-silicon channels and the bit lines, and peripheral contacts between the word lines and source lines, characterized in that, The 3D NAND memory device further comprises at least one metallic alloy deposit comprising nickel or cobalt as a metal and an element selected from the group consisting of boron, phosphorus and tungsten, and being made by the method of any one of claims 1 to 8.

10. The 3D NAND memory device of claim 9, wherein, The word line comprises the at least one metallic alloy deposit.

11. The 3D NAND memory device of claim 9, wherein, The contact between the polysilicon channel and the bit line comprises the at least one metallic alloy deposit.

12. The 3D NAND memory device of claim 9, wherein, The bit line comprises the at least one metallic alloy deposit.

13. The 3D NAND memory device of claim 9, wherein, The peripheral contact between the word line and the source line comprises the at least one metallic alloy deposit.

14. An electrolyte for manufacturing a 3D NAND memory device, comprising: - metal ions, wherein the metal ions comprise at least one metal salt of nickel or cobalt and have a concentration of 10 -3 M to 1 M; at least two reducing agents for the metal ions in a total amount of 400 mM to 550 mM; a stabilizer in an amount sufficient to complex the metal ions; an agent for adjusting and maintaining the pH value at 6 to 11; a polyethyleneimine having a number average molecular weight Mn of 500 to 700 g / mol; and an aliphatic polyamine having a Mn of less than 500 g / mol.

15. The electrolyte of claim 14, wherein, It comprises two reducing agents, which are hypophosphorous acid and dimethylaminoborane.

16. The electrolyte according to claim 14, wherein the stabilizer comprises citric acid.

17. The electrolyte according to claim 14, wherein the aliphatic polyamine comprises dipropylene triamine.

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