voltage regulator

Abstract

Various embodiments of the present disclosure generally relate to a voltage regulator. A voltage regulator is provided that provides a first voltage at a first output node and includes a first input transistor of a non-inverting stage and a second bias transistor of a non-inverting stage. The first transistor and the second transistor are coupled in series between the first node and a second node to which a second reference voltage is applied. The second transistor is configured to be controlled by a third voltage that is dependent on the first voltage.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices and, in particular, to voltage regulators. Background Art

[0002] A voltage regulator is an electronic component configured to maintain a substantially constant voltage at its output. For example, a voltage regulator can be a linear regulator, that is, a regulator that relies on active components operating in its linear region or on passive components (such as a Zener diode) operating in its reverse region.

[0003] One type of linear regulator is a so-called low dropout (LDO) regulator. This type of regulator produces an output voltage very close to the regulator supply voltage. Summary of the Invention

[0004] One embodiment provides a voltage regulator that provides a first voltage on a first output node and includes a first input transistor of a non-inverting stage and a second bias transistor of a non-inverting stage, the first transistor and the second transistor being coupled in series between the first node and a second node to which a second reference voltage is applied, the second transistor being configured to be controlled by a third voltage that depends on the first voltage.

[0005] Another embodiment provides a method of controlling a voltage regulator that provides a first voltage on a first output node and includes a first input transistor of a non-inverting stage and a second bias transistor of the non-inverting stage, the first transistor and the second transistor being coupled in series between the first node and a second node to which a second reference voltage is applied, the second transistor being controlled by a third voltage that depends on the first voltage.

[0006] According to one embodiment, the third voltage is configured to have a variation type of increase or decrease opposite to the variation type of the first voltage.

[0007] According to an embodiment, the first transistor is configured to be controlled by a fourth voltage that depends on a fifth set point voltage.

[0008] According to one embodiment, the regulator includes a third transistor coupled between a third node to which the sixth power supply voltage is applied and the first node.

[0009] According to one embodiment, the fourth junction node of the first transistor and the second transistor is coupled to the gate of the third transistor through a terminal of the fourth transistor.

[0010] According to one embodiment, the regulator comprises a circuit for generating a third voltage, receiving the first voltage as input.

[0011] According to one embodiment, the generating circuit includes a fifth transistor, a sixth transistor, and a seventh transistor coupled in series between the third node and the second node, the gate of the fifth transistor being coupled to the third node through the conduction terminal of the eighth transistor, and being coupled to the fourth connection node of the sixth and seventh transistors through the conduction terminal of the ninth transistor.

[0012] According to one embodiment, the generating circuit includes a tenth transistor configured to receive the first voltage at its control terminal and coupled between the fifth junction node of the fifth transistor and the sixth transistor and a sixth node via its conduction terminal, the generating circuit being configured to generate a third voltage at the sixth node.

[0013] According to one embodiment, the sixth node is coupled to the second node through an eleventh transistor and a twelfth transistor coupled in series, wherein the sixth node is coupled to a control terminal of the twelfth transistor.

[0014] According to one embodiment, the eleventh transistor and the ninth transistor are controlled by the same voltage.

[0015] According to one embodiment, the seventh transistor, the eighth transistor and the ninth transistor are configured to be controlled by a substantially constant voltage, and the sixth transistor is configured to be controlled by a fifth voltage.

[0016] According to one embodiment, a regulator includes a first resistor and a thirteenth and fourteenth transistors coupled in series between a seventh node to which a setpoint current is applied and a second node, the seventh node being coupled to a gate of the thirteenth transistor, and an eighth connection node between the thirteenth and fourteenth transistors being coupled to a gate of the fourteenth transistor. The regulator also includes a fifteenth and sixteenth transistors, a second resistor, and a seventeenth and eighteenth transistors coupled in series between the third and second nodes, a ninth connection node between the sixteenth node and the second resistor being coupled to a gate of the fifteenth transistor, a tenth connection node between the second resistor and the seventeenth transistor being coupled to a gate of the sixteenth transistor, a gate of the fifteenth transistor being coupled to a gate of the eighth transistor, a gate of the seventeenth transistor being coupled to a gate of the thirteenth transistor, a gate of the ninth transistor being coupled to a gate of the eleventh transistor, and a gate of the eighteenth transistor being coupled to a gate of the fourteenth transistor and a gate of the seventh transistor.

[0017] According to one embodiment, the first node is coupled to the fourth node through a first capacitor, and the fourth node and the fifth node are coupled through a second capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above features and advantages and other features and advantages will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0019] Figure 1 One embodiment of a low dropout regulator is schematically shown;

[0020] Figure 2 Shown in more detail Figure 1 a portion of an embodiment of ; and

[0021] Figure 3 A more detailed embodiment of a low dropout regulator is shown. DETAILED DESCRIPTION

[0022] In the various drawings, similar features are represented by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0023] For clarity, only the steps and elements that are useful for understanding the embodiments described herein are illustrated and described in detail.

[0024] Unless otherwise specified, when two elements are referred to as being connected together, this means they are directly connected without any intermediate elements (except conductors), and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0025] In the following disclosure, unless otherwise specified, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "above", "below", "upper" and "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.), reference is made to the orientation shown in the figures.

[0026] Unless otherwise specified, "about," "approximately," "substantially," and "approximately" mean within 10%, preferably within 5%.

[0027] In the following description, all transistors described are metal oxide semiconductor field effect transistors (MOSFETs).

[0028] Figure 1 An embodiment of a low dropout regulator or regulating circuit 10 is schematically shown.

[0029] Circuit 10 includes an output node 12. Circuit 10 provides an output voltage VOUT at node 12. Circuit 10 also includes an input node 14 to which a supply voltage VDD is applied. Circuit 10 also includes an input node 16 to which a reference voltage GND, such as ground, is applied. Output node 12 is coupled to a load (not shown), such as a circuit powered by voltage VOUT.

[0030] Circuit 10 includes transistor 18. Transistor 18 is preferably a P-channel transistor. Transistor 18 is coupled between node 12 and node 14. In other words, a conduction terminal, source, or drain (preferably the source) is coupled (preferably connected) to node 14. The other conduction terminal (e.g., drain) of transistor 18 is coupled (preferably connected) to node 12.

[0031] Circuit 10 includes transistor 20 and transistor 22. Transistor 20 and transistor 22 form a non-inverting stage or a non-inverting amplifier. Transistor 20 forms the input transistor of the non-inverting stage, and transistor 22 forms the bias transistor of the non-inverting stage. Transistor 22 biases the current flowing through transistor 20. Transistor 20 is preferably a P-channel transistor. Transistor 22 is preferably an N-channel transistor. Transistor 20 and transistor 22 are coupled in series between node 12 and node 16.

[0032] Transistor 20 is coupled between node 12 and node 24. In other words, a conduction terminal (e.g., source) of transistor 20 is coupled (preferably connected) to node 12. Another conduction terminal (e.g., drain) is coupled (preferably connected) to node 24. Transistor 20 is controlled by voltage VB. In other words, a gate or control terminal of transistor 20 is coupled (preferably connected) to a node to which voltage VB is applied. Voltage VB is, for example, a voltage that depends on the difference between output voltage VOUT and reference voltage Vref0.

[0033] Transistor 22 is coupled between node 24 and node 16. In other words, a conduction terminal (e.g., drain) of transistor 22 is coupled (preferably connected) to node 24. Another conduction terminal (e.g., source) is coupled (preferably connected) to node 16. Thus, node 24 is the junction node of transistor 20 and transistor 22. In other words, transistors 20 and 22 are coupled together via node 24 through their conduction terminals.

[0034] Circuit 10 also includes transistor 26. Transistor 26 is, for example, an N-channel transistor. Transistor 26 is coupled between node 24 and the gate of transistor 18. In other words, a conduction terminal (e.g., drain) of transistor 26 is coupled (preferably connected) to the gate of transistor 18, and another conduction terminal (e.g., source) of transistor 26 is coupled (preferably connected) to node 24. Transistor 26 is controlled by voltage VCN. In other words, the gate of transistor 26 is coupled (preferably connected) to a node to which voltage VCN is applied. Voltage VCN is preferably substantially constant.

[0035] Circuit 10 also includes circuit 28 for generating a control voltage for transistor 22. Circuit 28 is configured to provide a control voltage VA to transistor 22. In other words, circuit 28 includes an output to which voltage VA is applied, which is coupled (preferably connected) to the gate of transistor 22. Circuit 28 includes an input coupled (preferably connected) to node 12. Circuit 28 thus preferably receives output voltage VOUT.

[0036] Circuit 28 is configured so that voltage VA depends on voltage VOUT. More specifically, circuit 28 is configured so that voltage VA varies inversely to variations in output voltage VOUT. Thus, when voltage VOUT increases, voltage VA decreases, and when voltage VOUT decreases, voltage VA increases. For example, when the output voltage is constant and substantially equal to voltage Vref0, voltage VA is substantially constant and substantially equal to value VA0. When voltage VOUT is greater than voltage Vref0, voltage VA is less than voltage VA0. Similarly, when voltage VOUT is less than voltage Vref0, voltage VA is greater than voltage VA0.

[0037] During operation of circuit 10, the value of the current drawn by a load (not shown) at output node 12 may suddenly change. In other words, current consumption may occur at node 12. This may result in a change in the value of voltage VOUT. This change in value is then compensated for by circuit 10.

[0038] For example, if the load draws a larger current, voltage VOUT decreases. This change is transmitted to node 24 via transistor 20, causing the voltage at node 24 to decrease. Circuit 28, receiving voltage VOUT, then provides voltage VA with the same change. In this example, voltage VA increases. The increase in the control voltage of transistor 22 ensures that a larger current flows through transistor 22, and the voltage at node 24 decreases more rapidly.

[0039] The voltage change is then transmitted through transistor 26 to the gate of transistor 18. The reduction in the gate voltage of transistor 18 ensures that the current between the conduction terminals of transistor 18 becomes larger, which causes voltage VOUT to increase until voltage VOUT returns to a value substantially equal to the set point voltage, such as voltage Vref0.

[0040] Similarly, if the load draws a lower current, voltage VOUT increases. This change is transmitted to node 24 via transistor 20, causing the voltage at node 24 to increase. Circuit 28, receiving voltage VOUT, then provides voltage VA with the same change. In this example, voltage VA decreases. The reduction in the control voltage of transistor 22 ensures that the current flowing through transistor 22 is lower and the voltage at node 24 increases more rapidly.

[0041] The voltage change is then transmitted through transistor 26 to the gate of transistor 18. The increase in the gate voltage of transistor 18 ensures that the current between the conduction terminals of transistor 18 becomes lower, which causes voltage VOUT to decrease until voltage VOUT returns to a value substantially equal to the set point voltage, such as voltage Vref0.

[0042] Preferably, the change in voltage VA is inversely proportional to the change in voltage VOUT. In other words, if voltage VOUT decreases by 10%, the increase in voltage VA is substantially equal to 10%.

[0043] It is possible to choose to maintain the voltage VA at a constant value. However, the transmission of the changes at the node 24, and therefore the compensation of the changes in the voltage VOUT, will be slower. The voltage changes on the output node will be greater, and therefore the risk of damage to components (e.g., the load) will be greater.

[0044] Figure 2 Shown in more detail Figure 1 More precisely, Figure 2 Shown Figure 1 One embodiment of the circuit 28.

[0045] Circuit 28 includes an output node 30 to which voltage VA is applied. Circuit 28 includes an input node 32 to which a voltage representing voltage VOUT is applied, preferably voltage VOUT. The circuit also receives a supply voltage and reference voltages VDD and GND at its inputs. Circuit 28 is thus coupled to nodes 14 and 16.

[0046] Circuit 28 includes transistor 34 and transistor 36. Transistor 34 and transistor 36 are, for example, N-channel transistors. Transistor 34 and transistor 36 are coupled in series between node 30 and node 16.

[0047] Transistor 34 is coupled between node 30 and node 38. In other words, a conduction terminal (e.g., drain) of transistor 34 is coupled (preferably connected) to node 30, and another conduction terminal (e.g., source) of transistor 34 is coupled (preferably connected) to node 38. Transistor 34 is controlled by voltage VCN. In other words, a gate of transistor 34 is coupled (preferably connected) to node 40 to which control voltage VCN is applied.

[0048] Transistor 36 is coupled between node 38 and node 16. In other words, a conduction terminal (e.g., drain) of transistor 36 is coupled (preferably connected) to node 38, and another conduction terminal (e.g., source) of transistor 36 is coupled (preferably connected) to node 16. Transistor 36 is controlled by voltage VA. In other words, a gate of transistor 36 is coupled (preferably connected) to node 30.

[0049] Preferably, the substrates of transistors 34 and 36 are biased by voltage GND. In other words, the substrates of transistors 34 and 36 are coupled (preferably connected) to node 16.

[0050] Circuit 28 includes transistor 42 and transistor 44. Transistor 42 and transistor 44 are, for example, P-channel transistors. Transistor 42 and transistor 44 are coupled in series between node 14 and node 30.

[0051] Transistor 44 is coupled between node 30 and node 46. In other words, a conduction terminal (e.g., drain) of transistor 44 is coupled (preferably connected) to node 30, and another conduction terminal (e.g., source) of transistor 42 is coupled (preferably connected) to node 46. Transistor 42 is controlled by voltage VOUT. In other words, a gate of transistor 42 is coupled (preferably connected) to node 32.

[0052] Transistor 42 is coupled between node 46 and node 14. In other words, a conduction terminal (e.g., drain) of transistor 42 is coupled (preferably connected) to node 46, and another conduction terminal (e.g., source) of transistor 42 is coupled (preferably connected) to node 14. Transistor 42 is controlled by voltage V42. In other words, a gate of transistor 42 is coupled (preferably connected) to node 48 to which voltage V42 is applied.

[0053] Preferably, the substrate of transistor 42 is biased by voltage VDD. In other words, the substrate of transistor 42 is coupled (preferably connected) to node 14.

[0054] Circuit 28 includes transistor 50 and transistor 52. Transistor 50 and transistor 52 are, for example, a P-channel transistor and an N-channel transistor, respectively. Transistor 50 and transistor 52 are coupled in series between node 46 and node 16. In other words, transistor 42, transistor 50, and transistor 52 are coupled in series between node 14 and node 16.

[0055] Transistor 50 is coupled between node 46 and node 54. In other words, a conduction terminal (e.g., source) of transistor 50 is coupled (preferably connected) to node 46, and another conduction terminal (e.g., drain) of transistor 50 is coupled (preferably connected) to node 54. Transistor 50 is controlled by a setpoint voltage Vref. In other words, the gate of transistor 42 is coupled (preferably connected) to a node to which voltage Vref is applied. Preferably, voltage Vref is substantially equal to voltage Vref0 and substantially equal to voltage VOUT.

[0056] Transistor 52 is coupled between node 54 and node 16. In other words, a conduction terminal (e.g., drain) of transistor 52 is coupled (preferably connected) to node 54, and another conduction terminal (e.g., source) of transistor 52 is coupled (preferably connected) to node 16. Transistor 52 is controlled by voltage VMN. In other words, a gate of transistor 52 is coupled (preferably connected) to a node to which voltage VMN is applied.

[0057] Preferably, the substrate of transistor 52 is biased by voltage GND. In other words, the substrate of transistor 52 is coupled (preferably connected) to node 16.

[0058] Circuit 28, for example, includes a capacitor 56 coupled between node 46 and node 54. In other words, one terminal of capacitor 56 is coupled (preferably connected) to node 46, and the other terminal of capacitor 58 is coupled (preferably connected) to node 54. Similarly, circuit 28, for example, includes a capacitor 58 coupled between node 54 and node 32. In other words, one terminal of capacitor 58 is coupled (preferably connected) to node 32, and the other terminal of capacitor 58 is coupled (preferably connected) to node 54.

[0059] Circuit 28 includes transistor 60 and transistor 62. Transistor 60 and transistor 62 are, for example, a P-channel transistor and an N-channel transistor, respectively. Transistor 60 and transistor 62 are coupled in series between node 14 and node 54.

[0060] Transistor 60 is coupled between node 14 and node 48. In other words, a conduction terminal (e.g., source) of transistor 60 is coupled (preferably connected) to node 14, and another conduction terminal (e.g., drain) of transistor 60 is coupled (preferably connected) to node 48. Transistor 60 is controlled by voltage VMP. In other words, a gate of transistor 60 is coupled (preferably connected) to a node to which control voltage VMP is applied.

[0061] Transistor 62 is coupled between node 48 and node 54. In other words, a conduction terminal (e.g., drain) of transistor 62 is coupled (preferably connected) to node 48, and another conduction terminal (e.g., source) of transistor 62 is coupled (preferably connected) to node 54. Transistor 62 is controlled by voltage VCN. In other words, a gate of transistor 62 is coupled (preferably connected) to node 40.

[0062] Preferably, the substrates of transistors 60 and 62 are biased by voltage VDD and voltage GND, respectively. In other words, the substrates of transistors 60 and 62 are coupled (preferably connected) to node 14 and node 16, respectively.

[0063] Voltages VMN and VMP are preferably substantially constant voltages.

[0064] Figure 3 A more detailed embodiment of a low dropout regulator 70 or low dropout regulation circuit 70 is shown.

[0065] For example, the circuit 70 powers a load 71. Thus, the output node 12 of the circuit 70 is coupled (preferably connected) to the load 71.

[0066] The regulator 70 includes Figure 1 and Figure 2 Thus, the circuit 70 includes components such as Figure 2 The circuit 28, and Figure 1 The transistors 18, 20, 22 and 26 are described. These components will not be described again.

[0067] Regulator 70 includes a voltage generating circuit 72. Circuit 72 is configured to generate voltages VMP, VMN, VCP, and VCN. Voltages VMP, VMN, VCP, and VCN are preferably substantially constant voltages.

[0068] Circuit 72 includes a resistor 74 and transistors 76 and 78 coupled in series. Resistor 74 and transistors 76 and 78 are coupled in series between node 80 and node 16. Transistors 76 and 78 are preferably N-channel transistors. Transistors 76 and 78 are coupled, for example, in a cascode configuration.

[0069] Resistor 74 is coupled between node 80 and node 82. In other words, one terminal of resistor 80 is coupled (preferably connected) to node 80, and the other terminal of resistor 80 is coupled (preferably connected) to node 82.

[0070] Transistor 76 is coupled via its conduction terminal between node 82 and node 84. In other words, a conduction terminal (e.g., drain) of transistor 76 is coupled (preferably connected) to node 82, and another conduction terminal (e.g., source) of transistor 76 is coupled (preferably connected) to node 84.

[0071] Transistor 78 is coupled between node 82 and node 84. In other words, a conduction terminal (e.g., drain) of transistor 78 is coupled (preferably connected) to node 84, and another conduction terminal (e.g., source) of transistor 78 is coupled (preferably connected) to node 16.

[0072] Node 80 receives current IB. Current IB is, for example, substantially constant. Node 80 is, for example, coupled (preferably connected) to the gate of transistor 76. Node 82 is, for example, coupled (preferably connected) to the gate of transistor 78.

[0073] Preferably, the substrates of transistors 76 and 78 are biased by voltage GND. In other words, the substrates of transistors 76 and 78 are coupled (preferably connected) to node 16.

[0074] Circuit 72 also includes transistors 86 and 88, resistor 90, and transistors 92 and 94 coupled in series. Transistors 86 and 88, resistor 90, and transistors 92 and 94 are coupled in series between node 14 and node 16. Transistors 86 and 88 are, for example, P-channel transistors. Transistors 92 and 94 are, for example, N-channel transistors. Transistors 92 and 94 are coupled, for example, in a cascode configuration.

[0075] Transistor 86 is coupled via its conduction terminal between node 14 and node 96. In other words, a conduction terminal (e.g., source) of transistor 86 is coupled (preferably connected) to node 14, and another conduction terminal (e.g., drain) of transistor 86 is coupled (preferably connected) to node 96.

[0076] Transistor 88 is coupled via its conduction terminal between node 96 and node 98. In other words, a conduction terminal (e.g., source) of transistor 88 is coupled (preferably connected) to node 96, and another conduction terminal (e.g., drain) of transistor 88 is coupled (preferably connected) to node 98.

[0077] Resistor 90 is coupled between node 98 and node 100. In other words, one terminal of resistor 90 is coupled (preferably connected) to node 98, and the other terminal of resistor 90 is coupled (preferably connected) to node 100.

[0078] Preferably, the substrates of transistors 86 and 88 are biased by voltage VDD. In other words, the substrates of transistors 86 and 88 are coupled (preferably connected) to node 14.

[0079] Node 98 is, for example, coupled to (preferably connected to) the gate of transistor 86. Node 100 is, for example, coupled to (preferably connected to) the gate of transistor 88.

[0080] The voltage at the gate of transistor 86 is voltage VMP. Thus, voltage VMP is generated, for example, at node 98. The gate of transistor 86 is coupled (preferably connected) to the gate of transistor 60 of circuit 28. Transistor 86 and transistor 60 therefore have a common gate. Transistor 86 and transistor 60 are coupled, for example, as a current mirror.

[0081] The voltage on the gate of transistor 88 is voltage VCP. Therefore, voltage VCP is generated at node 100, for example.

[0082] Transistor 92 is coupled via its conduction terminal between node 100 and node 102. In other words, a conduction terminal (e.g., drain) of transistor 92 is coupled (preferably connected) to node 100, and another conduction terminal (e.g., source) of transistor 92 is coupled (preferably connected) to node 102.

[0083] Transistor 94 is coupled via its conduction terminal between node 102 and node 16. In other words, a conduction terminal (e.g., drain) of transistor 94 is coupled (preferably connected) to node 102, and another conduction terminal (e.g., source) of transistor 94 is coupled (preferably connected) to node 16.

[0084] Preferably, the substrates of transistors 92 and 94 are biased by voltage GND. In other words, the substrates of transistors 92 and 94 are coupled (preferably connected) to node 16.

[0085] Voltage VCN is generated at the gate of transistor 92. The gate of transistor 92 is coupled (preferably connected) to the gate of transistor 76. Therefore, the gate of transistor 92 is coupled (preferably connected) to node 80. Transistor 76 and transistor 92 are coupled, for example, as a current mirror. The gate of transistor 92 is coupled (preferably connected) to the gate of transistor 62, the gate of transistor 34, and the gate of transistor 26, for example.

[0086] Voltage VMN is generated at the gate of transistor 94. The gate of transistor 94 is coupled (preferably connected) to the gate of transistor 78. Therefore, the gate of transistor 94 is coupled (preferably connected) to node 82. Transistor 78 and transistor 94 are coupled, for example, as a current mirror. The gate of transistor 94 is coupled (preferably connected) to the gate of transistor 52, for example.

[0087] Circuit 70 includes transistor 104 and transistor 106. Transistor 104 and transistor 106 are P-channel and N-channel transistors, respectively. Transistor 104 and transistor 106 are coupled in series between node 108 and node 16. Node 108 is a node to which a setpoint voltage Vref is applied.

[0088] Transistor 104 is coupled between node 108 and node 110. In other words, a conduction terminal (e.g., source) of transistor 104 is coupled (preferably connected) to node 108, and another conduction terminal (e.g., drain) of transistor 104 is coupled (preferably connected) to node 110. Transistor 104 is, for example, a diode. Therefore, the gate of transistor 104 is coupled (preferably connected) to the gate of transistor 104.

[0089] Voltage VB is generated on the gate of transistor 104. The gate of transistor 104 is coupled (preferably connected) to the gate of transistor 20. Therefore, the gate of transistor 20 is coupled (preferably connected) to node 110.

[0090] As a variant, transistor 104 may be replaced by a circuit comprising an operational amplifier.

[0091] Transistor 106 is coupled between node 110 and node 16. In other words, a conduction terminal (eg, drain) of transistor 106 is coupled (preferably connected) to node 110, and another conduction terminal (eg, source) of transistor 106 is coupled (preferably connected) to node 16.

[0092] Transistor 106 is controlled by voltage VMN. In other words, the gate of transistor 106 is coupled (preferably connected) to the gates of transistor 52, transistor 78, and transistor 94. Thus, transistor 106 is coupled to transistor 78 as a current mirror.

[0093] Circuit 70 includes transistor 112, transistor 114, and transistor 116 coupled in series between node 32 and node 16. Transistor 112 is, for example, a P-channel transistor. Transistor 114 and transistor 116 are, for example, N-channel transistors.

[0094] Transistor 112 is coupled between node 32 and node 118. In other words, a conduction terminal (eg, source) of transistor 112 is coupled (preferably connected) to node 32, and another conduction terminal (eg, drain) of transistor 112 is coupled (preferably connected) to node 118.

[0095] Transistor 112 is controlled by voltage VB. The gate of transistor 112 is coupled (preferably connected) to the gates of transistor 20 and transistor 104.

[0096] Transistor 114 is coupled between node 118 and node 120. In other words, a conduction terminal (eg, drain) of transistor 114 is coupled (preferably connected) to node 118, and another conduction terminal (eg, source) of transistor 114 is coupled (preferably connected) to node 120.

[0097] Transistor 114 is controlled by voltage VCN. In other words, the gate of transistor 114 is coupled (preferably connected) to the gates of transistors 26, 34, 62, 76, and 92.

[0098] Transistor 116 is coupled between node 120 and node 16. In other words, a conduction terminal (e.g., drain) of transistor 116 is coupled (preferably connected) to node 120, and another conduction terminal (e.g., source) of transistor 116 is coupled (preferably connected) to node 16. The gate of transistor 116 is coupled (preferably connected) to node 118, for example.

[0099] Preferably, the substrates of transistors 114 and 116 are biased by voltage GND. In other words, the substrates of transistors 114 and 116 are coupled (preferably connected) to node 16.

[0100] Circuit 70 further includes transistor 122, transistor 124, transistor 126, and transistor 128. Transistor 122, transistor 122, transistor 126, and transistor 128 are coupled in series between node 14 and node 16. Transistor 122 and transistor 124 are, for example, P-channel transistors. Transistor 126 and transistor 128 are, for example, N-channel transistors.

[0101] Transistor 122 is coupled between node 14 and node 130. In other words, a conduction terminal (eg, source) of transistor 122 is coupled (preferably connected) to node 14, and another conduction terminal (eg, drain) of transistor 122 is coupled (preferably connected) to node 130.

[0102] Transistor 124 is coupled between node 130 and node 132. In other words, a conduction terminal (eg, source) of transistor 124 is coupled (preferably connected) to node 130, and another conduction terminal (eg, drain) of transistor 124 is coupled (preferably connected) to node 132.

[0103] Transistor 124 is controlled by voltage VCP. In other words, the gate of transistor 124 is coupled (preferably connected) to the gate of transistor 88.

[0104] Furthermore, the gate of transistor 122 is preferably coupled (preferably connected) to node 132 .

[0105] Transistor 126 is coupled between node 132 and node 134. In other words, a conduction terminal (eg, drain) of transistor 126 is coupled (preferably connected) to node 132, and another conduction terminal (eg, source) of transistor 126 is coupled (preferably connected) to node 134.

[0106] Transistor 126 is controlled by voltage VCN. The gate of transistor 126 is coupled (preferably connected) to the gates of transistors 26, 34, 62, 76, and 114, for example.

[0107] Transistor 128 is coupled between node 134 and node 16. In other words, a conduction terminal (eg, drain) of transistor 128 is coupled (preferably connected) to node 134, and another conduction terminal (eg, source) of transistor 128 is coupled (preferably connected) to node 16.

[0108] The gate of transistor 128 is coupled (preferably connected) to transistor 116. Transistor 116 and transistor 128 thus have a common gate. The gate of transistor 128 is coupled (preferably connected) to node 118, for example.

[0109] Preferably, the substrates of transistors 122 and 124 are biased by voltage VDD. In other words, the substrates of transistors 122 and 124 are coupled (preferably connected) to node 14. Preferably, the substrates of transistors 126 and 128 are biased by voltage GND. In other words, the substrates of transistors 126 and 128 are coupled (preferably connected) to node 16.

[0110] Transistors 114 , 116 , 126 , and 128 are thus coupled in a cascode current mirror arrangement.

[0111] Circuit 70 includes transistor 136 and transistor 138. Transistor 136 and transistor 138 are coupled in series between node 14 and node 140.

[0112] Transistor 136 is coupled between node 14 and node 142. In other words, a conduction terminal (eg, source) of transistor 136 is coupled (preferably connected) to node 14, and another conduction terminal (eg, drain) of transistor 136 is coupled (preferably connected) to node 142.

[0113] The gate of transistor 136 is coupled (preferably connected) to the gate of transistor 122. In other words, transistor 122 and transistor 136 have a common gate. Therefore, the gate of transistor 136 is coupled (preferably connected) to node 132.

[0114] Transistor 138 is thus coupled between node 142 and node 140. In other words, one conduction terminal (eg, source) of transistor 138 is coupled (preferably connected) to node 142, and the other conduction terminal (eg, drain) of transistor 138 is coupled (preferably connected) to node 140.

[0115] Transistor 138 is controlled by voltage VCP. Therefore, the gate of transistor 138 is coupled (preferably connected) to the node to which voltage VCP is applied. The gate of transistor 138 is coupled (preferably connected) to the gates of transistor 88 and transistor 124, for example.

[0116] Transistor 122 , transistor 124 , transistor 136 , and transistor 138 are thus coupled in a cascode current mirror component.

[0117] Node 140 is further coupled (preferably connected) to the gate of transistor 18. Node 140 is further coupled (preferably connected) to the conduction terminal (e.g., drain) of transistor 126. Thus, the conduction terminal (e.g., drain) of transistor 126 is coupled (preferably connected) to the gate of transistor 18 via node 140.

[0118] According to one embodiment, circuit 70 further includes capacitor 144 , capacitor 146 , and capacitor 148 .

[0119] Capacitor 144 is coupled between node 12 and node 140. In other words, one terminal of capacitor 144 is coupled (preferably connected) to node 12, and the other terminal of capacitor 144 is coupled (preferably connected) to node 140.

[0120] Capacitor 146 is coupled between node 12 and node 24. In other words, one terminal of capacitor 146 is coupled (preferably connected) to node 12, and the other terminal of capacitor 146 is coupled (preferably connected) to node 24.

[0121] Capacitor 148 is coupled between node 12 and node 118. In other words, one terminal of capacitor 148 is coupled (preferably connected) to node 12, and the other terminal of capacitor 148 is coupled (preferably connected) to node 118.

[0122] Capacitors 144, 146, and 148 are, for example, so-called Miller capacitance elements, and thus can increase the response speed to current consumption.

[0123] An advantage of the above described embodiment is that the circuit 10 or circuit 70 has a faster response to the current drawn from the load.

[0124] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these different embodiments and variations may be combined, and those skilled in the art will be able to conceive of other variations.

[0125] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0126] A voltage regulator (10, 70) provides a first voltage (VOUT) at a first output node (12) and can be summarized as including a first input transistor (20) of a non-inverting stage and a second bias transistor (22) of a non-inverting stage, the first transistor and the second transistor (20, 22) being coupled in series between the first node (12) and a second node (16) to which a second reference voltage (GND) is applied, the second transistor (22) being configured to be controlled by a third voltage (VA) that depends on the first voltage (VOUT).

[0127] A method of controlling a voltage regulator (10, 70) provides a first voltage (VOUT) at a first output node (12) and can be summarized as comprising a first input transistor (20) of a non-inverting stage and a second bias transistor (22) of a non-inverting stage, the first transistor and the second transistor (20, 22) being coupled in series between the first node (12) and a second node (16) to which a second reference voltage (GND) is applied, the second transistor (22) being configured to be controlled by a third voltage (VA) that is dependent on the first voltage (VOUT).

[0128] The third voltage (VA) may be configured to have a variation type of increase or decrease opposite to the variation type of the first voltage (VOUT).

[0129] The first transistor (20) may be configured to be controlled by a fourth voltage (VB) that depends on a fifth set point voltage (Vref).

[0130] The regulator may include a third transistor (18) coupled between a third node to which a sixth power supply voltage (VDD) is applied and the first node (12).

[0131] A fourth junction node (24) of the first and second transistors (20, 22) may be coupled to the gate of the third transistor (18) via a terminal of a fourth transistor (26).

[0132] The regulator (10, 70) may include a circuit (28) for generating a third voltage (VA) receiving the first voltage (VOUT) as input.

[0133] The generating circuit (28) may include a fifth transistor (42), a sixth transistor (50), and a seventh transistor (52) sequentially coupled in series between a third node (14) and a second node (16), wherein a gate of the fifth transistor (42) is coupled to the third node (14) via a conduction terminal of an eighth transistor (60), and is coupled to a fourth connection node (54) of the sixth transistor (50) and the seventh transistor (52) via a conduction terminal of a ninth transistor (62).

[0134] The generating circuit may include a tenth transistor (44) configured to receive the first voltage (VOUT) at its control terminal and coupled between a fifth connection node (46) of the fifth transistor (42) and the sixth transistor (50) and the sixth node (30) via its conduction terminal, the generating circuit being configured to generate a third voltage (VA) at the sixth node (30).

[0135] The sixth node (30) can be coupled to the second node (16) via an eleventh transistor (34) and a twelfth transistor (36) coupled in series, and the sixth node (30) is coupled to a control terminal of the twelfth transistor (36).

[0136] The eleventh transistor (34) can be controlled by the same voltage as the ninth transistor (62).

[0137] The seventh transistor (52), the eighth transistor (60), and the ninth transistor (62) may be configured to be controlled by a substantially constant voltage, and the sixth transistor (50) is configured to be controlled by a fifth voltage (Vref).

[0138] The regulator may include a first resistor (74) and a thirteenth transistor (76) and a fourteenth transistor (78) coupled in series between a seventh node (80) to which a set point current (IB) is applied and the second node (16), the seventh node (80) being coupled to the gate of the thirteenth transistor (76), and an eighth connection node (84) of the thirteenth transistor (76) and the fourteenth transistor (78) being coupled to the gate of the fourteenth transistor (78), and the regulator may also include a fifteenth transistor (86) and a sixteenth transistor (88), a second resistor (90), and a seventeenth transistor (92) and a fourth transistor (93) coupled in series between the third node (14) and the second node (16). The eighteenth transistor (94) is coupled to the gate of the fifteenth transistor (86), the ninth connection node (98) of the sixteenth node (88) and the second resistor (90), the tenth connection node (100) of the second resistor (90) and the seventeenth transistor (92) is coupled to the gate of the sixteenth transistor (88), the gate of the fifteenth transistor (86) is coupled to the gate of the eighth transistor (60), the gate of the seventeenth transistor (92) is coupled to the gate of the thirteenth transistor (76), the gate of the ninth transistor (62) and the gate of the eleventh transistor (34), and the gate of the eighteenth transistor (94) is coupled to the gate of the fourteenth transistor (78) and the gate of the seventh transistor (52).

[0139] The first node may be coupled to the fourth node (54) through a first capacitor (56), and the fourth node (54) and the fifth node (46) may be coupled through a second capacitor (58).

[0140] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally speaking, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A voltage regulator comprising: a first node configured to be powered by a first voltage from the voltage regulator; A second node is configured to provide a second voltage, wherein the second voltage is a reference voltage; Non-inverting stage, including: A first transistor having: a first conductive terminal coupled to the first node, and a second conductive terminal; and A second transistor having: a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conductive terminal coupled to the second node, and a control terminal to be controlled by a third voltage dependent on the first voltage; A third transistor having: a first conduction terminal coupled to a third node, wherein the third node provides a supply voltage; a second conductive terminal coupled to the first node; and Control terminals; The second conduction terminal of the first transistor and the first conduction terminal of the second transistor are coupled to the control terminal of the third transistor via the first conduction terminal and the second conduction terminal of an interposed fourth transistor. 2 . The voltage regulator according to claim 1 , wherein the third voltage is negatively correlated with the first voltage. 3 . The voltage regulator according to claim 2 , wherein the third voltage increases in response to a decrease in the first voltage, and the third voltage decreases in response to an increase in the first voltage. 4 . The voltage regulator of claim 1 , wherein the first transistor has a control terminal configured to be controlled by a fourth voltage, wherein the fourth voltage depends on a fifth voltage as a set point voltage.

5. The voltage regulator according to claim 1 , comprising: The circuit is configured as: generating the third voltage; as well as Receive the first voltage.

6. The voltage regulator of claim 5 , wherein the circuit comprises: a fifth transistor having a first conduction terminal, a second conduction terminal, and a control terminal, wherein the first conduction terminal of the fifth transistor is coupled to a third node; a sixth transistor having a first conduction terminal coupled to the second conduction terminal of the fifth transistor and having a second conduction terminal; a seventh transistor having a first conduction terminal coupled to the second conduction terminal of the sixth transistor and having a second conduction terminal coupled to the second node; an eighth transistor having a first conduction terminal coupled to the control terminal of the fifth transistor and a second conduction terminal coupled to the third node; as well as a ninth transistor having a first conduction terminal and a second conduction terminal, the first conduction terminal of the ninth transistor being coupled to the control terminal of the fifth transistor, and the second conduction terminal of the ninth transistor being coupled to the second conduction terminal of the sixth transistor and the first conduction terminal of the seventh transistor.

7. The voltage regulator of claim 6 , wherein the circuit comprises: a tenth transistor having a control terminal, a first conduction terminal, and a second conduction terminal, the control terminal of the tenth transistor being configured to receive the first voltage, the first conduction terminal of the tenth transistor being coupled to the second conduction terminal of the fifth transistor and the first conduction terminal of the sixth transistor, and the second conduction terminal of the tenth transistor being coupled to a sixth node, wherein the sixth node provides the third voltage.

8. The voltage regulator of claim 7, wherein the circuit comprises: an eleventh transistor having a first conduction terminal and a second conduction terminal, the first conduction terminal of the eleventh transistor being coupled to the sixth node; as well as a twelfth transistor having a first conduction terminal, a second conduction terminal, and a control terminal, the first conduction terminal of the twelfth transistor being coupled to the second conduction terminal of the eleventh transistor, the second conduction terminal of the twelfth transistor being coupled to the second node, and the control terminal of the twelfth transistor being coupled to the sixth node.

9. The voltage regulator of claim 8, wherein the eleventh transistor has a control terminal coupled to a control terminal of the ninth transistor, and wherein the eleventh transistor and the ninth transistor are controlled by a same voltage. 10 . The voltage regulator of claim 6 , wherein the seventh transistor, the eighth transistor, and the ninth transistor are configured to be controlled by a substantially constant voltage, and the sixth transistor is configured to be controlled by a fifth voltage.

11. The voltage regulator according to claim 8, comprising: a first resistor; a thirteenth transistor and a fourteenth transistor coupled in series between a seventh node and the second node, wherein the seventh node provides a set point current and the seventh node is coupled to a control terminal of the thirteenth transistor, and an eighth connection node of the thirteenth and fourteenth transistors is coupled to the control terminal of the fourteenth transistor; a fifteenth transistor and a sixteenth transistor; a second resistor; as well as A seventeenth transistor and an eighteenth transistor are coupled in series between the third node and the second node, a ninth link node between the sixteenth transistor and the second resistor is coupled to the control terminal of the fifteenth transistor, a tenth link node between the second resistor and the seventeenth transistor is coupled to the control terminal of the sixteenth transistor, the control terminal of the fifteenth transistor is coupled to the control terminal of the eighth transistor, the control terminal of the seventeenth transistor is coupled to the control terminals of the thirteenth transistor, the ninth transistor, and the eleventh transistor, and the control terminal of the eighteenth transistor is coupled to the control terminal of the fourteenth transistor and the control terminal of the seventh transistor. 12 . The voltage regulator of claim 6 , wherein the first node is coupled to a fourth node through a first capacitor, and the fourth node and a fifth node are coupled through a second capacitor.

13. A method of controlling a voltage regulator, comprising: providing a first voltage to a first node, wherein a first transistor of a non-inverting stage and a second transistor of the non-inverting stage are coupled in series between the first node and a second node; providing a reference voltage to the second node; controlling the second transistor by a third voltage that depends on the first voltage; wherein a third transistor has a first conduction terminal, a second conduction terminal, and a control terminal, the first conduction terminal of the third transistor being coupled to a third node, wherein the third node provides a supply voltage, and wherein the second conduction terminal of the third transistor is coupled to the first node; and The second conduction terminal of the first transistor and the first conduction terminal of the second transistor are coupled to the control terminal of the third transistor via the first conduction terminal and the second conduction terminal of an interposed fourth transistor. The method of claim 13 , wherein the third voltage is negatively correlated with the first voltage. 15 . The method of claim 14 , wherein the third voltage increases in response to a decrease in the first voltage, and the third voltage decreases in response to an increase in the first voltage.

16. The method according to claim 13, comprising: The first transistor is controlled by a fourth voltage, wherein the fourth voltage depends on a fifth voltage as a set point voltage.

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