Display panel and display device

Abstract

The present invention provides a display panel and a display device, which relate to the field of display technology and are used to enable signal lines intercepted by a light-transmitting area to transmit signals normally, and ensure the display consistency of the area around the light-transmitting area and other areas. The display panel includes a display area and a light-transmitting area; the display area includes a plurality of signal lines arranged along a first direction, and the signal lines extend along a second direction; a plurality of connecting lines, and the connecting lines are used to connect the signal lines located on both sides of the light-transmitting area along the second direction; the connecting lines include a plurality of first-class connecting lines, and at least part of the first-class connecting lines is located in the display area; the first-class connecting lines include edge connecting lines, and the edge connecting lines are the first-class connecting lines with the largest distance from the light-transmitting area among the first-class connecting lines; common lines include first-class common lines, and at least part of the first-class common lines is located in the display area; part of the first-class common lines is located on the side of the edge connecting lines close to the light-transmitting area.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. [Background technology]

[0002] As users' demands for diversified display panel designs increase, a solution has emerged to open through holes inside the display area of ​​the display panel to set up components such as cameras. Since the through holes opened inside the display area will cut off some signal lines, when opening through holes in the display area, how to connect the signal lines cut off by the through holes; and how to ensure the display consistency of the area around the through holes and other areas have become the research focus of researchers. [Summary of the invention]

[0003] In view of this, embodiments of the present invention provide a display panel and a display device to enable signal lines intercepted by a light-transmitting area to transmit signals normally and to ensure display consistency between areas around the light-transmitting area and other areas.

[0004] In one aspect, an embodiment of the present invention provides a display panel, including:

[0005] It comprises a display area and a light-transmitting area; the display area at least partially surrounds the light-transmitting area;

[0006] The display area includes:

[0007] A plurality of signal lines arranged along a first direction, wherein the signal lines extend along a second direction; the first direction and the second direction intersect;

[0008] a plurality of connection lines, the connection lines being used to connect signal lines located on both sides of the light-transmitting area along the second direction; the connection lines comprising a plurality of first-type connection lines, at least part of the first-type connection lines being located in the display area; the first-type connection lines comprising edge connection lines, the edge connection lines being sub-connection lines of the first-type connection lines that are the longest in distance from the light-transmitting area;

[0009] The common lines include a first type of common lines, at least a portion of the first type of common lines is located in the display area; and a portion of the first type of common lines is located on a side of the edge connection line close to the light-transmitting area.

[0010] On the other hand, an embodiment of the present invention provides a display device, including the above-mentioned display panel.

[0011] The display panel and the display device provided by the embodiments of the present invention can provide a light-transmitting area in the display panel, and subsequently provide a photosensitive element corresponding to the light-transmitting area, so that the display panel has functions such as shooting or biometrics, thereby enriching the user experience.

[0012] Moreover, the embodiment of the present invention arranges a first type of connecting line that is at least partially located in the display area, and the first type of connecting line is used to connect the signal lines located on both sides of the light-transmitting area along the extension direction of the signal lines. On the basis of ensuring the light transmittance of the light-transmitting area and ensuring the normal driving of the pixel driving circuits connected to the signal lines located on both sides of the light-transmitting area along the extension direction of the signal lines, the number of connecting lines arranged around the light-transmitting area can be reduced, thereby reducing the width of the non-display area between the light-transmitting area and the display area, which is beneficial to improving the visual effect of the display panel.

[0013] In addition, the embodiment of the present invention sets a common line for transmitting a common voltage, and makes the common line include a first type of common line that is at least partially located in the display area, and makes a part of the first type of common line be located on the side of the edge connection line close to the light-transmitting area. This can increase the conduction path of the common voltage between the edge connection line and the light-transmitting area, which is beneficial to reducing the voltage drop of the common voltage in the area far away from the binding area, for example, in the area between the edge connection line and the light-transmitting area, thereby improving the display consistency at the position close to the driver chip and the position far away from the driver chip in the display area.

[0014] In addition, the external ambient light can be reflected by the first type of common lines and the first type of connecting lines after being emitted to the display panel. Compared with the case where the first type of common lines are not set, based on the setting method provided in the embodiment of the present invention, the reflection consistency of the ambient light at the positions where the first type of connecting lines are set and the positions where the first type of connecting lines are not set in the display area can also be improved.

Brief Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 2 for Figure 1 A simplified schematic diagram of the signal lines and the first type of connection lines in the middle area Q1;

[0018] Figure 3 for Figure 1 A simplified schematic diagram of the common lines and connecting lines in the middle area Q1;

[0019] Figure 4 An equivalent circuit diagram of a sub-pixel provided by an embodiment of the present invention;

[0020] Figure 5 for Figure 3 A simplified enlarged schematic diagram of the middle region Q2;

[0021] Figure 6 For Figure 5 A corresponding wiring schematic diagram;

[0022] Figure 7 for Figure 6 A schematic top view of a semiconductor layer in FIG.

[0023] Figure 8 for Figure 6 A schematic top view of the first metal layer in FIG.

[0024] Fig. 9 for Figure 6 A schematic top view of the second metal layer in FIG.

[0025] Fig.10 for Figure 6 A schematic top view of the third metal layer in FIG.

[0026] Fig.11 for Figure 6 A schematic top view of the fourth metal layer in FIG.

[0027] Fig.12 for Figure 6 A schematic top view of the fifth metal layer in FIG.

[0028] Fig.13 A schematic cross-sectional view of a display area of ​​a display panel provided by an embodiment of the present invention;

[0029] Fig.14 for Figure 3 A simplified enlarged schematic diagram of the middle area Q3;

[0030] Fig.15 A partially enlarged schematic diagram of another display panel provided by an embodiment of the present invention;

[0031] Fig.16 for Fig.15 A simplified enlarged schematic diagram of the middle region Q4;

[0032] Fig.17 for Fig.15 A simplified enlarged schematic diagram of the middle area Q5;

[0033] Fig.18 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention;

[0034] Fig.19 for Fig.18A simplified enlarged schematic diagram of the second non-display area;

[0035] Fig. 20 For Fig.19 A corresponding wiring schematic diagram;

[0036] Fig.21 for Fig.19 A schematic top view of the fourth metal layer in FIG.

[0037] Fig. 22 A schematic cross-sectional view of a second non-display area of ​​a display panel provided by an embodiment of the present invention;

[0038] Fig.23 for Fig.19 A schematic top view of the fifth metal layer in FIG.

[0039] Fig.24 A cross-sectional schematic diagram of another second non-display area provided by an embodiment of the present invention;

[0040] Fig.25 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention;

[0041] Fig.26 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention;

[0042] Fig. 27 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention;

[0043] Fig.28 for Fig. 27 A schematic cross-sectional view along BB';

[0044] Fig.29 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention;

[0045] Fig.30 for Fig.29 A simplified enlarged schematic diagram of the middle area Q6;

[0046] Fig.31 for Figure 1 An enlarged schematic diagram of the middle region Q7;

[0047] Fig.32 A schematic diagram of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0048] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0051] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0052] It should be understood that although the terms first, second, third, etc. may be used to describe common lines in embodiments of the present invention, these common lines should not be limited to these terms. These terms are only used to distinguish common lines from each other. For example, without departing from the scope of embodiments of the present invention, the first common line may also be referred to as the second common line, and similarly, the second common line may also be referred to as the first common line.

[0053] An embodiment of the present invention provides a display panel, such as Figure 1 As shown, Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention includes a display area AA, a light-transmitting area TA and a first non-display area NA1, wherein the display area AA at least partially surrounds the light-transmitting area TA. The first non-display area NA1 at least partially surrounds the display area AA.

[0054] The display area AA includes a plurality of sub-pixels, Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, Figure 2 for Figure 1 A simplified schematic diagram of the signal lines and the first type of connection lines in the middle area Q1, Figure 3 for Figure 1 A simplified schematic diagram of the common lines and connecting lines in the middle area Q1, Figure 4 An equivalent circuit diagram of a sub-pixel provided by an embodiment of the present invention, Figure 5 for Figure 3 A simplified enlarged schematic diagram of the middle region Q2, Figure 6 For Figure 5A corresponding wiring schematic diagram, the sub-pixel includes an electrically connected pixel driving circuit 101 and a light-emitting element 102. The pixel driving circuit 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst. Among them, the third transistor T3 is a driving transistor.

[0055] like Figure 4 As shown, the display area AA also includes a first scan line S1, a second scan line S2, a light emitting control signal line E, a data line Data, a first power supply voltage line PVDD, a second power supply voltage line PVEE ( Figure 6 (not shown), a first reference voltage signal line Vref1 and a second reference voltage signal line Vref2.

[0056] The first transistor T1 is used to electrically connect the first power supply voltage line PVDD and the second node N2 under the control of the light emitting control signal line E; the second transistor T2 is used to electrically connect the data line Data and the second node N2 under the control of the second scan line S2; the third transistor T3 is used to electrically connect the second node N2 and the third node N3 under the control of the first node N1; the fourth transistor T4 is used to electrically connect the third node N3 and the first node N1 under the control of the second scan line S2; the fifth transistor T5 is used to electrically connect the first reference voltage signal line Vref1 and the first node N1 under the control of the first scan line S1; the sixth transistor T6 is used to electrically connect the third node N3 and the fourth node N4 under the control of the light emitting control signal line E; the seventh transistor T7 is used to electrically connect the second reference voltage signal line Vref2 and the fourth node N4 under the control of the second scan line S2. The first electrode of the light emitting element 102 is electrically connected to the fourth node N4, and the second electrode is electrically connected to the second power supply voltage line PVEE. The first plate of the storage capacitor Cst is electrically connected to the first power supply voltage line PVDD, and the second plate of the storage capacitor Cst is electrically connected to the first node N1.

[0057] The operation process of the pixel driving circuit 101 includes a reset phase, a charging phase and a light emitting phase. In the reset phase, the first scan line S1 controls the fifth transistor T5 to turn on, and the first reference voltage provided by the first reference voltage signal line Vref1 resets the first node N1 through the fifth transistor T5. In the charging phase, the second scan line S2 controls the second transistor T2, the fourth transistor T4 and the seventh transistor T7 to turn on, and the data voltage V provided by the data line Data is data The second node N2 is written through the second transistor T2. At this stage, the third transistor T3 is turned on. The potential of the first node N1 keeps changing until the potential V N1 Change to V N1 =V data -|Vth |, V data is the data voltage provided by the data line Data, V th is the threshold voltage of the third transistor T3. The second reference voltage provided by the second reference voltage signal line Vref2 resets the fourth node N4 through the seventh transistor T7. In the light-emitting stage, the first transistor T1, the sixth transistor T6 and the third transistor T3 are turned on, and under the action of the first power supply voltage provided by the first power supply voltage line PVDD and the second power supply voltage provided by the second power supply voltage line PVEE, the current path between the first power supply voltage line PVDD and the second power supply voltage line PVEE is turned on, and the light-emitting element 102 electrically connected to the pixel driving circuit 101 is lit.

[0058] Exemplarily, the first reference voltage and the second reference voltage may be different or the same. When the first reference voltage and the second reference voltage are the same, the first reference voltage signal line Vref1 and the second reference voltage signal line Vref2 may be collectively referred to as reference voltage signal lines. The first reference voltage and the second reference voltage respectively transmitted by the two may be collectively referred to as reference voltages. That is, the fifth transistor T5 and the seventh transistor T7 may both be connected to the reference voltage signal line to reset the first node N1 and the fourth node N4 using the same reference voltage. Unless otherwise specified, the embodiments of the present invention are described below by taking the first reference voltage and the second reference voltage as different examples.

[0059] Optional, such as Figure 6 As shown, the first scan line S1, the second scan line S2, and the light-emitting control signal line E all extend along the first direction h1 and are arranged along the second direction h2. The first direction h1 intersects with the second direction h2; Figure 6 The first direction h1 and the second direction h2 are perpendicular as an example. A plurality of pixel driving circuits 101 are arranged in an array in the first direction h1 and the second direction h2. A first scanning line S1, a second scanning line S2, and a light emitting control signal line E are all electrically connected to the plurality of pixel driving circuits 101 arranged along the first direction h1. The data line Data extends along the second direction h2, and the plurality of data lines Data are arranged along the first direction h1. A data line Data is electrically connected to the plurality of pixel driving circuits 101 arranged along the second direction h2. The specific wiring of the display area AA will be described later, and will not be repeated here.

[0060] For example, in the embodiment of the present invention, the first power supply voltage, the second power supply voltage, the first reference voltage, and the second reference voltage required for the operation of different pixel driving circuits 101 may be the same. That is, the first power supply voltage transmitted by the first power supply voltage line PVDD, the second power supply voltage transmitted by the second power supply voltage line PVEE, the first reference voltage transmitted by the first reference voltage signal line Vref1, and the second reference voltage transmitted by the second reference voltage signal line Vref2 may be common voltages shared by multiple pixel driving circuits 101.

[0061] In the embodiment of the present invention, the light-transmitting area TA includes a through hole or a blind hole. The above-mentioned sub-pixels and / or signal lines are not arranged in the light-transmitting area TA to improve the light transmittance of the light-transmitting area TA. For example, the display panel can be subsequently configured in conjunction with a photosensitive element such as a camera and an iris sensor, so that the orthographic projection of the photosensitive element on the plane where the display panel is located is at least partially located in the above-mentioned light-transmitting area TA, so that the external ambient light can be incident on the photosensitive element through the light-transmitting area TA.

[0062] Optional, such as Figure 2 As shown, the display panel includes a signal line 1. Part of the signal line 1 can be cut off by the light-transmitting area TA. That is, the extension line of part of the signal line 1 can pass through the light-transmitting area TA. The display panel also includes a plurality of connecting lines, which are used to connect the signal lines 1 located on both sides of the light-transmitting area TA along the extension direction of the signal line 1.

[0063] Exemplarily, at least one of the first scan line S1 , the second scan line S2 , the light emitting control signal line E, and the data line Data includes a signal line 1 that can be cut off by the light-transmitting area TA. Figure 2 A schematic diagram showing that the data line Data includes the signal line 1. When the data line Data includes the signal line 1, that is, when the signal line 1 extends along the second direction h2, the connecting line 2 is used to connect the signal lines 1 located on both sides of the light-transmitting area TA along the second direction h2. The two signal lines 1 connected by the connecting line 2 are electrically connected to a plurality of pixel driving circuits 101 arranged along the second direction h2.

[0064] In the embodiment of the present invention, the connection lines include a plurality of first-type connection lines 21, and at least a portion of the first-type connection lines 21 is located in the display area AA. Figure 2 As shown, the first type of connection line 21 includes at least two first sub-connection lines 2101 and a second sub-connection line 2102 located between two adjacent first sub-connection lines 2101. The first sub-connection lines 2101 and the second sub-connection lines 2102 are cross-connected and electrically connected. Optionally, the first sub-connection lines 2101 extend along the first direction h1. The second sub-connection lines 2102 extend along the second direction h2.

[0065] At least part of the first type of connection line 21 is located in the display area AA, that is, at least part of at least one of the first sub-connection line 2101 and the second sub-connection line 2102 is located in the display area AA. In this way, while ensuring that the signal line 1 intercepted by the light-transmitting area TA can receive the signal normally, the number of connection lines arranged between the light-transmitting area TA and the display area AA can be reduced, which is conducive to reducing the width of the non-display area around the light-transmitting area TA.

[0066] The first type connection lines 21 include edge connection lines 210_S, which are the first type connection lines 21 with the largest distance from the light-transmitting area TA. In other words, the edge connection lines 210_S are the first type connection lines 21 with the smallest distance from the first non-display area NA1.

[0067] Exemplarily, the display panel AA may include a plurality of edge connection lines 210_S located at different positions, and different edge connection lines 210_S are respectively disposed near different positions of the first non-display area NA1.

[0068] When the first sub-connection line 2101 and the second sub-connection line 2102 are both disposed in the display area AA, taking the outer contour of the display area AA as a quadrilateral as an example, Figure 1 As shown, the first non-display area NA1 includes a first sub-non-display area NA11, a second sub-non-display area NA12, a third sub-non-display area NA13 and a fourth sub-non-display area NA14. The first sub-non-display area NA11 and the second sub-non-display area NA12 are located on both sides of the display area AA in the second direction h2. The third sub-non-display area NA13 and the fourth sub-non-display area NA14 are located on both sides of the display area AA in the first direction h1. Figure 1 and Figure 2 As shown, one of the first sub-connection lines 2101 of the first type of connection lines 21 is located between the light-transmitting area TA and the first sub-non-display area NA11, and another first sub-connection line 2101 is located between the light-transmitting area TA and the second sub-non-display area NA12. The second sub-connection line 2102 of the first type of connection lines 21 is located between the light-transmitting area TA and the third sub-non-display area NA13, or between the light-transmitting area TA and the fourth sub-non-display area NA14. Figure 2 As an example, the second sub-connection lines 2102 of some first-type connection lines 21 are located between the light-transmitting area TA and the third sub-non-display area NA13, and the second sub-connection lines 2102 of another first-type connection lines 21 are located between the light-transmitting area TA and the fourth sub-non-display area NA14.

[0069] Accordingly, combined Figure 1 and Figure 2As shown, the edge connection line 210_S includes a first edge connection line 210_S1, a second edge connection line 210_S2, a third edge connection line 210_S3 and a fourth edge connection line 210_S4. The first edge connection line 210_S1 is located between the light-transmitting area TA and the first sub-non-display area NA11, the second edge connection line 210_S2 is located between the light-transmitting area TA and the second sub-non-display area NA12, the third edge connection line 210_S3 is located between the light-transmitting area TA and the third sub-non-display area NA13, and the fourth edge connection line 210_S4 is located between the light-transmitting area TA and the fourth sub-non-display area NA14.

[0070] Exemplarily, the first edge connection line 210_S1 may be electrically connected to the third edge connection line 210_S3 or the fourth edge connection line 210_S4, and / or the second edge connection line 210_S2 may be electrically connected to the third edge connection line 210_S3 or the fourth edge connection line 210_S4. Alternatively, the first edge connection line 210_S1 may be insulated from the third edge connection line 210_S3 or the fourth edge connection line 210_S4, and / or the second edge connection line 210_S2 may be insulated from the third edge connection line 210_S3 or the fourth edge connection line 210_S4.

[0071] For example, Figure 2 and Figure 3 As shown, the display panel may include at least two first edge connection lines 210_S1 and / or at least two second edge connection lines 210_S2, wherein the two first edge connection lines 210_S1 are electrically connected to different signal lines 1, and the two second sub-connection lines 2102 connected to the two first edge connection lines 210_S1 are respectively located on both sides of the light-transmitting area TA in the first direction h1. The two second edge connection lines 210_S2 are electrically connected to different signal lines 1. Moreover, the two second sub-connection lines 2102 connected to the two second edge connection lines 210_S2 are respectively located on both sides of the light-transmitting area TA in the first direction h1.

[0072] The display panel also includes a common line. Exemplarily, the common line can be used to transmit a common voltage. Optionally, the common voltage includes any one of the first power supply voltage, the second power supply voltage, and the reference voltage. The provision of the common line can reduce the voltage drop of the common voltage, which is beneficial to improving the brightness consistency of sub-pixels at different positions.

[0073] like Figure 3 As shown, the common lines include first-type common lines 31, at least part of which is located in the display area AA; and part of the first-type common lines 31 is located on the side of the edge connection line 210_S close to the light-transmitting area TA. It should be noted that Figure 2 and Figure 3The lines of different widths representing the signal line 1 , the first type common line 31 and the first type connecting line 21 are only used to distinguish the wiring lines, and do not represent the actual wiring widths.

[0074] In the embodiment of the present invention, a light-transmitting area TA is provided in the display panel, and a photosensitive element can be subsequently provided corresponding to the light-transmitting area TA, so that the display panel has functions such as shooting or biometrics recognition, which can enrich the user experience.

[0075] Moreover, the embodiment of the present invention arranges a first type of connecting line 21 that is at least partially located in the display area AA, and the first type of connecting line 21 is used to connect the signal line 1 located on both sides of the light-transmitting area TA along the extension direction of the signal line 1. On the basis of ensuring the light transmittance of the light-transmitting area TA and ensuring the normal driving of the pixel driving circuit 101 connected to the signal line 1 located on both sides of the light-transmitting area TA along the extension direction of the signal line 1, the number of connecting lines arranged around the light-transmitting area TA can be reduced, thereby reducing the width of the non-display area between the light-transmitting area TA and the display area AA, which is beneficial to improving the visual effect of the display panel.

[0076] For example, Figure 1 As shown, the display panel further includes a binding area BA, and the binding area BA includes a pad, and the driver chip is bound and connected to the pad. When the distance between the light-transmitting area TA and the binding area BA is large, that is, when the light-transmitting area TA is set at a position far away from the binding area BA, the embodiment of the present invention can increase the conduction path of the common voltage between the edge connection line 210_S and the light-transmitting area TA by setting a common line for transmitting a common voltage, and making the common line include at least a part of the first-class common line 31 located in the display area AA, and making a part of the first-class common line 31 located on the side of the edge connection line 210_S close to the light-transmitting area TA, which is conducive to reducing the voltage drop of the common voltage in the area far away from the binding area BA, for example, in the area between the edge connection line 210_S and the light-transmitting area TA, so as to improve the display consistency at a position close to the driver chip and a position far away from the driver chip in the display area AA.

[0077] In addition, the external ambient light can be reflected by the first type common line 31 and the first type connecting line 21 after being emitted to the display panel. Compared with the case where the first type common line 31 is not set, based on the setting method provided in the embodiment of the present invention, the reflection consistency of the ambient light at the position where the first type connecting line 21 is set and the position where the first type connecting line 21 is not set in the display area AA can also be improved.

[0078] For example, Figure 5 and Figure 6As shown, along the direction h3 perpendicular to the plane where the display panel is located, the embodiment of the present invention can make at least part of the first type of connecting line 21 or at least part of the first type of common line 31 overlap with the pixel driving circuit 101. Such a configuration can reduce the shielding of the light-transmitting area in the display area AA by the first type of connecting line 21 and / or the first type of common line 31, which is conducive to increasing the light-transmitting area of ​​the display area AA. When the display panel is matched with the fingerprint recognition module so that the display panel also has the fingerprint recognition function, the light intensity entering the fingerprint recognition module can be guaranteed, thereby ensuring the accuracy of fingerprint recognition.

[0079] The following combination Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 The wiring situation in the display area AA is described. Figure 7 for Figure 6 A top view of the semiconductor layer in FIG. Figure 8 for Figure 6 A top view of the first metal layer in FIG. Fig. 9 for Figure 6 A top view of the second metal layer in FIG. Fig.10 for Figure 6 A top view of the third metal layer in FIG. Fig.11 for Figure 6 A top view of the fourth metal layer in FIG. Fig.12 for Figure 6 A top view of the fifth metal layer in FIG. Fig.13 A cross-sectional schematic diagram of a display area of ​​a display panel provided by an embodiment of the present invention, wherein Figure 6 In the embodiment, each pixel driving circuit 101 may have the following Figure 3 The circuit connection relationship is shown.

[0080] like Fig.13 As shown, the display panel includes a substrate 100 and a first insulating layer IS1, a semiconductor layer S, a second insulating layer IS2, a first metal layer M1, a third insulating layer IS3, a second metal layer M2, a fourth insulating layer IS4, a third metal layer M3, a fifth insulating layer IS5, a fourth metal layer M4, a sixth insulating layer IS6 and a fifth metal layer M5 which are sequentially stacked on one side of the substrate 100.

[0081] For example, Figure 7As shown, the semiconductor layer S includes a first channel region S10 arranged corresponding to the pixel driving circuit 101, a first doping region S11 and a second doping region S12 located on both sides of the first channel region S10, a second channel region S20, a third doping region S21 and a fourth doping region S22 located on both sides of the second channel region S20, a third channel region S30, a fifth doping region S31 and a sixth doping region S32 located on both sides of the third channel region S30, a fourth channel region S40, a seventh doping region S41 and an eighth doping region S42 located on both sides of the fourth channel region S40, a fifth channel region S50, a ninth doping region S51 and a tenth doping region S52 located on both sides of the fifth channel region S50, a sixth channel region S60, an eleventh doping region S61 and a twelfth doping region S62 located on both sides of the sixth channel region S60, a seventh channel region S70, and a thirteenth doping region S71 and a fourteenth doping region S72 located on both sides of the seventh channel region S70. One of the two doped regions located on both sides of each channel region is a source region, and the other is a drain region. Impurities are doped in the source region and the drain region. The impurities include P-type impurities or N-type impurities. Exemplarily, the semiconductor layer S includes any one or more of low-temperature polysilicon, amorphous silicon, and an oxide semiconductor layer.

[0082] Combination Figure 6 and Figure 8 As shown, the first metal layer M1 includes the first scan line S1, the second scan line S2, the light emitting control signal line E and the first electrode plate C1 of the storage capacitor Cst.

[0083] Combination Figure 6 , Figure 7 and Figure 8As shown, along the direction h3 perpendicular to the plane where the display panel is located, the light-emitting control signal line E overlaps with the first channel region S10 and the sixth channel region S60 respectively, and the portions where the light-emitting control signal line E overlaps with the first channel region S10 and the sixth channel region S60 can respectively correspond to forming the gate G1 of the first transistor T1 and the gate G6 of the sixth transistor T6 in the same pixel driving circuit 101. The second scanning line S2 overlaps with the second channel region S20 and the fourth channel region S40 respectively. And the portions where the second scanning line S2 overlaps with the second channel region S20 and the fourth channel region S40 respectively correspond to forming the gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4 in the same pixel driving circuit 101. The first scanning line S1 overlaps with the fifth channel region S50 and the seventh channel region S70 respectively. Furthermore, the portions where the first scan line S1 overlaps with the fifth channel region S50 and the seventh channel region S70 correspond to forming the gate G5 of the fifth transistor T5 and the gate G7 of the seventh transistor T7, respectively. Exemplarily, in an embodiment of the present invention, the second scan line S2_i and the first scan line S1_i+1 may be connected to the same scan drive unit, that is, the signals of the two may be the same. The fifth transistor T5 and the seventh transistor T7 may respectively belong to two pixel drive circuits 101 adjacently arranged in the second direction h2. Furthermore, according to the scanning order of the display panel, the previous pixel drive circuit 101 includes the seventh transistor T7, and the next pixel drive circuit 101 includes the fifth transistor T5. Figure 8 Taking the illustrated first scan line S1_i+1 as an example, the overlapping portion of the first scan line S1_i+1 and the fifth channel region S50 forms the gate G5 of the fifth transistor T5 of the i+1th pixel driving circuit, and the overlapping portion of the first scan line S1_i+1 and the seventh channel region S70 forms the gate G7 of the seventh transistor T7 of the i-th pixel driving circuit.

[0084] The first plate C1 of the storage capacitor Cst overlaps with the third channel region S30 , and a portion of the first plate C1 of the storage capacitor Cst that overlaps with the third channel region S30 forms a gate G3 of the third transistor T3 .

[0085] For example, Figure 6 and Figure 8 As shown, the fourth transistor T4 and the fifth transistor T5 may form a double-gate transistor including two gates to reduce leakage current of the first node N1 and improve the potential stability of the first electrode N1.

[0086] Combination Figure 6 and Fig. 9As shown, the second metal layer M2 includes a second electrode plate C2 of the storage capacitor Cst, a first sub-reference voltage signal line Vref11, a second sub-reference voltage signal line Vref21, and a first sub-power supply voltage line PVDD1. The first sub-reference voltage signal line Vref11 is used to transmit a first reference voltage, and the second sub-reference voltage signal line Vref21 is used to transmit a second reference voltage. The first sub-power supply voltage line PVDD1 is used to transmit a first power supply voltage.

[0087] For example, Figure 6 and Fig. 9 As shown, the first sub-reference voltage signal line Vref11, the second sub-reference voltage signal line Vref21 and the first sub-power voltage line PVDD1 all extend along the first direction h1. The first sub-reference voltage signal line Vref11 and the second sub-reference voltage signal line Vref21 are alternately arranged in the second direction h2.

[0088] Exemplary, combined Figure 6 and Fig.10 As shown, the third metal layer M3 includes a third sub-reference voltage signal line Vref12, a fourth sub-reference voltage signal line Vref22 and a second sub-power voltage line PVDD2.

[0089] Combination Figure 6 , Fig. 9 and Fig.10 As shown, the extension direction of the third sub-reference voltage signal line Vref12 intersects with the extension direction of the first sub-reference voltage signal line Vref11. The extension direction of the fourth sub-reference voltage signal line Vref22 intersects with the extension direction of the second sub-reference voltage signal line Vref21. The extension direction of the second sub-power supply voltage line PVDD2 intersects with the extension direction of the first sub-power supply voltage line PVDD1. Fig.10 As an example, the third sub-reference voltage signal line Vref12, the fourth sub-reference voltage signal line Vref22 and the second sub-power voltage line PVDD2 all extend along the second direction h2. The third sub-reference voltage signal line Vref12 and the fourth sub-reference voltage signal line Vref22 are alternately arranged in the first direction h1.

[0090] The third sub-reference voltage signal line Vref12 is used to transmit the first reference voltage. Exemplarily, the third sub-reference voltage signal line Vref12 is electrically connected to the above-mentioned first sub-reference voltage signal line Vref11, so that the first reference voltage can form a grid in the transmission path within the display area AA through the first sub-reference voltage signal line Vref11 and the third sub-reference voltage signal line Vref12 to reduce the voltage drop of the first reference voltage.

[0091] The fourth sub-reference voltage signal line Vref22 is used to transmit the second reference voltage. Exemplarily, the fourth sub-reference voltage signal line Vref22 is electrically connected to the second sub-reference voltage signal line Vref21, so that the second reference voltage can form a grid shape through the transmission path of the second sub-reference voltage signal line Vref21 and the fourth sub-reference voltage signal line Vref22 in the display area AA, so as to reduce the voltage drop of the second reference voltage.

[0092] The second sub-power supply voltage line PVDD2 is used to transmit the first power supply voltage. Exemplarily, the second sub-power supply voltage line PVDD2 is electrically connected to the first sub-power supply voltage line PVDD1, so that the first power supply voltage can form a grid shape through the transmission path of the first sub-power supply voltage line PVDD1 and the second sub-power supply voltage line PVDD2 in the display area AA to reduce the voltage drop of the first power supply voltage.

[0093] For example, Fig.10 As shown, the third metal layer M3 also includes a first node N1, combined with Figure 7 As shown, one end of the first node N1 is electrically connected to the eighth doping region S42 and the tenth doping region S52 in the semiconductor layer S. Fig. 9 As shown, the second plate C2 of the storage capacitor Cst includes a first through hole K1. The other end of the first node N1 is electrically connected to the first plate C1 of the storage capacitor Cst, that is, the gate G3 of the third transistor T3, through the first through hole K1 and a through hole penetrating the fourth insulating layer IS4 and the third insulating layer IS3.

[0094] Exemplary, combined Figure 6 and Fig.11 As shown, the fourth metal layer M4 includes the first shielding layer X1. Fig.10 As shown, along the direction h3 perpendicular to the plane where the display panel is located, the first shielding layer X1 at least partially overlaps with the first node N1, and the first shielding layer X1 is used to shield the interference of other signals on the first node N1 to improve the potential stability of the first node N1. Exemplarily, the first shielding layer X1 is used to receive a constant signal. Optionally, the constant signal includes any one of the first power supply voltage, the second power supply voltage, and the reference voltage.

[0095] Exemplary, combined Figure 6 and Fig.11 As shown, the fourth metal layer M4 further includes a shielding connection portion X2, which is used to connect a plurality of first shielding layers X1 arranged along the first direction h1, and the shielding connection portion X2 is electrically connected to the first shielding layer X1.

[0096] Combination Figure 6 and Fig.12 As shown, the fifth metal layer M5 includes the data line Data.

[0097] For example, Fig.11 As shown, the fourth metal layer M4 also includes a first data connection electrode E1. Fig.10 As shown, the third metal layer M3 further includes a second data connection electrode E2. The data line Data is electrically connected to the third doping region S21 in the semiconductor layer S through the first data connection electrode E1 and the second data connection electrode E2.

[0098] For example, Fig. 9 As shown, the second metal layer M2 further includes a second shielding layer X3, and the second shielding layer X3 at least partially surrounds the first node N1 to further improve the potential stability of the first node N1. Exemplarily, the second shielding layer X3 is used to receive a constant signal. Optionally, the constant signal includes any one of the first power supply voltage, the second power supply voltage, and the reference voltage.

[0099] Exemplary, combined Fig.13 As shown, the display panel further includes a connecting electrode 103, and the pixel driving circuit 101 is electrically connected to the light emitting element 102 via the connecting electrode 103. The connecting electrode 103 includes a first sub-connecting electrode 1031, a second sub-connecting electrode 1032, and a third sub-connecting electrode 1033. Fig.10 and Fig.13 As shown, the first sub-connection electrode 1031 is located in the third metal layer M3. The first sub-connection electrode 1031 is electrically connected to the twelfth doping region S62 of the sixth transistor T6 through a second through hole K2 that penetrates the fourth insulating layer IS4, the third insulating layer IS3, and the second insulating layer IS2. Fig.11 and Fig.13 As shown, the second sub-connection electrode 1032 is located in the fourth metal layer M4. The second sub-connection electrode 1032 is electrically connected to the first sub-connection electrode 1031 through a third through hole K3 penetrating the fifth insulating layer IS5. Fig.12 and Fig.13 As shown, the third sub-connection electrode 1033 is located on the fifth metal layer M5. The third sub-connection electrode 1033 is electrically connected to the second sub-connection electrode 1032 through a fourth through hole K4 penetrating the sixth insulating layer IS6.

[0100] like Fig.13As shown, the display panel further includes a passivation layer PV and a planar layer PLN, and the passivation layer PV is located on the side of the fifth metal layer M5 away from the substrate 100. The planar layer PLN is located on the side of the passivation layer PV away from the fifth metal layer M5. The light-emitting element 102 includes a first electrode 1021, a light-emitting layer 1020, and a second electrode 1022. The first electrode 1021 is located on the sixth metal layer M6, and the sixth metal layer M6 is located on the side of the planar layer PLN away from the passivation layer PV. The first electrode 1021 is electrically connected to the third sub-connection electrode 1033 through a fifth through hole K5 that penetrates the planar layer PLN and the passivation layer PV.

[0101] Exemplary, combined Figure 3 , Figure 5 and Figure 6 As shown, the first type common line 31 includes a first sub-common line 3101 and / or a second sub-common line 3102. The first sub-common line 3101 and the second sub-common line 3102 extend in directions intersecting with each other and are electrically connected.

[0102] When arranging the first sub-connection line 2101, the second sub-connection line 2102, the first sub-common line 3101, and the second sub-common line 3102, illustratively, the embodiment of the present invention can make the first sub-connection line 2101 and the first sub-common line 3101 parallel to each other and arranged in the same layer, and / or make the second sub-connection line 2102 and the second sub-common line 3102 parallel to each other and arranged in the same layer. Such arrangement can simplify the manufacturing process of the display panel and reduce the thickness of the display panel. Figure 2 As an example, the first sub-connection line 2101 and the first sub-common line 3101 extend along the first direction h1, and the second sub-connection line 2102 and the second sub-common line 3102 extend along the second direction h2.

[0103] Optional, such as Figure 6As shown, along the direction h3 perpendicular to the plane where the display panel is located, the embodiment of the present invention can make the first sub-connection line 2101 at least partially overlap with the above-mentioned first sub-reference voltage signal line Vref11 or the second sub-reference voltage signal line Vref21, make the first sub-common line 3101 at least partially overlap with the above-mentioned first sub-reference voltage signal line Vref11 or the second sub-reference voltage signal line Vref21, and / or make the second sub-connection line 2102 at least partially overlap with the above-mentioned third sub-reference voltage signal line Vref12 or the fourth sub-reference voltage signal line Vref22, and make the second sub-common line 3102 at least partially overlap with the above-mentioned third reference voltage signal line Vref12 or the fourth reference voltage signal line Vref22. The signals transmitted by the first sub-reference voltage signal line Vref11, the second sub-reference voltage signal line Vref21, the third sub-reference voltage signal line Vref12 and the fourth sub-reference voltage signal line Vref22 are constant signals, so that the first sub-connection line 2101 at least partially overlaps with the above-mentioned first sub-reference voltage signal line Vref11 or the second sub-reference voltage signal line Vref21, and the second sub-connection line 2102 at least partially overlaps with the above-mentioned third reference voltage signal line Vref12 or the fourth reference voltage signal line Vref22. While ensuring the light-transmitting area within the display area AA, the interference between the signals transmitted by the first sub-connection line 2101 and the second sub-connection line 2102 can be reduced, which is beneficial to improving the accuracy of the signals transmitted by the first sub-connection line 2101 and the second sub-connection line 2102. In addition, by making the first sub-common line 3101 at least partially overlap with the above-mentioned first sub-reference voltage signal line Vref11 or the second sub-reference voltage signal line Vref21, and / or making the second sub-common line 3102 at least partially overlap with the above-mentioned third reference voltage signal line Vref12 or the fourth reference voltage signal line Vref22, it can be ensured that the environment around the first sub-common line 3101 and the first sub-connection line 2101 is the same, and / or that the environment around the second sub-common line 3102 and the second sub-connection line 2102 is the same.

[0104] Figure 6As an illustration, part of the first sub-connection line 2101 overlaps with the first sub-reference voltage signal line Vref11, another part of the first sub-connection line 2101 overlaps with the second sub-reference voltage signal line Vref12, part of the first sub-common line 3101 overlaps with the first sub-reference voltage signal line Vref11, another part of the first sub-common line 3101 overlaps with the second sub-reference voltage signal line Vref12, part of the second sub-connection line 2102 overlaps with the third sub-reference voltage signal line Vref12, another part of the second sub-connection line 2102 overlaps with the fourth sub-reference voltage signal line Vref22, part of the second sub-common line 3102 overlaps with the third sub-reference voltage signal line Vref12, and another part of the second sub-common line 3102 overlaps with the fourth sub-reference voltage signal line Vref22.

[0105] Optionally, in the embodiment of the present invention, the first sub-connection line 2101 and / or the first sub-common line 3101 can be arranged in the same layer with any one of the first scan line S1, the second scan line S2, the light emitting control signal line E, the first sub-reference voltage signal line Vref11, the second sub-reference voltage signal line Vref21, and the first shielding layer X1; and the second sub-connection line 2102 and / or the second sub-common line 3102 can be arranged in the same layer with any one of the second sub-power supply voltage line PVDD2, the third sub-reference voltage signal line Vref12, the fourth sub-reference voltage signal line Vref22, and the data line Data. With such arrangement, there is no need to add a new film layer in the display panel to arrange the first sub-connection line 2101, the first sub-common line 3101, the second sub-connection line 2102, and the second sub-common line 3102, which is conducive to simplifying the manufacturing process of the display panel and reducing the thickness of the display panel. Figure 6 and Fig.11 The first sub-connection line 2101 and the first sub-common line 3101 are located in the fourth metal layer M4, that is, the first sub-connection line 2101 and / or the first sub-common line 3101 are arranged in the same layer as the first shielding layer X1 as an example. Figure 6 and Fig.12 The second sub-connection line 2102 and the second sub-common line 3102 are located in the fifth metal layer M5, that is, the second sub-connection line 2102 and / or the second sub-common line 3102 are arranged in the same layer as the data line Data.

[0106] Exemplary, combined Figure 3 and Figure 5As shown, part of the first common line 31 includes a first common line 311; the first common line 311 is insulated and crosses the edge connection line 210_S; the display area AA includes a first pixel driving circuit 1011 and a second pixel driving circuit 1012 arranged along the extension direction of the first common line 311, and the first pixel driving circuit 1011 and the second pixel driving circuit 1012 are adjacent. The first common line 311 overlaps with the first pixel driving circuit 1011; the part of the first connection line 21 parallel to the first common line 311 overlaps with the second pixel driving circuit 1012.

[0107] Exemplarily, the first common line 311 includes a first sub-common line 3101 extending along the first direction h1 and / or a second sub-common line 3102 extending along the second direction h2. Figure 3 As an example, the first common line 311 includes a first sub-common line 3101 extending along a first direction h1 and a second sub-common line 3102 extending along a second direction h2.

[0108] like Figure 3 As shown, the first sub-common line 3101 in the first common line 311 may cross the third edge connection line 210_S3 and / or the fourth edge connection line 210_S4. For the first sub-common line 3101 crossing the third edge connection line 210_S3, the corresponding first pixel driving circuit 1011 and second pixel driving circuit 1012 are arranged along the first direction h1.

[0109] Combination Figure 5 and Fig.11 As shown, the end D of the first sub-common line 3101 3101 The end D of the first sub-connection line 2101 in the first type connection line 21 2101 The two are spaced apart, with a first gap 301 therebetween.

[0110] like Figure 3 As shown, the second sub-common line 3102 in the first common line 311 may cross the first edge connection line 210_S1 and / or the second edge connection line 210_S2. For the second sub-common line 3102 crossing the second edge connection line 210_S2, the corresponding first pixel driving circuit 1011 and second pixel driving circuit 1012 are arranged along the second direction h2.

[0111] Combination Figure 5 and Fig.12 As shown, the end D of the second sub-common line 3102 3102 The end D of the second sub-connection line 2102 in the first type connection line 21 2102 The two are spaced apart with a second gap 302 therebetween.

[0112] It should be noted that Figure 5 The first slit 301 shown is located between the first pixel driving circuit 1011 and the second pixel driving circuit 1012, and the overlapping arrangement of the second slit 302 and the second pixel driving circuit 1012 is only a schematic representation. The embodiment of the present invention does not limit the relative position relationship between the first slit 301 and the second slit 302 and the pixel driving circuit 101.

[0113] In the embodiment of the present invention, a first common line 311 insulated and crossed with the edge connection line 210_S is arranged in the display panel, and the first common line 311 is overlapped with the first pixel driving circuit 1011, and a portion of the first type connection line 21 parallel to the first common line 311 is overlapped with the second pixel driving circuit 1012, and the first pixel driving circuit 1011 and the second pixel driving circuit 1012 are arranged adjacent to each other along the extension direction of the first common line 311, so that the first common line 311 can be extended from the side of the edge connection line 210_S away from the light-transmitting area TA to the side close to the light-transmitting area TA. Compared with the method of terminating the first common line 311 at the position of the edge connection line 210_S, on the one hand, the conduction path of the common voltage in the area where the edge connection line 210_S is close to the light-transmitting area TA can be increased, which is conducive to further reducing the voltage drop of the common voltage in the area with a large distance from the driving chip, and improving the brightness consistency at different positions in the display area AA. On the other hand, the space utilization rate at the position where the first pixel driving circuit 1011 is located can be improved.

[0114] For example, Figure 3 As shown, the first type common line 31 includes a second common line 312; the second common line 312 is insulated and crosses the edge connection line 210_S. Fig.14 As shown, Fig.14 for Figure 3 A simplified enlarged schematic diagram of the middle area Q3 , the display area AA includes a first pixel driving circuit group 41 , and the first pixel driving circuit group 41 includes a plurality of pixel driving circuits 101 arranged along the extension direction of the second common line 312 .

[0115] Along the direction h3 perpendicular to the plane where the display panel is located, the multiple pixel driving circuits 101 in the first pixel driving circuit group 41 overlap with the second common line 312, and the multiple pixel driving circuits 101 in the first pixel driving circuit group 41 are staggered with the portion of the first type of connecting line 21 parallel to the second common line 312, that is, the multiple pixel driving circuits 101 in the first pixel driving circuit group 41 do not overlap with the portion of the first type of connecting line 21 parallel to the second common line 312. Fig.14 As shown, the extension line of the second common line 312 and the sub-connection lines in the first type of connection lines 21 that are parallel to the second common line 312 are staggered with each other.

[0116] Exemplarily, the second common line 312 includes a first sub-common line 3101 extending along the first direction h1 and / or a second sub-common line 3102 extending along the second direction h2. Figure 3 As an example, the second common line 312 includes a first sub-common line 3101 extending along the first direction h1 and a second sub-common line 3102 extending along the second direction h2.

[0117] In the embodiment of the present invention, by insulating and crossing the second common line 312 and the edge connection line 210_S, and overlapping the second common line 312 and the first pixel driving circuit group 41, the sub-connection line in the first type of connection line 21 parallel to the second common line 312 does not overlap with the first pixel driving circuit group 41, so that the length of the second common line 312 can be set as long as possible, and while increasing the conduction path of the common voltage between the edge connection line 210_S and the light-transmitting area TA and improving the display consistency in the display area AA, the short-circuit risk of the second common line 312 and the sub-connection line having the same extension direction as the second common line 312 can be reduced, which is beneficial to reducing the wiring difficulty in the display area AA.

[0118] like Figure 3 As shown, the length of the second common line 312 is greater than the length of the first common line 311 having the same extension direction. The second common line 312 may cross and electrically connect with the first common line 311 having a different extension direction.

[0119] For example, Figure 3 As shown, the multiple first-type connection lines 21 include at least a first connection line 211, a second connection line 212 and a third connection line 213 that are adjacently arranged, wherein the distance d12 between the sub-connection line in the second connection line 212 parallel to the extension direction of the second common line 312 and the sub-connection line in the first connection line 211 parallel to the extension direction of the second common line 312 is greater than or equal to the distance d23 between the sub-connection line in the second connection line 212 parallel to the extension direction of the second common line 312 and the sub-connection line in the third connection line 213 parallel to the extension direction of the second common line 312. With such a configuration, at least a setting space can be reserved for the second common line 312 between a sub-connection line in the second connection line 212 that is parallel to the extension direction of the second common line 312 and a sub-connection line in the first connection line 211 that is parallel to the extension direction of the second common line 312, so that the second common line 312 is located between a sub-connection line in the first connection line 211 that is parallel to the second common line 312 and a sub-connection line in the second connection line 212 that is parallel to the second common line 312.

[0120] Exemplarily, the number of the second common lines 312 can be adjusted according to the distance d12 between the second connection line 212 and the sub-connection line in the first connection line 211 that is parallel to the extension direction of the second common line 312. Figure 3As an example, two second common lines 312 are provided between the first connection line 211 and the second connection line 212 .

[0121] Exemplarily, in the embodiment of the present invention, the distance between the sub-connection line in the first connection line 211 parallel to the extension direction of the second common line 312 and the second common line 312 is greater than or equal to the distance between the sub-connection lines in the second connection line 212 and the third connection line 213 parallel to the extension direction of the second common line 312. And / or, the distance between the sub-connection line in the second connection line 212 parallel to the extension direction of the second common line 312 and the second common line 312 is greater than or equal to the distance between the sub-connection line in the second connection line 212 and the third connection line 213 parallel to the extension direction of the second common line 312. In this way, while increasing the conduction path of the common voltage and reducing the reduction of the common voltage, the distance between the sub-connection lines in the second connection line 212 and the third connection line 213 parallel to the extension direction of the second common line 312 can be minimized, so that the length difference between the second connection line 212 and the third connection line 213 can be small, which is conducive to reducing the load difference between the two.

[0122] For example, Fig.15 As shown, Fig.15 A partial enlarged schematic diagram of another display panel provided in an embodiment of the present invention, the display panel includes at least two light-transmitting areas TA. For example, photosensitive devices can be respectively provided corresponding to the two light-transmitting areas TA. The first type of common line 31 includes a third common line 313, at least part of which is located between two adjacent light-transmitting areas TA.

[0123] Exemplarily, the third common line 313 includes a first sub-common line 3101 and / or a second sub-common line 3102 . Fig.15 As an example, the third common line 313 includes a first sub-common line 3101 and a second sub-common line 3102 , and the first sub-common line 3101 and at least a portion of the second sub-common line 3102 crossing the first sub-common line 3101 are electrically connected.

[0124] The setting of the third common line 313 can further increase the conduction path of the common voltage in the area between the edge connection line 210_S and the light-transmitting area TA, can further reduce the voltage drop of the common signal transmitted by the common line, and can improve the display consistency at various positions in the display area AA.

[0125] like Fig.15 As shown, an extension line of the first sub-common line 3101 included in the third common line 313 passes through at least one of the light-transmitting areas TA.

[0126] The second sub common line 3102 included in the third common line 313 may be cross-electrically connected to the first sub common line 3101 in the first common line 311 and / or the first sub common line 3101 in the second common line 312 .

[0127] Combination Fig.15 and Fig.16 As shown, Fig.16 for Fig.15 A simplified enlarged schematic diagram of the middle area Q4, at least one first sub-display area AA1 is included between two adjacent light-transmitting areas TA, the first sub-display area AA1 includes a pixel driving circuits 101 arranged along the arrangement direction of the two adjacent light-transmitting areas TA, and the arrangement direction of the two adjacent light-transmitting areas TA includes the first direction h1 or the second direction h2. The first sub-display area AA1 also includes x sub-connection lines arranged along the arrangement direction of the two adjacent light-transmitting areas TA and y third common lines 313 arranged along the arrangement direction of the two adjacent light-transmitting areas TA, wherein the extension line of the third common line 313 is staggered with the light-transmitting area TA.

[0128] like Fig.16 As shown, when two adjacent light-transmitting areas TA are arranged along the first direction h1, the first sub-display area AA1 includes a pixel driving circuits 101 arranged along the first direction h1, y second sub-common lines 3102 arranged along the first direction h1, and x second sub-connection lines 2102 arranged along the first direction h1. Wherein, x+y≤a. That is, the total number of first-type connection lines 21 or third common lines 313 between the two light-transmitting areas TA does not exceed the number of pixel driving circuits 101. Based on this arrangement, the first-type connection lines 21 or third common lines 313 between the two light-transmitting areas TA can overlap with the pixel driving circuit 101 in the first sub-display area AA1, and the first-type connection lines 21 and the third common lines 313 can be avoided from being arranged at positions where the pixel driving circuit 101 is not arranged in the first sub-display area AA1, which is conducive to improving the light transmittance in the first sub-display area AA1. At the same time, at any position of each pixel driving circuit 101 in the first sub-display area AA1, at most one third common line 313 and one of the sub-connection lines in the first connection line 21 extending in a direction parallel to the third common line 313 can be set to avoid adding a new film layer in the display panel, which is beneficial to thinning the display panel.

[0129] For example, Fig.16 As shown, when a plurality of first sub-display areas AA1 are included between two adjacent light-transmitting areas TA, the plurality of first sub-display areas AA1 are arranged along the second direction h2, and the numbers of pixel driving circuits 101 in different first sub-display areas AA1 may be the same or different. Fig.16Take three first sub-display areas AA1 arranged along the second direction h2 between two adjacent light-transmitting areas TA as an illustration, wherein each first sub-display area AA1 includes six pixel driving circuits, two second sub-connecting lines 2102 and four second sub-common lines 3102, that is, a=6, x=2, y=4 as an illustration.

[0130] For example, Fig.15 As shown, the light-transmitting area TA adjacent to the first non-display area NA1 includes a first end D1 and a second end D2, the first end D1 is located on a side of the light-transmitting area TA close to another light-transmitting area TA, and the second end D2 is located on a side of the light-transmitting area TA close to the first non-display area NA1; Fig.15 As an example, the display panel includes two light-transmitting areas TA, and both light-transmitting areas TA are adjacent to the first non-display area NA1.

[0131] The signal line 1 includes a first signal line 11 passing through the light-transmitting area TA; the distance between the first signal line 11 and the first end D1 of the light-transmitting area TA through which it passes is smaller than the distance between the first signal line 11 and the second end D2; the portion of the first type connection line 21 electrically connected to the first signal line 11 is located between the second end D2 and the first non-display area NA1. Fig.15 As shown, the second sub-connection line 2102 of the first type connection line 21 electrically connected to the first signal line 11 is located between the second end D2 and the first non-display area NA1.

[0132] Such a configuration avoids setting the portion of the first type connection line 21 electrically connected to the first signal line 11 between two adjacent light-transmitting areas TA, so that a larger number of third common lines 313 can be set between two adjacent light-transmitting areas TA, which is beneficial to increasing the conduction path of the common voltage, reducing the voltage drop of the common voltage in the first sub-display area AA1, and improving the brightness consistency of different positions in the display area AA.

[0133] For example, Figure 3 and Fig.15 As shown, the first type connection line 21 at least includes a fourth connection line 214 and a fifth connection line 215, which are electrically connected to different signal lines 1. Along the first direction h1, the second sub-connection line 2102 of the fourth connection line 214 and the second sub-connection line 2102 of the fifth connection line 215 are located on both sides of the light-transmitting area TA.

[0134] like Figure 3 and Fig.15 As shown, the first type common line 31 further includes a fourth common line 314. The fourth common line 314 is located between the first sub-connection line 2101 of the fourth connection line 214 and the first sub-connection line 2101 of the fifth connection line 215. The fourth common line 314 can increase the conduction path of the common voltage and further reduce the voltage drop of the common voltage.

[0135] For example, Figure 3 As shown, the signal line 1 connected to the fourth connection line 214 and the signal line 1 connected to the fifth connection line 215 may be cut off by the same light-transmitting area TA, and the second sub-connection line 2102 of the fourth connection line 214 and the second sub-connection line 2102 of the fifth connection line 215 may include a light-transmitting area TA. Fig.15 As shown, the signal line 1 connected to the fourth connection line 214 and the signal line 1 connected to the fifth connection line 215 can be respectively cut off by different light-transmitting areas TA, and the second sub-connection line 2102 of the fourth connection line 214 and the second sub-connection line 2102 of the fifth connection line 215 can include at least two light-transmitting areas TA. Figure 3 and Fig.15 As shown, the signal line 1 electrically connected to the fourth connection line 214 and the signal line 1 electrically connected to the fifth connection line 215 are not adjacent.

[0136] like Figure 3 and Fig.15 As shown, the fourth common line 314 extends along the first direction h1. The sub-connection lines in the first type connection lines 21 that extend in a different direction from the fourth common line 314 do not overlap with the fourth common line 314.

[0137] Combination Fig.17 As shown, Fig.17 for Fig.15 A simplified enlarged schematic diagram of the middle area Q5, the display area AA also includes a second pixel driving circuit group 42, the second pixel driving circuit group 42 includes a plurality of pixel driving circuits 101 arranged along the extension direction of the fourth common line 314, and the embodiment of the present invention can make part of the pixel driving circuits 101 overlap with the first sub-connection line 2101 of the fourth connection line 214, make another part of the pixel driving circuits 101 overlap with the fourth common line 314, and make another part of the pixel driving circuits 101 overlap with the first sub-connection line 2101 of the fifth connection line 215. There is a third gap 303 between the first sub-connection line 2101 of the fourth connection line 214 and the fourth common line 314, and there is a fourth gap 304 between the first sub-connection line 2101 of the fifth connection line 215 and the fourth common line 314.

[0138] like Figure 3 and Fig.15 As shown, the fourth common line 314 is electrically connected to a portion of the first common line 311. The fourth common line 314 is staggered with the second common line 312 extending along the second direction h2. Fig.15 As shown, the fourth common line 314 and a portion of the third common line 313 are cross-electrically connected.

[0139] For example, Fig.18As shown, Fig.18 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention, the light-transmitting area TA includes at least two sub-light-transmitting areas TA1. Optionally, the two sub-light-transmitting areas TA1 may be arranged along the first direction h1.

[0140] like Fig.18 As shown, the display panel includes a second non-display area NA2 located between two adjacent sub-light-transmitting areas TA1; when the photosensitive devices are subsequently set, part of the photosensitive devices can be set to at least partially overlap with the second non-display area NA2, so that external ambient light can pass through the second non-display area NA2 and enter the photosensitive device set corresponding to the second non-display area NA2.

[0141] For example, Fig.18 As shown, the first type common line 31 includes a fifth common line 315 , and at least a portion of the fifth common line 315 is located in the second non-display area NA2 .

[0142] Exemplarily, the fifth common line 315 includes a first sub-common line 3101 extending along the first direction h1 and / or a second sub-common line 3102 extending along the second direction h2. Fig.18 Taking the fifth common line 315 including the first sub-common line 3101 and the second sub-common line 3102 as an example, at least a portion of the first sub-common line 3101 and the second sub-common line 3102 are cross-connected and electrically connected.

[0143] The fifth common line 315 can increase the conduction path of the common voltage around the light-transmitting area TA, reduce the voltage drop of the common voltage, and further improve the display consistency of different positions in the display area AA.

[0144] Optional, such as Fig.19 As shown, Fig.19 for Fig.18 A simplified enlarged schematic diagram of the second non-display area in FIG. 1 is a schematic diagram of a second non-display area in FIG. 1 , wherein the second non-display area NA2 includes a virtual pixel 5, and the virtual pixel 5 is not used for emitting light. Optionally, the virtual pixel 5 includes a pixel driving circuit 101 and / or a light-emitting element.

[0145] When the virtual pixel 5 includes a pixel driving circuit 101, illustratively, the structure of the pixel driving circuit 101 in the virtual pixel 5 is the same as the structure of the pixel driving circuit 101 of the sub-pixel in the display area AA, that is, the pixel driving circuit 101 in the virtual pixel 5 also includes Figure 3 The first transistor to the seventh transistor and the storage capacitor are shown. Among them, each pixel driving circuit 101 can adopt the same wiring method as the pixel driving circuit 101 in the display area AA. The setting of the pixel driving circuit 101 in the virtual pixel 5 can improve the uniformity of the pattern density in different areas of the display panel.

[0146] like Fig.19 As shown, along the direction h3 perpendicular to the plane where the display panel is located, the virtual pixel 5 and the fifth common line 315 partially overlap. Specifically, the pixel driving circuit 101 in the virtual pixel 5 and the fifth common line 315 partially overlap. In this way, while reducing the voltage drop of the common voltage, the space in the second non-display area NA2 can be reasonably utilized to avoid the setting of the fifth common line 315 reducing the light transmittance in the second non-display area NA2, so that more external ambient light can pass through the second non-display area NA2 into the photosensitive element.

[0147] Exemplary, combined Figure 5 and Fig.19 As shown, the spacing W11 between two adjacent second sub-common lines 3102 in the second non-display area NA2 is less than or equal to the spacing W12 between two adjacent second sub-common lines 3102 in the display area AA. And / or, the spacing W21 between two adjacent first sub-common lines 3101 in the second non-display area NA2 is less than or equal to the spacing W22 between two adjacent first sub-common lines 3101 in the display area AA. Fig.19 As an example, the spacing W21 between two adjacent first sub-common lines 3101 in the second non-display area NA2 is smaller than the spacing W22 between two adjacent first sub-common lines 3101 in the display area AA. Also, the spacing W11 between two adjacent second sub-common lines 3102 in the second non-display area NA2 is smaller than the spacing W12 between two adjacent second sub-common lines 3102 in the display area AA. In the second non-display area NA2, the first sub-common line 3101 is electrically connected to at least a portion of the second sub-common line 3102 intersecting therewith.

[0148] With such a configuration, the space of the second non-display area NA2 can be fully utilized, and the density of the first sub-common line 3101 and / or the second sub-common line 3102 in the fifth common line 315 in the second non-display area NA2 can be increased, thereby further increasing the conduction path of the common voltage, further reducing the voltage drop of the common voltage, and improving the display consistency at various positions in the display area.

[0149] like Fig.19 As shown, in the second non-display area NA2, the spacing W21 between two adjacent first sub-common lines 3101 is less than or equal to the height L2 of a pixel driving circuit 101 in the second direction h2. The spacing W11 between two adjacent second sub-common lines 3102 is less than or equal to the width L1 of a pixel driving circuit 101 in the first direction h1. Exemplarily, in the second non-display area NA2, the embodiment of the present invention can make two adjacent first sub-common lines 3101 overlap with different positions of the same pixel driving circuit 101, and make two adjacent second sub-common lines 3102 overlap with different positions of the same pixel driving circuit 101, so as to increase the density of common lines in the second non-display area NA2.

[0150] like Fig.18 As shown, the extension line of one of the two adjacent first sub-common lines 3101 in the fifth common line 315 can pass through part of the first sub-common line 3101 in the display area AA. Fig.18 and Fig.19 In FIG. 1 , the portion of the first sub-common line in the second non-display area NA2 is marked as 3101_1. The extension line of another first sub-common line 3101 does not pass through the first sub-common line 3101 in the display area AA. Fig.18 and Fig.19 In FIG. 3 , the portion of the first sub-common lines in the second non-display area NA2 is marked as 3101_2.

[0151] For example, Fig.18 As shown in FIG. 1 , part of the fifth common line 315 extends from the display area AA to the second non-display area NA2. Taking the arrangement of two sub-light-transmitting areas TA1 along the first direction h1 as an example, Fig.18 As shown, part of the second sub-common line 3102 in the fifth common line 315 extends from the display area AA to the second non-display area NA2. Fig.18 and Fig.19 The portion of the second sub-common line in the second non-display area NA2 is marked as 3102_1.

[0152] For example, Fig. 20 As shown, Fig. 20 For Fig.19 A corresponding wiring schematic diagram, the second non-display area NA2 includes a first scan line S1, a second scan line S2, a light emitting control signal line E, a data line Data, a first sub-reference voltage signal line Vref11, a second sub-reference voltage signal line Vref21, a third sub-reference voltage signal line Vref12, a fourth sub-reference voltage signal line Vref22, a first sub-power supply voltage line PVDD1 and a second sub-power supply voltage line PVDD2.

[0153] In the second non-display area NA2, the embodiment of the present invention can make the first sub-common line 3101_1 overlap with the first sub-reference voltage signal line Vref11 or the second sub-reference voltage signal line Vref21; and / or, make the second sub-common line 3102_1 overlap with the third sub-reference voltage signal line Vref12 or the fourth sub-reference voltage signal line Vref22, so as to improve the light transmittance of the second non-display area NA2 while making the wiring in the second non-display area NA2 and the wiring in the display area AA have the same wiring environment. When manufacturing the display panel, the first sub-common line 3101_1 in the second non-display area NA2 and the first sub-common line 3101 in the display area AA can be formed by the same process. The second sub-common line 3102_1 in the second non-display area NA2 and the second sub-common line 3102 in the display area AA can be formed by the same process.

[0154] like Fig.18 As shown in FIG. 1 , another portion of the second sub-common line 3102 in the fifth common line 315 ends at the edge of the second non-display area NA2 , that is, this portion of the second sub-common line 3102 does not extend to the display area AA. Fig.18 , Fig.19 and Fig. 20 The second sub-common lines in the second non-display area NA2 are marked as 3102_2. The second sub-common lines marked as 3102_2 can increase the conduction paths of the common voltage in the second non-display area NA2.

[0155] Optional, combined Figure 6 and Fig. 20 As shown, the virtual pixel 5 does not include at least part of the connecting electrode 103, so that the connection between the light-emitting element in the second non-display area NA2 and the pixel driving circuit is disconnected, so that the light-emitting element in the virtual pixel 5 does not emit light.

[0156] Optionally, an embodiment of the present invention may allow at least one of the first sub-common line 3101_1, the first sub-common line 3101_2, the second sub-common line 3102_1, and the second sub-common line 3102_2 in the fifth common line 315 to be arranged in the same layer as at least a portion of the connecting electrode 103 in the display area AA to avoid adding a new film layer in the display panel and reducing the thickness of the display panel.

[0157] For example, in the embodiment of the present invention, the first sub-common line 3101_1 and the first sub-common line 3101_2 in the fifth common line 315 may be disposed in the same layer as the second sub-connection electrode 1032 in the display area AA. Fig.11 , Fig. 20 and Fig.21 As shown, Fig.21 for Fig. 20, wherein the first sub-common line 3101_1 and the first sub-common line 3101_2 in the fifth common line 315 and the second sub-connecting electrode 1032 in the display area AA are arranged in the fourth metal layer M4 at the same layer as an example. Fig.13 and Fig. 22 As shown, Fig. 22 A schematic cross-sectional view of a second non-display area of ​​a display panel provided by an embodiment of the present invention shows that in the second non-display area NA2 , the fifth insulating layer IS5 does not include a through hole between the first sub-common line 3101_2 and the first sub-connection electrode 1031 .

[0158] Optionally, in the embodiment of the present invention, the extension line of the first sub common line 3101_2 in the second non-display area NA2 may pass through a plurality of second sub connection electrodes 1032 arranged along the first direction h1 in the display area AA.

[0159] For example, in the embodiment of the present invention, the second sub-common line 3102_1 and the second sub-common line 3102_2 in the fifth common line 315 can be disposed in the same layer as the third sub-connection electrode 1033 in the display area AA. Fig.12 , Fig. 20 and Fig.23 As shown, Fig.23 for Fig. 20 , wherein the second sub-common line 3102_1 and the second sub-common line 3102_2 in the fifth common line 315 and the third sub-connecting electrode 1033 in the display area AA are arranged in the fifth metal layer M5 as an example. Fig. 20 , Fig. 22 and Fig.23 As shown, in the embodiment of the present invention, the second sub-common line 3102_2 can pass through the sixth insulating layer IS6 ( Fig. 20 and Fig.23 The sixth through hole K6 (not shown) is electrically connected to the first sub common line 3101_2. The sixth through hole K6 and the fourth through hole K4 are formed in the same process.

[0160] Optionally, in the embodiment of the present invention, the extension line of the second sub common line 3102_2 in the second non-display area NA2 may pass through a plurality of third sub connection electrodes 1033 arranged along the second direction h2 in the display area AA.

[0161] like Fig. 22 As shown, in the second non-display area NA2, the planarization layer PLN and the passivation layer PV do not include a through hole between the second sub-common line 3102_2 and the first electrode 1021 to prevent the light emitting element 102 in the virtual pixel 5 from being electrically connected to the second sub-common line 3102_2.

[0162] Or, if Fig.24 As shown, Fig.24 Another cross-sectional schematic diagram of the second non-display area provided by an embodiment of the present invention, the embodiment of the present invention can make the virtual pixel 5 not include a light-emitting element, and make at least part of the fifth common line 315 be arranged in the same layer as the electrode of the light-emitting element in the display area AA. Fig.13 and Fig.24 As shown, in the embodiment of the present invention, the fifth common line 315 can be arranged in the same layer as the first electrode 1021 of the light emitting element 102, that is, the fifth common line 315 can be arranged in the sixth metal layer M6 to avoid adding a new film layer in the display panel and reducing the thickness of the display panel.

[0163] For example, Fig.25 As shown, Fig.25 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention, wherein the connection line further includes a second type of connection line 22, which is located on the side of the second non-display area NA2 close to the sub-light-transmitting area TA1, and the second type of connection line 22 partially surrounds the sub-light-transmitting area TA1. The second type of connection line 22 can connect the signal line 1 that is cut off by the sub-light-transmitting area TA1. It should be noted that in order to simplify the diagram, Fig.25 Only the connection lines and signal lines are shown, and other structures such as the common lines and the pixel driving circuit are not shown. In the embodiment of the present invention, by setting the second type of connection lines 22 on the side of the second non-display area NA2 close to the sub-light-transmitting area TA1, the number of the first type of connection lines 21 set in the display area AA can be reduced, so that more space can be reserved for the setting of the common lines in the display area AA, which is conducive to increasing the number of common lines in the display area AA and reducing the voltage drop of the common voltage. Exemplarily, the second type of connection lines 22 can be located between the sub-light-transmitting area TA1 and the above-mentioned virtual pixel ( Fig.25 not shown).

[0164] For example, Figure 1 , Figure 3 and Fig.15 As shown, the first non-display area NA1 includes a common bus 6, and the common bus 6 is electrically connected to the plurality of first-type common lines 31. Figure 1 As shown, the first sub non-display area NA11, the second sub non-display area NA12, the third sub non-display area NA13 and the fourth sub non-display area NA14 all include the common bus 6. Optionally, the common bus 6 can be electrically connected to the pad in the binding area BA, so that the common voltage transmitted by the driving chip is transmitted to the first type common line 31 located in the display area AA through the common bus 6.

[0165] For example, Fig.26 As shown, Fig.26A local enlarged schematic diagram of another display panel provided for an embodiment of the present invention, in which a portion of the first-type connecting line 21 and a portion of the first-type common line 31 are both located in the first non-display area NA1, so as to reduce the space occupied by the first-type connecting line 21 and the first-type common line 31 in the display area AA and reduce the wiring difficulty in the display area AA.

[0166] For example, Fig.26 As shown, in the first non-display area NA1, along the direction h3 perpendicular to the plane where the display panel is located, the first common lines 31 and the first connecting lines 21 partially overlap to improve the space utilization of the first non-display area NA1 and reduce the width of the first non-display area NA1.

[0167] For example, Fig.26 and Fig. 27 As shown, Fig. 27 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention, the display panel further includes a second type of common line 32, the second type of common line 32 is located on the side of the light-transmitting area TA close to the display area AA, and the second type of common line 32 at least partially surrounds the light-transmitting area TA. The second type of common line 32 is located between the light-transmitting area TA and the display area AA, and the second type of common line 32 is electrically connected to the first type of common line 31. The provision of the second type of common line 32 can further increase the conduction path of the common voltage around the light-transmitting area TA and reduce the voltage drop of the common voltage. Moreover, the second type of common line 32 does not need to occupy the space of the display area AA, which is conducive to reducing the wiring difficulty of the display area AA.

[0168] Exemplarily, the second type of common line 32 and the part of the first type of common line 31 electrically connected thereto are arranged in the same layer; the two are in contact and electrically connected. Alternatively, along a direction h3 perpendicular to the plane where the display panel is located, an insulating layer is included between the second type of common line 32 and at least part of the first type of common line 31, the insulating layer includes a through hole, and the second type of common line 32 and part of the first type of common line 31 are electrically connected through the through hole.

[0169] Combination Fig. 27 and Fig.28 As shown, Fig.28 for Fig. 27 In a cross-sectional schematic diagram along BB′, the first-type common line 31 includes a first sub-common line 3101 and a second sub-common line 3102 . The first sub-common line 3101 extends along a first direction h1 , and the second sub-common line 3102 extends along a second direction h2 . Fig. 27 and Fig.28The signal line 1, the second sub-common line 3102, and the second sub-connection line 2102 are arranged in the same layer on the fifth metal layer M5, and the first sub-common line 3101, the first sub-connection line 2101, and the second type common line 32 are arranged in the same layer on the fourth metal layer M4 as an example. The insulating layer between the second type common line 32 and the first type common line 31 includes the sixth insulating layer IS6. The sixth insulating layer IS6 includes a seventh through hole K7 for connecting the second type common line 32 and the second sub-common line 3102.

[0170] Optional, such as Fig.26 and Fig. 27 As shown, the shape of the orthographic projection of the second type common line 32 on the plane where the display panel is located includes a circular ring.

[0171] Or, if Fig.29 and Fig.30 As shown, Fig.29 A partial enlarged schematic diagram of another display panel provided by an embodiment of the present invention, Fig.30 for Fig.29 A simplified enlarged schematic diagram of the middle area Q6, the shape of the orthographic projection of the second type common line 32 on the plane where the display panel is located includes a sawtooth shape. For example, Fig.30 As shown, the second type of common lines 32 include a plurality of first sub-common lines 3201 and a plurality of second sub-common lines 3202. The first sub-common lines 3201 extend along a first direction h1, and the second sub-common lines 3202 extend along a second direction h2. The first sub-common lines 3201 and the second sub-common lines 3202 are cross-connected and electrically connected. The first sub-common lines 3201 and the second sub-common lines 3202 are both located between the display area AA and the light transmission area TA. Fig.30 As shown, the adjacent first sub-common line 3201 and the first sub-common line 3101 are electrically connected, and there is no gap between them. The adjacent first sub-common line 3201 and the first sub-connection line 2101 are arranged at intervals.

[0172] For example, Fig.31 As shown, Fig.31 for Figure 1 An enlarged schematic diagram of the middle area Q7, the common line also includes a third type of common line 33, and the third type of common line 33 is located on the side of the edge connection line away from the light-transmitting area TA. The provision of the third type of common line 33 can further increase the conduction path of the common voltage in the area away from the pad area BA, which is beneficial to improve the display consistency in different areas of the display area AA. Moreover, the embodiment of the present invention reduces the wiring difficulty of the third type of common line 33 by making the third type of common line 33 located on the side of the edge connection line away from the light-transmitting area TA, that is, the first type of connection line 21 is not provided at the position of the third type of common line 33, which is beneficial to improve the yield of the display panel.

[0173] Exemplarily, the third-type common line 33 includes a first sub-common line 3301 extending along the first direction h1 and / or a second sub-common line 3302 extending along the second direction h2. Fig.31 As an example, the third-type common line 33 includes a first sub-common line 3301 extending along the first direction h1 and a second sub-common line 3302 extending along the second direction h2.

[0174] Exemplarily, the third type common line 33 may be electrically connected to a portion of the first type common lines 31. The third type common line 33 does not cross the edge connection line.

[0175] For example, Figure 1 As shown, the display area AA includes a first area Q81 and a second area Q82 located between the light-transmitting area TA and the binding area BA, the distance between the first area Q81 and the binding area BA is greater than the distance between the second area Q82 and the binding area BA, the first area Q81 includes a third type of common line 33, and the second area Q82 may not be provided with a third type of common line.

[0176] Illustratively, an embodiment of the present invention can arrange the first sub-common line 3101 in the first type of common line 31 and the first sub-common line 3301 in the third type of common line 33 on the same layer, and arrange the second sub-common line 3102 in the first type of common line 31 and the second sub-common line 3302 in the third type of common line 33 on the same layer, so as to simplify the manufacturing process of the display panel and reduce the number of film layers in the display panel.

[0177] Optional, such as Figure 3 As shown, the first sub-common line 3101 and the second sub-common line 3102 in the first type common line 31 are electrically connected through the first connection hole 71 ; the first connection hole 71 penetrates the insulating layer between the first sub-common line 3101 and the second sub-common line 3102 .

[0178] like Fig.31 As shown, the first sub-common line 3301 and the second sub-common line 3302 in the third type common line 33 are electrically connected through the second connection hole 72 ; the second connection hole 72 penetrates the insulating layer between the first sub-common line 3301 and the second sub-common line 3302 .

[0179] Exemplarily, when the first sub common line 3101 and the first sub common line 3301 are located in the fourth metal layer M4 and the second sub common line 3102 and the second sub common line 3302 are located in the fifth metal layer M5, the first connection hole 71 and the second connection hole 72 penetrate the fifth insulating layer IS5.

[0180] In the embodiment of the present invention, the arrangement direction of at least some of the first connection holes 71 among the plurality of first connection holes 71 is parallel to the arrangement direction of at least some of the second connection holes 72 among the plurality of second connection holes 72; and / or, in the same direction, the distance between at least some of the adjacent two first connection holes 71 is the same as the distance between at least some of the adjacent two second connection holes 72. Figure 3 and Fig.31 As shown, in the embodiment of the present invention, at least a portion of the second connection holes 72 can be shifted to overlap with a portion of the first connection holes 71 , so as to improve the distribution uniformity of the connection holes at different positions in the display area AA.

[0181] The embodiment of the present invention further provides a display device, such as Fig.32 As shown, Fig.32 The following is a schematic diagram of a display device provided by an embodiment of the present invention, wherein the display device includes the above-mentioned display panel 1000. The specific structure of the display panel 1000 has been described in detail in the above-mentioned embodiment, and will not be repeated here. Fig.32 The display device shown is only for illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-book or a television. Optionally, the display device further includes a photosensitive element arranged corresponding to the light-transmitting area TA.

[0182] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: It comprises a display area and a light-transmitting area; the display area at least partially surrounds the light-transmitting area; The display area includes: A plurality of signal lines arranged along a first direction, wherein the signal lines extend along a second direction; the first direction and the second direction intersect; a plurality of connection lines, the connection lines being used to connect signal lines located on both sides of the light-transmitting area along the second direction; the connection lines comprising a plurality of first-type connection lines, at least part of the first-type connection lines being located in the display area; the first-type connection lines comprising edge connection lines, the edge connection lines being the first-type connection lines having the largest distance from the light-transmitting area among the first-type connection lines; Common lines, the common lines comprising first-type common lines, at least a portion of the first-type common lines being located in the display area; and a portion of the first-type common lines being located on a side of the edge connection line close to the light-transmitting area; The first type of common lines includes a first common line, and the first common line is insulated and crosses the edge connection line; The display area includes a first pixel driving circuit and a second pixel driving circuit which are adjacently arranged along the extending direction of the first common line, and the first pixel driving circuit and the second pixel driving circuit are both located on a side of the edge connection line close to the light-transmitting area; The first common line overlaps with the first pixel driving circuit; at least part of the first-type connecting lines that are parallel to the first common line overlaps with the second pixel driving circuit.

2. The display panel according to claim 1, characterized in that: The first type of common line includes a second common line; the second common line is insulated and crosses the edge connection line; The display area includes at least one first pixel driving circuit group, and the first pixel driving circuit group includes a plurality of pixel driving circuits arranged along the extension direction of the second common line; along a direction perpendicular to the plane where the display panel is located, the first pixel driving circuit group and the second common line overlap, and the first pixel driving circuit group and a portion of the first type of connecting line that is parallel to the second common line do not overlap.

3. The display panel according to claim 2, characterized in that: The plurality of first-category connection lines include at least a first connection line, a second connection line and a third connection line that are adjacently arranged, a portion of the second connection line that is parallel to the second common line is located between portions of the first connection line and the third connection line that are parallel to the second common line, and a distance between the second connection line and a portion of the first connection line that is parallel to the second common line is greater than a distance between the second connection line and a portion of the third connection line that is parallel to the second common line; the second common line is located between portions of the first connection line and the second connection line that are parallel to the second common line.

4. The display panel according to claim 3, characterized in that: The distance between the second common line and a portion of the first connecting line parallel to the second common line is greater than or equal to the distance between the second connecting line and a portion of the third connecting line parallel to the second common line; and / or, A distance between the second common line and a portion of the second connection line parallel to the second common line is greater than or equal to a distance between the second connection line and a portion of the third connection line parallel to the second common line.

5. The display panel according to claim 1, characterized in that: The display panel comprises at least two light-transmitting areas; The common lines further include a third common line, at least a portion of which is located between two adjacent light-transmitting areas.

6. The display panel according to claim 5, characterized in that: The display area includes a first sub-display area, the first sub-display area is located between two adjacent light-transmitting areas, the first sub-display area includes a pixel driving circuits arranged along the arrangement direction of the two adjacent light-transmitting areas, x first-type connecting lines arranged along the arrangement direction of the two adjacent light-transmitting areas, and y third common lines arranged along the arrangement direction of the two adjacent light-transmitting areas; wherein, x+y≤a; wherein the arrangement direction of the two adjacent light-transmitting areas includes the first direction or the second direction.

7. The display panel according to claim 5, characterized in that: Also comprising a first non-display area, wherein the first non-display area partially surrounds the display area; The light-transmitting area adjacent to the first non-display area comprises a first end and a second end, the first end is located at a side of the light-transmitting area close to another light-transmitting area, and the second end is located at a side of the light-transmitting area close to the first non-display area; The signal line includes a first signal line; the distance between the first signal line and the first end is smaller than the distance between the first signal line and the second end; the part of the first type connection line electrically connected to the first signal line is located between the second end and the first non-display area.

8. The display panel according to claim 1, characterized in that: The first type of connecting wires at least includes a fourth connecting wire and a fifth connecting wire, and the light-transmitting area is located between the fourth connecting wire and the fifth connecting wire; The first-type common line further includes a fourth common line, and the fourth common line is located between the fourth connection line and the fifth connection line.

9. The display panel according to claim 1, characterized in that: The light-transmitting area includes at least two sub-light-transmitting areas; The display panel comprises a second non-display area located between two adjacent sub-light-transmitting areas; The first type of common lines includes a fifth common line, and at least a portion of the fifth common line is located in the second non-display area.

10. The display panel according to claim 9, characterized in that: A portion of the fifth common line extends from the display area to the second non-display area.

11. The display panel according to claim 10, characterized in that: Another portion of the fifth common line ends at an edge of the second non-display area.

12. The display panel according to claim 11, characterized in that: The display panel includes a plurality of sub-pixels, each of which includes a pixel driving circuit and a light-emitting element that are electrically connected; In the second non-display area, the fifth common line extending from the display area to the second non-display area and the fifth common line ending at the edge of the second non-display area are in the same layer and adjacent, and the distance between the two is less than or equal to the width of one pixel driving circuit.

13. The display panel according to claim 9, characterized in that: The second non-display area includes a virtual pixel, and along a direction perpendicular to a plane where the display panel is located, the virtual pixel and the fifth common line partially overlap.

14. The display panel according to claim 13, characterized in that: The display panel includes a plurality of sub-pixels, each of which includes a pixel driving circuit, a connecting electrode and a light-emitting element; the pixel driving circuit is electrically connected to the light-emitting element through the connecting electrode; and the virtual pixel does not include a connecting electrode; At least a portion of the fifth common line is disposed in the same layer as the connection electrode.

15. The display panel according to claim 13, characterized in that: The display panel includes a plurality of sub-pixels, each of which includes a light-emitting element; the virtual pixel does not include a light-emitting element; and at least a portion of the fifth common line is disposed in the same layer as an electrode of the light-emitting element in the sub-pixel.

16. The display panel according to claim 9, characterized in that: The connection lines further include second-type connection lines, which are located at a side of the second non-display area close to the sub-light-transmitting area, and the second-type connection lines partially surround the sub-light-transmitting area.

17. The display panel according to claim 1, characterized in that: The display panel includes a first non-display area, wherein the first non-display area at least partially surrounds the display area; The first non-display area includes a common bus, and the common bus is electrically connected to a plurality of the first-type common lines.

18. The display panel according to claim 17, characterized in that: Part of the first-type connecting lines and part of the first-type common lines are both located in the first non-display area; in the first non-display area, along a direction perpendicular to the plane where the display panel is located, the first-type common lines and the first-type connecting lines partially overlap.

19. The display panel according to claim 1, characterized in that: The first type of connection wires include first sub-connection wires and second sub-connection wires that are electrically connected to each other; The first type of common lines include a first sub-common line and a second sub-common line that are electrically connected to each other; The first sub-connection line and the first sub-common line are parallel to each other and arranged in the same layer; The second sub-connecting line and the second sub-common line are parallel to each other and are arranged in the same layer.

20. The display panel according to claim 1, characterized in that: The display panel further includes a second type of common lines, which are located on a side of the light-transmitting area close to the display area and at least partially surround the light-transmitting area; and the second type of common lines are electrically connected to the first type of common lines.

21. The display panel according to claim 20, characterized in that: The second type of common line and the first type of common line electrically connected thereto are arranged in the same layer; or, Along a direction perpendicular to the plane where the display panel is located, an insulating layer is included between the second-type common line and the first-type common line, the insulating layer includes a through hole, and the second-type common line and the first-type common line are electrically connected through the through hole.

22. The display panel according to claim 20, characterized in that: The shape of the orthographic projection of the second-type common line on the plane where the display panel is located includes a sawtooth shape or a circular ring shape.

23. The display panel according to claim 1, characterized in that: The display panel includes a plurality of sub-pixels, each of which includes a pixel driving circuit and a light-emitting element that are electrically connected; The display panel further comprises a first power supply voltage line, a second power supply voltage line and a reference voltage line electrically connected to the pixel driving circuit; the first power supply voltage line is used to transmit a first power supply voltage, the second power supply voltage line is used to transmit a second power supply voltage, and the reference voltage line is used to transmit a reference voltage; The signal transmitted by the common line includes any one of a first power supply voltage, a second power supply voltage, and a reference voltage.

24. The display panel according to claim 1, characterized in that: The common lines further include a third type of common lines, and a portion of the third type of common lines is located on a side of the edge connection line away from the light-transmitting area.

25. The display panel according to claim 24, characterized in that: The common line includes a first sub-common line and a second sub-common line that are electrically connected to each other; The first sub-common line and the second sub-common line in the first type of common line are electrically connected through a first connection hole; The first sub-common line and the second sub-common line in the third type of common lines are electrically connected through a second connecting hole; An arrangement direction of the plurality of first connection holes is parallel to an arrangement direction of the plurality of second connection holes; And / or, in the same direction, the distance between two adjacent first connection holes is the same as the distance between two adjacent second connection holes.

26. The display panel according to claim 1, characterized in that: The signal line includes a data line; The first type of connection wires include first sub-connection wires and second sub-connection wires that are electrically connected to each other; The extension directions of the second sub-connection line and the data line are parallel to each other, and the second sub-connection line and the data line are arranged in the same layer.

27. The display panel according to claim 26, characterized in that: The display area includes a plurality of sub-pixels, each of which includes a pixel driving circuit and a light-emitting element electrically connected to each other; the pixel driving circuit includes a driving transistor, and the driving transistor is electrically connected to the first node; The display panel further includes a first shielding layer, and along a direction perpendicular to a plane where the display panel is located, the first shielding layer at least partially overlaps with the first node.

28. The display panel according to claim 27, characterized in that: The first shielding layer and the first sub-connection line are arranged on the same layer.

29. A display device, characterized in that: A display panel comprising any one of claims 1-28.

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