Multilayer Ceramic Capacitors

Abstract

The present invention provides an LW inverted type laminated ceramic capacitor capable of suppressing the occurrence of short circuit failure. A laminated ceramic capacitor (1), wherein a laminate (10) is in a dimensional relationship of w dimension in the width direction > l dimension in the length direction > t dimension in the height direction, a width length (W1) of a third face (40A3) of a first external electrode (40A) is smaller than a width length (W2) of a first face (40A1), a width length (W1) of an eighth face (40B3) of a second external electrode (40B) is smaller than a width length (W2) of a sixth face (40B1), a height length (T1) of a fourth face (40A4) and a fifth face (40A5) of the first external electrode (40A) is smaller than a height length (T2) of the first face, and a height length of a ninth face (40B4) and a tenth face (40B5) of the second external electrode is smaller than a height length of the sixth face.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, multilayer ceramic capacitors are known. A typical multilayer ceramic capacitor comprises a generally rectangular parallelepiped-shaped stacked body whose dimension in the longitudinal direction L is longer than its dimension in the width direction W, and external electrodes are provided at both ends of the stacked body in the longitudinal direction L. On the other hand, so-called LW inverted-type multilayer ceramic capacitors are also known, in which the relationship between the dimensions in the longitudinal direction L and the dimensions in the width direction W of the stacked body is reversed to reduce ESL (see Patent Documents 1 and 2).

[0003] Furthermore, in recent years, as substrate mounting density has increased, the mounting area of ​​multilayer ceramic capacitors has decreased. Consequently, demand is growing for multilayer ceramic capacitors that are mounted at the bottom edge of a substrate using the PoP (Package on Package) mounting method and the LSC (Land Side Capacitor) type. These LSC (Land Side Capacitor)-type multilayer ceramic capacitors are required to be thinner and shorter in height.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2020-57753

[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 2020-61524

[0008] Patent document 2 discloses the following LW inverted type stacked ceramic electronic component, that is, a recessed portion that is recessed from the end edge toward the first face portion is provided at the end edge of at least one of the fourth face portion and the fifth face portion of the external electrode, and the two side portions of the recess in the third direction serve as covering portions that cover the ridges of the two faces in the second direction of the component body.

[0009] However, the multilayer ceramic electronic component disclosed in Patent Document 2 is believed to have the following problem: the area and shape of the covering portion covering the edges of the two surfaces in the second direction of the component body may vary due to variations in the formation position and thickness of the base conductor layer and the covering conductor layer provided thereon. Therefore, when using solder to mount an LW-inverted multilayer ceramic electronic component on a mounting substrate, there is a possibility that the left-right differences in the area and shape of the covering portion will cause the solder to wet the covering portion differently on each surface, resulting in differences in the way the solder applies tensile stress. This is believed to reduce the self-alignment effect. As a result, there is a concern that the multilayer ceramic electronic component may be prone to rotation or tilting, resulting in reduced mountability. Furthermore, the short distance between the lands on the substrate on which the LW-inverted multilayer ceramic electronic component is mounted reduces the self-alignment effect. If the multilayer ceramic electronic component is rotated significantly, there is a possibility that an external electrode may be mounted so that it straddles lands with different polarity, causing a short circuit. Summary of the Invention

[0010] Problems to be solved by the invention

[0011] An object of the present invention is to provide an LW inversion type multilayer ceramic capacitor capable of suppressing the occurrence of short-circuit failures.

[0012] Technical solutions to solve problems

[0013] The multilayer ceramic capacitor according to the present invention comprises: a multilayer body having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the multilayer body having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface. The second external electrode has at least one of a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, and an eighth face portion located on a portion of the second main surface, a ninth face portion located on a portion of the first side surface, and a tenth face portion located on a portion of the second side surface. In the multilayer ceramic capacitor, the first end surface and the second end surface of the multilayer body are connected in the longitudinal direction. The length of is set to l, the length in the width direction connecting the first side surface and the second side surface is set to w, and the length in the height direction connecting the first main surface and the second main surface is set to t. At this time, the size relationship is w>l>t. When the first external electrode has the second face portion, the length in the width direction of the second face portion is smaller than the length in the width direction of the first face portion. When the first external electrode has the third face portion, the length in the width direction of the third face portion is smaller than the length in the width direction of the first face portion. When the second external electrode has the seventh face portion, the length in the width direction of the seventh face portion is smaller than the length in the width direction of the sixth face portion. When the second external electrode has the eighth face portion, the length in the width direction of the eighth face portion is smaller than the length in the width direction of the sixth face portion. The lengths in the height direction of the fourth face portion and the fifth face portion of the first external electrode are smaller than the length in the height direction of the first face portion. The lengths in the height direction of the ninth face portion and the tenth face portion of the second external electrode are smaller than the length in the height direction of the sixth face portion.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to provide an LW inversion type multilayer ceramic capacitor capable of suppressing the occurrence of short-circuit failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment.

[0017] Figure 2 Yes Figure 1 The illustrated multilayer ceramic capacitor is an arrow view when viewed from the first side surface along the direction of arrow II.

[0018] Figure 3 Yes Figure 1 The illustrated multilayer ceramic capacitor is an arrow view when viewed from the second side surface along the direction of arrow III.

[0019] Figure 4 Yes Figure 2 The illustrated multilayer ceramic capacitor is a view of the first main surface side as viewed in the direction of arrow IV.

[0020] Figure 5 Yes Figure 2 The illustrated multilayer ceramic capacitor is a view of the second main surface side viewed in the direction of arrow V.

[0021] Figure 6 yes Figure 4 A cross-sectional view of the multilayer ceramic capacitor taken along line VI-VI is shown.

[0022] Figure 7 yes Figure 6 A cross-sectional view of the multilayer ceramic capacitor taken along line VII-VII is shown.

[0023] Figure 8A yes Figure 6 The cross-sectional view taken along line VIIIA-VIIIA of the multilayer ceramic capacitor shown shows the first internal electrode layer.

[0024] Figure 8B yes Figure 6 The cross-sectional view of the multilayer ceramic capacitor taken along line VIIIB-VIIIB shows the second internal electrode layer.

[0025] Figure 9 yes Figure 4 The cross-sectional view of the multilayer ceramic capacitor shown along line IX-IX shows a first side surface of the multilayer body.

[0026] Figure 10A yes Figure 6 The enlarged view of the XA portion in FIG. 1 is a view showing a cross section of the first external electrode.

[0027] Figure 10B yes Figure 6 The enlarged view of the XB portion in FIG. 1 is a diagram showing a cross section of the second external electrode.

[0028] Figure 11Ais a cross-sectional view showing a modified example of the layer structure of the external electrodes of the multilayer ceramic capacitor according to the above embodiment, Figure 10A The corresponding figure.

[0029] Figure 11B is a cross-sectional view showing a modified example of the layer structure of the external electrodes of the multilayer ceramic capacitor according to the above embodiment, Figure 10B The corresponding figure.

[0030] Figure 12 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above embodiment.

[0031] Figure 13 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above embodiment.

[0032] Figure 14 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above embodiment.

[0033] Figure 15A This is a perspective view showing a first modified example of the shape of the external electrodes of the multilayer ceramic capacitor according to the above embodiment. Figure 1 The corresponding figure.

[0034] Figure 15B This is a perspective view showing a second modified example of the shape of the external electrodes of the multilayer ceramic capacitor according to the above embodiment. Figure 1 The corresponding figure.

[0035] Figure 15C This is a perspective view of the appearance of the second modified example as viewed from another angle.

[0036] Figure 15D This is a perspective view showing the appearance of a third modified example of the shape of the external electrodes of the multilayer ceramic capacitor according to the above embodiment. Figure 15B The corresponding figure.

[0037] Figure 16A This is a perspective view of the appearance of the multilayer ceramic capacitor of Comparative Example 1. Figure 1 The corresponding figure.

[0038] Figure 16B is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8A The corresponding figure.

[0039] Figure 16C is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8B The corresponding figure.

[0040] Figure 17AThis is a perspective view of the appearance of the multilayer ceramic capacitor of Comparative Example 2. Figure 1 The corresponding figure.

[0041] Figure 17B is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8A The corresponding figure.

[0042] Figure 17C is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8B The corresponding figure.

[0043] Figure 18A It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0044] Figure 18B It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0045] Figure 18C It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0046] Figure 18D It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0047] Description of Reference Numerals

[0048] 1: Multilayer ceramic capacitor;

[0049] 10: Laminated body

[0050] 11: inner layer;

[0051] 12: outer layer portion on the first main surface side;

[0052] 13: outer layer portion on the second main surface side;

[0053] LS1: 1st end face;

[0054] LS2: 2nd end face;

[0055] WS1: side 1;

[0056] WS2: side 2;

[0057] TS1: 1st main surface;

[0058] TS2: 2nd main surface;

[0059] 1: Length in the longitudinal direction;

[0060] w: length in width direction;

[0061] t: length in height direction;

[0062] 20: dielectric layer;

[0063] 30: internal electrode layer;

[0064] 31: first internal electrode layer;

[0065] 31A: first counter electrode portion;

[0066] 31B: 1st lead-out portion;

[0067] 32: second internal electrode layer;

[0068] 32A: second opposing electrode portion;

[0069] 32B: second lead-out portion;

[0070] 40: external electrode;

[0071] 40A: 1st external electrode;

[0072] 40A1: facial part 1;

[0073] 40A2: second face;

[0074] 40A3: face 3;

[0075] 40A4: 4th face;

[0076] 40A5: face 5;

[0077] 40B: second external electrode;

[0078] 40B1: facial 6;

[0079] 40B2: facial 7;

[0080] 40B3: face 8;

[0081] 40B4: 9th face;

[0082] 40B5: 10th face;

[0083] 50A: first base electrode layer;

[0084] 51A: 1st film layer;

[0085] 50B: second base electrode layer;

[0086] 51B: second film layer;

[0087] 60A: 1st plating layer;

[0088] 60B: second plating layer;

[0089] L: length direction;

[0090] W: width direction;

[0091] T: stacking direction. DETAILED DESCRIPTION

[0092] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. Figure 1 1 is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 Yes Figure 1 The illustrated multilayer ceramic capacitor 1 is a view when the first side surface WS1 is viewed along the direction of arrow II. Figure 3 Yes Figure 1 The illustrated multilayer ceramic capacitor 1 is a view when viewed from the second side surface WS2 along the direction of arrow III. Figure 4 Yes Figure 2 The illustrated multilayer ceramic capacitor 1 is a view when the first main surface TS1 side is viewed along the direction of arrow IV. Figure 5 Yes Figure 2 The illustrated multilayer ceramic capacitor 1 is a view when viewed from the second main surface TS2 side along the direction of arrow V. Figure 6 yes Figure 4 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VI-VI. Figure 7 yes Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VII-VII. Figure 8A yes Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VIIIA-VIIIA. Figure 8B yes Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VIIIB-VIIIB. Figure 9 yes Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 taken along line IX-IX shows the first side surface WS1 of the multilayer body 10 . Figure 10A yes Figure 6 The enlarged view of the XA portion in FIG. 1 is a diagram showing a cross section of the first external electrode 40A. Figure 10B yes Figure 6 The enlarged view of the XB portion in FIG. 1 is a diagram showing a cross section of the second external electrode 40B.

[0093] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40 .

[0094] exist Figures 1 to 9The XYZ orthogonal coordinate system is shown. The length direction L of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Y direction. The width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the X direction. The height direction T of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Z direction. Here, Figure 6 The section shown is also referred to as the LT section. Figure 7 The cross section shown is also referred to as the WT cross section. Figure 8A as well as Figure 8B The cross section shown is also referred to as the LW cross section.

[0095] like Figures 1 to 5 As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W perpendicular to the height direction T and the length direction L.

[0096] The laminate 10 has a generally rectangular parallelepiped shape. The corners and ridges of the laminate 10 are preferably rounded. A corner is where three surfaces of the laminate 10 intersect, and a ridge is where two surfaces of the laminate 10 intersect. Furthermore, a portion or all of the surface constituting the laminate 10 may have irregularities.

[0097] like Figure 6 as well as Figure 7 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the height direction T so as to sandwich the inner layer portion 11 .

[0098] The inner portion 11 includes multiple dielectric layers 20 and multiple internal electrode layers 30. In the height direction T, the inner portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 through the internal electrode layer 30 located closest to the second main surface TS2. In the inner portion 11, the multiple internal electrode layers 30 are arranged so as to face each other with the dielectric layer 20 interposed therebetween. The inner portion 11 is the portion that generates electrostatic capacitance and essentially functions as a capacitor. The inner portion 11 is also referred to as the effective layer portion.

[0099] The plurality of dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, a ceramic material. For example, the dielectric material may be a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When these components are the main components, secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may be added in a smaller amount than the main component, depending on the desired properties of the laminate.

[0100] The thickness of dielectric layer 20 is preferably not less than 0.5 μm and not more than 10 μm. The number of dielectric layers 20 stacked is preferably not less than 15 and not more than 700. The number of dielectric layers 20 is the sum of the number of dielectric layers in inner layer portion 11 and the number of dielectric layers in first principal surface-side outer layer portion 12 and second principal surface-side outer layer portion 13.

[0101] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 are arranged on the plurality of dielectric layers 20 and extended to the first end surface LS1. The second internal electrode layers 32 are arranged on the plurality of dielectric layers 20 and extended to the second end surface LS2. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the height direction T of the laminate 10, with the dielectric layers 20 interposed therebetween. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layer 20.

[0102] like Figure 8A As shown, the first internal electrode layer 31 includes a first opposing electrode portion 31A opposing the second internal electrode layer 32 and a first lead portion 31B led from the first opposing electrode portion 31A to the first end surface LS1 , a portion of the first side surface WS1 , and a portion of the second side surface WS2 .

[0103] The first counter electrode portion 31A is located inside the laminate 10. The first lead portion 31B is connected to the first counter electrode portion 31A and is exposed at the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0104] like Figure 8B As shown, the second internal electrode layer 32 includes a second opposing electrode portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led from the second opposing electrode portion 32A to the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0105] The second counter electrode portion 32A is located inside the laminate 10. The second lead portion 32B is connected to the second counter electrode portion 32A and is exposed at the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0106] Figure 9 yes Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 along the line IX-IX is a diagram showing the first side surface WS1 of the multilayer body 10. Figure 8A as well as Figure 8B In the figure, it is also shown that Figure 9 The IX-IX line is located in the cross-sectional view. Figure 9As shown, the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32 are exposed on the first side surface WS1 of the laminate 10 .

[0107] Although not shown in the figure, similarly to the first side face WS1 , the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32 are exposed on the second side face WS2 .

[0108] This shortens the distance between the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32, thereby shortening the path for current flow and reducing ESL.

[0109] In the present embodiment, the first counter electrode portion 31A and the second counter electrode portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting capacitor characteristics.

[0110] The shapes of the first counter electrode portion 31A and the second counter electrode portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or inclined.

[0111] The shapes of the first lead portion 31B and the second lead portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or inclined.

[0112] The first lead portion 31B is larger in width direction W than the first counter electrode portion 31A. The second lead portion 32B is larger in width direction W than the second counter electrode portion 32A.

[0113] The dimensions of the first lead portion 31B and the second lead portion 32B in the longitudinal direction L of the portion exposed at a portion of the first side surface WS1 are preferably not less than 20 μm and not more than 280 μm. The dimensions of the first lead portion 31B and the second lead portion 32B in the longitudinal direction L of the portion exposed at a portion of the second side surface WS2 are preferably not less than 20 μm and not more than 280 μm.

[0114] Furthermore, the plurality of first internal electrode layers 31 may all have the same shape, but may also have some different shapes. For example, the plurality of first internal electrode layers 31 arranged near the center in the height direction T may have the following shape: Figure 8AThe shape shown in FIG. 1 is exposed on the first side surface WS1 and the second side surface WS2. On the other hand, a portion of the first internal electrode layer 31 disposed near the first main surface side outer layer portion 12 and near the second main surface side outer layer portion 13 is not exposed on the first side surface WS1 and the second side surface WS2. For example, the shape described later may be Figure 16B The internal electrode layer has the shape shown.

[0115] Furthermore, the plurality of second internal electrode layers 32 may all have the same shape, but may also have some different shapes. For example, the plurality of second internal electrode layers 32 arranged near the center in the height direction T may have the following shape: Figure 8B The shape shown in FIG. 1 is exposed on the first side surface WS1 and the second side surface WS2. On the other hand, a portion of the second internal electrode layer 32 disposed near the first main surface side outer layer portion 12 and near the second main surface side outer layer portion 13 is not exposed on the first side surface WS1 and the second side surface WS2. For example, the shape described later may be Figure 16C The internal electrode layer has the shape shown.

[0116] Thus, the range in the height direction T formed by the plurality of first lead portions 31B exposed at a portion of the first side surface WS1 (see FIG. 1 ) can be controlled. Figure 9 The range in the height direction T formed by the plurality of first lead portions 31B exposed at a portion of the second side surface WS2 can be adjusted. In addition, the range in the height direction T formed by the plurality of second lead portions 32B exposed at a portion of the first side surface WS1 (refer to Figure 9 As a result, the length T1 of each of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A described later in the height direction T and the length T1 of the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B in the height direction T can be adjusted.

[0117] The first internal electrode layer 31 and the second internal electrode layer 32 are formed of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be formed of, for example, an Ag-Pd alloy.

[0118] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm to 2.0 μm, for example. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 to 200.

[0119] The first principal surface-side outer layer portion 12 is located on the first principal surface TS1 side of the laminate 10. The first principal surface-side outer layer portion 12 is an aggregate of multiple dielectric layers 20 located between the first principal surface TS1 and the internal electrode layer 30 closest to the first principal surface TS1. Specifically, the first principal surface-side outer layer portion 12 is formed from the multiple dielectric layers 20 located between the first principal surface TS1 and the internal electrode layer 30 closest to the first principal surface TS1 among the multiple internal electrode layers 30. The dielectric layers 20 used in the first principal surface-side outer layer portion 12 may be the same as the dielectric layers 20 used in the internal layer portion 11.

[0120] The second principal surface-side outer layer portion 13 is located on the second principal surface TS2 side of the laminate 10. The second principal surface-side outer layer portion 13 is an aggregate of multiple dielectric layers 20 located between the second principal surface TS2 and the internal electrode layer 30 closest to the second principal surface TS2. Specifically, the second principal surface-side outer layer portion 13 is formed from the multiple dielectric layers 20 located between the second principal surface TS2 and the internal electrode layer 30 closest to the second principal surface TS2 among the multiple internal electrode layers 30. The dielectric layers 20 used in the second principal surface-side outer layer portion 13 may be the same as the dielectric layers 20 used in the internal layer portion 11.

[0121] As described above, the laminate 10 includes a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminate 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0122] Furthermore, the laminate 10 includes an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing electrode portion 31A of the first internal electrode layer 31 and the second opposing electrode portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E constitutes a portion of the inner layer portion 11. Figure 8A as well as Figure 8B The figures show the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also referred to as a capacitor effective portion.

[0123] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 located on the first end face LS1 side and a second end face side outer layer portion LG2 located on the second end face LS2 side. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 and the first lead portion 31B located between the opposing electrode portion 11E and the first end face LS1. That is, the first end face side outer layer portion LG1 is a collection of portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions 31B. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 and the second lead portion 32B located between the opposing electrode portion 11E and the second end face LS2. That is, the second end face side outer layer portion LG2 is a collection of portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of second lead portions 32B. In Figure 6 、 Figure 8A as well as Figure 8B The ranges of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the longitudinal direction L are shown. The first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are also referred to as L intervals or end intervals.

[0124] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 located on the first side WS1 side and a second side outer layer portion WG2 located on the second side WS2 side. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. That is, the first side outer layer portion WG1 is a collection of portions of the plurality of dielectric layers 20 on the first side WS1 side. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. That is, the second side outer layer portion WG2 is a collection of portions of the plurality of dielectric layers 20 on the second side WS2 side. In Figure 7 、 Figure 8A as well as Figure 8B The range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the first side outer layer portion WG1 and the second side outer layer portion WG2 are also referred to as W intervals or side intervals.

[0125] like Figures 6 to 8BAs shown, the length of the laminate 10 in the longitudinal direction L connecting the first end face LS1 and the second end face LS2 is set to 1, the length in the width direction W connecting the first side face WS1 and the second side face WS2 is set to w, and the length in the height direction T connecting the first main face TS1 and the second main face TS2 is set to t. In this case, the relationship between these dimensions is w>l>t. This increases the width of the lead portion at the end face of the internal electrode layer 30. Furthermore, the distance between the first external electrode 40A and the second external electrode 40B (described later) can be shortened, thereby reducing the ESL of the laminated ceramic capacitor 1.

[0126] The length l of the stack 10 in the longitudinal direction L connecting the first end face LS1 and the second end face LS2 is preferably greater than 0.05 mm and less than 0.7 mm. In addition, the length w of the stack 10 in the width direction W connecting the first side face WS1 and the second side face WS2 is preferably greater than 0.15 mm and less than 1.5 mm. In addition, the length t of the stack 10 in the height direction T connecting the first main surface TS1 and the second main surface TS2 is preferably less than 150 μm. Thus, high-density mounting can be performed. In addition, the length t of the stack 10 in the height direction T connecting the first main surface TS1 and the second main surface TS2 is preferably less than 100 μm, more preferably less than 50 μm. Thus, higher-density mounting can be performed.

[0127] In addition, each dimension of l, w, and t of the laminated body 10 was measured by the following method.

[0128] First, the w dimension of the laminated body 10 is measured. Specifically, the w dimension of the laminated body 10 is measured at the exact middle position in the longitudinal direction L of the laminated ceramic capacitor 1, that is, at the position L / 2 of the laminated ceramic capacitor 1, using a micrometer screw.

[0129] Next, the l dimension and t dimension of the laminate 10 are measured. First, the same laminated ceramic capacitor 1 as the laminated ceramic capacitor 1 whose w dimension has been measured is ground parallel to the LT surface until it reaches the middle position in the width direction W of the laminated ceramic capacitor 1, that is, until it reaches the W / 2 position of the laminated ceramic capacitor 1. Then, the LT cross section exposed by the grinding is observed under a microscope. The l dimension of the laminate 10 is measured under a microscope at the middle position in the height direction T of the laminate 10 in the LT cross section, that is, at the t / 2 position of the laminate 10. The t dimension of the laminate 10 is measured under a microscope at the middle position in the length direction L of the laminate 10 in the LT cross section, that is, at the l / 2 position of the laminate 10.

[0130] The external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side and a second external electrode 40B arranged on the second end surface LS2 side.

[0131] The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A of this embodiment includes a first surface portion 40A1 located on the first end surface LS1, a second surface portion 40A2 located partially on the first main surface TS1, a third surface portion 40A3 located partially on the second main surface TS2, a fourth surface portion 40A4 located partially on the first side surface WS1, and a fifth surface portion 40A5 located partially on the second side surface WS2. Furthermore, the first external electrode 40A preferably includes at least one of the second surface portion 40A2 located partially on the first main surface TS1 and the third surface portion 40A3 located partially on the second main surface TS2, the first surface portion 40A1 located on the first end surface LS1, the fourth surface portion 40A4 located partially on the first side surface WS1, and the fifth surface portion 40A5 located partially on the second side surface WS2.

[0132] The first surface portion 40A1 is a portion that covers the entire first end surface LS1 and is connected to the first internal electrode layer 31. Either the second surface portion 40A2 or the third surface portion 40A3 is a portion that is connected to a land on the mounting substrate.

[0133] The fourth surface portion 40A4 is a portion connected to the first lead portion 31B exposed on the first side surface WS1 . The fifth surface portion 40A5 is a portion connected to the first lead portion 31B exposed on the second side surface WS2 .

[0134] The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B of this embodiment includes a sixth surface portion 40B1 located on the second end surface LS2, a seventh surface portion 40B2 located partially on the first main surface TS1, an eighth surface portion 40B3 located partially on the second main surface TS2, a ninth surface portion 40B4 located partially on the first side surface WS1, and a tenth surface portion 40B5 located partially on the second side surface WS2. Furthermore, the second external electrode 40B preferably includes at least one of the seventh surface portion 40B2 located partially on the first main surface TS1 and the eighth surface portion 40B3 located partially on the second main surface TS2, the sixth surface portion 40B1 located on the second end surface LS2, the ninth surface portion 40B4 located partially on the first side surface WS1, and the tenth surface portion 40B5 located partially on the second side surface WS2.

[0135] The sixth surface portion 40B1 is a portion that covers the entire second end surface LS2 and is connected to the second internal electrode layer 32. Either the seventh surface portion 40B2 or the eighth surface portion 40B3 is a portion that is connected to a land on the mounting substrate.

[0136] The ninth surface portion 40B4 is a portion connected to the second lead portion 32B exposed on the first side surface WS1 . The tenth surface portion 40B5 is a portion connected to the second lead portion 32B exposed on the second side surface WS2 .

[0137] The length W1 of the second and third surface portions 40A2, 40A3 of the first external electrode 40A in the width direction W is shorter than the length W2 of the first surface portion 40A1 in the width direction W. In other words, at both ends of the second and third surface portions 40A2, 40A3 of the first external electrode 40A in the width direction W, portions are exposed where no external electrodes are formed and the surface of the multilayer body 10 is exposed. Furthermore, the length W1 of the second and third surface portions 40A2, 40A3 of the first external electrode 40A in the width direction W is preferably shorter than the dimension w of the multilayer body 10 in the width direction W. This makes it easier for solder to wet the center portion of the second and third surface portions 40A2, 40A3 when mounting the multilayer ceramic capacitor 1 on a mounting substrate, rather than wetting the entire surface of the first surface portion 40A1 of the first external electrode 40A. Consequently, soldering can be performed centered on the center portion of the multilayer ceramic capacitor 1 in the width direction W, thereby ensuring stable mounting of the multilayer ceramic capacitor 1. Furthermore, even when the multilayer ceramic capacitor 1 is significantly rotated on the land, the length W1 of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the width direction W is smaller than the dimension w in the width direction W of the laminate 10. This prevents the capacitor from being mounted so as to straddle lands of different polarities. Consequently, the occurrence of short circuits can be prevented.

[0138] The length W1 of each of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the width direction W is preferably 80% to 95% of the dimension w in the width direction W of the laminate 10 , for example.

[0139] Furthermore, the length L1 of each of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the longitudinal direction L is preferably not less than 20% and not more than 40% of the dimension L of the laminate 10 in the longitudinal direction L. This not only improves the stability of mounting on the mounting substrate, but also, even if the multilayer ceramic capacitor 1 is significantly rotated on the land, the length W1 of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the width direction W is less than the dimension w in the width direction W of the laminate 10, thereby preventing the capacitor from being mounted across lands of different polarities. As a result, short circuits can be prevented.

[0140] The length W1 of the seventh and eighth surface portions 40B2 and 40B3 of the second external electrode 40B in the width direction W is shorter than the length W2 of the sixth surface portion 40B1 in the width direction W. In other words, at both ends of the seventh and eighth surface portions 40B2 and 40B3 of the second external electrode 40B in the width direction W, portions are exposed where no external electrodes are formed and the surface of the multilayer body 10 is exposed. Furthermore, the length W1 of the seventh and eighth surface portions 40B2 and 40B3 of the second external electrode 40B in the width direction W is preferably shorter than the dimension w in the width direction W of the multilayer body 10. This makes it easier for the solder to wet the center portion of the seventh and eighth surface portions 40B2 and 40B3 when mounting the multilayer ceramic capacitor 1 on a mounting substrate, rather than wetting the entire surface of the sixth surface portion 40B1 of the second external electrode 40B. Consequently, soldering can be performed centered on the center portion of the multilayer ceramic capacitor 1 in the width direction W, thereby stabilizing the mounting performance of the multilayer ceramic capacitor 1. Furthermore, even when the multilayer ceramic capacitor 1 is significantly rotated on the land, the length W1 of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B in the width direction W is smaller than the dimension w in the width direction W of the laminate 10. This prevents the capacitor from being mounted so as to straddle lands of different polarities. Consequently, the occurrence of short circuits can be prevented.

[0141] The length W1 of each of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B in the width direction W is preferably 80% to 95% of the dimension w in the width direction W of the laminate 10 .

[0142] Furthermore, the length L1 of each of the seventh and eighth surface portions 40B2 and 40B3 of the second external electrode 40B in the longitudinal direction L is preferably not less than 20% and not more than 40% of the dimension L of the laminate 10 in the longitudinal direction L. This not only improves the stability of mounting on the mounting substrate, but also, even if the multilayer ceramic capacitor 1 is significantly rotated on the land, the length W1 of the seventh and eighth surface portions 40B2 and 40B3 in the width direction W is less than the dimension w in the width direction W of the laminate 10, thereby preventing the capacitor from being mounted across lands of different polarities. As a result, short circuits can be prevented.

[0143] The length T1 of the fourth and fifth surface portions 40A4, 40A5 of the first external electrode 40A in the height direction T is shorter than the length T2 of the first surface portion 40A1 in the height direction T. In other words, at both ends of the fourth and fifth surface portions 40A4, 40A5 of the first external electrode 40A in the height direction T, portions are exposed where no external electrodes are formed and the surface of the multilayer structure 10 is exposed. Furthermore, the length T1 of the fourth and fifth surface portions 40A4, 40A5 of the first external electrode 40A in the height direction T is preferably shorter than the dimension t in the height direction T of the multilayer structure 10. This prevents solder from wetting the first and second side surfaces WS1 and WS2 of the multilayer structure 10 (the fourth and fifth surface portions 40A4, 40A5 of the first external electrode 40A), thereby reducing stress applied in the rotational direction. Consequently, the self-alignment effect is enhanced, and the mounting performance of the multilayer ceramic capacitor 1 is stabilized. Consequently, the occurrence of short circuit defects can be prevented.

[0144] The length T1 of each of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the height direction T is preferably 40% to 80% of the dimension t in the height direction T of the laminate 10 , for example, and more preferably 60% to 80%.

[0145] The length L2 of each of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the longitudinal direction L is preferably 4% to 40% of one dimension of the laminate 10 in the longitudinal direction L, and more preferably 10% to 20%.

[0146] The length T1 of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the height direction T is shorter than the length T2 of the sixth surface portion 40B1 in the height direction T. In other words, at both ends of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the height direction T, portions are exposed where no external electrodes are formed and the surface of the multilayer structure 10 is exposed. Furthermore, the length T1 of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the height direction T is preferably shorter than the dimension t in the height direction T of the multilayer structure 10. This prevents solder from wetting the first and second side surfaces WS1 and WS2 of the multilayer structure 10 (the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B), thereby reducing stress applied in the rotational direction. Consequently, the self-alignment effect is enhanced, and the mounting performance of the multilayer ceramic capacitor 1 is stabilized. Consequently, the occurrence of short circuits can be prevented.

[0147] The length T1 of each of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the height direction T is preferably 40% to 80% of the dimension t in the height direction T of the laminate 10 , for example, and more preferably 60% to 80%.

[0148] The length L2 of each of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the longitudinal direction L is preferably, for example, 4% to 40% of the dimension 1 in the longitudinal direction L of the laminate 10 , and more preferably 10% to 20%.

[0149] The shapes of the second surface portion 40A2 and the third surface portion 40A3 and the seventh surface portion 40B2 and the eighth surface portion 40B3 are not particularly limited, but are preferably rectangular.

[0150] The shapes of the fourth surface portion 40A4, the fifth surface portion 40A5, the ninth surface portion 40B4, and the tenth surface portion 40B5 are not particularly limited, but are preferably rectangular.

[0151] The length W2 of the first surface portion 40A1 of the first external electrode 40A in the width direction W and the length T2 of the first surface portion 40A1 of the first external electrode 40A in the height direction T are measured using a microscope. Specifically, the length W2 of the first surface portion 40A1 of the first external electrode 40A in the width direction W is measured at a position halfway along the height direction T of the multilayer ceramic capacitor 1, and the length T2 of the first surface portion 40A1 of the first external electrode 40A in the height direction T is measured at a position halfway along the width direction W of the multilayer ceramic capacitor 1.

[0152] The length W1 of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the width direction W, and the length L1 of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the longitudinal direction L were measured using a microscope. Specifically, the length W1 of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the width direction W was measured at a position half the length L1 of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the longitudinal direction L, respectively. The length L1 of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the longitudinal direction L was measured at a position half the length L of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the longitudinal direction W of the multilayer ceramic capacitor 1.

[0153] The length T1 of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the height direction T and the length L2 of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the length direction L were measured using a microscope. Specifically, the length T1 of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the height direction T was measured at a position half the length L2 of the fourth surface portion 40A4 and the fifth surface portion 40A5 in the length direction L of the first external electrode 40A, respectively. The length L2 of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the length direction L was measured at a position half the length T1 of the fourth surface portion 40A4 and the fifth surface portion 40A5 in the height direction T of the first external electrode 40A.

[0154] The length W2 of the sixth surface portion 40B1 of the second external electrode 40B in the width direction W and the length T2 of the sixth surface portion 40B1 of the second external electrode 40B in the height direction T are measured using a microscope. Specifically, the length W2 of the sixth surface portion 40B1 of the second external electrode 40B in the width direction W is measured at a position halfway along the height direction T of the multilayer ceramic capacitor 1, and the length T2 of the sixth surface portion 40B1 of the second external electrode 40B in the height direction T is measured at a position halfway along the width direction W of the multilayer ceramic capacitor 1.

[0155] The length W1 of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B in the width direction W, and the length L1 of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B in the longitudinal direction L were measured using a microscope. Specifically, the length W1 of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B in the width direction W was measured at a position half the length L1 of the seventh surface portion 40B2 and the eighth surface portion 40B3 in the longitudinal direction L of the second external electrode 40B, respectively. The length L1 of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B in the longitudinal direction L was measured at a position half the length L of the multilayer ceramic capacitor 1 in the width direction W.

[0156] The length T1 of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the height direction T and the length L2 of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the length direction L were measured using a microscope. Specifically, the length T1 of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the height direction T was measured at a position half the length T1 of the ninth and tenth surface portions 40B4 and 40B5 in the length direction L of the second external electrode 40B, respectively. The length L2 of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the length direction L was measured at a position half the length T1 of the ninth and tenth surface portions 40B4 and 40B5 in the height direction T of the second external electrode 40B.

[0157] like Figure 10A As shown, the first external electrode 40A includes a first foundation electrode layer 50A and a first plating layer 60A disposed on the first foundation electrode layer 50A. The first foundation electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is disposed to cover the first foundation electrode layer 50A.

[0158] like Figure 10B As shown, the second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B. The second foundation electrode layer 50B is disposed on the surface of the laminate 10. The second plating layer 60B is disposed so as to cover the second foundation electrode layer 50B.

[0159] The first foundation electrode layer 50A and the second foundation electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0160] In this embodiment, the first foundation electrode layer 50A and the second foundation electrode layer 50B are thin film layers. The thin film layer is a layer in which metal particles are deposited.

[0161] When the first foundation electrode layer 50A and the second foundation electrode layer 50B are formed of thin film layers, they are preferably formed by a thin film forming method such as sputtering or vapor deposition. Here, a sputtering electrode formed by sputtering will be described.

[0162] In this embodiment, the first foundation electrode layer 50A is composed of a first thin film layer 51A formed by a sputtering electrode. The second foundation electrode layer 50B is composed of a second thin film layer 51B formed by a sputtering electrode. When the foundation electrode layers are formed by sputtering electrodes, the sputtering electrodes are preferably formed directly on the first main surface TS1 and the second main surface TS2 of the stacked body 10.

[0163] like Figure 6 、 Figure 10A As shown, the first thin film layer 51A formed by the sputtering electrode is arranged on a portion of the first end face LS1 side on the first main surface TS1 and a portion of the first end face LS1 side on the second main surface TS2. Specifically, the first thin film layer 51A is preferably arranged on the first main surface TS1, Figure 4 The first thin film layer 51A is preferably arranged on the second main surface TS2. Figure 5 The portion shown is covered by the first external electrode 40A.

[0164] Furthermore, the first thin film layer 51A is preferably disposed on a portion of the first main surface TS1 so as to extend continuously from the portion on the first main surface TS1 and slightly extend around a portion of the first end surface LS1. The first thin film layer 51A is preferably disposed on a portion of the second main surface TS2 so as to extend continuously from the portion on the second main surface TS2 and slightly extend around a portion of the first end surface LS1.

[0165] For example, as used in the description of the manufacturing process described later Figure 12 As shown in FIG, when a chamfered portion C such as a rounded corner is formed on the ridgeline portion of the laminate 10, the first thin film layer 51A is preferably disposed on a portion of the first main surface TS1 on the first end surface LS1 side and the chamfered portion C on the first end surface LS1 side that is continuous with the portion. The first thin film layer 51A is preferably disposed on a portion of the second main surface TS2 on the first end surface LS1 side and the chamfered portion C on the first end surface LS1 side that is continuous with the portion. In this manner, the thin film layer can be easily formed by a sputtering method or the like.

[0166] By using the above method, when forming the plating layer, it is possible to control the distance between the portion of the first thin film layer 51A disposed on the first end face LS1 and the internal electrode layer 30 exposed on the first end face LS1. Therefore, deposition of the plating layer is facilitated also on the surface of the laminate 10 between the portion of the first thin film layer 51A disposed on the first end face LS1 and the internal electrode layer 30 exposed on the first end face LS1.

[0167] like Figure 6 、 Figure 10B As shown, the second thin film layer 51B formed by the sputtering electrode is arranged on a portion of the first main surface TS1 on the second end surface LS2 side and a portion of the second main surface TS2 on the second end surface LS2 side. Specifically, the second thin film layer 51B is preferably arranged on the first main surface TS1, Figure 4 The second thin film layer 51B is preferably arranged on the second main surface TS2. Figure 5 The portion shown is covered by the second external electrode 40B.

[0168] Furthermore, the second thin film layer 51B is preferably disposed on a portion of the first main surface TS1, and is disposed so as to extend continuously from a portion of the first main surface TS1 and slightly extend around a portion of the second end surface LS2. The second thin film layer 51B is preferably disposed on a portion of the second main surface TS2, and is disposed so as to extend continuously from a portion of the second main surface TS2 and slightly extend around a portion of the second end surface LS2.

[0169] For example, as used in the description of the manufacturing process described later Figure 12 As shown in FIG, when a chamfered portion C such as a rounded corner is formed on the ridgeline portion of the laminate 10, the second thin film layer 51B is preferably disposed on a portion of the first main surface TS1 on the second end surface LS2 side and the chamfered portion C on the second end surface LS2 side that is continuous with the portion. The second thin film layer 51B is preferably disposed on a portion of the second main surface TS2 on the second end surface LS2 side and the chamfered portion C on the second end surface LS2 side that is continuous with the portion. In this manner, the thin film layer can be easily formed by a sputtering method or the like.

[0170] By using the above method, when forming the plating layer, the distance between the portion of the second thin film layer 51B disposed on the second end surface LS2 and the internal electrode layer 30 exposed on the second end surface LS2 can be controlled. Therefore, deposition of the plating layer is facilitated also on the surface of the laminate 10 between the portion of the second thin film layer 51B disposed on the second end surface LS2 and the internal electrode layer 30 exposed on the second end surface LS2.

[0171] The thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This can improve the adhesion of the external electrode 40 to the stacked body 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a Ni-Cr alloy layer and a Ni-Cu alloy layer.

[0172] The thickness of the sputtering electrode in the stacking direction connecting the first main surface TS1 and the second main surface TS2 is preferably 50 nm to 400 nm, and more preferably 50 nm to 130 nm.

[0173] When a sputtering electrode is directly formed on the first main surface TS1 and the second main surface TS2 of the stacked body 10 to configure a base electrode layer, it is preferred to form a base electrode layer as a sintered layer on the first end surface LS1 and the second end surface LS2, or to directly form a plating layer (described later) without forming a base electrode layer. In this embodiment, a plating layer (described later) is directly formed on the first end surface LS1 and the second end surface LS2 without forming a base electrode layer.

[0174] In addition, as described later in a modified example, the first base electrode layer 50A and the second base electrode layer 50B may also be sintered layers. The sintered layers preferably contain a metal component, a glass component, or a ceramic component, or both. The metal component may, for example, contain at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component may, for example, contain at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material may be used. The ceramic component may, for example, contain at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0175] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and metal to the laminate 10 and sintering it. The sintered layer can be a sintered layer obtained by simultaneously sintering the laminated small pieces having internal electrode layers and dielectric layers and the conductive paste applied to the laminated small pieces. Alternatively, the sintered layer can be a sintered layer obtained by sintering the laminated small pieces having internal electrode layers and dielectric layers to obtain the laminate 10 and then applying a conductive paste to the laminate 10 and sintering it. In addition, when the laminated small pieces having internal electrode layers and dielectric layers and the conductive paste applied to the laminated small pieces are sintered simultaneously, the sintered layer is preferably formed by sintering a material to which a ceramic material has been added instead of a glass component. In this case, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20 as the added ceramic material. The sintered layer can also be a plurality of layers.

[0176] Alternatively, a configuration may be adopted in which the first and second base electrode layers 50A and 50B are not provided, and the first and second plating layers 60A and 60B described later are directly disposed on the laminate 10 .

[0177] The first plating layer 60A is arranged to cover the first foundation electrode layer 50A.

[0178] The second plating layer 60B is arranged to cover the second foundation electrode layer 50B.

[0179] The first plating layer 60A and the second plating layer 60B may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of a plurality of layers.

[0180] When the base electrode layer is formed of a thin film layer, the plating layer preferably has a three-layer structure comprising a Cu plating layer as a lower plating layer, a Ni plating layer as a middle plating layer, and a Sn plating layer as an upper plating layer. Specifically, the first plating layer 60A preferably comprises a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. The second plating layer 60B preferably comprises a second Cu plating layer 61B, a second Ni plating layer 62B, and a second Sn plating layer 63B. However, the first plating layer 60A and the second plating layer 60B are not limited to a three-layer structure and may also have other layer structures.

[0181] The first Cu plating layer 61A is arranged to cover the first end surface LS1 of the stack 10 and the first thin film layer 51A serving as the first base electrode layer 50A arranged on the first main surface TS1 and the second main surface TS2 of the stack 10. In this embodiment, the first Cu plating layer 61A is arranged to also cover the portions of the first side surface WS1 and the second side surface WS2 of the stack 10 where the internal electrode layers 30 are exposed. In this case, the gaps between the first thin film layer 51A and the internal electrode layers 30 exposed on the first end surface LS1 of the stack 10, as well as the gaps between the multiple internal electrode layers 30 exposed on the surface of the stack 10, are narrowed, so plating layers are also deposited in these gaps.

[0182] The first Ni plating layer 62A is arranged to cover the first Cu plating layer 61A. The first Sn plating layer 63A is arranged to cover the first Ni plating layer 62A. In the present embodiment, the first plating layer 60A is directly electrically connected to the first internal electrode layer 31 .

[0183] The second Cu plating layer 61B is arranged to cover the second end surface LS2 of the stack 10 and the second thin film layer 51B serving as the second base electrode layer 50B arranged on the first and second main surfaces TS1 and TS2 of the stack 10. In this embodiment, the second Cu plating layer 61B is arranged to also cover the portions of the first and second side surfaces WS1 and WS2 of the stack 10 where the internal electrode layers 30 are exposed. In this case, the gaps between the second thin film layer 51B and the internal electrode layers 30 exposed on the second end surface LS2 of the stack 10, as well as the gaps between the multiple internal electrode layers 30 exposed on the surface of the stack 10, are narrowed, and therefore, plating layers are also deposited in these gaps.

[0184] The second Ni plating layer 62B is arranged to cover the second Cu plating layer 61B. The second Sn plating layer 63B is arranged to cover the second Ni plating layer 62B. In the present embodiment, the second plating layer 60B is directly electrically connected to the second internal electrode layer 32 .

[0185] By providing a plating layer composed of a Cu plating layer and a Ni plating layer to cover the base electrode layer, the base electrode layer is prevented from being corroded by solder when mounting the multilayer ceramic capacitor 1. Furthermore, by further providing a Sn plating layer on the surface of the Ni plating layer, the wettability of the solder when mounting the multilayer ceramic capacitor 1 is improved. This facilitates mounting of the multilayer ceramic capacitor 1.

[0186] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of the first Cu plating layer 61A, the first Ni plating layer 62A, the first Sn plating layer 63A, the second Cu plating layer 61B, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of the first Cu plating layer 61A and the second Cu plating layer 61B is more preferably 5 μm or more and 8 μm or less. Furthermore, the average thickness of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0187] Furthermore, if the lengthwise dimension of the laminated ceramic capacitor 1, which includes the laminate 10 and the external electrode 40, connecting the first end surface LS1 and the second end surface LS2 is defined as the L dimension, the L dimension is preferably 0.1 mm or more and 0.8 mm or less. Furthermore, if the widthwise dimension of the laminated ceramic capacitor 1 connecting the first side surface WS1 and the second side surface WS2 is defined as the W dimension, the W dimension is preferably 0.2 mm or more and 1.6 mm or less. Furthermore, if the heightwise dimension of the laminated ceramic capacitor 1 connecting the first main surface TS1 and the second main surface TS2 is defined as the T dimension, the T dimension is preferably 0.05 mm or more and 0.2 mm or less. The lengthwise L dimension of the laminated ceramic capacitor 1 in this embodiment is smaller than the widthwise W dimension of the laminated ceramic capacitor 1. Furthermore, in this embodiment, the heightwise dimension of the laminated ceramic capacitor 1 connecting the first main surface TS1 and the second main surface TS2 corresponds to the stacking direction of the dielectric layers 20 and the internal electrode layers 30.

[0188] According to this embodiment, it is possible to suppress solder wetting on the first side WS1 and second side WS2 of the stack 10 (the fourth surface 40A4, the fifth surface 40A5, the ninth surface 40B4, and the tenth surface 40B5 of the external electrode 40). This is because, at the ridges of the first side WS1 and the second side WS2 of the stack 10, there are portions where no external electrodes are formed, exposing the surface of the stack 10. By suppressing solder wetting on the first side WS1 and the second side WS2 of the stack 10 (the fourth surface 40A4, the fifth surface 40A5, the ninth surface 40B4, and the tenth surface 40B5 of the external electrode 40), it is possible to suppress stress applied in the rotational direction. Consequently, the self-alignment effect is enhanced, and the mountability of the multilayer ceramic capacitor 1 is stabilized. As a result, it is possible to prevent the occurrence of short circuit defects and the like. The so-called self-alignment effect refers to the effect that, during soldering, a force acts on the molten solder, reducing its surface area—that is, surface tension. This causes the electronic component being mounted, supported by the molten solder, to move and position itself. This self-alignment effect prevents positional shifting during mounting.

[0189] Hereinafter, a modification of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 according to this embodiment will be described. In the following description, the same reference numerals are assigned to the same structures as those in the above embodiment, and detailed descriptions thereof will be omitted. Figure 11A as well as Figure 11B This is a cross-sectional view showing a modified example of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 10A as well as Figure 10B The corresponding figure.

[0190] In this modification, the structure of the external electrode 40 is different from that of the above-described embodiment.

[0191] The first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A. The first base electrode layer 50A of this modification is composed of a first sintered layer 52A. The first plating layer 60A of this modification includes a first Ni plating layer 62A and a first Sn plating layer 63A.

[0192] The second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B. The second foundation electrode layer 50B of this modification example is composed of a second sintered layer 52B. The second plating layer 60B of this modification example includes a second Ni plating layer 62B and a second Sn plating layer 63B.

[0193] In this modification, the first base electrode layer 50A, for example, similarly to the first external electrode 40A described above, includes a first face portion located on the first end surface LS1, a second face portion located partially on the first main surface TS1, a third face portion located partially on the second main surface TS2, a fourth face portion located partially on the first side surface WS1, and a fifth face portion located partially on the second side surface WS2. Furthermore, in this modification, the first base electrode layer 50A is connected to the first internal electrode layer 31.

[0194] The first Ni plating layer 62A is arranged to cover the first foundation electrode layer 50A. The first Sn plating layer 63A is arranged to cover the first Ni plating layer 62A.

[0195] In this modification, the second base electrode layer 50B, similar to the second external electrode 40B described above, includes a sixth surface portion located on the second end surface LS2, a seventh surface portion located partially on the first main surface TS1, an eighth surface portion located partially on the second main surface TS2, a ninth surface portion located partially on the first side surface WS1, and a tenth surface portion located partially on the second side surface WS2. Furthermore, in this modification, the second base electrode layer 50B is connected to the second internal electrode layer 32.

[0196] The second Ni plating layer 62B is arranged to cover the second foundation electrode layer 50B. The second Sn plating layer 63B is arranged to cover the second Ni plating layer 62B.

[0197] The first sintered layer 52A constituting the first base electrode layer 50A and the second sintered layer 52B constituting the second base electrode layer 50B may be, for example, sintered layers formed by applying a conductive paste containing glass and metal to the laminate and then sintering it. Furthermore, when the pre-sintered laminated pieces and the conductive paste applied to the laminated pieces are simultaneously fired, the sintered layers are preferably formed by sintering a material to which a ceramic material has been added in place of the glass component. In this case, the added ceramic material is preferably the same type of ceramic material as that used in the dielectric layer 20.

[0198] When the base electrode layer is formed of a sintered layer, the first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. In this case, the Ni plating layer prevents the base electrode layer from being corroded by the solder during assembly of the multilayer ceramic capacitor 1. Furthermore, the Sn plating layer improves the wettability of the solder during assembly of the multilayer ceramic capacitor 1, thereby facilitating assembly of the multilayer ceramic capacitor 1.

[0199] Furthermore, the first plating layer 60A and the second plating layer 60B are not limited to a two-layer structure, and may be formed of a three-layer structure including Cu plating as in the above embodiment, or may have other layer structures.

[0200] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. Specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0201] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described.

[0202] A dielectric sheet for dielectric layer 20 and a conductive paste for internal electrode layer 30 are prepared. The conductive paste for the dielectric sheet and internal electrode contains a binder and a solvent. The binder and solvent may be known binders and solvents. For example, the paste made of a conductive material may be a paste made by adding an organic binder and an organic solvent to metal powder.

[0203] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet by, for example, screen printing or gravure printing, using a printing plate designed with a pattern to form the shape of the internal electrode layer 30 of this embodiment. This prepares a dielectric sheet having a pattern formed on the first internal electrode layer 31 and a dielectric sheet having a pattern formed on the second internal electrode layer 32.

[0204] A predetermined number of dielectric sheets without internal electrode layer patterns printed thereon are stacked to form the portion that will become the first principal surface outer layer portion 12 on the first principal surface TS1 side. On this portion, dielectric sheets with patterns printed thereon for the first internal electrode layer 31 and dielectric sheets with patterns printed thereon for the second internal electrode layer 32 are alternately stacked to form the portion that will become the inner layer portion 11. A predetermined number of dielectric sheets without internal electrode layer patterns are stacked on this portion that will become the inner layer portion 11 to form the portion that will become the second principal surface outer layer portion 13 on the second principal surface TS2 side. In this manner, a laminated sheet is produced.

[0205] The laminated sheets are pressed in the lamination direction by isostatic pressing or the like, thereby producing a laminated block.

[0206] The stacked blocks are cut into predetermined sizes to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0207] The stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0208] In this embodiment, the base electrode layer is formed of a thin film layer. When the base electrode layer is formed of a thin film layer, the thin film layer is formed on the portion of the laminate 10 where the external electrode is to be formed, by applying a mask or the like. The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition. In this embodiment, a sputtering electrode serving as the thin film layer is formed by sputtering.

[0209] Figures 12 to 14 1 and 2 are views showing a midway state in the manufacturing process of the multilayer ceramic capacitor according to the present embodiment, and are views showing a state after the thin film layer is arranged on the laminate 10 and before the plating layer is arranged. Figure 12 The figure shows a state where the first thin film layer 51A and the second thin film layer 51B as thin film layers are arranged in the laminate 10. Figure 6 The LT section corresponds to the figure. Figure 13 This is a diagram showing a state in which the first thin film layer 51A as a thin film layer is arranged in the laminate 10. Figure 7 The WT cross section corresponds to FIG. Figure 14 This is a diagram showing a state in which the first thin film layer 51A and the second thin film layer 51B are arranged in the laminate 10. Figure 9 The corresponding figure shows the surface of the first side surface WS1 of the stacked body 10 .

[0210] The first thin film layer 51A formed by the sputtering electrode is arranged on a portion of the first end face LS1 side of the first main surface TS1 and a portion of the first end face LS1 side of the second main surface TS2. The second thin film layer 51B formed by the sputtering electrode is arranged on a portion of the second end face LS2 side of the first main surface TS1 and a portion of the second end face LS2 side of the second main surface TS2.

[0211] In this embodiment, a thin film layer formed by a sputtered electrode is disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and is arranged so as to continuously and slightly wrap around from a portion of the first main surface TS1 and a portion of the second main surface TS2 to a portion of the first end surface LS1 and a portion of the second end surface LS2. This makes it possible to control the distance between the thin film layer disposed so as to wrap around a portion of the first end surface LS1 and a portion of the second end surface LS2 and the internal electrode layer exposed on the first end surface LS1 and the second end surface LS2. Consequently, a plating layer can also be deposited on the surface of the laminate 10 between the thin film layer disposed so as to wrap around a portion of the first end surface LS1 and a portion of the second end surface LS2 and the internal electrode layer exposed on the first end surface LS1 and the second end surface LS2.

[0212] Then, a plating layer is formed on the surface of the base electrode layer and the laminate composed of the thin film layer. In this embodiment, three plating layers, namely, a Cu plating layer, a Ni plating layer, and a Sn plating layer, are formed as the plating layer.

[0213] When forming the plated layer, it is formed by electrolytic plating. As a plating process method, barrel plating is preferably used.

[0214] Furthermore, the plating layer is arranged to cover the portions of the first end face LS1 and the second end face LS2 of the stack 10 where the internal electrode layers are exposed. The plating layer is arranged to cover the portions of the first side face WS1 and the second side face WS2 of the stack 10 where the internal electrode layers are exposed. At this time, by narrowing the gaps between the thin film layer and the internal electrode layers exposed on the surface of the stack 10, and the gaps between the multiple internal electrode layers exposed on the surface of the stack 10, the plating layer is also deposited in the regions of these gaps.

[0215] In addition, when it is difficult to control the formation of the plating layer, the plating layer may be formed by providing a mask at a portion where the surface of the laminate 10 is exposed. This makes it easier to form a plating layer in a desired shape.

[0216] In the case where the base electrode layer is formed by a sintered layer, a conductive paste forming the first base electrode layer is applied to the first face portion located on the first end face LS1 of the stack 10, the second face portion located on a portion of the first main surface TS1, the third face portion located on a portion of the second main surface TS2, the fourth face portion located on a portion of the first side surface WS1, and the fifth face portion located on a portion of the second side surface WS2. Furthermore, on the second end face LS2 of the stack 10, a conductive paste forming the second base electrode layer is applied to the sixth face portion located on the second end face LS2 of the stack 10, the seventh face portion located on a portion of the first main surface TS1, the eighth face portion located on a portion of the second main surface TS2, the ninth face portion located on a portion of the first side surface WS1, and the tenth face portion located on a portion of the second side surface WS2.

[0217] In addition, masking is performed in advance on portions where the base electrode layer is not to be formed. After masking, a conductive paste containing a glass component and a metal is applied to the laminate 10 by methods such as dipping or screen printing. A sintering process is then performed to form the base electrode layer. The sintering process temperature is preferably between 700°C and 900°C.

[0218] Furthermore, when the pre-fired laminated pieces and the conductive paste applied to the laminated pieces are fired simultaneously, the sintered layer is preferably formed by sintering a material to which a ceramic material has been added in place of the glass component. In this case, the added ceramic material is particularly preferably the same type of ceramic material as that used in dielectric layer 20. In this case, the conductive paste is applied to the pre-fired laminated pieces, and the laminated pieces and the conductive paste applied to the laminated pieces are sintered simultaneously to form laminate 10, which forms the sintered layer.

[0219] Next, a plating layer is formed on the surface of the base electrode layer and the laminate 10, which is formed of a sintered layer. When the base electrode layer is formed of a sintered layer, two plating layers, for example, a Ni plating layer and a Sn plating layer, are formed as the plating layer. The plating layer is formed by electrolytic plating. Barrel plating is preferably used as the plating process.

[0220] In addition, when it is difficult to control the formation of the plating layer, the plating layer may be formed by providing a mask at a portion where the surface of the laminate 10 is exposed. This makes it easier to form a plating layer in a desired shape.

[0221] Through such manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0222] The structure of the external electrode 40 is not limited to the structure described above. A first modified example of the shape of the external electrode 40 of the multilayer ceramic capacitor 1 according to this embodiment will be described below. In the following description, the same reference numerals are used for the same structures as those in the above embodiment, and detailed descriptions thereof will be omitted. Figure 15A is a cross-sectional view showing a first modified example of the shape of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to FIG. Figure 1 The corresponding figure.

[0223] In this modification, the shape of the external electrode 40 is different from that of the above embodiment. In this modification, the first external electrode 40A and the second external electrode 40B are arranged only on either the first main surface TS1 or the second main surface TS2.

[0224] For example, the first external electrode 40A of this modification includes a first surface portion 40A1 located on the first end surface LS1, a third surface portion 40A3 located partially on the second main surface TS2, a fourth surface portion 40A4 located partially on the first side surface WS1, and a fifth surface portion 40A5 located partially on the second side surface WS2. In other words, the first external electrode 40A of this modification is not formed on the first main surface TS1.

[0225] For example, the second external electrode 40B of this modification includes a sixth surface portion 40B1 located on the second end surface LS2, an eighth surface portion 40B3 located partially on the second main surface TS2, a ninth surface portion 40B4 located partially on the first side surface WS1, and a tenth surface portion 40B5 located partially on the second side surface WS2. In other words, the second external electrode 40B of this modification is not formed on the first main surface TS1.

[0226] In this modified example, the length W1 of the third surface portion 40A3 of the first external electrode 40A in the width direction W is smaller than the length W2 of the first surface portion 40A1 in the width direction W. The length W1 of the third surface portion 40A3 of the first external electrode 40A in the width direction W is smaller than the dimension w in the width direction W of the laminate 10. The length W1 of the eighth surface portion 40B3 of the second external electrode 40B in the width direction W is smaller than the length W2 of the sixth surface portion 40B1 in the width direction W. The length W1 of the eighth surface portion 40B3 of the second external electrode 40B in the width direction W is smaller than the dimension w in the width direction W of the laminate 10.

[0227] This structure also suppresses the deterioration of the self-alignment effect, enabling stable mounting. Furthermore, by not arranging the first external electrode 40A and the second external electrode 40B on either the first principal surface TS1 or the second principal surface TS2, the dimension of the multilayer ceramic capacitor 1 in the height direction T is reduced, enabling a further reduction in the height of the multilayer ceramic capacitor 1. Furthermore, by not arranging the first external electrode 40A and the second external electrode 40B on either the first principal surface TS1 or the second principal surface TS2, the height dimension of the multilayer body 10 can be maintained in accordance with the thickness of the external electrodes 40. Consequently, the volume of the effective layer portion of the multilayer body 10 can be increased, enabling a higher capacitance of the multilayer ceramic capacitor 1.

[0228] The structure of the external electrode 40 is not limited to the structure described above. A second modified example of the shape of the external electrode 40 of the multilayer ceramic capacitor 1 according to this embodiment will be described below. In the following description, the same reference numerals are used for the same structures as those in the above embodiment, and detailed descriptions thereof will be omitted. Figure 15B is a cross-sectional view showing a second modified example of the shape of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to FIG. Figure 1 The corresponding figure. Figure 15C This is an external perspective view of the present modification example viewed from another angle so that the first surface portion 40A1 of the first external electrode 40A is visible.

[0229] In this modification, the shapes of the first surface portion 40A1 of the first external electrode 40A and the sixth surface portion 40B1 of the second external electrode 40B are different from those in the above-described embodiment.

[0230] The first surface portion 40A1 of this modification includes a first central portion 40A1A, a first extended portion 40A1B extending from the first central portion 40A1A to the first side surface WS1 , and a second extended portion 40A1C extending from the first central portion 40A1A to the second side surface WS2 .

[0231] The length W3 of the first central portion 40A1A in the width direction W may be smaller than the dimension w in the width direction W of the laminate 10 and equal to the length W1 of the second and third surface portions 40A2 and 40A3 of the first external electrode 40A in the width direction W.

[0232] Furthermore, the length T2 of the first central portion 40A1A in the height direction T is equal to the dimension t in the height direction T of the stacked body 10 , and the first central portion 40A1A is continuously connected to the second surface portion 40A2 and the third surface portion 40A3 .

[0233] The first and second extended portions 40A1B and 40A1C extend continuously from the first central portion 40A1A to the first and second side surfaces WS1 and WS2. The length T3 of the first and second extended portions 40A1B and 40A1C in the height direction T is less than the dimension t of the laminate 10 in the height direction T. In other words, at both ends of the first and second extended portions 40A1B and 40A1C in the height direction T, portions are exposed where no external electrodes are formed and the surface of the laminate 10 is exposed. This exposed surface of the laminate 10 makes it difficult for the solder to wet the entire first end surface LS1 when the multilayer ceramic capacitor 1 is mounted on a mounting substrate. Instead, the solder is more likely to wet the central portion where the second and third surface portions 40A2 and 40A3 are located. Consequently, soldering can be performed centered in the central portion of the multilayer ceramic capacitor 1 in the width direction W, further stabilizing the mounting performance of the multilayer ceramic capacitor 1.

[0234] The length T3 of the first extension portion 40A1B in the height direction T and the length T1 of the fourth surface portion 40A4 in the height direction T may be equal, or one of them may be greater. The length T3 of the second extension portion 40A1C in the height direction T and the length T1 of the fifth surface portion 40A5 in the height direction T may be equal, or one of them may be greater.

[0235] The sixth surface portion 40B1 of this modification includes a second central portion 40B1A, a third extended portion 40B1B extending from the second central portion 40B1A to the first side surface WS1 , and a fourth extended portion 40B1C extending from the second central portion 40B1A to the second side surface WS2 .

[0236] The length W3 of the second central portion 40B1A in the width direction W may be smaller than the dimension w in the width direction W of the laminate 10 and equal to the length W1 of the seventh and eighth surface portions 40B2 and 40B3 of the second external electrode 40B in the width direction W.

[0237] Furthermore, the length T2 of the second central portion 40B1A in the height direction T is equal to the dimension t in the height direction T of the stacked body 10 , and the second central portion 40B1A is continuously connected to the seventh surface portion 40B2 and the eighth surface portion 40B3 .

[0238] The third and fourth extended portions 40B1B and 40B1C extend continuously from the second central portion 40B1A to the first and second side surfaces WS1 and WS2. The length T3 of the third and fourth extended portions 40B1B and 40B1C in the height direction T is less than the dimension t in the height direction T of the laminate 10. In other words, at both ends of the third and fourth extended portions 40B1B and 40B1C in the height direction T, portions are exposed where no external electrodes are formed, thus exposing the surface of the laminate 10. This exposed surface of the laminate 10 makes it difficult for solder to wet the entire second end surface LS2 when the multilayer ceramic capacitor 1 is mounted on a mounting substrate. Instead, the solder is more likely to wet the central portion of the seventh and eighth surface portions 40B2 and 40B3. Consequently, soldering can be performed centered in the central portion of the multilayer ceramic capacitor 1 in the width direction W, further stabilizing the mounting performance of the multilayer ceramic capacitor 1.

[0239] The length T3 of the third extension portion 40B1B in the height direction T and the length T1 of the ninth surface portion 40B4 in the height direction T may be equal, or one of them may be greater. The length T3 of the fourth extension portion 40B1C in the height direction T and the length T1 of the tenth surface portion 40B5 in the height direction T may be equal, or one of them may be greater.

[0240] This structure also suppresses the deterioration of the self-alignment effect and enables stable mounting.

[0241] The structure of the external electrode 40 is not limited to the structure described above. A third modified example of the shape of the external electrode 40 of the multilayer ceramic capacitor 1 according to this embodiment will be described below. In the following description, the same reference numerals are used for the same structures as in the second modified example, and detailed descriptions thereof will be omitted. Figure 15D is a cross-sectional view showing a third modified example of the shape of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to FIG. Figure 15B The corresponding figure.

[0242] In this modification, the shape of the external electrode 40 is different from that in the above-described second modification. In this modification, the first external electrode 40A and the second external electrode 40B are arranged only on either the first main surface TS1 or the second main surface TS2.

[0243] For example, the first external electrode 40A of this modification includes a first surface portion 40A1 located on the first end surface LS1, a third surface portion 40A3 located partially on the second main surface TS2, a fourth surface portion 40A4 located partially on the first side surface WS1, and a fifth surface portion 40A5 located partially on the second side surface WS2. In other words, the first external electrode 40A of this modification is not formed on the first main surface TS1.

[0244] For example, the second external electrode 40B of this modification includes a sixth surface portion 40B1 located on the second end surface LS2, an eighth surface portion 40B3 located partially on the second main surface TS2, a ninth surface portion 40B4 located partially on the first side surface WS1, and a tenth surface portion 40B5 located partially on the second side surface WS2. In other words, the second external electrode 40B of this modification is not formed on the first main surface TS1.

[0245] By such a structure, it is also possible to suppress the deterioration of the self-alignment effect and to perform stable mounting. In addition, the same effects as those of the first and second modified examples can be obtained.

[0246] According to the multilayer ceramic capacitor 1 of this embodiment, the following effects are achieved.

[0247] (1) The multilayer ceramic capacitor 1 of the present embodiment comprises: a multilayer body 10 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction, a first end surface LS1 and a second end surface LS2 opposite to each other in the longitudinal direction perpendicular to the height direction, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction perpendicular to the height direction and the longitudinal direction; a first external electrode 40A having a first surface portion 40A1 located on the first end surface LS1, a second surface portion 40A2 located partially on the first main surface TS1, and a third surface portion 40A2 located partially on the second main surface TS2. The second external electrode 40B includes at least one of the sixth surface 40B1 located on the second end surface LS2, the seventh surface 40B2 located on the first main surface TS1, and the eighth surface 40B3 located on the second main surface TS2, the ninth surface 40B4 located on the first side surface WS1, and the tenth surface 40B5 located on the second side surface WS2. In the multilayer ceramic capacitor 1, the first end surface LS1 and the second end surface LS2 of the multilayer body 10 are connected. The length in the longitudinal direction is set to l, the length in the width direction connecting the first side surface WS1 and the second side surface WS2 is set to w, and the length in the height direction connecting the first main surface TS1 and the second main surface TS2 is set to t. At this time, the size relationship is w>l>t. When the first external electrode 40A has the second surface 40A2, the length W1 of the second surface 40A2 in the width direction is smaller than the length W2 of the first surface 40A1 in the width direction. When the first external electrode 40A has the third surface 40A3, the length W1 of the third surface 40A3 in the width direction is smaller than the length W2 of the first surface 40A1 in the width direction. When the second external electrode 40B has the seventh surface In the case of the second external electrode 40B having an eighth portion 40B3, the widthwise length W1 of the seventh portion 40B2 is smaller than the widthwise length W2 of the sixth portion 40B1. In the case of the second external electrode 40B having an eighth portion 40B3, the widthwise length W1 of the eighth portion 40B3 is smaller than the widthwise length W2 of the sixth portion 40B1. The heightwise length T1 of the fourth portion 40A4 and the fifth portion 40A5 of the first external electrode 40A is smaller than the heightwise length T2 of the first portion 40A1. The heightwise length T1 of the ninth portion 40B4 and the tenth portion 40B5 of the second external electrode 40B is smaller than the heightwise length T2 of the sixth portion 40B1. Thus, an LW inversion type multilayer ceramic capacitor can be provided that can suppress the occurrence of short-circuit failures.

[0248] For example, the multilayer ceramic capacitor 1 of the present embodiment may include: a first external electrode 40A including a first face portion 40A1 located on the first end surface LS1, a second face portion 40A2 located as a portion on the first main surface TS1, a third face portion 40A3 located as a portion on the second main surface TS2, a fourth face portion 40A4 located as a portion on the first side surface WS1, and a fifth face portion 40A5 located as a portion on the second side surface WS2; and a second external electrode 40B including a sixth face portion 40B1 located on the second end surface LS2, a seventh face portion 40B2 located as a portion on the first main surface TS1, an eighth face portion 40B3 located as a portion on the second main surface TS2, a ninth face portion 40B4 located as a portion on the first side surface WS1, and a ninth face portion 40B5 located as a portion on the second side surface WS2. In the multilayer ceramic capacitor 1, the length W1 of the second face portion 40A2 and the third face portion 40A3 of the first external electrode 40A in the width direction is smaller than the length W2 of the first face portion 40A1 in the width direction, the length W1 of the seventh face portion 40B2 and the eighth face portion 40B3 of the second external electrode 40B in the width direction is smaller than the length W2 of the sixth face portion 40B1 in the width direction, the length T1 of the fourth face portion 40A4 and the fifth face portion 40A5 of the first external electrode 40A in the height direction is smaller than the length T2 of the first face portion 40A1 in the height direction, and the length T1 of the ninth face portion 40B4 and the tenth face portion 40B5 of the second external electrode 40B in the height direction is smaller than the length T2 of the sixth face portion 40B1 in the height direction.

[0249] For example, the multilayer ceramic capacitor 1 of this embodiment may include: a first external electrode 40A having a first face portion 40A1 located on the first end surface LS1, a third face portion 40A3 located on a portion of the second main surface TS2, a fourth face portion 40A4 located on a portion of the first side surface WS1, and a fifth face portion 40A5 located on a portion of the second side surface WS2; and a second external electrode 40B having a sixth face portion 40B1 located on the second end surface LS2, an eighth face portion 40B3 located on a portion of the second main surface TS2, a ninth face portion 40B4 located on a portion of the first side surface WS1, and a tenth face portion 40B located on a portion of the second side surface WS2. 5. In the multilayer ceramic capacitor 1, the widthwise length W1 of the third surface portion 40A3 of the first external electrode 40A is smaller than the widthwise length W2 of the first surface portion 40A1. The widthwise length W1 of the eighth surface portion 40B3 of the second external electrode 40B is smaller than the widthwise length W2 of the sixth surface portion 40B1. The heightwise length T1 of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A is smaller than the heightwise length T2 of the first surface portion 40A1. The heightwise length T1 of the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B is smaller than the heightwise length T2 of the sixth surface portion 40B1.

[0250] (2) In the multilayer ceramic capacitor 1 of the present embodiment, when the first external electrode 40A has the second surface portion 40A2, the length W1 of the second surface portion 40A2 in the width direction is smaller than the w dimension of the multilayer body 10; when the first external electrode 40A has the third surface portion 40A3, the length W1 of the third surface portion 40A3 in the width direction is smaller than the w dimension of the multilayer body 10; and when the second external electrode 40B has the seventh surface portion 40B2, the length W1 of the seventh surface portion 40B2 in the width direction is smaller than the w dimension of the multilayer body 10. The width W1 of the eighth surface portion 40B3 is smaller than the w dimension of the laminate 10. When the second external electrode 40B has the eighth surface portion 40B3, the width W1 of the eighth surface portion 40B3 is smaller than the w dimension of the laminate 10. The height T1 of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A is smaller than the t dimension of the laminate 10. The height T1 of the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B is smaller than the t dimension of the laminate 10. Thus, an LW inverted type laminated ceramic capacitor can be provided that can suppress the occurrence of short circuit failures and can be stably mounted.

[0251] (3) In the multilayer ceramic capacitor 1 of this embodiment, when the first external electrode 40A has a second surface portion 40A2, the second surface portion 40A2 is rectangular. When the first external electrode 40A has a third surface portion 40A3, the third surface portion 40A3 is rectangular. When the second external electrode 40B has a seventh surface portion 40B2, the seventh surface portion 40B2 is rectangular. When the second external electrode 40B has an eighth surface portion 40B3, the eighth surface portion 40B3 is rectangular. Thus, an LW inverted type multilayer ceramic capacitor can be provided that can suppress the occurrence of short circuit failures and can be stably mounted.

[0252] (4) The length t in the height direction connecting the first main surface TS1 and the second main surface TS2 of the laminated body 10 of the laminated ceramic capacitor 1 of this embodiment is 150 μm or less. In such a low-profile laminated ceramic capacitor, the effects of this embodiment can be suitably obtained.

[0253] (5) The length t in the height direction connecting the first main surface TS1 and the second main surface TS2 of the laminated body 10 of the laminated ceramic capacitor 1 of this embodiment is 100 μm or less. In such a low-profile laminated ceramic capacitor, the effects of this embodiment can be suitably obtained.

[0254] (6) The length t in the height direction connecting the first main surface TS1 and the second main surface TS2 of the laminated body 10 of the laminated ceramic capacitor 1 of this embodiment is 50 μm or less. In such a low-profile laminated ceramic capacitor, the effects of this embodiment can be appropriately obtained.

[0255] The internal electrode layer 30 includes a first internal electrode layer 31 and a second internal electrode layer 32. The first internal electrode layer 31 includes a first opposing electrode portion 31A located within the laminate and opposing the second internal electrode layer 32, and a first lead portion 31B connected to the first opposing electrode portion 31A and exposed at the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2. The second internal electrode layer 32 includes a second opposing electrode portion 32A located within the laminate and opposing the first internal electrode layer 31, and a second lead portion 32B connected to the second opposing electrode portion 32A and exposed at the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. This shortens the distance between the lead portions of the first internal electrode layer 31 and the second internal electrode layer 32, thereby shortening the current path. Consequently, ESL can be reduced.

[0256] (8) The first external electrode 40A of the multilayer ceramic capacitor 1 of this embodiment includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B. The first base electrode layer 50A and the second base electrode layer 50B are sputtered electrodes. This allows the thickness of the external electrodes to be reduced, making it easier to ensure the thickness of the laminate 10. This ensures both capacitance and strength of the laminate 10.

[0257] <Experimental Example>

[0258] As samples of the experimental examples, multilayer ceramic capacitors were produced, and evaluations of mountability, capacitance, and base electrode layer thickness were conducted.

[0259] First, as a sample of the embodiment, a Figures 1 to 10B A multilayer ceramic capacitor 1 having the following specifications is shown. In addition, as a sample of Comparative Example 1, a Figure 16A The external electrodes 140 (first external electrode 140A, second external electrode 140B) shown in FIG. 1 are of a conventional structure of the multilayer ceramic capacitor 101. In addition, as a sample of Comparative Example 2, a Figure 17A The multilayer ceramic capacitor 201 has an external electrode 240 (a first external electrode 240A and a second external electrode 240B) provided with a recess R that is recessed from an end edge of the external electrode toward an end surface side of the stacked body 10 .

[0260] Figure 16A is a perspective view of the appearance of a multilayer ceramic capacitor 101 of Comparative Example 1. Figure 1 Corresponding diagram. Figure 16B is a diagram showing the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of Comparative Example 1, and is similar to Figure 8A The corresponding figure. Figure 16C is a diagram showing the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of Comparative Example 1, and is similar to Figure 8B The corresponding figure. Figure 17A This is a perspective view of the appearance of a multilayer ceramic capacitor 201 of Comparative Example 2. Figure 1 The corresponding figure. Figure 17B is a diagram showing the first internal electrode layer 231 of the multilayer ceramic capacitor 201 of Comparative Example 2. Figure 8A The corresponding figure. Figure 17C is a diagram showing the second internal electrode layer 232 of the multilayer ceramic capacitor 201 of Comparative Example 2. Figure 8B In addition, Figure 16B 、 Figure 16C 、 Figure 17B、 Figure 17C The external electrodes are omitted.

[0261] (Structure of the embodiment)

[0262] Dimensions of a multilayer ceramic capacitor: L×W×T=0.520mm×1.000mm×0.100mm

[0263] Dimensions of the laminate: L×W×T=0.500mm×0.980mm×0.070mm

[0264] ■Ceramic material for dielectric layer: BaTiO3

[0265] Capacitance: 0.47μF

[0266] Rated voltage: 4V

[0267] ■Material of internal electrode layer: Ni

[0268] ■ Pattern of internal electrode layer: Figure 8A 、 Figure 8B The pattern shown

[0269] ■Structure of external electrodes:

[0270] Base electrode layer: thin film layer (sputtered electrode)

[0271] Material of base electrode layer: Two-layer structure of NiCr layer and NiCu layer

[0272] Thickness of foundation electrode layer: Main surface thickness 0.2 μm (thickness of foundation electrode layer disposed on each of first main surface TS1 and second main surface TS2)

[0273] Plating layer: 3-layer structure of Cu plating layer, Ni plating layer, Sn plating layer

[0274] Cu plating layer thickness: 5.5μm

[0275] Ni plating layer thickness: 2.5μm

[0276] Sn plating layer thickness: 3.2μm

[0277] The length W1 of each of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the width direction W is 87% of the w dimension in the width direction W of the laminate 10 (the length W1 of the second surface portion 40A2 and the third surface portion 40A3 in the width direction W is 0.85 mm, and the w dimension of the laminate 10 is 0.980 mm).

[0278] The length L1 of each of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A in the longitudinal direction L is 30% of the single dimension in the longitudinal direction L of the laminate 10 (the length L1 of the second surface portion 40A2 and the third surface portion 40A3 in the longitudinal direction L is 0.15 mm, and the single dimension of the laminate 10 is 0.500 mm).

[0279] The length W1 of each of the seventh and eighth surface portions 40B2 and 40B3 of the second external electrode 40B in the width direction W is 87% of the width dimension W of the laminate 10 in the width direction W (the length W1 of the seventh and eighth surface portions 40B2 and 40B3 in the width direction W is 0.85 mm, and the width dimension W of the laminate 10 is 0.980 mm).

[0280] The length L1 of each of the seventh and eighth surface portions 40B2 and 40B3 of the second external electrode 40B in the longitudinal direction L is 30% of the single dimension in the longitudinal direction L of the laminate 10 (the length L1 of the seventh and eighth surface portions 40B2 and 40B3 in the longitudinal direction L is 0.15 mm, and the single dimension of the laminate 10 is 0.500 mm).

[0281] The length T1 of each of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the height direction T is 69% of the t dimension in the height direction T of the laminate 10 (the length T1 of the fourth surface portion 40A4 and the fifth surface portion 40A5 in the height direction T is 0.048 mm, and the t dimension of the laminate 10 is 0.070 mm).

[0282] The length L2 of each of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the longitudinal direction L is 20% of the single dimension in the longitudinal direction L of the laminate 10 (the length L2 of the fourth surface portion 40A4 and the fifth surface portion 40A5 in the longitudinal direction L is 0.1 mm, and the single dimension of the laminate 10 is 0.500 mm).

[0283] The length T1 of each of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the height direction T is 69% of the t dimension in the height direction T of the laminate 10 (the length T1 of the ninth and tenth surface portions 40B4 and 40B5 in the height direction T is 0.048 mm, and the t dimension of the laminate 10 is 0.070 mm).

[0284] The length L2 of each of the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B in the longitudinal direction L is 20% of the single dimension in the longitudinal direction L of the laminate 10 (the length L2 of the ninth and tenth surface portions 40B4 and 40B5 in the longitudinal direction L is 0.1 mm, and the single dimension of the laminate 10 is 0.500 mm).

[0285] (Structure of Comparative Example 1)

[0286] Dimensions of a multilayer ceramic capacitor: L×W×T=0.520mm×1.000mm×0.100mm

[0287] ■Ceramic material for dielectric layer: BaTiO3

[0288] Capacitance: 0.47μF

[0289] Rated voltage: 4V

[0290] ■Material of internal electrode layer: Ni

[0291] ■ Pattern of internal electrode layer: Figure 16B 、 Figure 16C The pattern shown

[0292] ■Structure of external electrodes:

[0293] Base electrode layer: A sintered layer coated with a conductive paste and sintered

[0294] Material of base electrode layer: Ni

[0295] Thickness of the underlying electrode layer: 10 μm at the end surface, 5 μm at the side surface, and 5 μm at the main surface (the thickness of the underlying electrode layer disposed on each of the first and second main surfaces TS1 and TS2)

[0296] Plating layer: 3-layer structure of Cu plating layer, Ni plating layer, Sn plating layer

[0297] Cu plating layer thickness: 5.5μm

[0298] Ni plating layer thickness: 2.5μm

[0299] Sn plating layer thickness: 3.2μm

[0300] (Structure of Comparative Example 2)

[0301] Dimensions of a multilayer ceramic capacitor: L×W×T=0.520mm×1.000mm×0.100mm

[0302] ■Ceramic material for dielectric layer: BaTiO3

[0303] Capacitance: 0.47μF

[0304] Rated voltage: 4V

[0305] ■Material of internal electrode layer: Ni

[0306] ■ Pattern of internal electrode layer: Figure 17B 、 Figure 17C The pattern shown

[0307] ■Structure of external electrodes:

[0308] Base electrode layer: thin film layer (sputtered electrode)

[0309] Materials of base electrode layer: NiCr layer and NiCu layer

[0310] Thickness of foundation electrode layer: Main surface thickness 0.2 μm (thickness of foundation electrode layer disposed on each of first main surface TS1 and second main surface TS2)

[0311] Plating layer: 3-layer structure of Cu plating layer, Ni plating layer, Sn plating layer

[0312] Cu plating layer thickness: 5.5μm

[0313] Ni plating layer thickness: 2.5μm

[0314] Sn plating layer thickness: 3.2μm

[0315] Next, the mountability was evaluated using the produced samples.

[0316] (Installation evaluation)

[0317] The mountability was evaluated using samples of the examples and samples of Comparative Examples 1 and 2. 100 samples were used for each evaluation. Table 1 shows the results of the mountability evaluation.

[0318] [Table 1]

[0319] Rotation Short Circuit Example 0 / 100 0 / 100 Comparative Example 1 1 / 100 0 / 100 Comparative Example 2 8 / 100 1 / 100

[0320] In Comparative Example 1, one sample was produced that had a rotational defect. In Comparative Example 2, eight samples were produced that had a rotational defect. One of the samples had a large rotation amount, and was installed so that an external electrode spanned a connection pad with different polarities, resulting in a short circuit. In the sample of Comparative Example 2, it is believed that the following situation exists: due to the formation position and thickness deviations of the base electrode layer and the plating layer provided thereon, the area and shape of the external electrodes covering the ridges of the first and second side surfaces of the stacked body are deviated, and the way the solder wets the external electrodes on the first and second side surfaces is easily changed, resulting in a large difference in the amount of solder wetted. As a result, it is speculated that there is a difference in the way the solder applies tensile stress to the multilayer ceramic capacitor, resulting in a rotational defect.

[0321] The evaluation method in this experimental example is shown below.

[0322] (Evaluation method for mountability)

[0323] Figures 18A to 18D This is a diagram for explaining the evaluation method of installability. Figure 18A Solder (solder composition Sn-3.0Ag-0.5Cu) is printed on the two connection pads 310A and 310B on the glass epoxy substrate 300 shown in FIG. At this time, a solder amount of 100 μm thick solder is printed on each connection pad. Figure 18A As shown, the length of the connection pad in the width direction is set to 1.0 mm, the length of the connection pad in the longitudinal direction is set to 0.3 mm, and the distance between the two connection pads is set to 0.2 mm.

[0324] Next, the multilayer ceramic capacitor is placed on the lands coated with solder. Figure 18B As shown in FIG. 1 , a reference line is taken at the center of the width direction of the connection pad so as to be perpendicular to the width direction of the connection pad, and the multilayer ceramic capacitor is placed so that the center of the multilayer ceramic capacitor in the width direction W is located at a position offset by 0.1 mm from the reference line in the width direction of the connection pad. Figure 18C The angle θ formed by the shown connecting plate and the stacked ceramic capacitor, that is, the angle θ on the acute angle side formed between any one of the opposing inner sides of the two connecting plates and the surface on the first end face LS1 side or the surface on the second end face LS2 side of the external electrode of the stacked ceramic capacitor, is within 5°.

[0325] Then, the external electrodes of the multilayer ceramic capacitor are soldered to the lands by reflow soldering, and the multilayer ceramic capacitor is mounted on the substrate. After mounting, the mounting state of the multilayer ceramic capacitor is observed, and if the angle θ between the lands and the multilayer ceramic capacitor is tilted by more than 5°, it is considered a rotation failure. Figure 18DThe multilayer ceramic capacitor shown above is short-circuited if it is mounted with the first external electrode or the second external electrode being greatly rotated and straddling two lands.

[0326] Based on the above results, the multilayer ceramic capacitor 1 of this embodiment can suppress wetting of the first side surface WS1 and the second side surface WS2 of the multilayer body 10 by the solder, thereby suppressing stress applied in the rotational direction of the multilayer ceramic capacitor 1. Consequently, the self-alignment effect is enhanced, and the mounting performance of the multilayer ceramic capacitor 1 is stabilized. As a result, short circuit failures and the like can be prevented.

[0327] The present invention is not limited to the configuration of the above embodiment, and can be applied with appropriate modifications within the scope of the present invention. In addition, a combination of two or more configurations of the preferred configurations described in the above embodiment also constitutes the present invention.

Claims

1. A laminated ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; The second external electrode has a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, a ninth face portion located on a portion of the first side surface, and a tenth face portion located on a portion of the second side surface. In the multilayer ceramic capacitor, The length of the stacked body in the longitudinal direction connecting the first end face and the second end face is set to l, the length of the stacked body in the width direction connecting the first side face and the second side face is set to w, and the length of the stacked body in the height direction connecting the first main face and the second main face is set to t. At this time, the dimensional relationship is w>l>t. The second surface portion of the first external electrode is formed continuously on the first main surface in the width direction and does not reach ridges of the laminate that are opposed in the width direction. The length of the second face portion in the width direction is smaller than the length of the first face portion in the width direction. The seventh surface portion of the second external electrode is formed continuously on the first main surface in the width direction and does not reach ridge portions of the laminate that are opposed in the width direction. The length of the seventh face portion in the width direction is smaller than the length of the sixth face portion in the width direction. The lengths of the fourth face portion and the fifth face portion of the first external electrode in the height direction are smaller than the length of the first face portion in the height direction. The lengths of the ninth surface portion and the tenth surface portion of the second external electrode in the height direction are smaller than the length of the sixth surface portion in the height direction.

2. The multilayer ceramic capacitor according to claim 1, wherein The fourth surface portion of the first external electrode is formed continuously on the first side surface in the height direction and does not reach ridge portions of the stacked body that are opposed in the height direction. The fifth surface portion of the first external electrode is formed continuously on the second side surface in the height direction and does not reach ridge portions of the stacked body that are opposed in the height direction. The ninth surface portion of the second external electrode is formed continuously on the first side surface in the height direction and does not reach ridge portions of the stacked body that are opposed in the height direction. The tenth surface portion of the second external electrode is formed continuously on the second side surface in the height direction and does not reach ridge portions of the stacked body that are opposed in the height direction.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The first external electrode further includes a third surface portion located on a portion of the second main surface. The third surface portion is formed continuously on the second main surface in the width direction and does not reach ridges of the laminated body that are opposed in the width direction. The length of the third face portion in the width direction is smaller than the length of the first face portion in the width direction. The second external electrode further includes an eighth surface portion located on a portion of the second main surface. The eighth surface portion is formed continuously on the second main surface in the width direction and does not reach ridges of the laminated body that are opposed in the width direction. The length of the eighth surface portion in the width direction is smaller than the length of the sixth surface portion in the width direction.

4. The multilayer ceramic capacitor according to claim 3, wherein: The second face portion is rectangular in shape, The third face portion is rectangular in shape, The seventh face portion is rectangular in shape, The eighth surface portion is in a rectangular shape.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The length of the stacked body in a height direction connecting the first main surface and the second main surface is 150 μm or less.

6. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The length of the stacked body in a height direction connecting the first main surface and the second main surface is 100 μm or less.

7. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The length of the stacked body in a height direction connecting the first main surface and the second main surface is 50 μm or less.

8. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The internal electrode layer includes a first internal electrode layer and a second internal electrode layer, The first internal electrode layer comprises: a first opposing electrode portion located inside the stack and opposed to the second internal electrode layer; and a first lead portion connected to the first opposing electrode portion and exposed at the first end surface, a portion of the first side surface, and a portion of the second side surface. The second internal electrode layer includes: a second opposing electrode portion located inside the stack and opposing the first internal electrode layer; and a second lead portion connected to the second opposing electrode portion and exposed at the second end surface, a portion of the first side surface, and a portion of the second side surface.

9. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The first external electrode includes a first base electrode layer and a first plating layer disposed on the first base electrode layer. The second external electrode includes a second base electrode layer and a second plating layer disposed on the second base electrode layer. The first foundation electrode layer and the second foundation electrode layer are sputtered electrodes.

10. A laminated ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; The second external electrode has a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, a ninth face portion located on a portion of the first side surface, and a tenth face portion located on a portion of the second side surface. In the multilayer ceramic capacitor, The length of the stacked body in the longitudinal direction connecting the first end face and the second end face is set to l, the length of the stacked body in the width direction connecting the first side face and the second side face is set to w, and the length of the stacked body in the height direction connecting the first main face and the second main face is set to t. At this time, the dimensional relationship is w>l>t. The length of the second face portion in the width direction is smaller than the length of the first face portion in the width direction. The length of the seventh face portion in the width direction is smaller than the length of the sixth face portion in the width direction. The lengths of the fourth face portion and the fifth face portion of the first external electrode in the height direction are smaller than the length of the first face portion in the height direction. The lengths of the ninth and tenth face portions of the second external electrode in the height direction are smaller than the length of the sixth face portion in the height direction. The fourth surface portion of the first external electrode is formed continuously on the first side surface in the height direction and does not reach ridge portions of the stacked body that are opposed in the height direction. The fifth surface portion of the first external electrode is formed continuously on the second side surface in the height direction and does not reach ridge portions of the stacked body that are opposed in the height direction. The ninth surface portion of the second external electrode is formed continuously on the first side surface in the height direction and does not reach ridge portions of the stacked body that are opposed in the height direction. The tenth surface portion of the second external electrode is formed continuously on the second side surface in the height direction and does not reach ridge portions of the stacked body that are opposed in the height direction.

Images