Fractionally dividing multi-modulus prescaler and pll

Abstract

The application provides a fractional-N multi-mode synchronous frequency divider and a PLL. The fractional-N multi-mode synchronous frequency divider comprises N frequency dividers connected in series, N-2 first logic modules connected in series and N+1 first flip-flops, and N is an integer greater than 2. The first logic module is configured to output a high level when a first input end of the first logic module and a second input end of the first logic module are both at a high level. The first flip-flop is configured to output a frequency division ratio switching signal corresponding to the first flip-flop when a signal received by a first input end of the first flip-flop is converted from a low level to a high level. The embodiment of the application realizes glitch-free switching inside the MMSD, and can effectively improve the accuracy of the fractional frequency output by the PLL.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a multi-mode synchronous frequency divider and PLL with fractional frequency division. Background Technology

[0002] Phase-locked loops (PLLs) are widely used in various clock circuits to provide clock references for other chips and to modulate and demodulate signals. PLLs support both integer and fractional frequency outputs. To output a fractional frequency, a Sigma Delta Modulator (SDM) is needed to continuously modulate the feedback divider in the PLL, causing its output frequency to jump between several adjacent division ratios. This dynamically adjusts the output frequency of the voltage-controlled oscillator (VCO) in the PLL, thus dynamically adjusting the PLL's output frequency.

[0003] Currently, multi-modulus dividers (MMDs) are commonly used as feedback dividers.

[0004] However, when MMD is used as a feedback divider, glitches may occur under certain circumstances where the division ratio is switched continuously. This can lead to incorrect division results from the MMD, resulting in poor accuracy of the fractional frequency output by the PLL. Summary of the Invention

[0005] This invention provides a multi-mode synchronous frequency divider and PLL with fractional frequency division to solve the problem of poor accuracy of fractional frequency output by PLL in the prior art.

[0006] This invention provides a multi-mode synchronous frequency divider with fractional frequency division, comprising:

[0007] N frequency dividers connected in series, N-2 first logic modules connected in series, and N+1 first flip-flops, where N is an integer greater than 2;

[0008] In the N frequency dividers, the first output of the preceding frequency divider is connected to the first input of the following frequency divider, and the second output of the following frequency divider is connected to the second input of the preceding frequency divider. The first input of the first-stage frequency divider serves as the first input of the fractional-order multi-mode synchronous frequency divider, and the second input of the first-stage frequency divider serves as the second input of the fractional-order multi-mode synchronous frequency divider. The first output of the Nth-stage frequency divider serves as the first output of the fractional-order multi-mode synchronous frequency divider. The synchronization terminals of N-2 target frequency dividers are correspondingly connected to the first inputs of the N-2 first logic modules. The frequency divider is any of the N frequency dividers except for the first-stage frequency divider and the Nth-stage frequency divider. The synchronization terminal of the Nth-stage frequency divider is connected to the second input terminal of the N-2th-stage first logic module in the N-2 first logic modules. In the N-2 first logic modules, the output terminal of the next-stage first logic module is connected to the second input terminal of the previous-stage first logic module. The output terminal of the first-stage first logic module is connected to the first input terminal of the N+1 first flip-flops. The second input terminal of the N+1 first flip-flops is used to receive the division ratio switching signal. The output terminal of the N+1 first flip-flops is correspondingly connected to the control terminal of the N frequency dividers and the second input terminal of the Nth-stage frequency divider.

[0009] The first logic module is configured to: output a high level when both the first input terminal and the second input terminal of the first logic module are at a high level;

[0010] The first flip-flop is used to output the frequency division ratio switching signal corresponding to the first flip-flop when the signal received at the first input terminal of the first flip-flop changes from low level to high level.

[0011] According to the present invention, a fractional-frequency multimode synchronous frequency divider further includes a second logic module.

[0012] The output of the first logic module of the first stage is connected to the first input of the N+1 first flip-flops through the second logic module; wherein, the output of the first logic module of the first stage is connected to the second input of the second logic module, the first input of the second logic module is used to receive a start signal, and the output of the second logic module is connected to the first input of the N+1 first flip-flops;

[0013] The second logic module is configured to: output a first signal upon receiving the start signal;

[0014] The first trigger is further configured to: upon receiving the first signal, output a frequency division ratio switching signal corresponding to the first trigger.

[0015] According to the present invention, a multi-mode synchronous frequency divider with fractional frequency division is provided, wherein the second logic module includes a second AND gate;

[0016] The first input terminal of the second AND gate serves as the first input terminal of the second logic module, the second input terminal of the second AND gate serves as the second input terminal of the second logic module, and the output terminal of the second AND gate serves as the output terminal of the second logic module.

[0017] According to the present invention, a multi-mode synchronous frequency divider with fractional frequency division is provided, wherein the first logic module includes a first AND gate;

[0018] The first input terminal of the first AND gate serves as the first input terminal of the first logic module, the second input terminal of the first AND gate serves as the second input terminal of the first logic module, and the output terminal of the first AND gate serves as the output terminal of the first logic module.

[0019] According to the present invention, a fractional-frequency multimode synchronous frequency divider further includes N-2 second flip-flops and a data selector MUX;

[0020] The first output of the second-stage frequency divider among the N frequency dividers is also connected to the first input of the N-2 second flip-flops and the first input of the MUX. The first output of the frequency dividers other than the first-stage and second-stage frequency dividers among the N frequency dividers is also connected to the second input of the N-2 second flip-flops. The output of the N-2 second flip-flops is connected to the N-2 second input of the MUX. The output of the MUX serves as the second output of the fractional-frequency multimode synchronous frequency divider.

[0021] The MUX is used to: select a target input terminal from the first input terminal of the MUX and N-2 second input terminals of the MUX based on the control signal received from the control terminal of the MUX, and output a second signal received from the target input terminal.

[0022] According to the present invention, a multi-mode synchronous frequency divider with fractional frequency division is provided, wherein the multi-mode synchronous frequency divider with fractional frequency division further includes a third flip-flop;

[0023] The MUX is used as the second output terminal of the fractional frequency divider multimode synchronous frequency divider via the third flip-flop.

[0024] The output of the MUX is connected to the second input of the third flip-flop. The first input of the third flip-flop is used to receive the input clock synchronization signal, and the output of the third flip-flop serves as the second output of the fractional-frequency multimode synchronous frequency divider.

[0025] The third flip-flop is used to: output a signal received from the second input terminal of the third flip-flop based on the clock signal.

[0026] According to the present invention, a fractional-frequency multimode synchronous frequency divider further includes a buffer.

[0027] The first output of the second-stage frequency divider is connected to the first input of the N-2 second flip-flops through the buffer.

[0028] According to the present invention, a multi-mode synchronous frequency divider with fractional frequency division is provided, wherein the first flip-flop, the second flip-flop, and the third flip-flop are all D flip-flops (DFFs).

[0029] According to the present invention, a multi-mode synchronous frequency divider with fractional frequency division is provided, wherein the frequency divider is a two-three frequency divider.

[0030] The present invention also provides a phase-locked loop (PLL), comprising: a fractional-frequency multimode synchronous frequency divider as described in any of the above embodiments, wherein the fractional-frequency multimode synchronous frequency divider serves as a feedback frequency divider in the PLL.

[0031] The multi-mode synchronous frequency divider and PLL provided by this invention, at the input of the MMSD, through the first logic module, controls the output of the synchronization terminals of the subsequent N-1 stage frequency dividers to be high-level, which is considered to indicate that the current frequency division cycle has been completed. Then, a high-level output is sent to the first input terminal of the first flip-flop, so that the rising edge triggers the first flip-flop to output the corresponding frequency division ratio switching signal to the N frequency dividers. It can be understood that when the frequency division ratio switching signal input to the first flip-flop changes, it does not immediately change the state of the MMSD and the frequency division result. Instead, the frequency division ratio is switched after the current frequency division cycle is completed. In principle, the switching timing is set at a safe position in the frequency division cycle, realizing glue-free switching inside the MMSD, which can effectively improve the accuracy of the fractional frequency output by the PLL. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is one of the structural schematic diagrams of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of a PLL loop in related technologies;

[0035] Figure 3 This is a schematic diagram of the structure of MMD in related technologies;

[0036] Figure 4 This is a schematic diagram of the internal state cycle of the three-level MMSD provided by the present invention;

[0037] Figure 5 This is a schematic diagram of the two-three frequency divider in the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention;

[0038] Figure 6 This is the second schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention;

[0039] Figure 7 This is the third schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention;

[0040] Figure 8 This is the fourth schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention;

[0041] Figure 9 This is the fifth schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention;

[0042] Figure 10 This is a waveform diagram of MMD output in related technologies;

[0043] Figure 11 This is a schematic diagram of the waveform output of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention;

[0044] Figure 12 This is the sixth schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention.

[0045] Figure label:

[0046] 100: A multi-mode synchronous frequency divider with fractional frequency division;

[0047] 101: Frequency divider; 102: First logic module; 103: First flip-flop; 104: Second logic module; 105: Second flip-flop; 106: MUX; 107: Third flip-flop; 108: Buffer. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0049] The following description, in conjunction with the accompanying drawings, describes the fractional-frequency multimode synchronous frequency divider and PLL of the present invention.

[0050] Figure 1 This is one of the structural schematic diagrams of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention, such as... Figure 1 As shown, the fractional frequency divider 100 includes: N frequency dividers 101 connected in series, N-2 first logic modules 102 and N+1 first flip-flops 103 connected in series, where N is an integer greater than 2;

[0051] The circuit connection structure of the fractional frequency divider 100 multi-mode synchronous frequency divider is as follows:

[0052] In the N frequency dividers 101, the first output of the previous frequency divider is connected to the first input of the next frequency divider, and the second output of the next frequency divider is connected to the second input of the previous frequency divider. The first input of the first-stage frequency divider (stage_0) in the N frequency dividers 101 serves as the first input of the fractional-order multimode synchronous frequency divider 100 (for receiving the clkp signal), and the second input of the first-stage frequency divider serves as the second input of the fractional-order multimode synchronous frequency divider (for receiving the clkn signal). The first output of the Nth-stage frequency divider (stage_N-1) in the N frequency dividers 101 serves as the first output of the fractional-order multimode synchronous frequency divider 100. The synchronization terminals (flag terminals, used to output the flag signal) of the N-2 target frequency dividers correspond to... The N-2 target frequency dividers are the frequency dividers excluding the first-stage frequency divider and the Nth-stage frequency divider among the N frequency dividers 101, namely stage_1 to stage_N-2. The synchronization terminal of the Nth-stage frequency divider is connected to the second input terminal of the N-2th-stage first logic module among the N-2 first logic modules 102. In the N-2 first logic modules 102, the output terminal of the next stage first logic module is connected to the second input terminal of the previous stage first logic module. The output terminal of the first stage first logic module is connected to the first input terminal of the N+1 first flip-flops 103 (for receiving the load signal). The second input terminal of the N+1 first flip-flops 103 is used to receive the division ratio switching signal fbdiv.<n:0>The output terminals of the N+1 first flip-flops 103 are connected to the control terminals of the N frequency dividers 101 and the second input terminal of the Nth-level frequency divider 101.

[0053] The first logic module 102 is configured to output a high level when both the first input terminal and the second input terminal of the first logic module 102 are at a high level;

[0054] The first flip-flop 103 is configured to: when the signal received at the first input terminal of the first flip-flop 103 changes from a low level to a high level, output the frequency division ratio switching signal (including P) corresponding to the first flip-flop 103. <0> To P <n>).

[0055] It should be noted that if the previous stage divider is stage_0, then the next stage divider is stage_1; if the next stage divider is stage_1, then the previous stage divider is stage_0, and so on.

[0056] Optionally, the frequency divider is a two-to-three frequency divider.

[0057] The relevant technologies will be introduced below:

[0058] Figure 2 This is a schematic diagram of the structure of a PLL loop in related technologies, such as... Figure 2 As shown, the PFD simultaneously receives the input reference frequency signal (ck_ref signal) and the feedback signal (ck_fb signal), continuously compares the frequency and phase of these two signals, and inputs the processed signal to the charge pump (CP). The CP then outputs the processed signal to the VCO, and the VCO outputs the ck_out signal. Additionally, the Feedback Divider divides the high-speed signal output from the VCO and uses the divided signal as the ck_fb signal, which is then fed into the PFD and compared with the ck_ref signal for frequency and phase. This continuously adjusts the VCO frequency, ultimately locking the PLL loop. The commonly used structure for the Feedback Divider is the MMD.

[0059] The structure of MMD in related technologies is introduced below. Figure 3 This is a structural diagram of MMD in related technologies, such as Figure 3 As shown, the MMD is composed of multiple stages of frequency dividers (DIV2_3) connected in series. Specifically, it consists of stage 0 (DIV2_3), stage 1 (DIV2_3) to stage n (DIV2_3) connected in series. Stage 0 (DIV2_3) receives the first clock signal clk and outputs the processed data to stage 1 (DIV2_3), and so on, until it reaches stage n (DIV2_3). The output of stage n (DIV2_3) is used as the output of the MMD. Furthermore, stage 0 (DIV2_3), stage 1 (DIV2_3) to stage n (DIV2_3) also receive corresponding control signals P. <0> P <1> To P <n>Additionally, the nth level DIV2_3 will adjust the signal modi. <n>Returning to the previous level DIV2_3, and so on, until the transmission reaches level 0 DIV2_3, where level 0 DIV2_3 outputs the adjustment signal modi. <0> .

[0060] Specifically, the divider consists of four latches and logic gates forming a divider loop. Each stage of the divider can perform a divide-by-two or divide-by-three operation, achieved by adjusting the modi and P signals. When both modi and P are high, it performs a divide-by-three operation; otherwise, it performs a divide-by-two operation.

[0061] A single-stage frequency divider includes a 2-3 divider, where the 3-3 divider adds one more input signal cycle compared to the 2-2 divider. For an n-stage frequency divider, the weight of the added cycle in the nth stage is twice that of the (n-1)th stage, so the maximum number of added cycles in an n-stage frequency divider is 1 + 2. 1 +2 2 +…+2 n-1 =2 n -1;

[0062] For an n-level MMD, the minimum division ratio is 2. n Adding the above-mentioned increase in the number of cycles can achieve a frequency division ratio of 2. n ~2 n+1 Consecutive integers between -1 and 1. A frequency division ratio extension technique can be used to lock the higher-order stages to achieve variations in the stage number n, thus enabling a wide range of integer frequency division ratios.

[0063] It should be noted that the PLL supports outputting both integer and fractional frequencies. If a fractional frequency is desired, the SDM needs to continuously modulate the feedback divider, causing the output frequency of the feedback divider to jump back and forth between several adjacent division ratios, thereby dynamically adjusting the VCO frequency, which in turn dynamically adjusts the PLL's output frequency.

[0064] In addition, the spread spectrum clocking (SSC) function in the PLL also requires the frequency divider to scan the division ratio back and forth from low to high.

[0065] Both of these scenarios require the frequency division value of the feedback divider to switch continuously without glitch. However, existing multi-mode divider structures can glitch under certain conditions of continuous switching of the division ratio, leading to incorrect frequency division results. Furthermore, the duty cycle of existing dividers is very small at high division ratios.

[0066] To address the aforementioned issues, this invention proposes a Multi Modulus Synchronization Divider (MMSD) suitable for fractional frequency division, which simultaneously achieves a wide range of integer and fractional division ratios and has a high duty cycle output. Specifically, it employs synchronization technology to synchronize the input and output signals of the divider to a specific modulus period signal in an appropriate mode.

[0067] When the input division ratio switching signal changes at the input of MMSD, the MMSD state and division result will not change immediately. Instead, the division ratio will be switched after the current division cycle is completed, thus placing the switching timing at a safe position within the division cycle in principle.

[0068] At the output end of the MMSD, the MMSD itself outputs signals from multiple different ports. There is glitch when the frequency division ratio between adjacent ports is switched. In this embodiment of the invention, a suitable synchronization signal is first selected to synchronize the multiple output ports, and then the data selector (multiplexer, MUX) selects the correct port for output, which ensures both a high duty cycle and no glitch in the output.

[0069] Specifically, conventional frequency dividers directly input the signal controlling the division ratio into the divider, which is only suitable for situations where the division ratio is fixed. However, with fractional division, the division ratio is constantly changing, and data cannot be written to all positions within the divider's output cycle. Writing the division ratio data during a non-shared state will cause glitch. Therefore, it is necessary to find a suitable time to write new data when all division ratios are shared to avoid glitch.

[0070] The MMSD proposed in this invention cycles through a frequency division cycle according to a certain pattern. Taking a three-stage MMSD (which includes three 2 / 3 frequency dividers) as an example, Figure 4 This is a schematic diagram of the internal state cycle of the three-level MMSD provided by the present invention, as shown below. Figure 4 As shown, the state of each two-to-three divider changes cyclically within one division cycle, and all divisions share a common state for approximately one-quarter of a cycle (starting from state 888 and entering the common state). Each two-to-three divider has four latches (Q... L1 Q L2 Q L3 Q L4 The state transitions are shown in Table 1 below.

[0071] Table 1. State transition table of the four latches for each stage of the two-to-three frequency divider.

[0072] state <![CDATA[F in ]]> <![CDATA[F out ]]> <![CDATA[Mod out ]]> <![CDATA[Q L1 Q L2 Q L3 Q L4 ]]> 0 0 1 0 0000 1 0 1 1 0001 2 1 1 0 0010 3 0 1 1 0011 4 1 0 0 0100 5 1 0 1 0101 8 1 1 0 1000 C 0 0 0 1100

[0073] Among them, F in This indicates the current signal level of the input frequency divider, with 1 representing high and 0 representing low.

[0074] F out This indicates the current signal level of the output frequency divider, where 1 represents high and 0 represents low.

[0075] Mod out The value of modo represents the output signal level of the frequency divider at the current moment, where 1 represents high and 0 represents low.

[0076] In the input synchronization of MMSD, this embodiment of the invention performs AND logic on the flag signal output from the synchronization terminal of each stage of the MMSD's two-thirds frequency divider, and finally outputs a load signal to the first input terminal of the first flip-flop. The flag signal represents the output state of latch_1 within each stage of the two-thirds frequency divider (DIV2_3). Figure 5 This is a schematic diagram of the two-three frequency divider in the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention, as shown below. Figure 5 As shown in the table above, when the flag signal of a certain stage of the divide-and-converter goes high, it can be considered that this stage of the divide-and-converter is ready to write data and enters state "8". When the load signal goes high, it can be considered that each stage of the divide-and-converter is ready to write data, that is, each stage enters state "8". At this time, the cycle state enters several shared cycles, and a new division ratio switching signal can be written.

[0077] The frequency division ratio switching signal, which controls the change of the frequency division ratio, is sampled at the rising edge of the load signal and then triggered by the first flip-flop at P. <n:0>The synchronization signal is sent to the control terminal of the corresponding divider in the MMSD. When the load signal switches to 1 (high level), it indicates that the division ratio switching is allowed. If the load signal is 0, the division ratio switching signal fbdiv is not enabled. <n:0>If a change has occurred, it is necessary to wait for the load signal to flip, thus ensuring no glitch switching within the same level of MMSD.

[0078] It should be noted that the modo signal in the diagram represents the output position of the control signal for the second and third frequency division of this stage, for example... Figure 5 The first level of modi <2> The input modi signal, modi <1> This is the output modo signal.

[0079] In the multi-mode synchronous frequency divider with fractional frequency division provided in this embodiment of the invention, at the input terminal of the MMSD, the first logic module controls the output of the synchronization terminals of the subsequent N-1 stage frequency dividers to be high-level, which is considered to indicate that the current frequency division cycle has been completed. Then, a high-level output is sent to the first input terminal of the first flip-flop, so that the rising edge triggers the first flip-flop to output the corresponding frequency division ratio switching signal to the N frequency dividers. It can be understood that when the frequency division ratio switching signal input to the first flip-flop changes, it will not immediately change the state of the MMSD and the frequency division result. Instead, the frequency division ratio is switched after the current frequency division cycle is completed. In principle, the switching timing is set at a safe position in the frequency division cycle, realizing glitch-free switching inside the MMSD, which can effectively improve the accuracy of the fractional frequency output by the PLL.

[0080] Optionally, Figure 6 This is the second schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention, as shown below. Figure 6 As shown, the fractional-frequency multimode synchronous frequency divider 100 also includes a second logic module 104;

[0081] The output of the first logic module of the first stage is connected to the first input of the N+1 first flip-flops 103 through the second logic module 104; wherein, the output of the first logic module of the first stage is connected to the second input of the second logic module 104, the first input of the second logic module 104 is used to receive the start signal (rst signal), and the output of the second logic module 104 is connected to the first input of the N+1 first flip-flops 103;

[0082] The second logic module 104 is configured to: output a first signal upon receiving the start signal;

[0083] The first trigger 103 is further configured to: output the division ratio switching signal corresponding to the first trigger when the first signal is received.

[0084] Specifically, in this embodiment of the invention, a second logic module is provided, and a first signal (rst signal) is added to prevent deadlock from occurring. This avoids the situation where the first input terminal of the first flip-flop does not have an initial rising edge during initialization. This embodiment of the invention can ensure that the first flip-flop successfully writes the frequency division ratio switching signal on the first attempt.

[0085] Optionally, such as Figure 6 As shown, the second logic module 104 includes a second AND gate;

[0086] The first input terminal of the second AND gate serves as the first input terminal of the second logic module 104, the second input terminal of the second AND gate serves as the second input terminal of the second logic module 104, and the output terminal of the second AND gate serves as the output terminal of the second logic module 104.

[0087] Optionally, such as Figure 6 As shown, the first logic module 102 includes a first AND gate;

[0088] The first input terminal of the first AND gate serves as the first input terminal of the first logic module 102, the second input terminal of the first AND gate serves as the second input terminal of the first logic module 102, and the output terminal of the first AND gate serves as the output terminal of the first logic module 102.

[0089] Optionally, the following describes the output synchronization of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention.

[0090] Figure 7 This is the third schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention, as shown below. Figure 7 As shown, the fractional-frequency divider multimode synchronous frequency divider 100 also includes: N-2 second flip-flops 105 and MUX 106;

[0091] It should be noted that, in order to clearly demonstrate the circuit structure of the output synchronization, Figure 7 The first logic module 102 and the first flip-flop 103, as well as the related circuit connection structure, are not shown in the diagram.

[0092] The first output terminal of the second-stage frequency divider among the N frequency dividers 101 is also connected to the first input terminal of the N-2 second flip-flops 105 and the first input terminal of the MUX 106. The first output terminals of the frequency dividers 101 other than the first-stage frequency divider and the second-stage frequency divider are also connected to the second input terminals of the N-2 second flip-flops 105. The output terminals of the N-2 second flip-flops 105 are connected to the N-2 second input terminals of the MUX 106. The output terminal of the MUX 106 serves as the second output terminal of the fractional-frequency multimode synchronous frequency divider 100.

[0093] The MUX 106 is used to: select a target input terminal from the first input terminal of the MUX 106 and the N-2 second input terminals of the MUX 106 based on the control signal received from the control terminal of the MUX 106, and output a second signal received from the target input terminal.

[0094] Specifically, in output synchronization, the output method of the MMSD of the present invention is to use the output of each stage by dividing and splitting the frequency as the output signal. Taking N=8 as an example, the frequency division of each port output is shown in Table 2 below.

[0095] Table 2 Frequency division ratio of each port output

[0096] Output port v<2> v<3> v<4> v<5> v<6> v<7> Frequency division ratio 8～15 16～31 32～63 64～127 128～255 256～511

[0097] Because there is a certain delay in signal propagation between different frequency dividers, glitch can occur when switching at a specific division ratio. For example... Figure 7 As shown, the output v of the second-stage frequency divider can be... <1> The same frequency signal is used as the second flip-flop for synchronizing the clock input to v. <2> to v <7> Then, the MUX selects the output port.

[0098] In related technologies, there is glitch between the output ports of MMD when the adjacent division ratios are switched. In this embodiment of the invention, a suitable synchronization signal is selected to synchronize the output ports. Specifically, the output signal of the second-stage divider is selected as the synchronization signal to synchronize the output ports. Then, the result of the MUX selecting the correct output port is used as the final output, which ensures both a high duty cycle and no glitch in the output.

[0099] Optionally, such as Figure 7 As shown, the fractional-frequency multimode synchronous frequency divider 100 also includes a third flip-flop 107;

[0100] The MUX 106 serves as the second output terminal of the fractional-frequency multimode synchronous frequency divider 100 via the third flip-flop 107;

[0101] The output of the MUX 106 is connected to the second input of the third flip-flop 107. The first input of the third flip-flop 107 is used to receive the input clock synchronization signal (clk signal), and the output of the third flip-flop 107 serves as the second output of the fractional-frequency multimode synchronous frequency divider 100.

[0102] The third flip-flop 107 is used to: output a signal received from the second input terminal of the third flip-flop 107 based on the clock signal.

[0103] Specifically, a third flip-flop is set between the MUX and the second output of the fractional-mode synchronous frequency divider. The third flip-flop is triggered by the input clock synchronization signal, which can effectively reduce the delay and noise accumulated by the MMSD and enhance the waveform of the MMSD output.

[0104] Optionally, such as Figure 7 As shown, the fractional-frequency multimode synchronous frequency divider 100 also includes a buffer 108;

[0105] The first output of the second-stage frequency divider is connected to the first input of the N-2 second flip-flops 105 via the buffer 108.

[0106] Specifically, a buffer is set between the second-stage frequency divider and the second flip-flop. The signal output from the first output terminal of the second-stage frequency divider can achieve a reasonable phase after passing through the buffer, and serve as the clock signal input for the second flip-flop, synchronizing all signals at the second input terminal of the second flip-flop.

[0107] Optionally, the first, second, and third flip-flops mentioned above can all be D flip-flops (DFF).

[0108] On the other hand, the present invention also provides a PLL, comprising: a fractional-frequency multimode synchronous divider as described in any of the above embodiments, wherein the fractional-frequency multimode synchronous divider serves as a feedback divider in the PLL.

[0109] The following example illustrates the multi-mode synchronous frequency divider with fractional frequency division provided in this embodiment of the invention, taking N=8, a frequency divider of two-three, a first logic module and a second logic module both including AND gates, and a first flip-flop, a second flip-flop and a third flip-flop all being DFFs.

[0110] Figure 8 This is a schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention.

[0111] Fourth, such as Figure 8 As shown, the control frequency division ratio switching signal is fbdiv<8:0>, which is then applied via load.

[0112] After the signal is sampled on the rising edge, the synchronization signal P<8:0> is sent to the eight divider dividers in the MMSD. When the load signal switches to 1, it means that writing to switch the divider ratio is allowed. If the divider ratio switching signal fbdiv<8:0> has changed when the load signal is 0, it is necessary to wait for the load signal to flip. This ensures that there is no glitch switching within the same number of MMSDs.

[0113] In addition, an rst signal was added to the last AND gate before the load signal output to prevent deadlock. This avoids the load not having an initial rising edge during initialization, ensuring that the first fbdiv<8:0> data is successfully written.

[0114] Figure 9 This is the fifth schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention, as shown below. Figure 9 As shown, in output synchronization, the MMSD of this invention uses the output of each stage's two-to-three division ratio as the output signal. Because there is a certain delay in signal propagation between different stages, glitch occurs when switching at a specific division ratio. Figure 9 As shown, v <1> Same frequency signal as synchronous clock input DFF synchronous v <2> to v <7> Then, the MUX selects the output port, and the selected signal is synchronized with a first-level DFF to obtain the output signal.

[0115] Figure 10 This is a waveform diagram of MMD output in related technologies, such as... Figure 10 As shown, the phase relationship of the output waveform can be seen. Before synchronization, v <2> to v <7> Each stage has a delay of about 40ps, so glitch occurs when switching between the division ratios of the two ports.

[0116] Figure 11 This is a schematic diagram of the waveform output of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention, as shown below. Figure 11 As shown, this embodiment of the invention eliminates the latency caused by transmission between each stage, achieving glitch-free switching between different ports. The MUX selection signal is composed of fbdiv<8:0> combinational logic, and the third flip-flop uses the input clock synchronization signal to effectively reduce the latency and noise accumulated by MMSD.

[0117] Figure 12 This is the sixth schematic diagram of the multi-mode synchronous frequency divider with fractional frequency division provided by the present invention, as shown below. Figure 12 As shown in the figure, this figure is the overall structure diagram of the MMSD provided by the present invention. After implementing the input and output synchronization method provided in the embodiment of the present invention, this MMSD achieves continuous fractional frequency division switching between 8 and 511 without glitch, and achieves a high duty cycle (25% to 50%). In addition, the continuous integer frequency division range of this frequency divider is 4 to 511.

[0118] In this embodiment of the invention, a multi-mode synchronous frequency divider suitable for fractional frequency division PLL is proposed, which realizes glitch-free switching between continuous integer frequency division between 4 and 511 and continuous fractional frequency division between 8 and 511, and achieves high duty cycle (25% to 50%) for all frequency division ratios.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. < / n> < / n> < / n>

Claims

1. A multi-mode synchronous frequency divider with fractional frequency division, characterized in that, include: N frequency dividers connected in series, N-2 first logic modules connected in series, and N+1 first flip-flops, where N is an integer greater than 2; In the N frequency dividers, the first output of the preceding frequency divider is connected to the first input of the following frequency divider, and the second output of the following frequency divider is connected to the second input of the preceding frequency divider. The first input of the first-stage frequency divider serves as the first input of the fractional-frequency-division multimode synchronous frequency divider, and the second input of the first-stage frequency divider serves as the second input of the fractional-frequency-division multimode synchronous frequency divider. The first output of the Nth-stage frequency divider serves as the first output of the fractional-frequency-division multimode synchronous frequency divider. The synchronization terminals of N-2 target frequency dividers are correspondingly connected to the first inputs of the N-2 first logic modules. The frequency divider is any of the N frequency dividers except for the first-stage frequency divider and the Nth-stage frequency divider. The synchronization terminal of the Nth-stage frequency divider is connected to the second input terminal of the (N-2)th-stage first logic module in the N-2 first logic modules. In the N-2 first logic modules, the output terminal of the next-stage first logic module is connected to the second input terminal of the previous-stage first logic module. The output terminal of the first-stage first logic module is connected to the first input terminal of the N+1 first flip-flops. The second input terminal of the N+1 first flip-flops is used to receive the division ratio switching signal. The output terminal of the N+1 first flip-flops is correspondingly connected to the control terminal of the N frequency dividers and the second input terminal of the Nth-stage frequency divider. The first logic module is configured to: output a high level when both the first input terminal and the second input terminal of the first logic module are at a high level; The first flip-flop is used to output the frequency division ratio switching signal corresponding to the first flip-flop when the signal received at the first input terminal of the first flip-flop changes from low level to high level.

2. The multi-mode synchronous frequency divider with fractional frequency division according to claim 1, characterized in that, The fractional-frequency multimode synchronous frequency divider also includes a second logic module; The output of the first logic module of the first stage is connected to the first input of the N+1 first flip-flops through the second logic module; wherein, the output of the first logic module of the first stage is connected to the second input of the second logic module, the first input of the second logic module is used to receive a start signal, and the output of the second logic module is connected to the first input of the N+1 first flip-flops; The second logic module is configured to: output a first signal upon receiving the start signal; The first trigger is further configured to: upon receiving the first signal, output a frequency division ratio switching signal corresponding to the first trigger.

3. The multi-mode synchronous frequency divider with fractional frequency division according to claim 2, characterized in that, The second logic module includes a second AND gate; The first input terminal of the second AND gate serves as the first input terminal of the second logic module, the second input terminal of the second AND gate serves as the second input terminal of the second logic module, and the output terminal of the second AND gate serves as the output terminal of the second logic module.

4. The multi-mode synchronous frequency divider with fractional frequency division according to any one of claims 1 to 3, characterized in that, The first logic module includes a first AND gate; The first input terminal of the first AND gate serves as the first input terminal of the first logic module, the second input terminal of the first AND gate serves as the second input terminal of the first logic module, and the output terminal of the first AND gate serves as the output terminal of the first logic module.

5. The multi-mode synchronous frequency divider with fractional frequency division according to claim 4, characterized in that, The fractional-frequency divider multimode synchronous frequency divider also includes N-2 second flip-flops and a data selector MUX; The first output of the second-stage frequency divider among the N frequency dividers is also connected to the first input of the N-2 second flip-flops and the first input of the MUX. The first output of the frequency dividers other than the first-stage and second-stage frequency dividers among the N frequency dividers is also connected to the second input of the N-2 second flip-flops. The output of the N-2 second flip-flops is connected to the N-2 second input of the MUX. The output of the MUX serves as the second output of the fractional-frequency multimode synchronous frequency divider. The MUX is used to: select a target input terminal from the first input terminal of the MUX and N-2 second input terminals of the MUX based on the control signal received from the control terminal of the MUX, and output a second signal received from the target input terminal.

6. The multi-mode synchronous frequency divider with fractional frequency division according to claim 5, characterized in that, The fractional frequency divider multimode synchronous frequency divider also includes a third trigger; The MUX is used as the second output terminal of the fractional frequency divider multimode synchronous frequency divider via the third flip-flop. The output of the MUX is connected to the second input of the third flip-flop. The first input of the third flip-flop is used to receive the input clock synchronization signal, and the output of the third flip-flop serves as the second output of the fractional-frequency multimode synchronous frequency divider. The third flip-flop is used to: output a signal received from the second input terminal of the third flip-flop based on the clock synchronization signal.

7. The multi-mode synchronous frequency divider with fractional frequency division according to claim 6, characterized in that, The fractional-frequency multimode synchronous frequency divider also includes a buffer; The first output of the second-stage frequency divider is connected to the first input of the N-2 second flip-flops through the buffer.

8. The multi-mode synchronous frequency divider with fractional frequency division according to claim 7, characterized in that, The first flip-flop, the second flip-flop, and the third flip-flop are all D flip-flops (DFFs).

9. The multi-mode synchronous frequency divider with fractional frequency division according to claim 8, characterized in that, The frequency divider is a two-to-three frequency divider.

10. A phase-locked loop (PLL), characterized in that, include: The fractional-frequency multimode synchronous frequency divider as described in any one of claims 1 to 9, wherein the fractional-frequency multimode synchronous frequency divider serves as a feedback frequency divider in the PLL.

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