Time-interleaved analog-to-digital converter

Abstract

A time-interleaved analog-to-digital converter includes multiple coarse converter circuits, a control logic circuit, multiple first and second transfer circuits, a fine converter circuit, and an encoder circuit. The multiple coarse converter circuits sequentially sample input signals and perform multiple coarse conversions to generate multiple decision signals. The control logic circuit generates multiple coarse digital codes based on the decision signals. The multiple first and second transfer circuits transfer multiple first and second residual value signals, respectively. The fine converter circuits perform fine conversion based on the corresponding first and second residual value signals to generate fine digital codes. The sampling period for sampling the input signal and the coarse conversion period for performing coarse conversion are set based on the fine conversion period for performing fine conversion. The encoder circuit generates a digital output based on the corresponding coarse and fine digital codes.

Description

Technical Field

[0001] The present disclosure relates to a time-interleaved analog-to-digital converter (ADC), and more particularly to a time-interleaved ADC with a noise shaping function and multiple operation timings. Background Art

[0002] Analog-to-digital converters (ADCs) are commonly found in various electronic devices, converting analog signals into corresponding digital signals for subsequent signal processing. As operating speeds increase, the operating period within which ADCs can convert signals becomes shorter and shorter. Consequently, the specifications required for certain ADC circuits (e.g., sampling circuits, comparator circuits, etc.) (e.g., switching speed, power consumption, etc.) are becoming increasingly stringent, significantly increasing the difficulty of implementing ADC circuits suitable for high-speed applications. Summary of the Invention

[0003] In some embodiments, one of the objectives of the present disclosure is (but not limited to) to provide a time-interleaved analog-to-digital converter with multiple operation timings applicable to high-speed applications and high signal-to-noise ratio.

[0004] In some embodiments, a time-interleaved analog-to-digital converter includes a plurality of coarse converter circuit systems, a control logic circuit, a plurality of first transfer circuits, a fine converter circuit system, a plurality of second transfer circuits, and an encoder circuit. The plurality of coarse converter circuit systems sequentially samples an input signal and performs a plurality of coarse analog-to-digital conversions to generate a plurality of decision signals. The control logic circuit generates a plurality of coarse digital codes corresponding to the coarse analog-to-digital conversions based on the decision signals. The plurality of first transfer circuits sequentially transfer a plurality of first residual value signals from the coarse converter circuit systems based on a plurality of first control signals, wherein the first residual value signals are generated by the coarse analog-to-digital conversions performed sequentially by the coarse converter circuit systems. The fine converter circuit system is configured to perform fine analog-to-digital conversion based on a first signal among the first residual value signals and a second signal among the second residual value signals to generate a fine digital code, wherein a sampling period during which each of the coarse converter circuit systems samples the input signal and a coarse conversion period during which each of the coarse analog-to-digital conversions is performed are set based on a fine conversion period during which the fine converter circuit system performs the fine analog-to-digital conversion. A plurality of second transfer circuits are configured to sequentially transfer the second residual value signals from the coarse converter circuit systems to the fine converter circuit system based on a plurality of second control signals, wherein the second residual value signals are generated by the coarse converter circuit systems in response to the fine analog-to-digital conversion. An encoder circuit is configured to generate a digital output based on a corresponding one of the coarse digital codes and the fine digital code.

[0005] The features, implementation and technical effects of the present disclosure are described in detail below with reference to the accompanying drawings for preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of a time-interleaved analog-to-digital converter according to some embodiments of the present disclosure is shown;

[0007] Figure 2 A schematic diagram of a time-interleaved analog-to-digital converter according to some embodiments of the present disclosure is shown;

[0008] Figure 3 According to some embodiments of the present disclosure Figure 1 (or Figure 2 ) is a schematic diagram of a first operation timing of the time-interleaved analog-to-digital converter;

[0009] Figure 4 According to some embodiments of the present disclosure Figure 1 (or Figure 2 ) is a schematic diagram of a second operation timing of the time-interleaved analog-to-digital converter;

[0010] Figure 5 According to some embodiments of the present disclosure Figure 1 (or Figure 2 ) is a schematic diagram of a third operation timing of the time-interleaved analog-to-digital converter; and

[0011] Figure 6 According to some embodiments of the present disclosure Figure 1 (or Figure 2 ) is a schematic diagram of the fourth operation timing of the time-interleaved analog-to-digital converter.

[0012] Explanation of symbols

[0013] 100, 200: Time-interleaved analog-to-digital converter

[0014] 110, 120, 130, 140: Coarse converter circuit system

[0015] 111, 121, 131, 141: Capacitor array circuits

[0016] 112, 122, 132, 142, 170: Quantizer circuits

[0017] 150: Control logic circuit

[0018] 151, 152, 153, 154, T1-T4: transfer circuit

[0019] 160: Noise shaping circuit

[0020] 175: Thin converter circuit system

[0021] 180: Encoder circuit

[0022] 205: Summing Circuit

[0023] CLK 1C , CLK 2C , CLK 3C , CLK 4C : Control signal

[0024] CLK 1F , CLK 2F , CLK 3F , CLK 4F : Control signal

[0025] CLK 1S , CLK 2S , CLK 3S , CLK 4S : Control signal

[0026] CLK 1T , CLK 2T , CLK 3T , CLK 4T : Control signal

[0027] D1~D4: coarse digital code

[0028] DO1: Fine digital code

[0029] DO2: Digital output

[0030] S10, S20, S30, S40: sampling signals

[0031] S11, S21, S31, S41: Decision signals

[0032] SI: Signal

[0033] VIN: input signal

[0034] VRES1, VRES2: residual value signals

[0035] t1, t2, t3, t4, t5, t6, t7, t8, t9, t10: period DETAILED DESCRIPTION

[0036] All terms used herein have their ordinary meanings. The definitions of the aforementioned terms in commonly used dictionaries, including any usage examples of any term discussed herein, are provided for illustrative purposes only and should not limit the scope and meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments described herein.

[0037] As used herein, the terms "coupled" or "connected" may refer to direct physical or electrical contact between two or more elements, or indirect physical or electrical contact between two or more elements, or to the mutual operation or action of two or more elements. As used herein, the term "circuitry" may refer to a single system formed by at least one circuit, and the term "circuit" may refer to a device composed of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0038] As used herein, "about," "close," or "the same" generally refers to an error or range of about 20% of the actual value, preferably about 10%, and more preferably about 5%. Unless otherwise specified, the numerical values ​​mentioned are deemed to be approximate values, that is, the error or range indicated by "about," "close," or "the same."

[0039] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. Terms such as first, second, and third are used herein to describe and identify individual elements. Thus, a first element herein could also be referred to as a second element without departing from the spirit of the present disclosure. For ease of understanding, similar elements in the drawings will be designated with the same reference numerals.

[0040] In some embodiments, the implementation of some circuits may refer to the relevant circuits in the first document (U.S. Patent No. 10,763,875), the second document (U.S. Patent No. 10,778,242), and the third document (U.S. Patent No. 10,790,843), but the implementation of these circuits is not limited to the implementations mentioned in the above documents.

[0041] In some embodiments, coarse analog-to-digital conversion (hereinafter referred to as coarse conversion) is analog-to-digital conversion performed on a sampled input signal, and fine analog-to-digital conversion (hereinafter referred to as fine conversion) is analog-to-digital conversion performed based on the results of noise shaping, wherein the noise shaping is performed based on the residual value generated by the previous analog-to-digital conversion. In some embodiments, noise shaping can be used to feed back a residual signal (e.g., residual signal VRES1 and / or residual signal VRES2, described below) to the input of a quantizer circuit (e.g., quantizer circuit 170, described below). Through noise shaping, the spectral characteristics of the noise (particularly the quantization noise) can be modified (i.e., shaped) so that the noise has lower power in the low-frequency band. As a result, the desired signal can have a higher signal-to-noise ratio in the low-frequency band.

[0042] Figure 1 FIG1 is a schematic diagram of a time-interleaved analog-to-digital converter 100 according to some embodiments of the present disclosure. The time-interleaved analog-to-digital converter 100 includes a plurality of coarse converter circuits 110 , 120 , 130 , and 140 , a control logic circuit 150 , a plurality of transfer circuits T1 - T4 , a plurality of transfer circuits 151 - 154 , a fine converter circuit 175 , and an encoder circuit 180 .

[0043] Coarse converter circuit systems 110, 120, 130, and 140 sequentially sample input signal VIN and perform coarse conversions to generate decision signals S11, S21, S31, and S41. Control logic circuit 150 generates coarse digital codes D1-D4 corresponding to the coarse conversions based on decision signals S11, S21, S31, and S41. In some embodiments, control logic circuit 150 may be implemented by logic circuits that execute a specific algorithm (e.g., but not limited to, a successive approximation algorithm, a binary search algorithm, etc.).

[0044] Specifically, the coarse converter circuit system 110 includes a capacitor array circuit 111 and a quantizer circuit 112. The capacitor array circuit 111 is controlled by a control signal CLK. 1S The quantizer circuit 112 is coupled to the capacitor array circuit 111 to receive the sampled signal S10 and to generate a sampled signal S10 according to the control signal CLK. 1C A corresponding coarse conversion is performed on the sampled signal S10 to generate a corresponding decision signal S11. The control logic circuit 150 may execute the aforementioned specific algorithm based on the decision signal S11 to generate a corresponding coarse digital code D1. In some embodiments, the coarse conversion may be a successive approximation register analog-to-digital conversion, wherein the control logic circuit 150 may switch the capacitor array circuit 111 based on the results of the specific algorithm to gradually generate multiple bits of the coarse digital code D1.

[0045] Similarly, the coarse converter circuit system 120 includes a capacitor array circuit 121 and a quantizer circuit 122. The coarse converter circuit system 130 includes a capacitor array circuit 131 and a quantizer circuit 132. The coarse converter circuit system 140 includes a capacitor array circuit 141 and a quantizer circuit 142. The capacitor array circuit 121, the control signal CLK 2S and the corresponding relationship between the sampling signal S20, the capacitor array circuit 131, the control signal CLK 3S and the corresponding relationship between the sampling signal S30, the capacitor array circuit 141, the control signal CLK 4S and the corresponding relationship between the sampling signal S40 can refer to the capacitor array circuit 111, the control signal CLK1S The corresponding relationship between the quantizer circuit 122 and the control signal CLK is omitted. 2C , the corresponding relationship between the decision signal S21 and the coarse digital code D2, the quantizer circuit 132, the control signal CLK 3C , the corresponding relationship between the decision signal S31 and the coarse digital code D3, and the quantizer circuit 142, the control signal CLK 4C The corresponding relationship between the decision signal S41 and the coarse digital code D4 can refer to the quantizer circuit 112 and the control signal CLK 1C , the corresponding relationship between the decision signal S11 and the coarse digital code D1 is not repeated here.

[0046] In some embodiments, the implementation of each of the plurality of capacitor array circuits 111, 121, 131, and 141 may refer to the capacitor C1 in the first reference or the capacitor array circuit CT1 in the second and third references, but the present disclosure is not limited thereto. In this example, each of the plurality of sample signals S10, S20, S30, and S40 may be the signal on the node N1 mentioned in the first, second, and / or third references, but the present disclosure is not limited thereto.

[0047] The plurality of transfer circuits T1 to T4 are used to control the plurality of control signals CLK. 1T , CLK 2T , CLK 3T and CLK 4T The plurality of first residual signals are sequentially transferred from the plurality of coarse converter circuit systems 110, 120, 130, and 140, wherein the first residual signals are generated by the plurality of coarse converter circuit systems 110, 120, 130, and 140 performing the coarse conversion in sequence. Specifically, each transfer circuit T1-T4 is configured to transfer the first residual signals to the plurality of coarse converter circuit systems 110, 120, 130, and 140 according to the plurality of control signals CLK after a corresponding coarse converter circuit system in the plurality of coarse converter circuit systems 110, 120, 130, and 140 completes a corresponding coarse conversion. 1T , CLK 2T , CLK 3T and CLK 4T A corresponding one of the coarse converter circuits transmits the corresponding sampled signal from the capacitor array circuit in the corresponding coarse converter circuit system as a corresponding first residual signal. For example, after the coarse converter circuit system 110 completes the coarse conversion, the first residual signal is the signal on the capacitor array circuit 111. After the coarse converter circuit system 110 completes the coarse conversion, the transfer circuit T1 is connected to the capacitor array circuit 111 according to the control signal CLK. 1TThe capacitor array circuit 111 is turned on to transmit the sampled signal S10 as the corresponding first residual signal. Similarly, the corresponding relationship between the remaining plurality of first residual signals, the plurality of coarse converter circuit systems 120, 130, and 140, and the transfer circuits T2-T4 can be understood. In some embodiments, each of the transfer circuits T1-T4 can be implemented by a switching circuit, but the present disclosure is not limited thereto.

[0048] The fine converter circuit system 175 is used to convert a first signal (hereinafter referred to as residual signal VRES1, indicated at Figures 3 to 6 ) and a second signal among the plurality of second residual value signals (hereinafter referred to as residual value signal VRES2, indicated at Figures 3 to 6 ) performs fine conversion to generate a fine digital code DO1. For example, the fine converter circuit system 175 may perform noise shaping based on the residual signal VRES2, and perform analog-to-digital conversion based on the noise shaping result (e.g., signal SI) and the residual signal VRES1 to generate the fine digital code DO1. In various embodiments, a sampling period for each of the plurality of coarse converter circuit systems 110, 120, 130, and 140 to sample the input signal VIN and a coarse conversion period for each coarse conversion may be set based on a fine conversion period for the fine converter circuit system 175 to perform fine conversion. The configuration method herein will be described later. Figures 3 to 6 illustrate.

[0049] The plurality of transfer circuits 151-154 are used to control the plurality of control signals CLK 1F , CLK 2F , CLK 3F and CLK 4F The plurality of coarse converter circuit systems 110, 120, 130, and 140 sequentially transfer a plurality of second residual value signals to the fine converter circuit system 175. In some embodiments, the plurality of second residual value signals are generated by the coarse converter circuit systems 110, 120, 130, and 140 in response to the fine conversion. For example, each of the plurality of transfer circuits 151-154 may be configured to receive a plurality of control signals CLK when the fine conversion performed after a corresponding one of the plurality of coarse analog-to-digital conversions is completed. 1F , CLK 2F , CLK 3F and CLK 4FA corresponding one of the coarse converter circuits transfers the sampled signal from the capacitor array circuit in the corresponding coarse converter circuit system to a corresponding one of the plurality of second residual signals. For example, fine converter circuit system 175 may perform fine conversion based on residual signal VRES1 from coarse converter circuit system 110. After the fine conversion is completed, sampled signal S10 on capacitor array circuit 111 in coarse converter circuit system 110 is residual signal VRES2. Transfer circuit 151 may receive a corresponding one of the plurality of second residual signals based on control signal CLK. 1F The residual signal VRES2 (ie, the sampling signal S10) is transmitted to the noise shaping circuit 160. The operation here will be referred to later. Figure 3 Detailed description.

[0050] Specifically, the fine converter circuit system 175 includes a noise shaping circuit 160 and a quantizer circuit 170. The noise shaping circuit 160 is coupled to the plurality of transfer circuits 151-154 to sequentially receive the plurality of second residual signals and perform noise shaping based on the residual signal VRES2 to generate a signal SI (equivalent to the noise shaping result). The quantizer circuit 170 sequentially receives the plurality of first residual signals from the plurality of transfer circuits T1-T4 and generates a fine digital code DO1 based on the residual signal VRES1 and the signal SI. In this embodiment, the quantizer circuit 170 may be a comparator circuit having more than two input terminals. For example, the comparator circuit may include two input pairs (corresponding to the plurality of input terminals described above), one input pair receiving the residual signal VRES1 and the other input pair receiving the signal SI. The comparator circuit may generate the fine digital code DO1 based on the sum of the residual signal VRES1 and the signal SI. In some embodiments, the noise shaping circuit 160 may include an integrator circuit and a circuit portion for storing the residual signal VRES2. In some embodiments, the implementation of the plurality of transfer circuits 151-154 can refer to the third document. Figure 5 The implementation of the multiple capacitors Cex5-Cex6 in A and the noise shaping circuit 160 can refer to the third document. Figure 5 The implementation of the circuit 120 (or circuit 122) in A and the quantizer circuit 170 can refer to the third document. Figure 5 A, but the disclosure is not limited thereto.

[0051] Encoder circuit 180 is configured to generate a digital output DO2 based on a corresponding one of a plurality of coarse digital codes D1-D4 and fine digital code DO1. For example, when fine digital code DO1 is generated based on the first residual signal from coarse converter circuitry 110 (i.e., when residual signal VRES1 is from capacitor array circuit 111), encoder circuit 180 may combine fine digital code DO1 with the coarse digital code D1 corresponding to coarse converter circuitry 110 to generate digital output DO2. Similarly, when fine digital code DO1 is generated based on the first residual signal from coarse converter circuitry 120 (i.e., when residual signal VRES1 is from capacitor array circuit 121), encoder circuit 180 may combine fine digital code DO1 with the coarse digital code D2 corresponding to coarse converter circuitry 120 to generate digital output DO2. Similarly, the relationship between the plurality of coarse digital codes D1-D4, fine digital code DO1, and digital output DO2 can be understood. In some embodiments, encoder circuit 180 may be implemented by a plurality of digital logic circuits.

[0052] Figure 2 FIG2 is a schematic diagram of a time-interleaved analog-to-digital converter 200 according to some embodiments of the present disclosure. Figure 1 In the time-interleaved ADC 100, in the time-interleaved ADC 200, the fine converter circuit system 175 further includes a summing circuit 205, which is configured to sum the residual signal VRES1 (i.e., a corresponding one of the plurality of sampled signals S10, S20, S30, and S40) with the signal SI. In this embodiment, the quantizer circuit 170 may be a comparator circuit having two input terminals, one of which may receive the sum of the residual signal VRES1 and the signal SI from the summing circuit 205, and the other input terminal (not shown) may receive a common-mode voltage (or reference voltage). The quantizer circuit 170 may perform quantization based on the sum of the residual signal VRES1 and the signal SI to generate the fine digital code DO1. In some embodiments, the summing circuit 205 may be implemented by a switched capacitor circuit. For example, the implementation of the quantizer circuit 170 may refer to the comparator circuit 220 in the first document, and the implementation of the summing circuit 205 may refer to the switching circuit 120 in the first document, but the present disclosure is not limited thereto.

[0053] Figure 3 According to some embodiments of the present disclosure Figure 1 The time-interleaved analog-to-digital converter 100 (or Figure 2 Schematic diagram of a first operation timing of the time-interleaved analog-to-digital converter 200 in FIG.

[0054] For ease of understanding, Figures 3 to 6In the embodiment of the present invention, "operation name" is supplemented by "(number)" to indicate the length of time that a specific circuit system performs a specific operation (e.g., coarse conversion or sampling), thereby indicating the time sequence of the coordinated operation of multiple circuit systems in the time-interleaved analog-to-digital converter 100 (or 200). For example, sampling (110) represents the sampling period during which the coarse converter circuit system 110 samples the input signal VIN, and coarse conversion (110) represents the coarse conversion period during which the coarse converter circuit system 110 performs coarse conversion. Similarly, it can be understood that sampling (120), sampling (130), and sampling (140) represent the sampling periods of the multiple coarse converter circuit systems 120, 130, and 140, respectively, and coarse conversion (120), coarse conversion (130), and coarse conversion (140) represent the coarse conversion periods of the multiple coarse converter circuit systems 120, 130, and 140, respectively. In addition, fine conversion (110) represents a fine conversion period of fine conversion performed by fine converter circuit system 175 in response to residual signal VRES1 from coarse converter circuit system 110. Similarly, it can be understood that a corresponding one of fine conversion (120), fine conversion (130), and fine conversion (140) represents a fine conversion period of fine conversion performed by fine converter circuit system 175 in response to residual signal VRES1 from a corresponding one of the plurality of coarse converter circuit systems 120, 130, and 140. In this embodiment, each of the fine conversion period, the coarse conversion period, and the sampling period has the same time length. In other words, during Figure 3 In the embodiment, each of the plurality of periods t1 to t10 has the same time length.

[0055] In this embodiment, when a first converter circuit system (e.g., coarse converter circuit system 110) among the plurality of coarse converter circuit systems 110, 120, 130, and 140 performs a first coarse conversion among the plurality of coarse conversions (e.g., during period t2), a second converter circuit system (e.g., coarse converter circuit system 120) among the plurality of coarse converter circuit systems 110, 120, 130, and 140 samples the input signal VIN. In other words, the coarse conversion period (e.g., coarse conversion (110)) of the first converter circuit system overlaps with the sampling period (e.g., sampling (120)) of the second converter circuit system.

[0056] Specifically, during period t1, the control signal CLK 1S Under this condition, the coarse converter circuit system 110 can sample the input signal VIN to generate the sampled signal S10. During period t2, the control signal CLK 1CUnder this condition, the coarse converter circuit system 110 can perform coarse conversion according to the sampling signal S10 to generate a decision signal S11, and the control logic circuit 150 can generate a coarse digital code D1 according to the decision signal S11. In response to this coarse conversion, the capacitor array circuit 111 generates a residual signal VRES1 (i.e., the sampling signal S10 after the coarse conversion is completed). In addition, during period t2, the control signal CLK 2S Under this condition, the coarse converter circuit system 120 can sample the input signal VIN to generate a sample signal S20.

[0057] During period t3, the control signal CLK 1T has an enable level. Under this condition, transfer circuit T1 can be turned on to transfer residual signal VRES1 (i.e., sampled signal S10) from capacitor array circuit 111 in coarse converter circuit system 110 to fine converter circuit system 175. Since coarse converter circuit system 140 has not yet begun operation during period t3, residual signal VRES2 during period t3 is 0 (and therefore not shown in period t3). Therefore, during period t3, fine converter circuit system 175 can perform fine conversion based on signal SI (which is the result of noise shaping based on residual signal VRES2 (which is 0 during period t3)) and residual signal VRES1 to generate fine digital code DO1. After fine digital code DO1 is generated, encoder circuit 180 can generate digital output DO2 based on coarse digital code D1 and fine digital code DO1. In response to this fine conversion, capacitor array circuit 111 generates residual signal VRES2 (i.e., sampled signal S10 after fine conversion). After the fine conversion is completed, the transfer circuit 151 can be controlled by the control signal CLK 1F The residual signal VRES2 (ie, the sampling signal S10) is transmitted to the noise shaping circuit 160. In addition, during the period t3, the control signal CLK 2C Under this condition, the coarse converter circuit system 120 can perform coarse conversion based on the sample signal S20 to generate a decision signal S21, and the control logic circuit 150 can generate a coarse digital code D2 based on the decision signal S21. In response to this coarse conversion, the capacitor array circuit 121 generates a residual signal VRES1 (i.e., the sample signal S20 after the coarse conversion is completed).

[0058] During period t4, the control signal CLK 2Thas an enable level. Under this condition, the transfer circuit T2 can be turned on to transfer the residual signal VRES1 (i.e., the sampling signal S20) from the capacitor array circuit 121 in the coarse converter circuit system 120 to the fine converter circuit system 175. The fine converter circuit system 175 can perform fine conversion based on the residual signal VRES1 from the coarse converter circuit system 120 and the signal SI (which is the noise shaping result performed based on the residual signal VRES2 from the coarse converter circuit system 110) to generate a fine digital code DO1. After the fine digital code DO1 is generated, the encoder circuit 180 can generate a digital output DO2 based on the coarse digital code D2 and the fine digital code DO1. In response to this fine conversion, the capacitor array circuit 121 generates the residual signal VRES2 (i.e., the sampling signal S20 after the fine conversion is performed). After this fine conversion is completed, the transfer circuit 152 can 2F The residual signal VRES2 (ie, the sampling signal S20 ) is transmitted to the noise shaping circuit 160 .

[0059] Similarly, during period t3, the control signal CLK 3S Under this condition, the coarse converter circuit system 130 can sample the input signal VIN to generate the sampled signal S30. During period t4, the control signal CLK 3C Under this condition, the coarse converter circuit system 130 can perform coarse conversion according to the sampling signal S30 to generate a decision signal S31, and the control logic circuit 150 can generate a coarse digital code D3 according to the decision signal S31. In response to this coarse conversion, the capacitor array circuit 131 generates a residual signal VRES1 (i.e., the sampling signal S30 after the coarse conversion is completed). In addition, during period t4, the control signal CLK 4S Under this condition, the coarse converter circuit system 140 can sample the input signal VIN to generate a sample signal S40.

[0060] During period t5, the control signal CLK 3Thas an enable level. Under this condition, the transfer circuit T3 can be turned on to transfer the residual signal VRES1 (i.e., the sampling signal S30) from the capacitor array circuit 131 in the coarse converter circuit system 130 to the fine converter circuit system 175. The fine converter circuit system 175 can perform fine conversion based on the residual signal VRES1 from the coarse converter circuit system 130 and the signal SI (which is the result of noise shaping performed based on the residual signal VRES2 from the coarse converter circuit system 120) to generate a fine digital code DO1. After the fine digital code DO1 is generated, the encoder circuit 180 can generate a digital output DO2 based on the coarse digital code D3 and the fine digital code DO1. In response to this fine conversion, the capacitor array circuit 131 generates the residual signal VRES2 (i.e., the sampling signal S30 after the fine conversion is performed). After this fine conversion is completed, the transfer circuit 153 can 3F The residual signal VRES2 (ie, the sampling signal S30) is transmitted to the noise shaping circuit 160. In addition, during the period t5, the control signal CLK 4C With an enable level and a control signal CLK 1S Under this condition, the coarse converter circuit system 140 can perform coarse conversion based on the sample signal S40 to generate a decision signal S41, and the control logic circuit 150 can generate a coarse digital code D4 based on the decision signal S41. In response to this coarse conversion, the capacitor array circuit 141 generates a residual signal VRES1 (i.e., the sample signal S40 after the coarse conversion is completed). The coarse converter circuit system 110 can sample the input signal VIN to generate a sample signal S10.

[0061] During period t6, the control signal CLK 4T has an enable level. Under this condition, the transfer circuit T4 can be turned on to transfer the residual signal VRES1 (i.e., the sampling signal S40) from the capacitor array circuit 141 in the coarse converter circuit system 140 to the fine converter circuit system 175. The fine converter circuit system 175 can perform fine conversion based on the residual signal VRES1 from the coarse converter circuit system 140 and the signal SI (which is the result of noise shaping performed based on the residual signal VRES2 from the coarse converter circuit system 130) to generate a fine digital code DO1. After the fine digital code DO1 is generated, the encoder circuit 180 can generate a digital output DO2 based on the coarse digital code D4 and the fine digital code DO1. In response to this fine conversion, the capacitor array circuit 141 generates the residual signal VRES2 (i.e., the sampling signal S40 after the fine conversion is performed). After this fine conversion is completed, the transfer circuit 154 can generate a fine digital code DO1 based on the control signal CLK 4F The residual signal VRES2 (ie, the sampling signal S40) is transmitted to the noise shaping circuit 160. In addition, during the period t6, the control signal CLK 1C With an enable level and a control signal CLK2S Under this condition, the coarse converter circuit system 110 can perform coarse conversion based on the sample signal S10 to generate a decision signal S11, and the control logic circuit 150 can generate a coarse digital code D1 based on the decision signal S11. In response to this coarse conversion, the capacitor array circuit 111 generates a residual signal VRES1 (i.e., the sample signal S10 after the coarse conversion is completed). The coarse converter circuit system 120 can sample the input signal VIN to generate a sample signal S20.

[0062] Similarly, during period t7, the control signal CLK 1T Under this condition, transfer circuit T1 can be turned on to transfer residual signal VRES1 (i.e., sampled signal S10) from capacitor array circuit 111 in coarse converter circuit system 110 to fine converter circuit system 175. Fine converter circuit system 175 can perform fine conversion based on residual signal VRES1 from coarse converter circuit system 110 and signal SI (which is the result of noise shaping performed on residual signal VRES2 from coarse converter circuit system 140) to generate fine digital code DO1. The remaining operations during periods t7-t10 can be referred to the description of periods t1-t6 above, and will not be repeated here.

[0063] Figure 4 According to some embodiments of the present disclosure Figure 1 The time-interleaved analog-to-digital converter 100 (or Figure 2 Schematic diagram of the second operation timing of the time-interleaved analog-to-digital converter 200 in FIG. Figure 3 In this embodiment, when a first converter circuit system (e.g., coarse converter circuit system 110) among the plurality of coarse converter circuit systems 110, 120, 130, and 140 performs a first coarse conversion among a plurality of coarse conversions, a second converter circuit system (e.g., coarse converter circuit system 120) among the plurality of coarse converter circuit systems 110, 120, 130, and 140 samples the input signal VIN, and the sampling period of the second converter circuit system overlaps with the coarse conversion period and the sampling period during which the first converter circuit system performs the first coarse conversion. For example, the sampling period (labeled as sampling (120)) of the converter circuit system 120 overlaps with the coarse conversion period (labeled as coarse conversion (110)) and the sampling period (labeled as sampling (110)) of the converter circuit system 110. The related operations within each operation period are similar to Figure 3 , so I will not repeat it here.

[0064] like Figure 4As shown, the sampling period is longer than the coarse conversion period and also longer than the fine conversion period. For example, the coarse conversion period and the fine conversion period have the same time length, and the time length of the sampling period is the same as three times the time length of the fine conversion period (assuming that the periods t1 to t10 are all the same length). For example, during the periods t4 to t6, the time length of the sampling period (i.e., sampling (120)) of the coarse conversion circuit system 120 is equivalent to the total time length of the three fine conversions (i.e., fine conversion (120), fine conversion (130), and fine conversion (140)) performed by the fine converter circuit system 175 in response to the signal VRES1 from the multiple coarse converter circuit systems 120, 130, and 140. Through the above configuration, the multiple capacitor array circuits 111, 121, 131, and 141 can use more time to sample the input signal VIN. In this way, the hardware specifications required for the multiple capacitor array circuits 111, 121, 131, and 141 can be reduced, thereby saving circuit cost and / or reducing overall power consumption.

[0065] Figure 5 According to some embodiments of the present disclosure Figure 1 The time-interleaved analog-to-digital converter 100 (or Figure 2 Schematic diagram of a third operation timing of the time-interleaved analog-to-digital converter 200 in FIG. 1 . In this embodiment, when a first coarse converter circuit system (e.g., coarse converter circuit system 110) among the plurality of coarse converter circuit systems 110, 120, 130, and 140 performs a first coarse analog-to-digital conversion among a plurality of coarse conversions, a second coarse converter circuit system (e.g., coarse converter circuit system 120) among the plurality of coarse converter circuit systems 110, 120, 130, and 140 samples the input signal VIN, and the coarse conversion period of performing the first coarse conversion overlaps with the sampling period and the coarse conversion period of the second coarse converter circuit system. For example, the coarse conversion period of the coarse converter circuit system 110 (labeled as coarse conversion (110)) overlaps with the sampling period (labeled as sampling (120)) and the coarse conversion period (labeled as coarse conversion (120), which partially overlaps with the coarse conversion (110)) of the coarse converter circuit system 120. The related operations during each operation period are similar to Figure 3 , so I will not repeat it here.

[0066] Furthermore, if Figure 5As shown, the start time of the sampling period of the second coarse converter circuit system is the same as the start time of the coarse conversion period of the first coarse converter circuit system, the coarse conversion period is longer than the sampling period, and the duration of the sampling period is the same as the duration of the fine conversion period. For example, the start time of the sampling period (labeled as sampling (120)) of the coarse converter circuit system 120 is the same as the start time of the coarse conversion period (labeled as coarse conversion (110)) of the coarse converter circuit system 110, and the duration of the coarse conversion period is the same as twice the duration of the sampling period. For example, during periods t6 and t7, the duration of the coarse conversion period (labeled as coarse conversion (120)) during which the coarse conversion is performed by the coarse conversion circuit system 120 is equivalent to the total duration of two fine conversions (i.e., fine conversion (140) and fine conversion (110)) performed by the fine converter circuit system 175 in sequence in response to the residual signal VRES1 from the plurality of coarse converter circuit systems 140 and 110. With the above configuration, the multiple quantizer circuits 112, 122, 132, and 142, the control logic circuit 150, and / or the multiple transfer circuits T1-T4 can utilize more time to generate the multiple coarse digital codes D1-D4 and / or transfer the residual signal VRES1. This can reduce the hardware specifications required for these circuits, thereby saving circuit cost and / or reducing overall power consumption.

[0067] Figure 6 According to some embodiments of the present disclosure Figure 1 The time-interleaved analog-to-digital converter 100 (or Figure 2 FIG4 is a schematic diagram of a fourth operation sequence of the time-interleaved analog-to-digital converter 200 in FIG4. Figure 5 In this embodiment, the sampling period of the second coarse converter circuit system starts earlier than the coarse conversion period of the first coarse converter circuit system. For example, the sampling period of coarse converter circuit system 120 (labeled as Sampling (120)) starts earlier than the coarse conversion period of coarse converter circuit system 110 (labeled as Coarse Conversion (110)). The sampling period (labeled as sampling (130)) of a third coarse converter circuit system (e.g., coarse converter circuit system 130) among the plurality of coarse converter circuit systems 110, 120, 130, and 140 overlaps with the coarse conversion period (labeled as coarse conversion (110)) during which the first coarse conversion is performed, and the coarse conversion period (labeled as coarse conversion (140)) of a fourth coarse converter circuit system (labeled as coarse converter circuit system 140) among the plurality of coarse converter circuit systems 110, 120, 130, and 140 overlaps with the sampling period (labeled as sampling (120)) of the second coarse converter circuit system, and the time length of the sampling period is the same as the time length of the coarse conversion period.

[0068] Furthermore, the duration of the sampling period is twice the duration of the fine conversion period. For example, during periods t4 to t6, the duration of the sampling period (i.e., sampling (120)) of the coarse conversion circuit system 120 is equivalent to the total duration of two fine conversions (i.e., fine conversion (120) and fine conversion (130)) performed by the fine converter circuit system 175 in sequence in response to the residual signal VRES1 from the plurality of coarse converter circuit systems 120 and 130. Through the above configuration, the plurality of capacitor array circuits 111, 121, 131, and 141, the plurality of quantizer circuits 112, 122, 132, and 142, the control logic circuit 150, and / or the plurality of transfer circuits T1 to T4 can utilize more time to generate the plurality of coarse digital codes D1 to D4 and / or transfer the residual signal VRES1. In this way, the hardware specifications required for these circuits can be reduced, thereby saving circuit cost and / or reducing overall power consumption.

[0069] In the above embodiments, Figure 1 or Figure 2 The number of the coarse converter circuit systems (ie, the plurality of coarse converter circuit systems 110, 120, 130, and 140) is 4, but the present disclosure is not limited thereto. Figures 3 to 6 It can be seen that the time-interleaved analog-to-digital converter 100 (or Figure 2 The operating speed of the time-interleaved analog-to-digital converter 200 may be mainly determined by the fine conversion period, and the sampling period and / or the coarse conversion period may be adjusted based on the fine conversion period and actual circuit requirements. Figures 3 to 6 The various operation timings shown are for illustrative purposes only and the present disclosure is not limited thereto. In various embodiments, the duration of the sampling period or the coarse conversion period may be set to be shorter than the duration of the fine conversion period based on actual application requirements.

[0070] In the above Figures 3 to 6 Depending on different circuit applications, the period during which the noise shaping circuit 160 performs noise shaping may precede or overlap the fine conversion period. For example, in some applications, there is a non-overlapping period between the coarse conversion period and the fine conversion period, and the noise shaping circuit 160 may perform noise shaping during this non-overlapping period (which precedes the fine conversion period) to generate the signal SI before the fine conversion period. Alternatively, in other examples, the noise shaping circuit 160 may perform noise shaping during the fine conversion period and generate the signal SI within the fine conversion period. The above-described configuration of the period during which noise shaping is performed is for illustrative purposes only and is not intended to limit the present disclosure.

[0071] In summary, the time-interleaved analog-to-digital converter in some embodiments of the present disclosure can utilize multiple operation timings to perform coarse conversion and fine conversion including noise shaping. This can improve the signal-to-noise ratio in high-speed applications and reduce the specification requirements of some circuits.

[0072] Although the embodiments of the present disclosure are described above, these embodiments are not intended to limit the present disclosure. Persons skilled in the art may make changes to the technical features of the present disclosure based on the explicit or implicit content of the present disclosure. All such changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be determined by the claims of this specification.

Claims

1. A time-interleaved analog-to-digital converter, comprising: a plurality of coarse converter circuit systems for sequentially sampling an input signal and performing a plurality of coarse analog-to-digital conversions to generate a plurality of decision signals; a control logic circuit for generating a plurality of coarse digital codes corresponding to the coarse analog-to-digital conversions according to the decision signals; a plurality of first transfer circuits for sequentially transferring a plurality of first residual signals from the coarse converter circuit systems according to a plurality of first control signals, wherein the first residual signals are generated by the coarse converter circuit systems sequentially performing the coarse analog-to-digital conversions; a fine converter circuit system for performing a fine analog-to-digital conversion based on a first signal among the first residual value signals and a second signal among the second residual value signals to generate a fine digital code, wherein a sampling period for each of the coarse converter circuit systems to sample the input signal and a coarse conversion period for each of the coarse analog-to-digital conversions are set based on a fine conversion period for the fine converter circuit system to perform the fine analog-to-digital conversion; a plurality of second transfer circuits for sequentially transferring the second residual signals from the coarse converter circuit systems to the fine converter circuit system according to a plurality of second control signals, wherein the second residual signals are generated by the coarse converter circuit systems in response to the fine analog-to-digital conversion, respectively; and An encoder circuit is used to generate a digital output according to a corresponding one of the coarse digital codes and the fine digital code.

2. The time-interleaved ADC of claim 1 , wherein when the coarse converter circuitry samples the input signal or performs the coarse ADCs, the fine converter circuitry performs the fine ADC, wherein the fine ADC is an ADC performed based on a result of noise shaping and the first signal, and the noise shaping is performed based on the second signal. 3 . The time-interleaved analog-to-digital converter of claim 1 , wherein the number of the coarse converter circuit systems is four.

4. The time-interleaved ADC of claim 1 , wherein the second signal is generated by a first coarse converter circuit system among the coarse converter circuit systems in response to the fine ADC, the first signal is generated by a second coarse converter circuit system among the coarse converter circuit systems performing a corresponding one of the coarse ADCs, and a start time of the sampling period of the first coarse converter circuit system is earlier than a start time of the sampling period of the second coarse converter circuit system.

5. The time-interleaved ADC of claim 1 , wherein when a first coarse converter circuit system among the coarse converter circuit systems performs a first coarse ADC among the coarse ADCs, a second coarse converter circuit system among the coarse converter circuit systems samples the input signal, and the fine conversion period, the coarse conversion period, and the sampling period each have the same time length.

6. The time-interleaved ADC of claim 1 , wherein when a first coarse converter circuit system among the coarse converter circuit systems performs a first coarse ADC among the coarse ADCs, a second coarse converter circuit system among the coarse converter circuit systems samples the input signal, and the sampling period of the second coarse converter circuit system overlaps the coarse conversion period of performing the first coarse ADC and the sampling period of the first coarse converter circuit system. 7 . The time-interleaved analog-to-digital converter of claim 6 , wherein the sampling period is longer than the coarse conversion period and longer than the fine conversion period.

8. The time-interleaved ADC of claim 1 , wherein when a first coarse converter circuit system among the coarse converter circuit systems performs a first coarse ADC among the coarse ADCs, a second coarse converter circuit system among the coarse converter circuit systems samples the input signal, and the coarse conversion period of performing the first coarse ADC overlaps the sampling period and the coarse conversion period of the second coarse converter circuit system. 9 . The time-interleaved ADC of claim 8 , wherein a start time of the sampling period of the second coarse converter circuit system is earlier than or the same as a start time of the coarse conversion period of the first coarse converter circuit system.

10. The time-interleaved ADC of claim 9, wherein when a start time of the sampling period of the second coarse converter circuit system is the same as a start time of the coarse conversion period of the first coarse converter circuit system, the coarse conversion period is longer than the sampling period.

Images