Fan speed regulation system and uninterruptible power supply

Abstract

The application provides a fan speed regulation system and an uninterruptible power supply. The system comprises a power supply transformer, a fan, an auxiliary power supply, a speed regulation switching circuit, a controller and a speed regulation driving circuit. The first switching path of the speed regulation switching circuit is connected to the high-voltage output end of the power supply transformer and the fan when the first control path is not turned on. The second switching path is connected to the low-voltage output end of the power supply transformer and the fan when the second control path is turned on. The speed regulation driving circuit processes the high-speed initial signal and the low-speed initial signal of the fan output by the controller and outputs the high-speed control signal and the low-speed control signal to make the first and second control paths be turned on at the same time, be turned off at the same time or make the first control path be turned on and the second control path be turned off. The auxiliary power supply is used to supply power to the controller, the first and second control paths. The above structure not only prevents the short circuit of the power supply transformer, but also enables the fan to run at full speed when the auxiliary power supply is powered off, thereby ensuring the safe and stable operation of the uninterruptible power supply.

Description

TECHNICAL FIELD

[0001] The present application relates to the fan technology field, and particularly to a fan speed regulation system and an uninterruptible power supply. BACKGROUND

[0002] The UPS (Uninterruptible Power Supply) needs to use a fan for heat dissipation. Usually, the fan used by a nuclear power unit is an alternating current fan, which needs to be powered by a power supply autotransformer. Further, the fan can be divided into three gears of low speed, medium speed and high speed for operation. However, when the software drive is abnormal or the hardware is short-circuited, the common conduction of multiple gears will cause the short-circuit of the winding of the power supply autotransformer, resulting in burning of the power supply autotransformer, so that the fan and the uninterruptible power supply cannot work normally. SUMMARY

[0003] Therefore, the present application provides a fan speed regulation system and an uninterruptible power supply, which can solve the common conduction problem of the fan caused by abnormal software drive or hardware short-circuit.

[0004] In a first aspect, the present application provides a fan speed regulation system, comprising: a power supply transformer and a fan, wherein the power supply transformer supplies power to the fan through a high-voltage output end and a low-voltage output end;

[0005] Further comprising:

[0006] a speed regulation switching circuit, which comprises a first control path, a second control path, a first switching path and a second switching path; the first switching path connects the high-voltage output end and the fan when the first control path is not turned on; the second switching path connects the low-voltage output end and the fan when the second control path is turned on;

[0007] a controller, which is used to output a high-speed initial signal and a low-speed initial signal;

[0008] a speed regulation drive circuit, which is used to process the high-speed initial signal and the low-speed initial signal, and output a high-speed control signal and a low-speed control signal, which make the first control path and the second control path be turned on at the same time, be turned off at the same time, or make the first control path be turned on and the second control path be turned off; and

[0009] an auxiliary power supply, which is used to supply power to the controller, the first control path and the second control path.

[0010] In a possible implementation, the power supply transformer further supplies power to the fan through a medium-voltage output end;

[0011] The speed regulation switching circuit further comprises a third control path and a third switching path; the third switching path connects the medium voltage output end and the fan when the third control path is turned on;

[0012] The controller is further configured to output a medium speed initial signal;

[0013] The speed regulation driving circuit is specifically configured to process the high speed initial signal, the medium speed initial signal and the low speed initial signal, and output high speed control signals, medium speed control signals and low speed control signals capable of enabling the first control path, the second control path and the third control path to work in a first combined state, a second combined state, a third combined state or a fourth combined state; the first combined state is that the first control path, the second control path and the third control path are all turned off; the second combined state is that the first control path and the second control path are turned on and the third control path is turned off; the third combined state is that the first control path and the third control path are turned on and the second control path is turned off; and the fourth combined state is that the first control path is turned on alone.

[0014] The auxiliary power supply is further configured to supply power for the third control path.

[0015] In a possible implementation, the speed regulation driving circuit comprises a first OR gate, a second OR gate, a first NAND gate, a second NAND gate, a third NAND gate and a first AND gate;

[0016] The first input end of the first OR gate is connected to the high speed initial signal, the second input end of the first OR gate is connected to the medium speed initial signal, and the output end of the first OR gate is connected to the first input end of the second OR gate; the first input end and the second input end of the first NAND gate are both connected to the low speed initial signal, the output end of the first NAND gate is connected to the second input end of the second OR gate, the output end of the second OR gate is connected to the first input end and the second input end of the second NAND gate respectively, and the output end of the second NAND gate outputs the low speed control signal;

[0017] The first input end and the second input end of the third NAND gate are both connected to the high speed initial signal, the output end of the third NAND gate outputs the high speed control signal; the output end of the third NAND gate is connected to the first input end of the first AND gate, the second input end of the first AND gate is connected to the medium speed initial signal, and the output end of the first AND gate outputs the medium speed control signal.

[0018] In a possible implementation, the first control path comprises a first switch tube and a first diode;

[0019] The first switching path comprises a first relay;

[0020] a first end of the first switch tube is connected to the high-speed control signal, a second end of the first switch tube is grounded, and a third end of the first switch tube is connected to an anode of the first diode and a first power supply end of the first relay, respectively;

[0021] a normally closed contact of the first relay is connected to a high-voltage output end of the power supply transformer, and a movable contact of the first relay is connected to a power supply end of the fan.

[0022] In one possible implementation, the second control path includes a second switch tube and a second diode.

[0023] The second switching path includes a second relay.

[0024] a first end of the second switch tube is connected to the low-speed control signal, a second end of the second switch tube is grounded, and a third end of the second switch tube is connected to an anode of the second diode and a first power supply end of the second relay, respectively;

[0025] a normally closed contact of the second relay is connected to a low-voltage output end of the power supply transformer, and a movable contact of the second relay is connected to a power supply end of the fan.

[0026] In one possible implementation, the third control path includes a third switch tube and a third diode, and the third switching path includes a third relay.

[0027] a first end of the third switch tube is connected to the medium-speed control signal, a second end of the third switch tube is grounded, and a third end of the third switch tube is connected to an anode of the third diode and a first power supply end of the third relay, respectively;

[0028] a normally closed contact of the third relay is connected to a medium-voltage output end of the power supply transformer, and a movable contact of the third relay is connected to a power supply end of the fan.

[0029] In one possible implementation, the fan speed regulation system further includes a fault alarm circuit.

[0030] The fault alarm circuit is connected with a fan fault signal generated by the fan, and is also connected with the speed regulation driving circuit and used for monitoring the fan in a first combined state, a second combined state or a third combined state of the first control path, the second control path and the third control path.

[0031] In a possible implementation, the fan speed regulation system further comprises a fault alarm circuit.

[0032] The fault alarm circuit comprises a fourth NAND gate, a third OR gate and a second AND gate.

[0033] The first input end of the third OR gate is connected with the output end of the first OR gate, and the second input end of the third OR gate is connected with the low-speed initial signal; and the output end of the third OR gate is connected with the first input end of the second AND gate.

[0034] The first input end and the second input end of the fourth NAND gate are connected with the fan fault signal of the fan, and the output end of the fourth NAND gate is connected with the second input end of the second AND gate.

[0035] The output end of the second AND gate outputs a fault alarm signal.

[0036] In a possible implementation, the output end of the second AND gate is connected with an LED lamp.

[0037] In a second aspect, the embodiments of the present application provide an uninterruptible power supply comprising the fan speed regulation system as described in the first aspect.

[0038] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0039] The fan speed regulation system provided by the embodiments of the present application comprises a power supply transformer, a fan, an auxiliary power supply, a speed regulation switching circuit, a controller and a speed regulation driving circuit, wherein the first switching path in the speed regulation switching circuit is connected with the high-voltage output end of the power supply transformer and the fan when the first control path is not turned on; the second switching path is connected with the low-voltage output end of the power supply transformer and the fan when the second control path is turned on; the speed regulation driving circuit processes the high-speed initial signal and the low-speed initial signal of the fan output by the controller, and outputs the high-speed control signal and the low-speed control signal for simultaneously turning on the first control path and the second control path, simultaneously turning off the first control path and the second control path or turning on the first control path and turning off the second control path; and the auxiliary power supply is used for supplying power to the controller, the first control path and the second control path. The above structure not only prevents the short circuit of the power supply transformer, but also enables the fan to run at full speed when the auxiliary power supply is powered off, thereby ensuring the safe and stable operation of the uninterruptible power supply. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0041] Figure 1 is a structural schematic diagram of a fan speed regulation system provided by an embodiment of the present application;

[0042] Figure 2 is a schematic diagram of a speed regulation driving circuit provided by an embodiment of the present application;

[0043] Figure 3 is a schematic diagram of a first control path provided by an embodiment of the present application;

[0044] Figure 4 is a schematic diagram of a first switching path provided by an embodiment of the present application;

[0045] Figure 5 is a schematic diagram of a second switching path provided by an embodiment of the present application;

[0046] Figure 6 is a schematic diagram of a third switching path provided by an embodiment of the present application;

[0047] Figure 7 is a schematic diagram of a fault alarm circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0048] In the following description, specific details are set forth in order to provide a thorough understanding of embodiments of the present application. However, persons of ordinary skill in the art will readily recognize that embodiments of the present application can be practiced without these specific details. In other instances, well-known structures, devices, circuits, and methods have not been described in detail in order to avoid obscuring the present application.

[0049] In order to make the objects, technical solutions and advantages of the present application clearer, the following will be described with reference to the accompanying drawings through specific embodiments.

[0050] Figure 1 is a structural schematic diagram of a fan speed regulation system provided by an embodiment of the present application. As shown in Figure 1 , the fan speed regulation system comprises a power supply transformer 40 and a fan 50, the power supply transformer 40 supplies power to the fan 50 through a high-voltage output end and a low-voltage output end, and further comprises:

[0051] a speed regulating switching circuit 30, comprising a first control path 31, a second control path 33, a first switching path 32 and a second switching path 34; the first switching path 32 connects the high-voltage output end and the fan 50 when the first control path 31 is not turned on; the second switching path 34 connects the low-voltage output end and the fan 50 when the second control path 33 is turned on;

[0052] a controller 10 for outputting a high-speed initial signal and a low-speed initial signal;

[0053] a speed regulating driving circuit for processing the high-speed initial signal and the low-speed initial signal, and outputting a high-speed control signal and a low-speed control signal for simultaneously turning on the first control path 31 and the second control path 33, simultaneously turning off the first control path 31 and the second control path 33, or turning on the first control path 31 and turning off the second control path 33; and

[0054] an auxiliary power supply for supplying power to the controller 10, the first control path 31 and the second control path 33.

[0055] Specifically, the controller 10 can be a digital signal processor (DSP), and the power supply transformer 40 can be an autotransformer. After receiving the high-speed initial signal and the low-speed initial signal, the speed regulating driving circuit only outputs one valid control signal, and the high-speed control signal is high-level valid, and the low-speed control signal is low-level valid. In this way, the first control path 31 is not turned on when the received high-speed control signal is low-level or the auxiliary power supply is powered off, so that the first switching path 32 connects the high-voltage output end of the power supply transformer 40 and the fan 50; the second control path 33 is turned on when the received low-speed control signal is high-level, so that the second switching path 34 connects the low-voltage output end of the power supply transformer 40 and the fan 50. Thus, it is ensured that no matter how many high-level signals are output by the controller 10 from the high-speed initial signal and the low-speed initial signal, at most one of the first switching path 32 and the second switching path 34 is turned on, preventing the power supply transformer 40 from being short-circuited, and ensuring the safe and stable operation of the uninterruptible power supply when the auxiliary power supply is powered off.

[0056] In a possible implementation, the power supply transformer 40 also supplies power to the fan 50 through a medium-voltage output end;

[0057] The speed regulating switching circuit 30 further comprises a third control path and a third switching path; the third switching path connects the medium-voltage output end and the fan 50 when the third control path is turned on;

[0058] The controller 10 is also used for outputting a medium-speed initial signal;

[0059] The speed regulation driving circuit 20 is specifically configured to process the high-speed initial signal, the medium-speed initial signal and the low-speed initial signal, and output high-speed control signals, medium-speed control signals and low-speed control signals capable of enabling the first control path 31, the second control path 33 and the third control path to work in a first combined state, a second combined state, a third combined state or a fourth combined state; the first combined state is that the first control path 31, the second control path 33 and the third control path are all turned off; the second combined state is that the first control path 31 and the second control path 33 are turned on and the third control path is turned off; the third combined state is that the first control path 31 and the third control path are turned on and the second control path 33 is turned off; and the fourth combined state is that the first control path 31 is turned on alone.

[0060] The auxiliary power supply is further configured to supply power for the third control path.

[0061] Specifically, when the fan 50 is in three-speed regulation, the speed regulation switching circuit 30 further comprises a third control path and a third switching path, and the speed regulation driving circuit 20 is further configured to process the medium-speed initial signal output by the controller 10, so that only one of the output high-speed control signals, medium-speed control signals and low-speed control signals is effective, thereby achieving the effect of preventing common conduction. In addition, the medium-speed control signal is also set to be effective at a high level, so that when the auxiliary power supply is disabled, the fan 50 only runs at high speed.

[0062] In one possible implementation, Figure 2 The speed regulation driving circuit 20 provided by the embodiment is shown in the figure, which comprises a first or gate IC7A, a second or gate IC7D, a first NAND gate IC3B, a second NAND gate IC8A, a third NAND gate IC8D and a first AND gate IC4D. Figure 2 As shown in the figure, the speed regulation driving circuit 20 comprises a first or gate IC7A, a second or gate IC7D, a first NAND gate IC3B, a second NAND gate IC8A, a third NAND gate IC8D and a first AND gate IC4D.

[0063] The first input end of the first or gate IC7A is connected to the high-speed initial signal, the second input end of the first or gate IC7A is connected to the medium-speed initial signal, and the output end of the first or gate IC7A is connected to the first input end of the second or gate IC7D; the first input end and the second input end of the first NAND gate IC3B are both connected to the low-speed initial signal, the output end of the first NAND gate IC3B is connected to the second input end of the second or gate IC7D, and the output end of the second or gate IC7D is connected to the first input end and the second input end of the second NAND gate IC8A respectively, and the output end of the second NAND gate IC8A outputs the low-speed control signal.

[0064] The first input end and the second input end of the third NAND gate IC8D are connected to the high-speed initial signal, and the output end of the third NAND gate IC8D outputs the high-speed control signal; the output end of the third NAND gate IC8D is connected to the first input end of the first AND gate IC4D, the second input end of the first AND gate IC4D is connected to the medium-speed initial signal, and the output end of the first AND gate IC4D outputs the medium-speed control signal.

[0065] In the embodiment, as shown in Figure 2 The output end of the high-speed initial signal of the controller 10 is connected to the first input end of the first OR gate IC7A through the resistance R15, the first input end of the first OR gate IC7A is further connected to the 0V ground through the parallel connection of the capacitor C14 and the resistance R14, the output end of the medium-speed initial signal of the controller 10 is connected to the second input end of the first OR gate IC7A through the resistance R18, the second input end of the first OR gate IC7A is further connected to the 0V ground through the parallel connection of the capacitor C19 and the resistance R21, and the output end of the first OR gate IC7A is connected to the first input end of the second OR gate IC7D; the low-speed initial signal of the controller 10 is connected to the first input end and the second input end of the first NAND gate IC3B through the parallel connection of the diode D18 and the resistance R24, the first input end and the second input end of the first NAND gate IC3B are further connected to the 0V ground through the parallel connection of the resistance R100 and the capacitor C24, the output end of the first NAND gate IC3B is connected to the second input end of the second OR gate IC7D, the output end of the second OR gate IC7D is connected to the first input end and the second input end of the second NAND gate IC8A, and the output end of the IC8A outputs the low-speed control signal.

[0066] The output end of the high-speed initial signal of the controller 10 is further connected to the first input end and the second input end of the third NAND gate IC8D through the parallel connection of the resistance R28 and the diode D22, the first input end and the second input end of the third NAND gate IC8D are further connected to the 0V ground through the parallel connection of the capacitor C27 and the resistance R101; the output end of the third NAND gate IC8D outputs the high-speed control signal and is connected to the first input end of the first AND gate IC4D, the output end of the medium-speed initial signal of the controller 10 is further connected to the second input end of the first AND gate IC4D through the parallel connection of the resistance R33 and the diode D25, the second input end of the first AND gate IC4D is further connected to the 0V ground through the parallel connection of the capacitor C29 and the resistance R102, and the output end of the first AND gate IC4D outputs the medium-speed control signal.

[0067] In the embodiment, based on the structure of the speed regulation driving circuit 20, the truth table of the high-speed initial signal, the medium-speed initial signal, the low-speed initial signal, the high-speed control signal, the medium-speed control signal and the low-speed control signal is shown in Table 1, and the high-speed initial signal, the medium-speed initial signal and the low-speed initial signal are high-level effective, the high-speed control signal is low-level effective, and the medium-speed control signal and the low-speed control signal are high-level effective. As can be seen from Table 1, through the processing of the speed regulation driving circuit 20, no matter how many effective signals in the three initial signals, only one effective control signal is output.

[0068] Table 1

[0069]

[0070] In one possible implementation, as shown in Figure 3 the first control path 31 includes a first switch tube and a first diode;

[0071] the first switching path 32 includes a first relay;

[0072] the first end of the first switch tube is connected to the high-speed control signal, the second end of the first switch tube is grounded, and the third end of the first switch tube is connected to the anode of the first diode and the first power supply end of the first relay, respectively; the second power supply end of the first relay and the cathode of the first diode are connected to the auxiliary power supply;

[0073] the normally closed contact of the first relay is connected to the high-voltage output end of the power supply transformer 40, and the moving contact of the first relay is connected to the power supply end of the fan 50.

[0074] In the embodiment, Figure 3 a schematic diagram of the first control path 31 is shown; as shown in Figure 3 the first control path 31 further includes a resistor R38, a capacitor C38 and a resistor R39, the first ends of the capacitor C38, the resistor R38 and the resistor R39 are connected to the first end of the first switch tube Q3, the second ends of the capacitor C38 and the resistor R39 are connected to the second end of the first switch tube Q3; and the second end of the resistor R38 is the input end of the high-speed control signal.

[0075] In one possible implementation, as shown in Figure 4 the first switching path 32 further includes a first capacitor C37 and a second capacitor C36;

[0076] The first end of the first capacitor C37 is connected to the normally closed contact 3 of the first relay RLY3, and the second end of the first capacitor C37 is connected to the power supply terminal of the fan 50. The first end of the second capacitor C36 is connected to the normally open contact 5 of the first relay RLY3, and the second end of the second capacitor C36 is connected to the power supply terminal of the fan 50.

[0077] In one possible implementation, the second control path 33 includes a second switch and a second diode;

[0078] The second switching path 34 includes a second relay;

[0079] The first terminal of the second switching transistor is connected to the low-speed control signal, the second terminal of the second switching transistor is grounded, the third terminal of the second switching transistor is connected to the anode of the second diode and the first power supply terminal of the second relay, and the second power supply terminal of the second relay and the cathode of the second diode are both connected to the auxiliary power supply.

[0080] The normally open contact of the second relay is connected to the low-voltage output terminal of the power supply transformer 40, and the moving contact of the second relay is connected to the power supply terminal of the fan 50.

[0081] In this embodiment, the second control path 33 further includes a third resistor, a fourth capacitor, and a fourth resistor. The first ends of the fourth capacitor, the third resistor, and the fourth resistor are all connected to the first end of the second switch transistor, and the second ends of the fourth capacitor and the third resistor are all connected to the second end of the second switch transistor. The second end of the fourth resistor is the input end of the low-speed control signal.

[0082] like Figure 5 As shown, the second switching path 34 also includes capacitors C30 and C31. One end of capacitor C30 is connected to the normally open contact of the second relay RLY1, and the other end is connected to the power supply terminal of the fan 50. One end of capacitor C31 is connected to the normally closed contact of the second relay RLY1, and the other end is connected to the power supply terminal of the fan 50.

[0083] In one possible implementation, the third control path includes a third switch and a third diode; the third switching path includes a third relay.

[0084] The first terminal of the third switch is connected to the medium-speed control signal, the second terminal of the third switch is grounded, the third terminal of the third switch is connected to the anode of the third diode and the first power supply terminal of the third relay, and the second power supply terminal of the third relay and the cathode of the third diode are both connected to the auxiliary power supply.

[0085] The normally open contact of the third relay is connected with the medium voltage output end of the power supply transformer 40, and the movable contact of the third relay is connected with the power supply end of the fan 50.

[0086] In the embodiment, the third control path further comprises a first resistor, a third capacitor and a second resistor, the first end of the third capacitor, the first resistor and the second resistor are connected with the first end of the third switch tube, the second end of the third capacitor and the first resistor are connected with the second end of the third switch tube; and the second end of the second resistor is the input end of the medium speed control signal.

[0087] As shown in Figure 6 The third switching path further comprises capacitors C33 and C34, one end of the capacitor C33 is connected with the normally closed contact of the third relay RLY2, and the other end is connected with the power supply end of the fan 50, one end of the capacitor C34 is connected with the normally open contact of the third relay RLY2, and the other end is connected with the power supply end of the fan 50.

[0088] For example, the high voltage output end of the power supply transformer 40 outputs 220Vac electricity, the medium voltage output end outputs 200Vac electricity, and the low voltage output end outputs 180Vac electricity.

[0089] In a possible implementation, the fan speed regulation system further comprises a fault alarm circuit;

[0090] The fault alarm circuit is connected with the fan fault signal emitted by the fan 50, and is also connected with the speed regulation driving circuit 20, and is used for monitoring the fault of the fan when the first control path 31, the second control path 33 and the third control path work in the first combined state, the second combined state or the third combined state.

[0091] In the embodiment, the fan outputs a low-level fan fault signal when a fault of the fan is monitored, but the fan also continuously outputs a low-level fan fault signal when the fan is not started, in order to avoid the situation that the low-level fan fault signal output by the fan when the fan is not started causes the operation and maintenance personnel to be unable to distinguish whether the fault is a fault of the fan itself or a fault of the power supply system, the fault alarm circuit provided in the embodiment judges whether the fan is in a running state when the fan fault alarm signal is acquired, if the fan is in the running state (the first combined state, the second combined state or the third combined state), an alarm fault signal is output based on the fan fault signal, and if the fan is not in the running state (the fourth combined state), even if the fan fault signal is low, the fault alarm circuit also outputs a low-level alarm fault signal, and does not perform fan fault alarm.

[0092] In a possible implementation, as Figure 7As shown in the figure, the fault alarm circuit comprises a fourth NAND gate IC3A, a third OR gate IC7B and a second AND gate IC4A;

[0093] The first input end of the third OR gate IC7B is connected with the output end of the first OR gate IC7A, and the second input end of the third OR gate IC7B is connected with the low-speed initial signal; the output end of the third OR gate IC7B is connected with the first input end of the second AND gate IC4A;

[0094] The first input end and the second input end of the fourth NAND gate IC3A are connected with the fan fault signals of the fans respectively, and the output end of the fourth NAND gate IC3A is connected with the second input end of the second AND gate IC4A;

[0095] The output end of the second AND gate IC4A outputs a fault alarm signal.

[0096] In the embodiment, when there are three fans in the uninterruptible power supply, the control signal controls the speed gears of the three fans simultaneously, and the fault alarm circuit is as shown in the figure. Figure 7 As shown in the figure, the fault alarm circuit further comprises a fifth NAND gate, a sixth NAND gate, a third AND gate and a fourth AND gate;

[0097] The first input end of the third OR gate IC7B is connected with the output end of the first OR gate IC7A, and the second input end of the third OR gate IC7B is connected with the low-speed initial signal; the output end of the third OR gate IC7B is connected with the first input end of the second AND gate IC4A;

[0098] The first input end and the second input end of the fourth NAND gate IC3A are connected with the fan fault signals of the fan 1 respectively, the output end of the fourth NAND gate IC3A is connected with the second input end of the second AND gate IC4A, and the output end of the second AND gate IC4A outputs a fault alarm signal 1.

[0099] The output end of the third OR gate IC7B is connected with the first input end of the third AND gate IC4B; the first input end and the second input end of the fifth NAND gate IC3C are connected with the fan fault signals of the fan 2 respectively, the output end of the fifth NAND gate IC3C is connected with the second input end of the third AND gate IC4B, and the output end of the third AND gate IC4B outputs a fault alarm signal 2.

[0100] The output end of the third OR gate IC7B is connected with the first input end of the fourth AND gate IC4C; the first input end and the second input end of the sixth NAND gate IC3D are connected with the fan fault signals of the fan 3 respectively, the output end of the sixth NAND gate IC3D is connected with the second input end of the fourth AND gate IC4C, and the output end of the fourth AND gate IC4C outputs a fault alarm signal 3.

[0101] Specifically, as can be known from the above fault alarm circuit, when any of the three initial signals of "high-speed initial signal", "medium-speed initial signal" and "low-speed initial signal" is high, the output of the OR gate IC7B is high, that is, one of the inputs of the AND gate IC4A, IC4B and IC4C is high, and the output of the AND gate IC4A, IC4B and IC4C is possible to be high, triggering the alarm. In other words, if none of the initial signals of the fans is high, the fault alarm signal will not be triggered.

[0102] Under the premise that any of the initial signals of the fans is high, if any fan fails, the fault alarm signal is low, becomes high after the NAND gate IC3A / IC3C / IC3D, enters the AND gate IC4A / IC4B / IC4C, at this time, the output of the AND gate IC4A / IC4B / IC4C is high, and the fault alarm signal can be output, monitoring which fan is abnormal.

[0103] Specifically, the truth table of the initial signal for controlling the speed of the fan, the three fan fault signals and the fault alarm signal is shown in Table 2.

[0104] Table 2

[0105]

[0106]

[0107] In one possible implementation, the output end of the second AND gate IC4A is connected with the LED lamp.

[0108] In the embodiment, the LED lamp is lighted when the output end of the second AND gate IC4A outputs high level.

[0109] In a second aspect, the embodiment of the application provides an uninterruptible power supply, which comprises the fan speed regulating system as described in the first aspect.

[0110] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the above-described embodiments of the present application have been described in detail, those skilled in the art should understand that: the technical solutions recorded in the above-described embodiments can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A fan speed regulation system, comprising a power supply transformer and a fan, the power supply transformer supplying power to the fan through a high voltage output, a medium voltage output and a low voltage output; characterized in that, Also comprising: a speed regulation switching circuit comprising a first control path, a second control path, a third control path, a first switching path, a second switching path and a third switching path; the first switching path connects the high-voltage output end and the fan when the first control path is not turned on; the second switching path connects the low-voltage output end and the fan when the second control path is turned on; the third switching path connects the medium-voltage output end and the fan when the third control path is turned on; a controller for outputting a high-speed initial signal, a medium-speed initial signal and a low-speed initial signal; a speed regulation driving circuit for processing the high-speed initial signal, the medium-speed initial signal and the low-speed initial signal, and outputting a high-speed control signal, a medium-speed control signal and a low-speed control signal capable of making the first control path, the second control path and the third control path work in a first combined state, a second combined state, a third combined state or a fourth combined state; the first combined state is that the first control path, the second control path and the third control path are all turned off; the second combined state is that the first control path and the second control path are turned on and the third control path is turned off; the third combined state is that the first control path and the third control path are turned on and the second control path is turned off; the fourth combined state is that the first control path is turned on alone; and, an auxiliary power supply for supplying power to the controller, the first control path, the third control path and the second control path; the speed regulation driving circuit is specifically configured to: when the high-speed initial signal, the medium-speed initial signal and the low-speed initial signal are low-level signals, output a high-speed control signal of high level, a medium-speed control signal of low level and a low-speed control signal of low level, so as to make the first control path, the second control path and the third control path work in the fourth combined state.

2. The blower speed control system of claim 1, wherein The speed regulation driving circuit comprises a first OR gate, a second OR gate, a first NAND gate, a second NAND gate, a third NAND gate and a first AND gate; a first input end of the first OR gate is connected to the high-speed initial signal, a second input end of the first OR gate is connected to the medium-speed initial signal, and an output end of the first OR gate is connected to a first input end of the second OR gate; a first input end and a second input end of the first NAND gate are both connected to the low-speed initial signal, an output end of the first NAND gate is connected to a second input end of the second OR gate, an output end of the second OR gate is connected to a first input end and a second input end of the second NAND gate, and an output end of the second NAND gate outputs the low-speed control signal; a first input end and a second input end of the third NAND gate are both connected to the high-speed initial signal, and an output end of the third NAND gate outputs the high-speed control signal; the output end of the third NAND gate is connected to a first input end of the first AND gate, a second input end of the first AND gate is connected to the medium-speed initial signal, and an output end of the first AND gate outputs the medium-speed control signal.

3. The blower speed control system of claim 1, wherein The first control path comprises a first switch tube and a first diode; The first switching path comprises a first relay; The first end of the first switch tube is connected to the high-speed control signal, the second end of the first switch tube is grounded, the third end of the first switch tube is connected to the anode of the first diode and the first power supply end of the first relay respectively, and the second power supply end of the first relay and the cathode of the first diode are connected to the auxiliary power supply; The normally closed contact of the first relay is connected to the high-voltage output end of the power supply transformer, and the movable contact of the first relay is connected to the power supply end of the fan.

4. The blower speed control system of claim 1, wherein The second control path comprises a second switch tube and a second diode; The second switching path comprises a second relay; The first end of the second switch tube is connected to the low-speed control signal, the second end of the second switch tube is grounded, the third end of the second switch tube is connected to the anode of the second diode and the first power supply end of the second relay respectively, and the second power supply end of the second relay and the cathode of the second diode are connected to the auxiliary power supply; The normally open contact of the second relay is connected to the low-voltage output end of the power supply transformer, and the movable contact of the second relay is connected to the power supply end of the fan.

5. The blower speed control system of claim 1, wherein The third control path comprises a third switch tube and a third diode; the third switching path comprises a third relay; The first end of the third switch tube is connected to the medium-speed control signal, the second end of the third switch tube is grounded, the third end of the third switch tube is connected to the anode of the third diode and the first power supply end of the third relay respectively, and the second power supply end of the third relay and the cathode of the third diode are connected to the auxiliary power supply; The normally open contact of the third relay is connected to the medium-voltage output end of the power supply transformer, and the movable contact of the third relay is connected to the power supply end of the fan.

6. The blower speed control system of claim 2, wherein The fan speed regulation system further comprises a fault alarm circuit; The fault alarm circuit is connected to the fan fault signal emitted by the fan; the fault alarm circuit is also connected to the speed regulation driving circuit, and is used for monitoring the fault of the fan when the first control path, the second control path and the third control path work in the first combination state, the second combination state or the third combination state.

7. The blower speed control system of claim 6, wherein The fan speed regulation system further comprises a fault alarm circuit; The fault alarm circuit comprises a fourth NAND gate, a third OR gate and a second AND gate; The first input end of the third OR gate is connected to the output end of the first OR gate, and the second input end of the third OR gate is connected to the low-speed initial signal; the output end of the third OR gate is connected to the first input end of the second AND gate; The first input end and the second input end of the fourth NAND gate are connected to the fan fault signal of the fan respectively, and the output end of the fourth NAND gate is connected to the second input end of the second AND gate; The output end of the second AND gate outputs a fault alarm signal.

8. The blower speed control system of claim 7, wherein, The output end of the second AND gate is connected to an LED lamp.

9. An uninterruptible power supply, characterized by The fan speed regulation system comprises any one of claims 1 to 8.

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