Method and system for generating AC IRIG-B code based on FPGA

Abstract

The application discloses a kind of based on the generation method and system of alternating current IRIG-B code of FPGA, belong to time unified technical field.Based on the generation method of alternating current IRIG-B code of FPGA, comprising: generating waveform data, and the waveform data is imported into the ROM of FPGA, the waveform data includes big wave data and several small wave data;Big wave data and small wave data are read based on 1PPS synchronization signal;Select a small wave data, and according to the direct current bias obtained by pre-computation, small wave data is compensated;Big wave data and small wave data are amplified respectively;According to BDC signal, amplified big wave data or small wave data is selected and output;The big wave data or small wave data is converted into analog signal.The application modulates BDC signal into BAC signal using the logic resource in FPGA, and the modulation precision can be improved by increasing the sampling rate of DAC.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of time unification, and particularly relates to a method and system for generating alternating IRIG-B code based on FPGA. BACKGROUND

[0002] IRIG-B code is a commonly used serial transmission mode in a time system, and has the advantages of simple physical continuity, long transmission distance, standardized interface and international generalization compared with parallel transmission modes. However, the existing IRIG-B (AC) scheme has the problems of complex hardware, low synchronization accuracy and single modulation ratio and amplitude. SUMMARY

[0003] The application aims to overcome the defects of the prior art and provide a method and system for generating alternating IRIG-B code based on FPGA.

[0004] The application is achieved by the following technical scheme.

[0005] According to a first aspect of the application, the method for generating alternating IRIG-B code based on FPGA comprises the following steps.

[0006] Waveform data is generated and imported into the ROM of FPGA, wherein the waveform data comprises large wave data and a plurality of small wave data;

[0007] The large wave data and the small wave data are read based on a 1PPS synchronization signal;

[0008] One small wave data is selected, and the small wave data is compensated according to a pre-calculated direct current bias;

[0009] The large wave data and the small wave data are respectively amplitude-modulated;

[0010] The amplitude-modulated large wave data or small wave data is selected and output according to a BDC signal;

[0011] The large wave data and the small wave data are converted into analog signals.

[0012] Further, the modulation ratios of different small wave data in the plurality of small wave data are different.

[0013] Further, before the waveform data is imported into the ROM of FPGA, the waveform data is converted into a binary file that can be imported into the FPGA.

[0014] Further, one of the plurality of wavelet data is selected, and the selected wavelet data is compensated according to a pre-calculated DC bias, including:

[0015] The plurality of wavelet data is selected by a multiplexer.

[0016] The selected wavelet data is compensated by an adder according to the pre-calculated DC bias.

[0017] Further, the large wave data and the plurality of wavelet data are amplitude-modulated respectively, including:

[0018] The large wave data and the plurality of wavelet data are amplitude-modulated by multipliers respectively.

[0019] According to a second aspect of the present application, a system for generating AC IRIG-B code based on FPGA, comprising:

[0020] An FPGA module is configured to receive and store waveform data, the waveform data including large wave data and a plurality of wavelet data; read the large wave data and the plurality of wavelet data based on a 1PPS synchronization signal; select one of the plurality of wavelet data, and compensate the selected wavelet data according to a pre-calculated DC bias; amplitude-modulate the large wave data and the plurality of wavelet data respectively; select and output the amplitude-modulated large wave data or the amplitude-modulated wavelet data according to a BDC signal;

[0021] A DAC module is configured to receive the large wave data and the plurality of wavelet data output by the FPGA module, and convert the large wave data and the plurality of wavelet data into analog signals.

[0022] Further, the plurality of wavelet data have different modulation ratios.

[0023] Further, one of the plurality of wavelet data is selected, and the selected wavelet data is compensated according to a pre-calculated DC bias, including:

[0024] The plurality of wavelet data is selected by a multiplexer.

[0025] The selected wavelet data is compensated by an adder according to the pre-calculated DC bias.

[0026] Further, the large wave data and the plurality of wavelet data are amplitude-modulated respectively, including:

[0027] The large wave data and the plurality of wavelet data are amplitude-modulated by multipliers respectively.

[0028] The beneficial effects of the present application are: the embodiment utilizes the logic resources inside the FPGA to modulate the BDC signal into the BAC signal, and the modulation precision can be further improved by increasing the sampling rate of the DAC.For example, when the sampling rate is 250KHz, the carrier frequency is 1K, one symbol is 10MS, the sampling point number is 2500, and the theoretical precision can reach 4us. The address register lookup table can ensure that each symbol has 10 complete sine periods, preventing data errors. The multiplexer can select data with different modulation ratios, and the multiplier can adjust the signal amplitude. By adding a DC bias to the wavelet (the bias value can be calculated in advance and stored in the FPGA register), the continuity of the wavelet is ensured. The high and low levels of the BDC are used as wavelet switching signals. The digital signal output by the FPGA can be directly converted into an analog signal by the DAC

[0029] (1) The present application utilizes the logic resources inside the FPGA to modulate the BDC signal into the BAC signal, and the modulation precision can be further improved by increasing the sampling rate of the DAC. For example, when the sampling rate is 250KHz, the carrier frequency is 1K, one symbol is 10MS, the sampling point number is 2500, and the theoretical precision can reach 4us.

[0030] (2) By adding a DC bias compensation to the wavelet, the continuity of the wavelet is ensured.

[0031] (3) The modulation part of the present application is realized by logic, and has high portability and simple hardware. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a flow chart of an embodiment of the generation method of the alternating IRIG-B code in the present application;

[0033] Figure 2 is a schematic diagram of a measured waveform;

[0034] Figure 3 is a precision schematic diagram in an embodiment. DETAILED DESCRIPTION

[0035] The technical solutions of the present application will be described in detail below with reference to the embodiments. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0036] Referring to Figures 1-3 , the present embodiment provides a generation method and system of alternating IRIG-B code based on FPGA:

[0037] The first aspect of the present application provides a method for generating an alternating IRIG-B code based on FPGA. Figure 1 As shown in the figure, the method for generating the alternating IRIG-B code comprises:

[0038] S100. Generating waveform data and importing the waveform data into the ROM of the FPGA, wherein the waveform data comprises large wave data and a plurality of small wave data.

[0039] For example, taking 250-point data of one period of 16-bit data as an example, the data can be exported by software (such as Excel) and converted into binary data. In order to realize the adjustment of the amplitude, the original data can be reduced by the required multiple, and in this case, the large wave amplitude is adjustable from 0.5V to 10V with a step of 0.5V. 10V corresponds to 65536, so 0.5V is 65536 / 20=3276. The original data / 20 (i.e. the original data divided by 20) obtains the ROM of the large wave. The way to realize the modulation ratio is to cooperate with different small waves. When the modulation ratio is 6:1, the small wave ROM data is the original data / 20 / 6 (i.e. the original data divided by 20 and then divided by 6). When the modulation ratio is 5:1, the small wave ROM data is the original data / 20 / 5 (i.e. the original data divided by 20 and then divided by 5). 4:1, 3:1, 2:1 and so on can be extended to n:1, and similarly, the amplitude can also be adjusted by n times. In this case, the original data is reduced by 20 times when generating the waveform data, so that there will be no overflow when adjusting the amplitude (such as multiplying by 20 times).

[0040] Generally, before importing the waveform data into the ROM of the FPGA, the waveform data is converted into a binary file that can be imported into the FPGA. For example, Gaoke is an MI file and xilinx is a coe file.

[0041] Specifically, the modulation ratios of different small wave data in the plurality of small wave data are different.

[0042] S200. Reading the large wave data and the small wave data based on the 1PPS synchronization signal.

[0043] For example, the address register looks up the large wave data and the small wave data according to the second edge trigger of the 1PPS synchronization signal. The 1PPS synchronization signal is used to realize second synchronization, ensure that the symbols output by the BAC are synchronized with the second, and ensure the timing accuracy.

[0044] S300. Selecting one small wave data and compensating the small wave data according to the direct current bias calculated in advance.

[0045] For example, the modulation ratio of the required wavelet data is determined, the wavelet data with the corresponding modulation ratio is selected from a plurality of wavelet data by a multiplexer, and the wavelet data is compensated by an adder according to a pre-calculated direct current bias. The continuity of the subsequent waveform can be ensured by compensating the direct current bias of the wavelet data.

[0046] S400. The large wave data and the small wave data are respectively amplitude modulated.

[0047] In some embodiments, the large wave data and the small wave data are respectively amplitude modulated by a multiplier. Generally, the same coefficient is multiplied when the large wave data and the small wave data are amplitude modulated.

[0048] S500. The amplitude-modulated large wave data or small wave data is selected and output according to the BDC signal.

[0049] That is, the BDC signal is used to switch the output of the large wave and the small wave, for example, the large wave data is output when the BDC signal is at a high level, and the small wave data is output when the BDC signal is at a low level.

[0050] The amplitude-modulated large wave data or small wave data is output to a DAC module in this step.

[0051] S600. The large wave data and the small wave data are converted into analog signals.

[0052] Specifically, the DAC module converts the large wave data and the small wave data from the FPGA module into analog signals.

[0053] As shown in FIG. 6, the waveform when the amplitude is 0.5V (DAC output 0.26V, and the hardware operational amplifier amplifies twice), and the modulation ratio is 6:1. The high-low level waveform is a 1pps synchronization signal, and the sinusoidal waveform is the waveform of the BAC. As shown in FIG. 7, the precision when the sampling rate is 500K is 2us. Figure 2 Figure 3

[0054] This embodiment uses the logic resources in the FPGA to modulate the BDC signal into the BAC signal, and the modulation precision can be further improved by increasing the DAC sampling rate. For example, when the sampling rate is 250KHz, the carrier frequency is 1K, one symbol is 10MS, the sampling point number is 2500, and the theoretical precision can be up to 4us. The address register lookup table can ensure that each symbol has 10 complete sinusoidal periods, preventing data errors. The multiplexer can select data with different modulation ratios, and the multiplier can adjust the signal amplitude. By adding a direct current bias to the small wave (the bias value can be calculated in advance and stored in the register of the FPGA), the continuity of the large wave and the small wave is ensured. The high-low level of the BDC is used as a switching signal of the large wave and the small wave. The digital signal from the FPGA can be directly converted into an analog signal by the DAC.

[0055] ​​It should be noted that the numbering of the steps in the embodiment does not mean that the corresponding steps must be executed in the order of the numbering.

[0056] The second aspect of the application provides an FPGA-based AC IRIG-B code generation system, comprising an FPGA module and a DAC module.

[0057] The FPGA module is configured to receive and store waveform data, wherein the waveform data comprises a large wave data and a plurality of small wave data; read the large wave data and the small wave data based on a 1PPS synchronization signal; select one small wave data and compensate the small wave data according to a pre-calculated direct current bias; respectively amplify the large wave data and the small wave data; and select and output the amplified large wave data or small wave data according to a BDC signal.

[0058] Generally, the modulation ratios of different small wave data in the plurality of small wave data are different. By compensating the direct current bias of the small wave data, the continuity of the subsequent output signal can be ensured. Generally, the coefficients for amplifying the large wave data and the small wave data are the same.

[0059] The DAC module is configured to receive the large wave data and the small wave data output by the FPGA module, and convert the large wave data and the small wave data into an analog signal.

[0060] The above only describes the preferred embodiments of the application, and it should be understood that the application is not limited to the forms disclosed herein, and should not be considered as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concepts described herein by the above teachings or related art or knowledge. Any modification and change made by those skilled in the art without departing from the spirit and scope of the application shall be within the protection scope of the appended claims of the application.

Claims

1. A method for generating AC IRIG-B code based on FPGA, characterized in that, The method comprises the following steps: generating waveform data, and importing the waveform data into a ROM of an FPGA, wherein the waveform data comprises large wave data and a plurality of small wave data; reading the large wave data and the small wave data based on a 1PPS synchronization signal; selecting one small wave data, and compensating the small wave data according to a pre-calculated direct current bias; amplifying the large wave data and the small wave data respectively; selecting and outputting the amplified large wave data or small wave data according to a BDC signal; converting the large wave data and the small wave data into analog signals; the modulation ratios of different small wave data in the plurality of small wave data are different; selecting one small wave data comprises determining the modulation ratio of the required small wave data, and selecting the small wave data with the corresponding modulation ratio from the plurality of small wave data by using a multiplexer.

2. The method for generating AC IRIG-B code based on FPGA according to claim 1, characterized in that, Before importing the waveform data into the ROM of the FPGA, the waveform data is converted into a binary file that can be imported into the FPGA.

3. The method for generating AC IRIG-B code based on FPGA according to claim 1, characterized in that, selecting one small wave data and compensating the small wave data according to a pre-calculated direct current bias comprises: selecting one small wave data from the plurality of small wave data by using a multiplexer; compensating the small wave data by using an adder according to the pre-calculated direct current bias.

4. The method for generating AC IRIG-B code based on FPGA according to claim 1, characterized in that, amplifying the large wave data and the small wave data respectively comprises: amplifying the large wave data and the small wave data by using multipliers respectively.

5. A system for generating AC IRIG-B code based on FPGA, characterized in that, The method comprises the following steps: an FPGA module is used for receiving and storing waveform data, wherein the waveform data comprises large wave data and a plurality of small wave data; reading the large wave data and the small wave data based on a 1PPS synchronization signal; selecting one small wave data, and compensating the small wave data according to a pre-calculated direct current bias; amplifying the large wave data and the small wave data respectively; and selecting and outputting the amplified large wave data or small wave data according to a BDC signal; a DAC module is used for receiving the large wave data and the small wave data output by the FPGA module, and converting the large wave data and the small wave data into analog signals; the modulation ratios of different small wave data in the plurality of small wave data are different; selecting one small wave data comprises determining the modulation ratio of the required small wave data, and selecting the small wave data with the corresponding modulation ratio from the plurality of small wave data by using a multiplexer.

6. The FPGA-based generation of AC IRIG-B code system of claim 5, wherein, selecting one small wave data and compensating the small wave data according to a pre-calculated direct current bias comprises: selecting one small wave data from the plurality of small wave data by using a multiplexer; compensating the small wave data by using an adder according to the pre-calculated direct current bias.

7. The FPGA-based AC IRIG-B code generation system of claim 5, wherein, amplifying the large wave data and the small wave data respectively comprises: amplifying the large wave data and the small wave data by using multipliers respectively.

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