Mapping table updating method, memory storage device and memory control circuit unit

Abstract

The present invention provides a mapping table update method, a memory storage device, and a memory control circuit unit. The method comprises: receiving multiple operation instructions from a host system; performing a first table update operation according to a first operation instruction and a third operation instruction among the multiple operation instructions to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and, after completing the first table update operation, performing a second table update operation according to a second operation instruction among the multiple operation instructions to read and update a second mapping table from the rewritable non-volatile memory module. This effectively improves the efficiency of mapping table updates.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and in particular to a mapping table updating method, a memory storage device and a memory control circuit unit. Background Art

[0002] The rapid growth of smartphones, tablets, and personal computers in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideal for integration into the various portable multimedia devices mentioned above due to their non-volatility, power efficiency, compact size, and mechanical structure.

[0003] When reading or writing data to a rewritable non-volatile memory module, the memory controller reads one or more mapping tables from the rewritable non-volatile memory module into a buffer memory. The memory controller then accesses data from the rewritable non-volatile memory module and updates the mapping tables accordingly based on the mapping information in the mapping tables. The updated mapping tables are then stored back in the rewritable non-volatile memory module.

[0004] Typically, a memory controller reads the mapping table required for each operation, one by one, based on the multiple operation instructions in the instruction buffer. However, if the logic units corresponding to the multiple operation instructions in the instruction buffer are widely dispersed, the memory controller will frequently read and write the mapping table from the rewritable non-volatile memory module, resulting in excessive write amplification (WA). Excessive WA can significantly increase the wear and tear of the rewritable non-volatile memory module, thereby reducing its service life. Summary of the Invention

[0005] The present invention provides a mapping table updating method, a memory storage device and a memory control circuit unit, which can effectively improve the updating efficiency of the mapping table.

[0006] An exemplary embodiment of the present invention provides a mapping table update method for a rewritable non-volatile memory module. The mapping table update method comprises: receiving a plurality of operation instructions from a host system, wherein the plurality of operation instructions include a first operation instruction, a second operation instruction, and a third operation instruction, wherein the first operation instruction instructs to update data belonging to a first logical unit, the second operation instruction instructs to update data belonging to a second logical unit, and the third operation instruction instructs to update data belonging to a third logical unit; performing a first table update operation according to the first operation instruction and the third operation instruction, wherein the first table update operation comprises: reading a first mapping table from the rewritable non-volatile memory module to a buffer memory; reading a first address information from the rewritable non-volatile memory module according to first address information in the first mapping table; The first sub-mapping table and the third sub-mapping table are stored in the buffer memory; and the first mapping table and the third mapping table are updated in the buffer memory according to the first operation instruction and the third operation instruction; and after completing the first table update operation, a second table update operation is performed according to the second operation instruction, wherein the second table update operation includes: reading the second mapping table from the rewritable non-volatile memory module to the buffer memory; reading the second sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to the second address information in the second mapping table; and updating the second sub-mapping table in the buffer memory according to the second operation instruction.

[0007] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit, wherein the connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: receive a plurality of operation instructions from the host system, wherein the plurality of operation instructions include a first operation instruction, a second operation instruction and a third operation instruction, wherein the first operation instruction indicates to update the data belonging to the first logical unit, the second operation instruction indicates to update the data belonging to the second logical unit, and the third operation instruction indicates to update the data belonging to the third logical unit; perform a first table update operation according to the first operation instruction and the third operation instruction, wherein the first table update operation includes: reading a first mapping table from the rewritable non-volatile memory module to a buffer memory; reading a first address information from the rewritable non-volatile memory module according to the first address information in the first mapping table; The block reads the first sub-mapping table and the third sub-mapping table to the buffer memory; and updates the first mapping table and the third mapping table in the buffer memory according to the first operation instruction and the third operation instruction; and after completing the first table update operation, performs a second table update operation according to the second operation instruction, wherein the second table update operation includes: reading the second mapping table from the rewritable non-volatile memory module to the buffer memory; reading the second sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to the second address information in the second mapping table; and updating the second mapping table in the buffer memory according to the second operation instruction.

[0008] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used to: receive a plurality of operation instructions from the host system, wherein the plurality of operation instructions include a first operation instruction, a second operation instruction, and a third operation instruction, wherein the first operation instruction indicates an update of data belonging to a first logical unit, the second operation instruction indicates an update of data belonging to a second logical unit, and the third operation instruction indicates an update of data belonging to a third logical unit; perform a first table update operation according to the first operation instruction and the third operation instruction, wherein the first table update operation includes: reading a first mapping table from the rewritable non-volatile memory module to a buffer memory; and reading a first address information from the rewritable non-volatile memory module according to the first address information in the first mapping table. Reading the first sub-mapping table and the third sub-mapping table to the buffer memory; and updating the first mapping table and the third mapping table in the buffer memory according to the first operation instruction and the third operation instruction; and after completing the first table update operation, performing a second table update operation according to the second operation instruction, wherein the second table update operation includes: reading the second mapping table from the rewritable non-volatile memory module to the buffer memory; reading the second sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to the second address information in the second mapping table; and updating the second mapping table in the buffer memory according to the second operation instruction.

[0009] Based on the above, after receiving multiple operation instructions from the host system, the first table update operation can be performed according to the first operation instruction and the third operation instruction in the operation instructions. In the first table update operation, the first mapping table can be first read from the rewritable non-volatile memory module, and then the first sub-mapping table and the third sub-mapping table can be read from the rewritable non-volatile memory module according to the first address information in the first mapping table for updating. After completing the first table update operation, the second table update operation can be performed according to the second operation instruction in the operation instruction. In the second table update operation, the second mapping table can be first read from the rewritable non-volatile memory module, and then the second sub-mapping table can be read from the rewritable non-volatile memory module according to the second address information in the second mapping table for updating. In this way, the query efficiency of a single mapping table can be optimized and / or the number of times the mapping table is read and written can be effectively reduced. In this way, the update efficiency of the mapping table can be effectively improved and / or the write amplification to the rewritable non-volatile memory module can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0011] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0012] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0013] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0014] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0015] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0016] Figure 7 is a schematic diagram of multi-layer mapping according to an exemplary embodiment of the present invention;

[0017] Figures 8 to 10 is a schematic diagram of a mapping table update operation according to an exemplary embodiment of the present invention;

[0018] Figure 11 FIG. 4 is a flowchart of a method for updating a mapping table according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0020] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to the memory storage device or read data from the memory storage device.

[0021] Figure 1FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0022] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 , and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 , and the data transmission interface 114 may be connected to a system bus 110 .

[0023] In one exemplary embodiment, the host system 11 may be connected to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 may be connected to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I / O device 12 or receive input signals from the I / O device 12 via the system bus 110.

[0024] In one exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 via a wired or wireless method.

[0025] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a Wi-Fi (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a display 209, and a speaker 210, via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0026] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can each include Figure 3 The memory storage device 30 and the host system 31 are connected.

[0027] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0028] Figure 4 FIG is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0029] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In one exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0030] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions from the host system 11.

[0031] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which each cell can store one bit), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which each cell can store two bits), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which each cell can store three bits), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which each cell can store four bits), other flash memory modules, or other memory modules with similar characteristics.

[0032] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining the one or more bits stored in the memory cell.

[0033] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical erasing cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than two bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0034] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit may be a physical page or a physical sector. If a physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area includes 32 physical sectors, and the size of each physical sector is 512 bytes (bytes). However, in other exemplary embodiments, the data bit area may include 8, 16, or a larger or smaller number of physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erase. That is, each physical erase unit contains the minimum number of storage cells to be erased together. For example, a physical erase unit is a physical block.

[0035] Figure 5 FIG is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0036] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 is in operation, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0037] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 includes a microprocessor unit (not shown) and a read-only memory (ROM) (not shown), and these control instructions are burned into the ROM. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0038] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in the form of program code in a specific area of the rewritable non-volatile memory module 43 (e.g., a system area of the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (RAM) (not shown). Specifically, the ROM includes a boot code. When the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the RAM of the memory management circuit 51. The microprocessor unit then executes these control instructions to perform operations such as writing, reading, and erasing data.

[0039] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 43 to write data to the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0040] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0041] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and corresponding command sequences for instructing various memory operations (e.g., changing a read voltage level or performing garbage collection operations). These command sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0042] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0043] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure data accuracy. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates an error correcting code (ECC) and / or an error detecting code (EDC) corresponding to the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it also reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0044] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10 .

[0045] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0046] Figure 6 FIG is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602 .

[0047] In one exemplary embodiment, a physical unit includes one or more physical programming units. A physical unit may include multiple physical nodes. In one exemplary embodiment, each physical node may store data with a length of 4 KB. In one exemplary embodiment, each physical node may also store more or less data, and the present invention is not limited thereto.

[0048] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1 user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1) to 610(B) in the idle area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In one exemplary embodiment, the idle area 602 is also called a free pool.

[0049] The memory management circuit 51 can configure logical units 612(0)-612(C) to map physical units 610(0)-610(A) in the storage area 601. In one exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple consecutive or non-consecutive logical addresses.

[0050] Note that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it indicates that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, it indicates that the data currently stored in the physical unit is invalid data.

[0051] Note that a logical unit can also be mapped to one or more physical nodes. If a physical node is currently mapped by a logical unit, it means that the data currently stored in this physical node includes valid data. Conversely, if a physical node is not currently mapped by any logical unit, it means that the data currently stored in this physical node is invalid data.

[0052] In one exemplary embodiment, the memory management circuit 51 may record mapping information (also referred to as logical-to-physical mapping information) describing the mapping relationship between logical units and physical units (or physical nodes) in at least one mapping table (also referred to as a logical-to-physical mapping table). When the host system 11 wishes to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 based on the information in the mapping table (i.e., the mapping information). In one exemplary embodiment, the memory management circuit 51 uses a multi-layer mapping to access the mapping table (i.e., the logical-to-physical mapping table).

[0053] Figure 7 is a schematic diagram of multi-layer mapping according to an exemplary embodiment of the present invention. Figure 7 In one exemplary embodiment, the memory management circuit 51 may establish a mapping table 71. The mapping table 71 corresponds to the logical range A. For example, the logical range A may include consecutive logical units LBA(0)-LBA(p).

[0054] In one exemplary embodiment, the memory management circuit 51 may further establish a sub-mapping table Tb(i). The sub-mapping table Tb(i) may be used to record mapping information related to the logical range A. For example, the memory management circuit 51 may store mapping information related to the logical range A in the sub-mapping table Tb(i). For example, the memory management circuit 51 may store mapping information related to at least one of the logical units LBA(0)-LBA(p) in the sub-mapping table Tb(i).

[0055] In one exemplary embodiment, the mapping table 71 may be used to record the address information of the sub-mapping table Tb(i). For example, the memory management circuit 51 may store the address information of the sub-mapping table Tb(i) in the mapping table 71. The address information of the sub-mapping table Tb(i) may reflect the storage address of the sub-mapping table Tb(i) in the rewritable non-volatile memory module 43. For example, the address information of the sub-mapping table Tb(i) may reflect the specific physical unit and / or physical node in the rewritable non-volatile memory module 43 where the sub-mapping table Tb(i) is stored. Thereafter, the memory management circuit 51 may access the sub-mapping table Tb(i) based on the information in the mapping table 71 (e.g., the address information of the sub-mapping table Tb(i)).

[0056] In an exemplary embodiment, the sub-mapping table Tb(i) may be used to record the mapping information of the logical unit LBA(x). For example, the logical unit LBA(x) may be one of the logical units LBA(0) to LBA(p). The memory management circuit 51 may store the mapping information of the logical unit LBA(x) in the sub-mapping table Tb(i). The mapping information of the logical unit LBA(x) may reflect the mapping relationship between the logical unit LBA(x) and a specific physical unit (or a specific physical node) in the rewritable non-volatile memory module 43. For example, the mapping information of the logical unit LBA(x) may reflect that the logical unit LBA(x) is mapped to the physical node 701 in the rewritable non-volatile memory module 43. Alternatively, from another perspective, the mapping information of the logical unit LBA(x) may reflect that the data belonging to the logical unit LBA(x) is stored in the physical node 701. Thereafter, the memory management circuit 51 may access the physical node 701 according to the information in the sub-mapping table Tb(i) (eg, mapping information of the logical unit LBA(x)).

[0057] In an exemplary embodiment, the memory management circuit 51 may further establish a mapping table 72. The mapping table 72 corresponds to the logical range B. For example, the logical range B may include consecutive logical units LBA(q)-LBA(r).

[0058] In one exemplary embodiment, the memory management circuit 51 may further establish a sub-mapping table Tb(j). Sub-mapping table Tb(j) may be used to record mapping information related to logical range B. For example, the memory management circuit 51 may store mapping information related to logical range B in sub-mapping table Tb(j). For example, the memory management circuit 51 may store mapping information related to at least one of logical units LBA(q)-LBA(r) in sub-mapping table Tb(j).

[0059] In one exemplary embodiment, the mapping table 72 may be used to record the address information of the sub-mapping table Tb(j). For example, the memory management circuit 51 may store the address information of the sub-mapping table Tb(j) in the mapping table 72. The address information of the sub-mapping table Tb(j) may reflect the storage address of the sub-mapping table Tb(j) in the rewritable non-volatile memory module 43. For example, the address information of the sub-mapping table Tb(j) may reflect the specific physical unit and / or physical node in the rewritable non-volatile memory module 43 where the sub-mapping table Tb(j) is stored. Thereafter, the memory management circuit 51 may access the sub-mapping table Tb(j) based on the information in the mapping table 72 (e.g., the address information of the sub-mapping table Tb(j)).

[0060] In an exemplary embodiment, the sub-mapping table Tb(j) may be used to record the mapping information of the logical unit LBA(y). For example, the logical unit LBA(y) may be one of the logical units LBA(q) to LBA(r). The memory management circuit 51 may store the mapping information of the logical unit LBA(y) in the sub-mapping table Tb(j). The mapping information of the logical unit LBA(y) may reflect the mapping relationship between the logical unit LBA(y) and a specific physical unit (or a specific physical node) in the rewritable non-volatile memory module 43. For example, the mapping information of the logical unit LBA(y) may reflect that the logical unit LBA(y) is mapped to the physical node 702 in the rewritable non-volatile memory module 43. Alternatively, from another perspective, the mapping information of the logical unit LBA(y) may reflect that the data belonging to the logical unit LBA(y) is stored in the physical node 702. Thereafter, the memory management circuit 51 may access the physical node 702 according to the information in the sub-mapping table Tb(j) (eg, the mapping information of the logical unit LBA(y)).

[0061] In one exemplary embodiment, mapping tables 71 and 72 are used to perform first-level mapping, and sub-mapping tables Tb(i) and Tb(j) are used to perform second-level mapping. For example, in the first-level mapping, the address information of sub-mapping table Tb(i) recorded in mapping table 71 can reflect the mapping relationship between sub-mapping table Tb(i) and the storage address of sub-mapping table Tb(i). In the second-level mapping, the mapping information of logical unit LBA(x) recorded in sub-mapping table Tb(i) can reflect the mapping relationship between logical unit LBA(x) and physical unit 701. In one exemplary embodiment, during the process of establishing the first-level mapping, the memory management circuit 51 can correspondingly update mapping tables 71 and / or 72, and during the process of establishing the second-level mapping, the memory management circuit 51 can correspondingly update sub-mapping tables Tb(i) and / or Tb(j). Furthermore, the total number of mapping tables used in the first-level mapping, the total number of mapping tables used in the second-level mapping, and the information recorded in each mapping table can be adjusted according to practical needs and are not limited by the present invention.

[0062] In one exemplary embodiment, the memory management circuit 51 may receive an operation command from the host system 11. This operation command may be used to instruct the reading, writing, or deletion of data belonging to the logical unit LBA(x). In response to this operation command, the memory management circuit 51 may send a read command sequence to the rewritable non-volatile memory module 43 based on the logical range A to which the logical unit LBA(x) belongs. This read command sequence may be used to read the mapping table 71 from the rewritable non-volatile memory module 43. The memory management circuit 51 may then cache the read mapping table 71 in the buffer memory 55.

[0063] After caching the mapping table 71 in the buffer memory 55, the memory management circuit 51 can obtain the address information of the sub-mapping table Tb(i) from the mapping table 71. The memory management circuit 51 can send a read command sequence to the rewritable non-volatile memory module 43 based on the address information of the sub-mapping table Tb(i). This read command sequence can be used to read the sub-mapping table Tb(i) from the rewritable non-volatile memory module 43. The memory management circuit 51 can then cache the read sub-mapping table Tb(i) in the buffer memory 55.

[0064] In one exemplary embodiment, in response to the operation instruction being a read instruction, the memory management circuit 51 may send a read instruction sequence to the rewritable non-volatile memory module 43 based on the mapping information of the logical unit LBA(x) in the sub-mapping table Tb(i). The read instruction sequence is used to instruct the rewritable non-volatile memory module 43 to read data belonging to the logical unit LBA(x) from the physical node 701.

[0065] In one exemplary embodiment, in response to the operation instruction being a write instruction, the memory management circuit 51 may update (e.g., add or modify) the mapping information of the logical unit LBA(x) in the sub-mapping table Tb(i). For example, the memory management circuit 51 may add mapping information that reflects the mapping relationship between the logical unit LBA(x) and the physical node 701 in the sub-mapping table Tb(i). At the same time, the memory management circuit 51 may send a write instruction sequence to the rewritable non-volatile memory module 43. This write instruction sequence is used to instruct the rewritable non-volatile memory module 43 to write the data stored as instructed by the write instruction to the physical node 701.

[0066] In one exemplary embodiment, in response to the operation instruction being a delete instruction, the memory management circuit 51 may also update (e.g., remove) the mapping information of the logical unit LBA(x) in the sub-mapping table Tb(i). For example, the memory management circuit 51 may remove the mapping information reflecting the mapping relationship between the logical unit LBA(x) and the physical node 701 in the sub-mapping table Tb(i). In one exemplary embodiment, removing the mapping information of the logical unit LBA(x) from the sub-mapping table Tb(i) is equivalent to deleting the data belonging to the logical unit LBA(x) from the rewritable non-volatile memory module 43.

[0067] In one exemplary embodiment, if the next operation command from the host system 11 instructs to read, write, or delete data belonging to the logical unit LBA(y), the memory management circuit 51 may first restore the mapping table 71 in the buffer memory 55 to the rewritable non-volatile memory module 43 to free up additional storage space in the buffer memory 55. The memory management circuit 51 may then send a read command sequence to the rewritable non-volatile memory module 43 based on the logical range B to which the logical unit LBA(y) belongs. This read command sequence may be used to read the mapping table 72 from the rewritable non-volatile memory module 43. The memory management circuit 51 may then cache the read mapping table 72 in the buffer memory 55. The memory management circuit 51 may then query the mapping table 72 to perform the relevant table query or update operation, which will not be repeated here.

[0068] It should be noted that, in an exemplary embodiment, if the multiple logical units to be accessed indicated by the multiple operation instructions received continuously from the host system 11 are located in different logical ranges, and the buffer memory 55 is used to store the mapping table required for performing the first layer mapping (e.g. Figure 7If the storage space of the mapping tables 71 and / or 72 is relatively limited, the multiple mapping tables required for performing the first-level mapping will be frequently read from and stored back to the rewritable non-volatile memory module 43 during the continuous execution of these operation instructions, thereby causing additional write amplification. In one exemplary embodiment, the memory management circuit 51 can improve this problem by using an optimized mapping table update mechanism.

[0069] Figures 8 to 10 Schematic diagram of the mapping table update operation according to an exemplary embodiment of the present invention. Figure 8 The memory management circuit 51 may receive a plurality of operation commands CMD(0) to CMD(4) from the host system 11. Each operation command may instruct to update data belonging to a specific logical unit. For example, the operation commands CMD(0) to CMD(4) may be used to update data belonging to logical units LBA(a) to LBA(e), respectively. For the sake of convenience, it is assumed that the operation commands CMD(0) to CMD(4) are all write commands.

[0070] In one exemplary embodiment, the memory management circuit 51 may sequentially cache the operation instructions CMD(0)-CMD(4) in a command queue of the buffer memory 55. For example, assuming that the operation instruction CMD(0) is received first and the operation instruction CMD(4) is received last, the order of the operation instructions CMD(0)-CMD(4) in the command queue is as follows: Figure 8 shown.

[0071] In one exemplary embodiment, it is assumed that logical units LBA(a), LBA(c), and LBA(e) belong to logical range A (i.e., LBA(0)-LBA(p)), and logical units LBA(b) and LBA(d) belong to logical range B (i.e., LBA(q)-LBA(r)). However, in another exemplary embodiment, the logical ranges to which logical units LBA(a)-LBA(e) belong may be adjusted according to practical needs, and the present invention is not limited thereto.

[0072] Please refer to Figure 8 and Figure 9 After receiving the operation instructions CMD(0) to CMD(4), the memory management circuit 51 can perform a table update operation (also called a first table update operation) according to the operation instructions CMD(0), CMD(2) and CMD(4) corresponding to the same logical range (i.e., logical range A) in the buffer memory 55.

[0073] In the first table update operation, the memory management circuit 51 may read the mapping table 71 (also referred to as the first mapping table) corresponding to the logical range A from the rewritable non-volatile memory module 43 and cache the mapping table 71 in the buffer memory 55. The mapping table 71 may record the address information of the sub-mapping tables Tb(0), Tb(2), and Tb(4). After obtaining the mapping table 71, the memory management circuit 51 may read the address information of the sub-mapping tables Tb(0), Tb(2), and Tb(4) from the mapping table 71. Based on the address information of the sub-mapping tables Tb(0), Tb(2), and Tb(4), the memory management circuit 51 may read the sub-mapping tables Tb(0), Tb(2), and Tb(4) from the rewritable non-volatile memory module 43. Then, the memory management circuit 51 may cache the sub-mapping tables Tb(0), Tb(2), and Tb(4) in the buffer memory 55.

[0074] After caching the sub-mapping tables Tb(0), Tb(2) and Tb(4) in the buffer memory 55, the memory management circuit 51 can update (for example, add or modify) the mapping information of the logical units LBA(a), LBA(c) and LBA(e) in the sub-mapping tables Tb(0), Tb(2) and Tb(4) respectively according to the operation instructions CMD(0), CMD(2) and CMD(4). For example, according to the operation instructions CMD(0), CMD(2), and CMD(4), the memory management circuit 51 may add mapping information of the logical unit LBA(a) in the sub-mapping table Tb(0) to reflect the mapping relationship between the logical unit LBA(a) and the physical node 901, add mapping information of the logical unit LBA(c) in the sub-mapping table Tb(2) to reflect the mapping relationship between the logical unit LBA(c) and the physical node 902, and add mapping information of the logical unit LBA(e) in the sub-mapping table Tb(4) to reflect the mapping relationship between the logical unit LBA(e) and the physical node 903. At the same time, the memory management circuit 51 may send multiple write command sequences to the rewritable non-volatile memory module 43 according to the operation instructions CMD(0), CMD(2), and CMD(4). These write command sequences are used to instruct the rewritable non-volatile memory module 43 to store the data indicated by the operation commands CMD( 0 ), CMD( 2 ) and CMD( 4 ) in the physical nodes 901 ˜ 903 , respectively.

[0075] In one exemplary embodiment, the memory management circuit 51 continuously checks whether there are any unexecuted operation instructions corresponding to the logical range A in the buffer memory 55. In response to the absence of any unexecuted operation instructions corresponding to the logical range A in the buffer memory 55, the memory management circuit 51 may restore the mapping table 71 to the rewritable non-volatile memory module 43. However, if there are any unexecuted operation instructions corresponding to the logical range A in the buffer memory 55, the memory management circuit 51 may temporarily retain the mapping table 71 in the buffer memory 55 and continue to perform the first table update operation based on the mapping table 71. In addition, after restoring the mapping table 71 to the rewritable non-volatile memory module 43, the memory management circuit 51 may delete the mapping table 71 from the buffer memory 55 to release new storage space.

[0076] In one exemplary embodiment, before restoring the mapping table 71, the memory management circuit 51 may also update the address information of the sub-mapping tables Tb(0), Tb(2), and Tb(4) in the mapping table 71. For example, the updated address information of the sub-mapping tables Tb(0), Tb(2), and Tb(4) may reflect the new storage addresses of the sub-mapping tables Tb(0), Tb(2), and Tb(4) in the rewritable non-volatile memory module 43. Then, the memory management circuit 51 may restore the updated mapping table 71 to the rewritable non-volatile memory module 43. Thereafter, the memory management circuit 51 may store the sub-mapping tables Tb(0), Tb(2), and Tb(4) at the new storage addresses.

[0077] Please refer to Figure 8 and Figure 10 After completing the update of the sub-mapping tables Tb(0), Tb(2) and Tb(4) (i.e., the first table update operation), the memory management circuit 51 can perform another table update operation (also referred to as the second table update operation) according to the operation instructions CMD(1) and CMD(3) corresponding to another logical range (i.e., logical range B) in the buffer memory 55.

[0078] In the second table update operation, the memory management circuit 51 may read the mapping table 72 (also referred to as the second mapping table) corresponding to the logical range B from the rewritable non-volatile memory module 43 and cache the mapping table 72 in the buffer memory 55. The mapping table 72 may record the address information of the sub-mapping tables Tb(1) and Tb(3). After obtaining the mapping table 72, the memory management circuit 51 may read the address information of the sub-mapping tables Tb(1) and Tb(3) from the mapping table 72. Based on the address information of the sub-mapping tables Tb(1) and Tb(3), the memory management circuit 51 may read the sub-mapping tables Tb(1) and Tb(3) from the rewritable non-volatile memory module 43. Then, the memory management circuit 51 may cache the sub-mapping tables Tb(1) and Tb(3) in the buffer memory 55.

[0079] After caching the sub-mapping tables Tb(1) and Tb(3) in the buffer memory 55, the memory management circuit 51 may update (e.g., add or modify) the mapping information of the logical units LBA(b) and LBA(d) in the sub-mapping tables Tb(1) and Tb(3) respectively according to the operation instructions CMD(1) and CMD(3). For example, according to the operation instructions CMD(1) and CMD(3), the memory management circuit 51 may add the mapping information of the logical unit LBA(b) in the sub-mapping table Tb(1) to reflect the mapping relationship between the logical unit LBA(b) and the physical node 1001 and add the mapping information of the logical unit LBA(d) in the sub-mapping table Tb(3) to reflect the mapping relationship between the logical unit LBA(d) and the physical node 1002. At the same time, the memory management circuit 51 may send multiple write command sequences to the rewritable non-volatile memory module 43 according to the operation instructions CMD(1) and CMD(3). These write command sequences are used to instruct the rewritable non-volatile memory module 43 to store the data indicated by the operation commands CMD( 1 ) and CMD( 3 ) into the physical nodes 1001 and 1002 , respectively.

[0080] In one exemplary embodiment, the memory management circuit 51 may continuously check whether there are any unexecuted operation instructions corresponding to the logical range B in the buffer memory 55. In response to the absence of any unexecuted operation instructions corresponding to the logical range B in the buffer memory 55, the memory management circuit 51 may restore the mapping table 72 to the rewritable non-volatile memory module 43. However, if there are any unexecuted operation instructions corresponding to the logical range B in the buffer memory 55, the memory management circuit 51 may temporarily retain the mapping table 72 in the buffer memory 55 and continue to perform the second table update operation based on the mapping table 72.

[0081] In one exemplary embodiment, before restoring the mapping table 72, the memory management circuit 51 may also update the address information of the sub-mapping tables Tb(1) and Tb(3) in the mapping table 72. For example, the updated address information of the sub-mapping tables Tb(1) and Tb(3) may reflect the new storage addresses of the sub-mapping tables Tb(1) and Tb(3) in the rewritable non-volatile memory module 43. Thereafter, the memory management circuit 51 may store the sub-mapping tables Tb(1) and Tb(3) at the new storage addresses.

[0082] In particular, Figure 8 In the exemplary embodiment, by updating the mapping tables in the buffer memory 55, either once or continuously, for operation instructions corresponding to the same logical range, the access frequency of the mapping tables used for the first-level mapping (e.g., mapping tables 71 and 72) can be effectively reduced. This effectively improves the efficiency of updating the mapping tables and / or reduces write amplification on the rewritable non-volatile memory module. Furthermore, if the capacity of the buffer memory 55 is large, multiple mapping tables used for the first-level mapping (e.g., mapping tables 71 and 72) can also be stored in the buffer memory 55 and used simultaneously, although the present invention is not limited thereto.

[0083] Figure 11 is a flow chart of a method for updating a mapping table according to an exemplary embodiment of the present invention. Figure 11 , in step S1110, multiple operation instructions are received from the host system. In step S1120, a first table update operation is performed according to a first operation instruction and a third operation instruction among the multiple operation instructions. Step S1120 may include steps S1121 to S1123. In step S1121, a first mapping table is read from a rewritable non-volatile memory module to a buffer memory. In step S1122, a first sub-mapping table and a third sub-mapping table are read from a rewritable non-volatile memory module to a buffer memory according to first address information in the first mapping table. In step S1123, first mapping information in the first sub-mapping table and third mapping information in the third sub-mapping table are updated in the buffer memory according to the first operation instruction and the third operation instruction.

[0084] After completing the first table update operation, in step S1130, a second table update operation is performed according to a second operation instruction among the multiple operation instructions. Step S1130 may include steps S1131 to S1133. In step S1131, the second mapping table is read from the rewritable non-volatile memory module into the buffer memory. In step S1132, the second sub-mapping table is read from the rewritable non-volatile memory module into the buffer memory according to the second address information in the second mapping table. In step S1133, the second mapping information in the second sub-mapping table is updated in the buffer memory according to the second operation instruction.

[0085] However, Figure 11 The steps have been described in detail above and will not be repeated here. Figure 11 Each step can be implemented as multiple program codes or circuits, which is not limited in this case. Figure 11 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and this case is not limited thereto.

[0086] In summary, the mapping table update method, memory storage device, and memory control circuit unit proposed in exemplary embodiments of the present invention can effectively reduce the access frequency of the mapping table used for the first-level mapping by updating the mapping table for operation instructions corresponding to the same logical range in the buffer memory, either once or continuously. This effectively improves the efficiency of mapping table updates and / or reduces write amplification in the rewritable non-volatile memory module.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A mapping table updating method, characterized in that: For a rewritable non-volatile memory module, the mapping table updating method includes: receiving a plurality of operation instructions from the host system, wherein the plurality of operation instructions include a first operation instruction, a second operation instruction, and a third operation instruction, wherein the first operation instruction instructs to update data belonging to the first logical unit, the second operation instruction instructs to update data belonging to the second logical unit, and the third operation instruction instructs to update data belonging to the third logical unit; Perform a first table update operation according to the first operation instruction and the third operation instruction, wherein the first table update operation includes: Reading a first mapping table from the rewritable non-volatile memory module to a buffer memory; Reading the first sub-mapping table and the third sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to the first address information in the first mapping table; and updating the first sub-mapping table and the third sub-mapping table in the buffer memory according to the first operation instruction and the third operation instruction; and After completing the first table update operation, performing a second table update operation according to the second operation instruction, wherein the second table update operation includes: Reading a second mapping table from the rewritable non-volatile memory module to a buffer memory; Reading a second sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to second address information in the second mapping table; and The second sub-mapping table is updated in the buffer memory according to the second operation instruction.

2. The mapping table updating method according to claim 1, wherein the first address information reflects the first storage address of the first sub-mapping table and the third sub-mapping table in the rewritable non-volatile memory module, and the second address information reflects the second storage address of the second sub-mapping table in the rewritable non-volatile memory module.

3. The mapping table updating method according to claim 1 , wherein the step of updating the first sub-mapping table in the buffer memory comprises: Updating the first mapping information of the first logical unit in the first sub-mapping table, The step of updating the second sub-mapping table in the buffer memory comprises: updating the second mapping information of the second logical unit in the second sub-mapping table, and The step of updating the third sub-mapping table in the buffer memory comprises: The third mapping information of the third logical unit is updated in the third sub-mapping table.

4. The mapping table updating method according to claim 1 , wherein the first table updating operation further comprises: After updating the first sub-mapping table and the third sub-mapping table, the first mapping table is restored to the rewritable non-volatile memory module to release storage space in the buffer memory for storing the second mapping table. 5 . The mapping table updating method according to claim 1 , wherein the first logical unit and the third logical unit belong to a first logical range, the second logical unit belongs to a second logical range, and the first logical range is different from the second logical range.

6. The mapping table updating method according to claim 1, further comprising: caching the plurality of operation instructions in the instruction queue of the buffer memory, Wherein, in the instruction queue, the second operation instruction is arranged between the first operation instruction and the third operation instruction.

7. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; Rewritable non-volatile memory module; as well as a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module; The memory control circuit unit is used to: receiving a plurality of operation instructions from the host system, wherein the plurality of operation instructions include a first operation instruction, a second operation instruction, and a third operation instruction, wherein the first operation instruction instructs to update data belonging to the first logical unit, the second operation instruction instructs to update data belonging to the second logical unit, and the third operation instruction instructs to update data belonging to the third logical unit; Perform a first table update operation according to the first operation instruction and the third operation instruction, wherein the first table update operation includes: Reading a first mapping table from the rewritable non-volatile memory module to a buffer memory; Reading the first sub-mapping table and the third sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to the first address information in the first mapping table; and updating the first sub-mapping table and the third sub-mapping table in the buffer memory according to the first operation instruction and the third operation instruction; and After completing the first table update operation, performing a second table update operation according to the second operation instruction, wherein the second table update operation includes: Reading a second mapping table from the rewritable non-volatile memory module to a buffer memory; Reading a second sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to second address information in the second mapping table; and The second sub-mapping table is updated in the buffer memory according to the second operation instruction.

8. The memory storage device according to claim 7, wherein the first address information reflects a first storage address of the first sub-mapping table and the third sub-mapping table in the rewritable non-volatile memory module, and the second address information reflects a second storage address of the second sub-mapping table in the rewritable non-volatile memory module.

9. The memory storage device according to claim 7, wherein the operation of the memory control circuit unit updating the first sub-mapping table in the buffer memory comprises: Updating the first mapping information of the first logical unit in the first sub-mapping table, The operation of the memory control circuit unit updating the second sub-mapping table in the buffer memory includes: updating the second mapping information of the second logical unit in the second sub-mapping table, and The operation of the memory control circuit unit updating the third sub-mapping table in the buffer memory includes: The third mapping information of the third logical unit is updated in the third sub-mapping table.

10. The memory storage device of claim 7, wherein the first table update operation further comprises: After updating the first sub-mapping table and the third sub-mapping table, the first mapping table is restored to the rewritable non-volatile memory module to release storage space in the buffer memory for storing the second mapping table. 11 . The memory storage device of claim 7 , wherein the first logical unit and the third logical unit belong to a first logical range, the second logical unit belongs to a second logical range, and the first logical range is different from the second logical range.

12. The memory storage device according to claim 7, wherein the memory control circuit unit is further configured to: caching the plurality of operation instructions in the instruction queue of the buffer memory, Wherein, in the instruction queue, the second operation instruction is arranged between the first operation instruction and the third operation instruction.

13. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, the memory control circuit unit includes: A host interface for connecting to a host system; a memory interface for connecting to the rewritable non-volatile memory module; and A memory management circuit connected to the host interface and the memory interface, The memory management circuit is used to: receiving a plurality of operation instructions from the host system, wherein the plurality of operation instructions include a first operation instruction, a second operation instruction, and a third operation instruction, wherein the first operation instruction instructs to update data belonging to the first logical unit, the second operation instruction instructs to update data belonging to the second logical unit, and the third operation instruction instructs to update data belonging to the third logical unit; Perform a first table update operation according to the first operation instruction and the third operation instruction, wherein the first table update operation includes: Reading a first mapping table from the rewritable non-volatile memory module to a buffer memory; Reading the first sub-mapping table and the third sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to the first address information in the first mapping table; and updating the first sub-mapping table and the third sub-mapping table in the buffer memory according to the first operation instruction and the third operation instruction; and After completing the first table update operation, performing a second table update operation according to the second operation instruction, wherein the second table update operation includes: Reading a second mapping table from the rewritable non-volatile memory module to a buffer memory; Reading a second sub-mapping table from the rewritable non-volatile memory module to the buffer memory according to second address information in the second mapping table; and The second sub-mapping table is updated in the buffer memory according to the second operation instruction.

14. The memory control circuit unit according to claim 13, wherein the first address information reflects a first storage address of the first sub-mapping table and the third sub-mapping table in the rewritable non-volatile memory module, and the second address information reflects a second storage address of the second sub-mapping table in the rewritable non-volatile memory module.

15. The memory control circuit unit according to claim 13 , wherein the operation of the memory management circuit updating the first sub-mapping table in the buffer memory comprises: Updating the first mapping information of the first logical unit in the first sub-mapping table, The operation of the memory management circuit updating the second sub-mapping table in the buffer memory includes: updating the second mapping information of the second logical unit in the second sub-mapping table, and The operation of the memory management circuit updating the third sub-mapping table in the buffer memory includes: The third mapping information of the third logical unit is updated in the third sub-mapping table.

16. The memory control circuit unit according to claim 13, wherein the first table update operation further comprises: After updating the first sub-mapping table and the third sub-mapping table, the first mapping table is restored to the rewritable non-volatile memory module to release storage space in the buffer memory for storing the second mapping table. 17 . The memory control circuit unit according to claim 13 , wherein the first logic unit and the third logic unit belong to a first logic range, the second logic unit belongs to a second logic range, and the first logic range is different from the second logic range.

18. The memory control circuit unit according to claim 13, wherein the memory management circuit is further configured to: caching the plurality of operation instructions in the instruction queue of the buffer memory, Wherein, in the instruction queue, the second operation instruction is arranged between the first operation instruction and the third operation instruction.

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