Check circuit, method for neural network processor and neural network processor

Abstract

The embodiment of the application provides a check circuit, a method and a neural network processor for the neural network processor. The check circuit comprises a host processor, a check processor and an exclusive or comparison module. The host processor and the check processor configure a check working mode through an instruction channel. In an independent check working mode, the host processor and the check processor write the same first source data and first instructions into a first memory space and a second memory space respectively, obtain the first source data and the first instructions from the first memory space and the second memory space through two independent first data paths respectively, calculate first and second calculation results according to the obtained data respectively, and send the second calculation result to the host processor through a second data path. The exclusive or comparison module compares and checks the first and second calculation results. Through the provided check scheme, data checking of the neural network processor can be realized, and the check result is prevented from being affected by the outside world.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of neural network, and particularly relates to a check circuit, a method and a neural network processor for a neural network processor. BACKGROUND

[0002] With the rapid development of neural networks, the application fields of the neural networks are also more and more wide, for example, the neural networks are widely applied in target identification, economic prediction, intelligent driving and the like, and people's requirements for the neural networks are also continuously improved, and neural network products with mass production and high reliability are urgently needed. Most of the existing neural network processors can basically complete corresponding functions, but the reliability is always not good, and the data errors of the processors are caused by external environment influences such as electromagnetic interference (EMI), electro-static discharge (ESD) and the like, which limits the use fields, and therefore, it is urgent to provide a neural network processor with a check function. SUMMARY

[0003] In order to solve the above technical problems, the present application provides a check circuit, a method and a neural network processor for a neural network processor.

[0004] In a first aspect, the present application provides a check circuit for a neural network processor, comprising: the neural network processor comprising: a main processor and a check processor, the main processor and the check processor are connected, and the main processor comprises an exclusive or comparison module.

[0005] The main processor and the check processor are configured to configure a check working mode through an instruction channel, wherein the check working mode comprises an independent check working mode.

[0006] In the independent check working mode, the main processor and the check processor are configured to write same first source data and first instructions into a first memory space and a second memory space respectively, and the first memory space and the second memory space are memory spaces with same capacity and different addresses.

[0007] The main processor and the check processor are further configured to obtain the source data and the instructions from the first memory space and the second memory space through two independent first data paths respectively.

[0008] The main processor is further configured to calculate a first calculation result according to the source data and the instructions.

[0009] The check processor is further configured to calculate a second calculation result according to the first source data and the first instruction, and send the second calculation result to the main processor through a second data channel;

[0010] The XOR comparison module of the main processor is configured to compare and check the first calculation result and the second calculation result.

[0011] According to an embodiment of the present disclosure, the check working mode further includes a homologous check working mode;

[0012] In the homologous check working mode, the main processor is configured to read second source data and second instructions from an external memory, and send the second source data and the second instructions to the check processor through a third data channel;

[0013] The main processor is configured to calculate a third calculation result according to the second source data and the second instruction;

[0014] The check processor is configured to calculate a fourth calculation result according to the second source data and the second instruction;

[0015] The XOR comparison module of the main processor is configured to compare and check the third calculation result and the fourth calculation result.

[0016] According to an embodiment of the present disclosure, the main processor is configured to configure a prohibited check working mode through an instruction channel;

[0017] In the prohibited check working mode, the main processor or the check processor is configured to independently process data, and close the check function of the XOR comparison module.

[0018] According to an embodiment of the present disclosure, the XOR comparison module includes a first first-in-first-out queue and a second first-in-first-out queue;

[0019] In the independent check working mode, when the first first-in-first-out queue and the second first-in-first-out queue are not full, the first first-in-first-out queue is configured to receive the first calculation result, and the second first-in-first-out queue is configured to receive the second calculation result;

[0020] When the first first-in-first-out queue or the second first-in-first-out queue is full, the main processor is configured to block the data channels of the first first-in-first-out queue and the second first-in-first-out queue, and prohibit writing data to the first first-in-first-out queue and the second first-in-first-out queue;

[0021] When the first first-in-first-out queue or the second first-in-first-out queue is not empty, the exclusive or comparison module of the main processor is configured to synchronously read data of the same data segment of the first first-in-first-out queue and the second first-in-first-out queue.

[0022] According to an embodiment of the present disclosure, in the independent verification mode, the exclusive or comparison module of the main processor is configured to perform exclusive or operation on the first calculation result read from the first first-in-first-out queue and the second calculation result synchronously read from the second first-in-first-out queue bit by bit. If the result of the exclusive or operation is 1, an Error interrupt signal is triggered, and the verification result fails. If the result of the exclusive or operation is 0, the verification result passes, and the data read from the first first-in-first-out queue or the data read from the second first-in-first-out queue is written into an external memory.

[0023] According to an embodiment of the present disclosure, the exclusive or comparison module comprises a first first-in-first-out queue and a second first-in-first-out queue.

[0024] In the homologous verification mode, when the first first-in-first-out queue and the second first-in-first-out queue are not full, the first first-in-first-out queue is configured to receive the third calculation result, and the second first-in-first-out queue is configured to receive the fourth calculation result.

[0025] According to an embodiment of the present disclosure, the exclusive or comparison module of the main processor is configured to perform exclusive or operation on the third calculation result read from the first first-in-first-out queue and the fourth calculation result synchronously read from the second first-in-first-out queue bit by bit.

[0026] According to an embodiment of the present disclosure, the main processor further comprises a verification register.

[0027] The main processor is further configured to configure the verification register to start or close the verification function of the exclusive or comparison module.

[0028] In a second aspect, an embodiment of the present disclosure provides a verification method for a neural network processor, applied to the verification circuit for the neural network processor provided in the first aspect; the verification method comprises:

[0029] The main processor and the verification processor configure a verification working mode through an instruction channel, wherein the verification working mode comprises an independent verification working mode;

[0030] In the independent verification working mode, the main processor and the verification processor write the same first source data and first instructions into a first memory space and a second memory space respectively, and the first memory space and the second memory space are memory spaces with the same capacity and different addresses.

[0031] The main processor and the check processor obtain the first source data and the first instruction from the first memory space and the second memory space respectively through two independent first data paths;

[0032] The main processor calculates a first calculation result according to the first source data and the first instruction;

[0033] The check processor calculates a second calculation result according to the first source data and the first instruction, and sends the second calculation result to the main processor through a second data path;

[0034] The exclusive or comparison module of the main processor compares and checks the first calculation result and the second calculation result.

[0035] In a third aspect, an embodiment of the present application provides a neural network processor, which comprises a software end and a hardware end, and the hardware end comprises the check circuit for the neural network processor according to the first aspect.

[0036] The check circuit, the method and the neural network processor provided by the present application can realize data checking of the neural network processor, can flexibly set whether to enable checking according to user demand, have an independent checking working mode, a same-source checking working mode and a prohibited checking working mode, the main processor works independently and does not perform checking in the prohibited checking working mode, and the calculation results of the main processor and the check processor are checked bit by bit in the independent checking working mode and the same-source checking working mode, so that the processor failure caused by random data errors in an external harsh environment is avoided through the data checking mechanism of the main processor and the check processor. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope of protection of the present application. In each drawing, similar components are denoted by similar reference numerals.

[0038] Figure 1 Fig. 1 shows a structure schematic diagram of the check circuit for the neural network processor provided by an embodiment of the present application;

[0039] Figure 2 Fig. 2 shows another structure schematic diagram of the check circuit for the neural network processor provided by an embodiment of the present application;

[0040] Figure 3 Fig. 3 shows a structure schematic diagram of the neural network processor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application.

[0042] The components of the embodiments of the present application generally described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of the present application.

[0043] Hereinafter, the terms "include", "have", and their conjugates, used in various embodiments of the present application, are merely intended to denote a certain characteristic, number, step, operation, element, component, or a combination thereof, and not to exclude the presence or addition of one or more other characteristics, numbers, steps, operations, elements, components, or combinations thereof.

[0044] In addition, the terms "first", "second", "third", and the like are used only to distinguish the description, and cannot be understood as indicating or implying a relative importance.

[0045] Unless otherwise defined, all terms used herein (including technical terms and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. The terms (such as those defined in a generally used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized or overly formal meaning unless clearly defined in various embodiments of the present application.

[0046] Embodiment 1

[0047] The present embodiment provides a check circuit for a neural network processor.

[0048] Referring to Figure 1 The check circuit 100 for a neural network processor includes a host processor 101 and a check processor 102, the host processor 101 and the check processor 102 are connected, the host processor 101 includes an XOR comparison module 1011;

[0049] The main processor 101 and the check processor 102 are configured to configure a check working mode through an instruction channel, wherein the check working mode comprises an independent check working mode.

[0050] In the independent check working mode, the main processor 101 and the check processor 102 are respectively configured to write same first source data and first instructions into a first memory space and a second memory space, and the first memory space and the second memory space are memory spaces with same capacity and different addresses.

[0051] The main processor 101 and the check processor 102 are further configured to acquire the first source data and the first instructions from the first memory space and the second memory space through two independent first data channels respectively.

[0052] The main processor 101 is further configured to calculate a first calculation result according to the first source data and the first instructions.

[0053] The check processor 102 is further configured to calculate a second calculation result according to the first source data and the first instructions, and send the second calculation result to the main processor through a second data channel.

[0054] The XOR comparison module 1011 of the main processor 101 is configured to compare and check the first calculation result and the second calculation result.

[0055] It should be noted that the main processor can also be referred to as a primary core, the check processor can also be referred to as an auxiliary core, and the XOR comparison module can also be referred to as an XOR COMPARE module. The main processor and the check processor have same calculation logic, and the main difference lies in that the main processor integrates the XOR comparison module. The main processor 101 and the check processor 102 use different memory spaces. For example, a processing system (PS) end of a neural network processor allocates a first data segment and a second data segment with same size and different addresses on an external memory, and writes same source data and instructions into the first data segment and the second data segment respectively. The external memory can be a double data rate (DDR) memory, or other hard disks, etc. The main processor 101 and the check processor 102 acquire data on the corresponding first data segment and second data segment through two independent first data channels and perform calculation, the second calculation result of the check processor 102 is output to the main processor 101 through a data channel, and the XOR comparison module compares and checks the second calculation result of the check processor 102 and the first calculation result of the main processor 101.

[0056] In the embodiment, the check work mode can be configured by the instruction channel, and the check work mode includes the independent check work mode, the same source check work mode and the prohibited check work mode.

[0057] In an embodiment, the check work mode further includes the same source check work mode.

[0058] In the same source check work mode, the main processor 101 is configured to read second source data and second instructions from an external memory and send the second source data and the second instructions to the check processor 102 through a third data channel.

[0059] The main processor 101 is configured to calculate a third calculation result according to the second source data and the second instructions.

[0060] The check processor 102 is configured to calculate a fourth calculation result according to the second source data and the second instructions.

[0061] The exclusive or check module 1011 of the main processor 101 is configured to compare and check the third calculation result and the fourth calculation result.

[0062] In the embodiment, in the same source work mode, the check processor 102 shares the data of the main processor 101, the main processor 101 reads data from the external memory each time, and then shares the data to the check processor 102 through the data channel, the main processor 101 and the check processor 102 use the same data for calculation, and the calculation result each time is compared and checked by the exclusive or check module 1011.

[0063] It should be noted that in the same source check mode, the main processor 101 reads data from the external memory, and then shares the data to the check processor 102 through the data channel, and the main processor 101 and the check processor 102 use the same data for calculation.

[0064] In an embodiment, the main processor is configured to configure a prohibited check work mode through an instruction channel.

[0065] In the prohibited check work mode, the main processor 101 or the check processor 102 is configured to read and process data independently, and the check function of the exclusive or comparison module 1011 is closed.

[0066] In the embodiment, in the prohibited check work mode, the main processor 101 and the check processor 102 work independently, access memory data through independent data channels, there is no data interaction between the main processor 101 and the check processor 102, and the check function is closed. In the prohibited check work mode, the processor computing power can be improved.

[0067] Referring to Figure 2 , the XOR comparison module 1011 includes a first first-in-first-out queue 1012 and a second first-in-first-out queue 1013;

[0068] In the independent verification mode, when the first first-in-first-out queue 1012 and the second first-in-first-out queue 1013 are not full, the first first-in-first-out queue 1012 is used to receive the first calculation result, and the second first-in-first-out queue 1013 is used to receive the second calculation result;

[0069] When the first first-in-first-out queue 1012 or the second first-in-first-out queue 1013 is full, the main processor 101 is used to block the data channel of the first first-in-first-out queue 1012 and the second first-in-first-out queue 1013, and disable writing data to the first first-in-first-out queue 1012 and the second first-in-first-out queue 1013;

[0070] When the first first-in-first-out queue 1012 or the second first-in-first-out queue 1013 is not empty, the XOR comparison module 1011 of the main processor 101 is used to synchronously read the data of the same data segment of the first first-in-first-out queue 1012 and the second first-in-first-out queue 1013.

[0071] In this embodiment, the main processor 101 and the verification processor 102 use the same instruction to drive the calculation, so the data amount is the same, and on this premise, the data synchronization of the main processor 101 and the verification processor 102 is guaranteed by the two first-in-first-out (FIFO) structures of the XOR comparison module 1011.

[0072] Referring again to Figure 2 , the XOR comparison module 1011 designs two AXI-stream port first-in-first-out queues 1012 and 1013 to respectively receive the calculation results input by the main processor 101 and the verification processor 102. If the first first-in-first-out queue 1012 and the second first-in-first-out queue 1013 are not full, the data is received; if full, the data channel is blocked, the ready signal is pulled down, and the FIFO cannot be written. When the first first-in-first-out queue 1012 and the second first-in-first-out queue 1013 are not empty, one data of the first first-in-first-out queue 1012 and the second first-in-first-out queue 1013 is read out at the same time, and this data is the same data bit of the calculation results of the main processor 101 and the verification processor 102.

[0073] In an embodiment, in the independent verification mode, the exclusive or comparison module 1011 of the main processor 101 is configured to perform exclusive or operation on the first calculation result read from the first first-in-first-out queue 1012 and the second calculation result synchronously read from the second first-in-first-out queue 1013, if the result of the exclusive or operation is 1, the Error interrupt signal is triggered, and the verification result is failed; if the result of the exclusive or operation is 0, the verification result is passed, and the data read from the first first-in-first-out queue 1012 or the data read from the second first-in-first-out queue 1013 is written into the external memory.

[0074] Please refer to Figure 2 , the exclusive or comparison module 1011 performs exclusive or operation on the calculation result, if the result is 1, the Error signal is pulled high, the PS end receives the Error interrupt signal, discards the calculation, and performs the calculation again. If the result is 0, the data is normal, and the data is written into the corresponding address in the external memory through the data path. The external memory can be DDR or other hardware devices, which is not limited here.

[0075] In an embodiment, in the homologous verification mode, when the first first-in-first-out queue 1012 and the second first-in-first-out queue 1013 are not full, the first first-in-first-out queue 1012 is configured to receive the third calculation result, and the second first-in-first-out queue 1013 is configured to receive the fourth calculation result.

[0076] In an embodiment, the exclusive or comparison module 1011 of the main processor 101 is configured to perform exclusive or operation on the third calculation result read from the first first-in-first-out queue 1012 and the fourth calculation result synchronously read from the second first-in-first-out queue 1013.

[0077] In an embodiment, the main processor 101 further comprises a verification register;

[0078] The main processor 101 is configured to configure the verification register to start or close the verification function of the exclusive or comparison module.

[0079] Please refer to Figure 2 , the verification function of the main processor can be enabled or disabled by configuring the verification register. When the verification function is disabled, the exclusive or comparison module is disabled, and the data of the main processor is directly written into the external memory through the data path without being processed by the exclusive or comparison module.

[0080] In addition, in Figure 2In the embodiment, the exclusive or comparison module 1011 is also connected with a data switch SW, and the data switch SW is also connected with the main processor 101. The data switch SW is used for selecting one of two input data of the exclusive or comparison module 1011 and the main processor 101 as output data according to register configuration.

[0081] The verification circuit for the neural network processor provided in the embodiment can realize data verification of the neural network processor, can flexibly set whether to enable verification according to user demand, has an independent verification working mode, a same-source verification working mode and a prohibited verification working mode, the main processor works independently in the prohibited verification working mode, and the calculation results of the main processor and the verification processor are verified bit by bit in the independent verification working mode and the same-source verification working mode. Through the data verification mechanism of the main processor and the verification processor, processor failure caused by random data errors in an external harsh environment is avoided.

[0082] Embodiment 2

[0083] The embodiment further provides a verification method for a neural network processor, which is applied to the verification circuit for the neural network processor provided in the embodiment; the verification method comprises the following steps of:

[0084] The main processor and the verification processor configure a verification working mode through an instruction channel, wherein the verification working mode comprises an independent verification working mode;

[0085] In the independent verification working mode, the main processor and the verification processor write same first source data and first instructions into a first memory space and a second memory space respectively, and the first memory space and the second memory space are memory spaces with same capacity and different addresses;

[0086] The main processor and the verification processor acquire the source data and the instructions from the first memory space and the second memory space respectively through two independent first data paths;

[0087] The main processor calculates a first calculation result according to the source data and the instructions;

[0088] The verification processor calculates a second calculation result according to the source data and the instructions, and sends the second calculation result to the main processor through a second data path;

[0089] The exclusive or comparison module of the main processor compares and verifies the first calculation result and the second calculation result.

[0090] In an embodiment, the verification working mode further comprises a same-source verification working mode; and the verification method further comprises the following steps of:

[0091] In the homologous check mode, the main processor reads second source data and second instructions from an external memory, and sends the second source data and the second instructions to the check processor through a third data channel;

[0092] The main processor calculates a third calculation result according to the second source data and the second instructions;

[0093] The check processor calculates a fourth calculation result according to the second source data and the second instructions;

[0094] The exclusive or check module of the main processor compares and checks the third calculation result and the fourth calculation result.

[0095] In an embodiment, the main processor is configured to configure a disabled check mode through an instruction channel; the check method further comprises:

[0096] In the disabled check mode, the main processor reads data and closes the check function of the exclusive or comparison module.

[0097] In an embodiment, the exclusive or comparison module comprises a first first-in-first-out queue and a second first-in-first-out queue; the check method further comprises:

[0098] In the independent check mode, when the first first-in-first-out queue and the second first-in-first-out queue are not full, the first first-in-first-out queue receives the first calculation result, and the second first-in-first-out queue receives the second calculation result;

[0099] When the first first-in-first-out queue or the second first-in-first-out queue is full, the main processor blocks the data channel of the first first-in-first-out queue and the second first-in-first-out queue, and disables writing data to the first first-in-first-out queue and the second first-in-first-out queue;

[0100] When the first first-in-first-out queue or the second first-in-first-out queue is not empty, the exclusive or comparison module of the main processor synchronously reads data of the same data segment of the first first-in-first-out queue and the second first-in-first-out queue.

[0101] In an embodiment, the check method further comprises:

[0102] In the independent verification mode, the XOR comparison module of the main processor performs XOR operation on the first calculation result read from the first FIFO queue and the second calculation result synchronously read from the second FIFO queue bit by bit, if the XOR operation result is 1, the Error interrupt signal is triggered, and the verification result is failed; if the XOR operation result is 0, the verification result is passed, and the data read from the first FIFO queue or the data read from the second FIFO queue is written into the external memory.

[0103] In an embodiment, the verification method further comprises:

[0104] In the homologous verification mode, when the first FIFO queue and the second FIFO queue are not full, the first FIFO queue receives the third calculation result, and the second FIFO queue receives the fourth calculation result.

[0105] In an embodiment, the verification method further comprises:

[0106] The XOR comparison module of the main processor performs XOR operation on the third calculation result read from the first FIFO queue and the fourth calculation result synchronously read from the second FIFO queue bit by bit.

[0107] In an embodiment, the main processor further comprises a verification register;

[0108] The verification method further comprises:

[0109] The main processor configures the verification register to start or close the verification function of the XOR comparison module.

[0110] The verification method for the neural network processor provided in the embodiment is applied to the verification circuit for the neural network processor provided in Embodiment 1, and the corresponding effects of the verification circuit for the neural network processor can be achieved. To avoid repetition, details are not described here.

[0111] The verification method for the neural network processor provided in the embodiment can realize data verification of the neural network processor, can flexibly set whether to enable verification according to user demand, has an independent verification mode, a homologous verification mode and a prohibited verification mode, the main processor works independently in the prohibited verification mode, and the calculation results of the main processor and the verification processor are verified bit by bit in the independent verification mode and the homologous verification mode. Through the data verification mechanism of the main processor and the verification processor, processor failure caused by random data errors in an external harsh environment is avoided.

[0112] Embodiment 3

[0113] In addition, the embodiment of the present disclosure provides a neural network processor, including a software end and a hardware end, and the hardware end includes the check circuit for the neural network processor provided in the embodiment 1.

[0114] In the embodiment, the hardware end can also be referred to as a programmable logic (PL) end, and the software end can also be referred to as a processing system (PS) end. Please refer to Figure 3 , the PL end can also be referred to as the hardware end, and the PS end can also be referred to as the software end. The configuration channel AXI-Lite of the main processor 101 and the check processor 102 of the PL end is connected with the HP3 end of the PS end through the AXI-interconnect channel, and the data port of the check processor 102 of the PL end is connected with the HP2 end of the PS end through the AXI4-Full channel. The data port of the main processor 101 is connected with the HP0 end of the PS end through the AXI4-Full channel, and the ERROR port of the exclusive or comparison module 1011 is connected with the INT end of the PS end. Among them, the AXI-Interconnect is an interconnection module of the AXI protocol, which supports the interconnection of multiple AXI channels. The INT end is an interrupt port of the PS end, which accepts the error interrupt signal. The HP0-3 is a high-performance port (High-Performance ports), and the HP0-3 port has four ports, which can efficiently access the external memory.

[0115] The PS end of the neural network processor configures the registers of the main processor 101 and the check processor 102 through AXI_Lite, for example, the check mode is configured as independent check, the check state is configured as starting check, and the source data, instructions and target addresses used by the processor 101 and the check processor 102 are configured. The source data, instructions and target addresses are all independent memory spaces.

[0116] In the independent check mode, the PS end of the neural network processor configures the start register of the main processor 101 and the check processor 102 through AXI_Lite to start the accelerator work. The processor 101 and the check processor 102 respectively read the data in the external memory through the AXI-Full channel according to the instructions to perform the calculation.

[0117] The results calculated by the main processor 101 and the check processor 102 are output to two FIFOs in the XOR comparison module 1011 through an AXI-Stream channel, the two FIFOs being a first first-in-first-out queue 1012 and a second first-in-first-out queue 1013, and if the FIFO is not full, the data is received; if the FIFO is full, the data channel is blocked, the ready signal is pulled down, and the FIFO cannot be written. When the two FIFOs are not empty, one data of the two FIFOs is read out at the same time, so as to ensure that the calculation results of the processor 101 and the check processor 102 are the same data bits, and the calculation results are processed asynchronously bit by bit to realize the check. The PS end monitors the Error interrupt, if the Error is 0, the calculation results of the processor 101 and the check processor 102 are written into the respective memory spaces through an Axi-Full channel, if the Error is 1, the calculation is stopped, and the data is discarded. The foregoing check process is performed until all instructions are processed.

[0118] In the homologous check mode, the PS end configures the registers of the main processor 101 and the check processor 102 through AXI_Lite, mainly including: source data address, destination address, check mode and whether to enable check, etc. The instruction space of the main processor 101 and the check processor 102 is configured to be consistent, and the same instruction is used. The PS end configures the start register of the processor 101 and the check processor 102 through AXI_Lite, and starts the accelerator to work.

[0119] The main processor 101 reads the data in the external memory through an AXI-Full channel according to the instruction, and shares the data with the check processor 102 through an AXI-Stream channel. The main processor 101 and the check processor 102 guarantee synchronization through the ready signal and the valid handshake of AXI. When the main processor 101 shares the data, the valid is 1, if the ready signal of the check processor 102 is 0, the check processor 102 stops sharing the data, until the valid and the ready are both 1, then the data sharing is started. The external memory can be DDR.

[0120] The results calculated by the main processor 101 and the check processor 102 are output to two FIFOs in the XOR comparison module 1011 through an AXI-Stream channel, and if the two FIFOs are not full, the data is received; if the two FIFOs are full, the data channel is blocked, the ready signal is pulled down, and the FIFO cannot be written. When both FIFOs are not empty, one data of the two FIFOs is read out at the same time, so as to ensure that the result data of the two main processors 101 and the check processor 102 is the same data bit, and the asynchronous processing is performed bit by bit to realize the check. The PS end monitors the Error interrupt, if the Error is 0, the main processor 101 calculates the result and writes it into the memory space through the Axi-Full channel, if the Error is 1, the calculation is stopped and the data is discarded. The foregoing check process is performed until all instructions are processed.

[0121] In the disabled check working mode, the PS end configures the registers of the main processor 101 and the check processor 102 through AXI_Lite, mainly including the following information: source data address, destination address, check mode and whether to enable the check, and the source data, instructions and target address space used by the main processor 101 and the check processor 102 are independent memory spaces, and the main processor 101 and the check processor 102 run relatively independently. The PS end configures the start register of the main processor 101 and the check processor 102 through AXI_Lite to start the accelerator. The main processor 101 and the check processor 102 work independently, access their own memory space data and instructions through AXI-Full according to the instructions, and calculate in parallel. This mode does not support the check function, so the calculation result is written into the respective memory space through the respective AXI-Full. The instructions are repeatedly processed according to the independent processing mode until all instructions are processed.

[0122] The neural network processor provided in the embodiment can realize data check of the neural network processor, can flexibly set whether to enable the check according to user demand, has an independent check working mode, a same-source check working mode and a disabled check working mode, the main processor works independently in the disabled check working mode, and the calculation results of the main processor and the check processor are checked bit by bit in the independent check working mode and the same-source check working mode, and through the data check mechanism of the main processor and the check processor, the processor failure caused by random data errors in an external harsh environment is avoided.

[0123] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other manners. The apparatus embodiments described above are merely illustrative, for example, the flowcharts and structural diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in alternative implementation manners, the functions noted in the blocks can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the structural diagram and / or flowchart, and the combination of blocks in the structural diagram and / or flowchart, can be implemented by a dedicated hardware-based system for executing the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0124] In addition, each functional module or unit in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0125] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or the part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0126] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A check circuit for a neural network processor, the check circuit comprising: The application relates to a main processor and a check processor connected with the main processor, wherein the main processor comprises an exclusive or comparison module. The main processor and the check processor are configured to configure a check working mode through an instruction channel, wherein the check working mode comprises an independent check working mode. In the independent check working mode, the main processor and the check processor are respectively configured to write the same first source data and first instructions into a first memory space and a second memory space, wherein the first memory space and the second memory space are memory spaces with the same capacity and different addresses. The main processor and the check processor are further configured to acquire the first source data and the first instructions from the first memory space and the second memory space through two independent first data channels respectively. The main processor is further configured to calculate a first calculation result according to the first source data and the first instructions. The check processor is further configured to calculate a second calculation result according to the first source data and the first instructions and send the second calculation result to the main processor through a second data channel. The exclusive or comparison module of the main processor is configured to compare and check the first calculation result and the second calculation result. The check working mode further comprises a same-source check working mode.

2. The check circuit of claim 1, wherein, In the same-source check working mode, the main processor is configured to read second source data and second instructions from an external memory and send the second source data and the second instructions to the check processor through a third data channel. The main processor is configured to calculate a third calculation result according to the second source data and the second instructions. The check processor is configured to calculate a fourth calculation result according to the second source data and the second instructions. The exclusive or check module of the main processor is configured to compare and check the third calculation result and the fourth calculation result. The main processor is configured to configure a prohibited check working mode through an instruction channel.

3. The check circuit of claim 1, wherein, In the prohibited check working mode, the main processor or the check processor is configured to independently process data and close the check function of the exclusive or comparison module. The exclusive or comparison module comprises a first first-in-first-out queue and a second first-in-first-out queue.

4. The check circuit of claim 1, wherein, In the independent check working mode, when the first first-in-first-out queue and the second first-in-first-out queue are not full, the first first-in-first-out queue is configured to receive the first calculation result and the second first-in-first-out queue is configured to receive the second calculation result. When the first first-in-first-out queue or the second first-in-first-out queue is full, the main processor is configured to block the data channels of the first first-in-first-out queue and the second first-in-first-out queue and prohibit writing data into the first first-in-first-out queue and the second first-in-first-out queue. When the first first-in-first-out queue or the second first-in-first-out queue is not empty, the exclusive or comparison module of the main processor is configured to synchronously read the data of the same data segment of the first first-in-first-out queue and the second first-in-first-out queue. ​ 5. The check circuit of claim 4, wherein, In the independent verification mode, the exclusive or comparison module of the main processor is configured to perform exclusive or operation on the first calculation result read from the first first-in-first-out queue and the second calculation result synchronously read from the second first-in-first-out queue, if the result of the exclusive or operation is 1, an Error interrupt signal is triggered, and the verification result is failed; if the result of the exclusive or operation is 0, the verification result is passed, and the data read from the first first-in-first-out queue or the data read from the second first-in-first-out queue is written into an external memory.

6. The check circuit of claim 2, wherein, The exclusive or comparison module comprises a first first-in-first-out queue and a second first-in-first-out queue. In the homologous verification mode, when the first first-in-first-out queue and the second first-in-first-out queue are not full, the first first-in-first-out queue is configured to receive the third calculation result, and the second first-in-first-out queue is configured to receive the fourth calculation result.

7. The check circuit of claim 6, wherein, The exclusive or comparison module of the main processor is configured to perform exclusive or operation on the third calculation result read from the first first-in-first-out queue and the fourth calculation result synchronously read from the second first-in-first-out queue.

8. The check circuit of claim 1, wherein, The main processor further comprises a verification register. The main processor is further configured to configure the verification register to start or close the verification function of the exclusive or comparison module.

9. A method for verifying a neural network processor, the method comprising: The verification method comprises the steps of: The main processor and the verification processor configure a verification mode through an instruction channel, wherein the verification mode comprises an independent verification mode; In the independent verification mode, the main processor and the verification processor write the same first source data and first instructions into a first memory space and a second memory space, respectively, wherein the first memory space and the second memory space are memory spaces with the same capacity and different addresses; The main processor and the verification processor obtain the first source data and the first instructions from the first memory space and the second memory space through two independent first data paths, respectively; The main processor calculates a first calculation result according to the first source data and the first instructions; The verification processor calculates a second calculation result according to the first source data and the first instructions, and sends the second calculation result to the main processor through a second data path; The exclusive or comparison module of the main processor compares and verifies the first calculation result and the second calculation result.

10. A neural network processor, comprising: The neural network processor comprises a software end and a hardware end, and the hardware end comprises the verification circuit for the neural network processor according to any one of claims 1-8. The neural network processor comprises a software end and a hardware end, and the hardware end comprises the verification circuit for the neural network processor according to any one of claims 1-8.

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