Gate drive circuit and driving method thereof

Abstract

The application discloses a gate drive circuit and a driving method thereof. The gate drive circuit comprises an output control module, a first output module, a second output module and a threshold adjusting module. The threshold adjusting module is used for turning on in response to a first adjusting signal in a threshold adjusting stage, so as to transmit a first potential signal to a control end of the second output module. The second output module comprises a transistor. The threshold adjusting module transmits the first potential signal to the control end of the second output module in the threshold adjusting stage, so as to partially offset the positive or negative bias of the threshold voltage of the second output module caused by a high-temperature environment, and ensure the normal output of the output signal of the gate drive circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to gate driving circuits and driving methods thereof. Background Technology

[0002] The display panel includes multiple pixels and a gate driving circuit. The gate driving circuit is used to output gate signals to control the turning on and off of the pixels.

[0003] The gate driving circuit includes an output module, which outputs a gate signal, such as a light emission control signal or a scan signal, to the pixel to drive the pixel to emit light. The output module of the gate driving circuit includes a transistor. Under high-temperature conditions, the threshold voltage of the transistor is prone to shift, leading to abnormal output gate signals. Summary of the Invention

[0004] This invention provides a gate driving circuit and its driving method to alleviate the threshold voltage offset of the output module included in the gate driving circuit and ensure that the signal output by the gate driving circuit is normal under high temperature environment.

[0005] According to one aspect of the present invention, a gate driving circuit is provided, comprising: an output control module, a first output module, a second output module, and a threshold adjustment module;

[0006] The output control module is used to control the potential of the first node and the second node; wherein, the control terminal of the first output module is electrically connected to the first node, and the control terminal of the second output module is electrically connected to the second node;

[0007] The first output module is used to transmit a third potential signal to the output terminal of the gate drive circuit according to the potential of the first node, wherein the third potential signal is used as an effective control signal.

[0008] The second output module is used to control the transmission of a second potential signal to the output terminal of the gate drive circuit according to the potential of the second node, wherein the second potential signal is used as an invalid control signal;

[0009] The threshold adjustment module is used to respond to the first adjustment signal during the threshold adjustment stage to transmit the first potential signal to the control terminal of the second output module.

[0010] Optionally, the gate driving circuit further includes: a cutoff module, wherein a first terminal of the second output module is connected to the second potential signal, a second terminal of the second output module is electrically connected to the first terminal of the cutoff module, a second terminal of the cutoff module is electrically connected to the output terminal of the gate driving circuit, and a control terminal of the cutoff module is connected to a second adjustment signal. The cutoff module is used to turn off in response to the second adjustment signal during the threshold adjustment phase.

[0011] Optionally, the threshold adjustment module includes a first transistor, the first terminal of the first transistor is connected to the first potential signal, the second terminal of the first transistor is electrically connected to the control terminal of the second output module, and the gate of the first transistor is connected to the first adjustment signal.

[0012] The cutoff module includes a second transistor, the first terminal of which is electrically connected to the second terminal of the second output module, the second terminal of which is electrically connected to the output terminal of the gate drive circuit, and the gate of the second transistor is connected to the second adjustment signal.

[0013] Optionally, the threshold adjustment module is further configured to shut down in response to the first adjustment signal during the transition phase, and the cutoff module is configured to shut down in response to the second adjustment signal during the transition phase.

[0014] Optionally, the absolute value of the difference between the first potential signal and the second potential signal is greater than the absolute value of the difference between the third potential signal and the second potential signal;

[0015] Optionally, the second output module includes a transistor, and the transistor included in the second output module is a P-type transistor, wherein the absolute value of the difference between the first potential signal and the second potential signal is greater than the absolute value of the difference between the third potential signal and the second potential signal.

[0016] Optionally, the second output module includes a transistor, and the transistor included in the second output module is an N-type transistor, wherein the difference between the first potential signal and the second potential signal is greater than the difference between the third potential signal and the second potential signal.

[0017] Optionally, the output control module includes a first output control module and a second output control module;

[0018] The output terminal of the first output control module is electrically connected to the first node. The first output control module is used to transmit to the first node according to the first clock signal, the second clock signal, the potential control start signal of the internal node of the second output control module, and the second potential signal.

[0019] The output terminal of the second output control module is electrically connected to the second node. The second output control module is used to control the transmission of the first clock signal and the second potential signal to the second node according to the first clock signal, the second clock signal and the potential of the first node.

[0020] Optionally, the first output control module includes an input unit and a first node control unit. The input terminal of the input unit is connected to the start signal, the control terminal of the input unit is connected to the second clock signal, and the output terminal of the input unit is electrically connected to the first node. The input unit is used to control the transmission of the start signal to the first node according to the second clock signal.

[0021] The input terminal of the first node control unit is connected to the second potential signal, the first control terminal of the first node control unit is electrically connected to the internal node of the second output control module, the second control terminal of the first node control unit is connected to the first clock signal, and the output terminal of the first node control unit is electrically connected to the first node. The first node control unit is used to control the transmission of the second potential signal to the first node according to the potential of the internal node of the second output control module and the first clock signal.

[0022] The second output control module includes: a third node control unit and a second node control unit; the first input terminal of the third node control unit is connected to the third potential signal, the second input terminal of the third node control unit is connected to the second clock signal, the first control terminal of the third node control unit is connected to the second clock signal, the second control terminal of the third node control unit is connected to the first node, and the output terminal of the third node control unit is electrically connected to the third node. The third node control unit is used to control the transmission of the third potential signal and the second clock signal to the third node according to the second clock signal and the potential of the first node, wherein the third node serves as an internal node of the second output control module.

[0023] The first input terminal of the second node control unit is connected to the first clock signal, the second input terminal of the second node control unit is connected to the second potential signal, the first control terminal of the second node control unit is electrically connected to the third node, the second control terminal of the second node control unit is connected to the first clock signal, the third control terminal of the second node control unit is electrically connected to the first node, and the output terminal of the second node control unit is electrically connected to the second node. The second node control unit is used to control the transmission of the first clock signal and the second potential signal to the second node according to the potential of the third node, the first clock signal, and the potential of the first node.

[0024] Preferably, the second node control unit includes a first sub-control unit and a second sub-control unit. The input terminal of the first sub-control unit is connected to the first clock signal, the first control terminal of the first sub-control unit is electrically connected to the third node, the second control terminal of the first sub-control unit is connected to the first clock signal, and the output terminal of the first sub-control unit is electrically connected to the second node. The first sub-control unit is used to control the transmission of the first clock signal to the second node according to the potential of the third node and the first clock signal. The input terminal of the second sub-control unit is connected to the second potential signal, the control terminal of the second sub-control unit is electrically connected to the first node, and the output terminal of the second sub-control unit is electrically connected to the second node. The second sub-control unit is used to control the transmission of the second potential signal to the second node according to the potential of the first node.

[0025] According to another aspect of the present invention, a driving method for a gate driving circuit is provided, the gate driving circuit including an output control module, a first output module, a second output module, and a threshold adjustment module; the control terminal of the first output module is electrically connected to a first node, and the control terminal of the second output module is electrically connected to a second node;

[0026] The driving method of the gate driving circuit includes:

[0027] During the display phase, the output control module controls the potentials of the first node and the second node to alternately transmit the second potential signal or the third potential signal to the output terminal of the gate driving circuit. The first output module controls the transmission of the third potential signal to the output terminal of the gate driving circuit according to the potential of the first node, wherein the third potential signal is a valid control signal. The second output module controls the transmission of the second potential signal to the output terminal of the gate driving circuit according to the potential of the second node, wherein the second potential signal is an invalid control signal. The threshold adjustment module turns off in response to the first adjustment signal.

[0028] During the threshold adjustment phase, the threshold adjustment module responds to the first adjustment signal and turns on to transmit the first potential signal to the control terminal of the second output module.

[0029] Optionally, the threshold adjustment stage is located in the display blank area between two adjacent frames.

[0030] Optionally, the gate driving circuit further includes a cutoff module, wherein a first terminal of the second output module is connected to the second potential signal, a second terminal of the second output module is electrically connected to the first terminal of the cutoff module, the second terminal of the cutoff module is electrically connected to the output terminal of the gate driving circuit, and the control terminal of the cutoff module is electrically connected to a second adjustment signal. The driving method of the gate driving circuit further includes:

[0031] During the transition phase, the threshold adjustment module turns off in response to the first potential signal, and the cutoff module turns off in response to the second adjustment signal.

[0032] During the threshold adjustment completion phase, the threshold adjustment module turns off in response to the first potential signal, and the cutoff module turns on in response to the second adjustment signal.

[0033] The gate driving circuit provided in this embodiment of the invention includes an output control module, a first output module, a second output module, and a threshold adjustment module. The output control module is used to control the potentials of a first node and a second node. The control terminal of the first output module is electrically connected to the first node, and the control terminal of the second output module is electrically connected to the second node. The first output module is used to control the transmission of a third potential signal to the output terminal of the gate driving circuit based on the potential of the first node. The second output module is used to control the transmission of a second potential signal to the output terminal of the gate driving circuit based on the potential of the second node. The threshold adjustment module is used to conduct in response to a first adjustment signal during the threshold adjustment phase, so as to transmit the first potential signal to the control terminal of the second output module. The first potential signal is less than the second potential signal, or the first potential signal is greater than the second potential signal. The second output module includes a transistor. During the threshold adjustment phase, the threshold adjustment module transmits the first potential signal to the control terminal of the second output module, thereby increasing the absolute value of the voltage difference between the control terminal of the second output module and the terminal connected to the second potential signal. This causes the threshold voltage of the transistor included in the second output module to be negatively or positively biased, partially offsetting the positive or negative bias of the threshold voltage of the second output module caused by the high-temperature environment, ensuring the normal output signal of the gate driving circuit.

[0034] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of a gate drive circuit;

[0037] Figure 2 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0042] Figure 7 This is a driving timing diagram of a gate driving circuit provided in an embodiment of the present invention;

[0043] Figure 8 This is a flowchart of a driving method for a gate driving circuit provided in an embodiment of the present invention;

[0044] Figure 9 This is a flowchart of another driving method for a gate driving circuit provided in an embodiment of the present invention. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] As described in the background art, in a high-temperature environment, the threshold voltage of the output module included in the gate driving circuit is extremely likely to shift, resulting in abnormal signals output by the gate driving circuit. Figure 1 is a schematic structural diagram of a gate driving circuit. Refer to Figure 1 , the gate driving circuit includes a first output module and a second output module. The first output module includes a first transistor T1, and the second output module includes a second transistor T2. After the first transistor T1 is turned on, a third potential signal VGL2 is transmitted to the output terminal OUT. After the second transistor T2 is turned on, a second potential signal VGH is transmitted to the output terminal OUT. In this embodiment, it is exemplarily shown that both the first transistor T1 and the second transistor T2 are P-type transistors, and the third potential signal VGL2 is an effective potential signal, where the effective potential signal is a signal for controlling pixel light emission. Exemplarily, the third potential signal VGL2 is -7V, the second potential signal VGH is 7V, and the threshold voltage of the second transistor T2 under normal circumstances is about -3V. During the period when the first transistor T1 is turned on and the second transistor T2 is turned off, the threshold voltage of the second transistor T2 undergoes a positive shift due to the high-temperature environment. Exemplarily, the shift amplitude is 4.5V. At this time, the threshold voltage Vth of the second transistor T2 becomes 1.5V, and the voltage for turning off the second transistor T2 is 7V. The gate-source voltage difference Vgs (voltage difference between the gate and the source) of the second transistor T2 = 7V - 7V = 0V. The gate-source voltage difference Vgs of the second transistor T2 < Vth, the second transistor T2 is turned on, and after the second transistor T2 is turned on, the second potential signal VGH is transmitted to the output terminal OUT, affecting the output of a low level at the output terminal OUT, resulting in abnormal gate signals output by the gate driving circuit.

[0048] Based on the above reasons, an embodiment of the present invention provides a new type of gate driving circuit. Figure 2 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention. Refer to Figure 2 , the gate driving circuit includes an output control module 1, a first output module 2, a second output module 3, and a threshold adjustment module 4;

[0049] The output control module 1 is used to control the potentials of the first node N1 and the second node N2; wherein, the control end of the first output module 2 is electrically connected to the first node N1, and the control end of the second output module 3 is electrically connected to the second node N2;

[0050] The first output module 2 is used to control the transmission of the third potential signal VGL2 to the output terminal OUT of the gate driving circuit according to the potential of the first node N1, where the third potential signal VGL2 is used as an effective control signal;

[0051] The second output module 3 is used to control the transmission of the second potential signal VGH to the output terminal OUT of the gate drive circuit according to the potential of the second node N2, wherein the second potential signal VGH is used as an invalid control signal;

[0052] The threshold adjustment module 4 is used to turn on in response to the first adjustment signal RE1 during the threshold adjustment stage, so as to transmit the first potential signal VGL1 to the control terminal of the second output module 3. The first potential signal VGL1 is less than the second potential signal VGH, or the first potential signal VGL1 is greater than the second potential signal VGH.

[0053] The output control module 1 controls the potentials of the first node N1 and the second node N2. Specifically, it controls the transmission of a start signal EIN to the first node N1. During the phase when the first output module 2 needs to be turned on, the output control module 1 connects the start signal EIN to the first node N1 to control the first output module 2 to turn on. The output control module 1 also controls the transmission of a first clock signal ECK1 and a second potential signal VGH to the second node N2. That is, the output control module 1 connects the first clock signal ECK1 to the second node N2 so that the second node N2 turns on or off according to the first clock signal ECK1; or it connects the second potential signal VGH to the second node N2 so that the second output module 3 turns off according to the second potential signal VGH. The second potential signal VGH is the signal that controls the second output module 3 to turn off. For example, the second output module 3 includes transistors. When the included transistors are P-type transistors, the second potential signal VGH is at a high level; when the included transistors are N-type transistors, the second potential signal VGH is at a low level.

[0054] Taking the signal output from the gate drive circuit's output terminal OUT as the light-emitting control signal as an example, the third potential signal VGL2 is the effective control signal. When the gate drive circuit outputs the third potential signal VGL2, it controls the corresponding pixel circuit to drive the light-emitting device to emit light. However, during the process of the first output module 2 being turned on and outputting the third potential signal VGL2, if the threshold voltage of the transistor included in the second output module 3 is positively offset due to the high temperature environment, it is very easy for the second output module 3 to be turned on. The turned-on second output module 3 transmits the third potential signal VGH, i.e., the invalid control signal, to the output terminal OUT, affecting the normal output of the effective control signal by the gate drive circuit.

[0055] In this embodiment, the end of the second output module 3 connected to the second potential signal VGH is referred to as the first end. The second output module 3 includes a transistor. Under high temperature conditions, the transistor included in the second output module 3 is prone to threshold voltage shift. If the transistor included in the second output module 3 is an N-type transistor, the threshold voltage is prone to negative bias; if the transistor included in the second output module 3 is a P-type transistor, the threshold voltage is prone to positive bias. When the transistor included in the second output module 3 is a P-type transistor, the first potential signal VGL1 is less than the second potential signal VGH, the second potential signal VGH is at a high level (e.g., 7V), and the third potential signal VGL2 is at a low level (e.g., -7V). During the threshold adjustment phase, the threshold adjustment module 4 is turned on to transmit the first potential signal VGL1 to the control terminal of the second output module 3, i.e., the second node N2. Since the first potential signal VGL1 is less than the second potential signal VGH, for example, the first potential signal VGL1 can be 5V, -5V, etc. During the threshold adjustment phase, the potential of the second node N2 is high level, i.e., 7V. After the first potential signal VGL1 is written to the control terminal of the second output module 3, the voltage difference between the control terminal and the first terminal of the second output module 3 is reduced, thereby causing the threshold voltage of the transistors included in the second output module 3 to be negatively biased to partially offset the positive bias of the threshold voltage of the second output module 3 caused by the high temperature environment.

[0056] When the transistors included in the second output module 3 are N-type transistors, the first potential signal VGL1 is greater than the second potential signal VGH, and the second potential signal VGH is at a low level, for example, -7V. The third potential signal VGL2 is at a high level, for example, 7V. During the threshold adjustment stage, the threshold adjustment module 4 is turned on to transmit the first potential signal VGL1 to the control terminal of the second output module 3. Since the first potential signal VGL1 is greater than the second potential signal VGH, for example, the first potential signal VGL1 can be -6V, 8V, etc., during the threshold adjustment stage, the potential of the second node N2 is at a low level, i.e., -7V. After the first potential signal VGL1 is written to the control terminal of the second output module 3, the voltage difference between the control terminal and the first terminal of the second output module 3 increases, thereby causing the threshold voltage of the transistors included in the second output module 3 to be positively biased to partially offset the negative bias of the threshold voltage of the second output module 3 caused by the high temperature environment.

[0057] It is worth noting that the gate driving circuit may include a light-emitting control circuit, and the signal output from the output terminal of the gate driving circuit is a light-emitting control signal. The gate driving circuit may also include a scanning circuit, and the signal output from the output terminal of the gate driving circuit is a scanning signal.

[0058] The second output module includes a transistor. During the threshold adjustment stage, the threshold adjustment module transmits a first potential signal to the control terminal of the second output module, thereby increasing the absolute value of the voltage difference between the control terminal of the second output module and the terminal connected to the second potential signal. This causes the threshold voltage of the transistor included in the second output module to be negatively biased, partially offsetting the positive bias of the threshold voltage of the second output module caused by the high temperature environment, or causing the threshold voltage of the transistor included in the second output module to be positively biased, partially offsetting the negative bias of the threshold voltage of the second output module caused by the high temperature environment, thus ensuring the normal output signal of the gate drive circuit.

[0059] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 3 Optionally, the first terminal of the threshold adjustment module 4 is connected to the first potential signal VGL1, and the second terminal of the threshold adjustment module 4 is electrically connected to the control terminal of the second output module 3. The control terminal of the threshold adjustment module 4 is connected to the first adjustment signal RE1. The gate drive circuit further includes: a cutoff module 5, the first terminal of the second output module 3 is connected to the second potential signal VGH, the second terminal of the second output module 3 is electrically connected to the first terminal of the cutoff module 5, the second terminal of the cutoff module 5 is electrically connected to the output terminal OUT of the gate drive circuit, and the control terminal of the cutoff module 5 is connected to the second adjustment signal RE2. The cutoff module 5 is used to turn off in response to the second adjustment signal RE2 during the threshold adjustment stage.

[0060] The threshold adjustment phase is located in the display blank area between two adjacent frames. During the threshold adjustment phase, the first output module 2 is turned on and the second output module 3 is turned off. In this phase, influenced by the first potential signal VGL1, the second output module 3 may turn on, thereby transmitting the second potential signal VGH to the output terminal OUT of the gate drive circuit, affecting the normal output of the third potential signal VGL2 from the output terminal OUT. Therefore, a cutoff module 5 is set between the second terminal of the second output module 3 and the output terminal OUT of the gate drive circuit. The cutoff module 5 turns off in response to the second adjustment signal RE2 during the threshold adjustment phase, ensuring that even if the second output module 3 is turned on during the threshold adjustment phase, the second potential signal VGH cannot be transmitted to the output terminal OUT of the gate drive circuit via the turned-off cutoff module 5, thus guaranteeing the normal output of the third potential signal VGL2 from the output terminal OUT of the gate drive circuit.

[0061] Continue to refer to Figure 3 Optionally, the threshold adjustment module 4 is also used to turn off in response to the first adjustment signal RE1 during the transition phase, and the cutoff module 5 is used to turn off in response to the second adjustment signal RE2 during the transition phase.

[0062] After the threshold adjustment phase ends, the gate drive circuit enters the transition phase. During the transition phase, the first adjustment signal RE1 controls the threshold adjustment module 4 to turn off, thereby stopping the transmission of the first potential signal VGL1 to the second node N2. The threshold adjustment process of the transistors included in the second output module 3 ends.

[0063] Continue to refer to Figure 3 Optionally, the absolute value of the difference between the first potential signal VGL1 and the second potential signal VGH is greater than the absolute value of the difference between the third potential signal VGL2 and the second potential signal VGH.

[0064] Optionally, the second output module 3 includes a transistor, and the transistor included in the second output module 3 is a P-type transistor, wherein the absolute value of the difference between the first potential signal VGL1 and the second potential signal VGH is greater than the absolute value of the difference between the third potential signal VGL2 and the second potential signal VGH.

[0065] When the transistor included in the second output module 3 is a P-type transistor, the second potential signal VGH is at a high level, and the third potential signal VGL2 is at a low level. For example, the absolute value of the second potential signal VGH is equal to the absolute value of the third potential signal VGL2, where the second potential signal VGH is 7V and the third potential signal VGL2 is -7V. The absolute value of the difference between the first potential signal VGL1 and the second potential signal VGH is greater than the absolute value of the difference between the third potential signal VGL2 and the second potential signal VGH. For example, the first potential signal VGL1 is set to -8V, making the first potential signal VGL1 opposite to the second potential signal VGH, and the absolute value of the first potential signal VGL1 is greater than the absolute value of the second potential signal VGH. Because during the threshold adjustment phase, the potential of the second node N2 is equal to the second potential signal VGH, by setting the absolute value of the difference between the first potential signal VGL1 and the second potential signal VGH to be greater than the absolute value of the difference between the third potential signal VGL2 and the second potential signal VGH, the first potential signal VGL1 can sufficiently pull the potential of the second node N2 down to a low level, thereby making the threshold voltage of the transistor included in the second output module 3 sufficiently negatively biased.

[0066] Optionally, the second output module 3 includes a transistor, and the transistor included in the second output module 3 is an N-type transistor, and the difference between the first potential signal VGL1 and the second potential signal VGH is greater than the difference between the third potential signal VGL2 and the second potential signal VGH.

[0067] When the transistors included in the second output module 3 are N-type transistors, the second potential signal VGH is at a low level, and the third potential signal VGL2 is at a high level. For example, the absolute values ​​of the second potential signal VGH and the third potential signal VGL2 are equal, with VGH being -7V and VGL2 being 7V. The difference between the first potential signal VGL1 and the second potential signal VGH is greater than the difference between the third potential signal VGL2 and the second potential signal VGH. For example, the first potential signal VGL1 is set to 8V, making it opposite to VGH and greater than VGH. Because the potential of the second node N2 is equal to the second potential signal VGH during the threshold adjustment stage, by setting the difference between VGL1 and VGH to be greater than the difference between VGL2 and VGH, the first potential signal VGL1 can sufficiently raise the potential of the second node N2, thereby sufficiently forward biasing the threshold voltage of the transistors included in the second output module 3.

[0068] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 4 Optionally, the output control module 1 includes a first output control module 11 and a second output control module 12;

[0069] The output terminal of the first output control module 11 is electrically connected to the first node N1. The first output control module 11 is used to transmit to the first node N1 according to the first clock signal ECK1, the second clock signal ECK2, the potential control start signal EIN of the internal node of the second output control module 12, and the second potential signal VGH.

[0070] The output terminal of the second output control module 12 is electrically connected to the second node N2. The second output control module 12 is used to control the transmission of the first clock signal ECK1 and the second potential signal VGH to the second node N2 according to the first clock signal ECK1, the second clock signal ECK2 and the potential of the first node N1.

[0071] The first output control module 11 is used to control the transmission of a start signal EIN and a second potential signal VGH to the first node N1 based on the first clock signal ECK1, the second clock signal ECK2, and the potential of the internal node of the second output control module 12. Specifically, the first output control module 11 controls the transmission of the start signal EIN to the first node N1 based on the second clock signal ECK2, and also controls the transmission of the second potential signal VGH to the first node N1 based on the potential of the internal node of the second output control module 12 and the first clock signal ECK1. The second output control module 12 is used to control the transmission of the first clock signal ECK1 and the second potential signal VGH to the second node N2 based on the first clock signal ECK1, the second clock signal ECK2, and the potential of the first node N1. Specifically, the second output control module 12 controls the transmission of the first clock signal ECK1 to the second node N2 based on the first clock signal ECK1 and the second clock signal ECK2, and also controls the transmission of the second potential signal VGH to the second node N2 based on the potential of the first node N1.

[0072] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 5 Optionally, the first output control module 11 includes an input unit 111 and a first node control unit 112. The input terminal of the input unit 111 is connected to the start signal EIN, the control terminal of the input unit 111 is connected to the second clock signal ECK2, and the output terminal of the input unit 111 is electrically connected to the first node N1. The input unit 111 is used to control the start signal EIN to be transmitted to the first node N1 according to the second clock signal ECK2.

[0073] The input terminal of the first node control unit 112 is connected to the second potential signal VGH. The first control terminal of the first node control unit 112 is electrically connected to the internal node of the second output control module 12. The second control terminal of the first node control unit 112 is connected to the first clock signal ECK1. The output terminal of the first node control unit 112 is electrically connected to the first node N1. The first node control unit 112 is used to control the transmission of the second potential signal VGH to the first node N1 according to the potential of the internal node of the second output control module 12 and the first clock signal ECK1.

[0074] The second output control module 12 includes: a third node control unit 121 and a second node control unit 122; the first input terminal of the third node control unit 121 is connected to a third potential signal VGL2, the second input terminal I1 of the third node control unit 121 is connected to a second clock signal ECK2, the first control terminal K1 of the third node control unit 121 is connected to the second clock signal ECK2, the second control terminal of the third node control unit 121 is connected to a first node N1, and the output terminal of the third node control unit 121 is electrically connected to a third node N3. The third node control unit 121 is used to control the transmission of the third potential signal VGL2 and the second clock signal ECK2 to the third node N3 according to the potential of the second clock signal ECK2 and the first node N1, wherein the third node N3 serves as an internal node of the second output control module 12.

[0075] The first input terminal I2 of the second node control unit 122 is connected to the first clock signal ECK1, the second input terminal of the second node control unit 122 is connected to the second potential signal VGH, the first control terminal of the second node control unit 122 is electrically connected to the third node N3, the second control terminal K2 of the second node control unit 122 is connected to the first clock signal ECK1, the third control terminal of the second node control unit 122 is electrically connected to the first node N1, and the output terminal of the second node control unit 122 is electrically connected to the second node N2. The second node control unit 122 is used to control the transmission of the first clock signal ECK1 and the second potential signal VGH to the second node N2 according to the potential of the third node N3, the first clock signal ECK1 and the potential of the first node N1.

[0076] Specifically, the first node control unit 112 is used to control the transmission of the second potential signal VGH to the first node N1 based on the potential of the internal node of the second output control module 12 and the first clock signal ECK1. Specifically, when both the potential of the internal node (third node N3) of the second output control module 12 and the potential of the first clock signal ECK1 are valid potential signals (signals that control the first node control unit 112 to turn on), the first node control unit 112 is turned on to transmit the second potential signal VGH to the first node N1. The third node control unit 121 is used to control the transmission of the third potential signal VGL2 and the second clock signal ECK2 to the third node N3 based on the second clock signal ECK2 and the potential of the first node N1. Specifically, the third node control unit 121 controls the transmission of the third potential signal VGL2 to the third node N3 based on the second clock signal ECK2, and also controls the transmission of the second clock signal ECK2 to the third node N3 based on the potential of the first node N1.

[0077] Optionally, the second node control unit 122 includes a first sub-control unit 1221 and a second sub-control unit 1222. The input terminal of the first sub-control unit 1221 is connected to a first clock signal ECK1. The first control terminal of the first sub-control unit 1221 is electrically connected to a third node N3. The second control terminal of the first sub-control unit 1221 is connected to the first clock signal ECK1. The output terminal of the first sub-control unit 1221 is electrically connected to the second node N2. The first sub-control unit 1221 is used to control the transmission of the first clock signal ECK1 to the second node N2 according to the potential of the third node N3 and the first clock signal ECK1. The input terminal of the second sub-control unit 1222 is connected to a second potential signal VGH. The control terminal of the second sub-control unit 1222 is electrically connected to the first node N1. The output terminal of the second sub-control unit 1222 is electrically connected to the second node N2. The second sub-control unit 1222 is used to control the transmission of the second potential signal VGH to the second node N2 according to the potential of the first node N1.

[0078] The first sub-control unit 1221 is used to control the transmission of the first clock signal ECK1 to the second node N2 based on the potential of the third node N3 and the first clock signal ECK1. Specifically, when both the potential of the third node N3 and the potential of the first clock signal ECK1 are valid potential signals (signals that control the first sub-control unit 1221 to turn on), the first sub-control unit 1221 turns on to transmit the first clock signal ECK1 connected to the input terminal of the first sub-control unit 1221 to the second node N2.

[0079] This invention also provides a schematic diagram of a specific structure of a gate driving circuit. Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 6 Corresponding to Figure 5 For the specific structure shown, please refer to... Figure 5 and Figure 6 Optionally, the threshold adjustment module 4 includes a first transistor T1, the first terminal of the first transistor T1 is connected to a first potential signal VGL1, the second terminal of the first transistor T1 is electrically connected to the control terminal of the second output module 3, and the gate of the first transistor T1 is connected to a first adjustment signal RE1.

[0080] The cutoff module 5 includes a second transistor T2. The first terminal of the second transistor T2 is electrically connected to the second terminal of the second output module 3. The second terminal of the second transistor T2 is electrically connected to the output terminal OUT of the gate drive circuit. The gate of the second transistor T2 is connected to the second adjustment signal RE2.

[0081] Both the first transistor T1 and the second transistor T2 can be either N-type or P-type transistors; this embodiment does not impose a specific limitation on either. The threshold adjustment module 4 and the cutoff module 5 each consist of only one transistor, resulting in a simple structure that is easy to implement.

[0082] Continue to refer to Figure 5 and Figure 6Optionally, the third node control unit 121 includes a third transistor T3 and a fourth transistor, wherein the fourth transistor is a dual-gate transistor, consisting of a first sub-transistor T4-1 and a second sub-transistor T4-2. The first terminal of the third transistor T3 is connected to the third potential signal VGL2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The gate of the third transistor T3 serves as the first control terminal K1 of the third node control unit 121, connected to the second clock signal ECK2. The first terminal of the first sub-transistor T4-1 serves as the second input terminal I1 of the third node control unit 121, connected to the second clock signal ECK2. The second terminal of the first sub-transistor T4-1 is electrically connected to the first terminal of the second sub-transistor T4-2, and the second terminal of the second sub-transistor T4-2 is electrically connected to the second terminal of the third sub-transistor T3. The gates of both the first sub-transistor T4-1 and the second sub-transistor T4-2 are electrically connected to the first node N1. The second output control module also includes a fifth transistor T5. The first terminal of the fifth transistor T5 is electrically connected to the second terminal of the third transistor T3. The second terminal of the fifth transistor T5 is electrically connected to the third node N3. The gate of the fifth transistor T5 is connected to the third potential signal VGL2. Specifically, the third potential signal VGL2 is an effective potential signal for the fifth transistor T5, thus making the fifth transistor T5 a normally open transistor. The third transistor T3 is indirectly electrically connected to the third node N3 through the fifth transistor T5. The first sub-control unit 1221 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The first terminal of the sixth transistor T6 serves as the input terminal I2 of the second node control unit 122, connected to the first clock signal ECK1. The second terminal of the sixth transistor T6 is electrically connected to the first terminal of the seventh transistor T7. The gate of the sixth transistor T6 is electrically connected to the third node N3. The second terminal of the seventh transistor T7 is electrically connected to the second node N2. The gate of the seventh transistor T7 serves as the second control terminal K2 of the second node control unit 122, connected to the first clock signal ECK1. The first capacitor C1 is connected between the second terminal and the gate of the sixth transistor T6. The second sub-control unit 1222 includes an eighth transistor T8. The first terminal of the eighth transistor T8 is connected to the second potential signal VGH, the second terminal of the eighth transistor T8 is electrically connected to the second node N2, and the gate of the eighth transistor T8 is electrically connected to the first node N1. The fifth transistor T5 can suppress the transmission of the ultra-low potential of the gate of the sixth transistor T6 to the third node N3 due to the bootstrap effect of the first capacitor C1, thereby reducing the probability of breakdown of the third transistor T3 and the fourth transistor and improving the stability of the gate drive circuit. The input unit 111 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is connected to the start signal EIN, the second terminal of the ninth transistor T9 is electrically connected to the first node N1, and the gate of the ninth transistor T9 is connected to the second clock signal ECK2.The first node control unit 112 includes a tenth transistor T10 and an eleventh transistor T11. The first terminal of the tenth transistor T10 is connected to a second potential signal VGH, and the second terminal of the tenth transistor T10 is electrically connected to the first terminal of the eleventh transistor T11. The gate of the tenth transistor T10 is electrically connected to the third node N3, and the second terminal of the eleventh transistor T11 is electrically connected to the first node N1. The gate of the eleventh transistor T11 is connected to a first clock signal ECK1. The first output control module also includes a twelfth transistor T12, which is connected between the third node N3 and the gate of the tenth transistor T10. The gate of the twelfth transistor T12 is connected to a third potential signal VGL2. Specifically, the third potential signal VGL2 is an effective potential signal for the twelfth transistor T12, thus making the twelfth transistor T12 a normally open transistor. The gate of the tenth transistor T10 is indirectly electrically connected to the third node N3 through the twelfth transistor T12. The twelfth transistor T12 can suppress the transmission of the ultra-low potential from the gate of the sixth transistor T6 to the third node N3 due to the bootstrap effect of the first capacitor C1, reduce the probability of the gate insulating layer of the tenth transistor T10 being broken down, and improve the stability of the gate drive circuit. The first output module 2 includes a fourteenth transistor T14 and a second capacitor C2. The first terminal of the fourteenth transistor T14 is connected to the third potential signal VGL2, and the second terminal of the fourteenth transistor T14 is electrically connected to the output terminal OUT of the gate drive circuit. The gate of the fourteenth transistor T14 is electrically connected to the first node N1. The first terminal of the second capacitor C2 is connected to the first clock signal ECK1, and the second terminal of the second capacitor C2 is electrically connected to the first node N1. The first output control module also includes a thirteenth transistor T13, which is connected between the first node N1 and the gate of the fourteenth transistor T14. The gate of the thirteenth transistor T13 is connected to the third potential signal VGL2. The thirteenth transistor T13 is a normally open transistor, and the gate of the fourteenth transistor T14 is indirectly electrically connected to the first node N1 through the thirteenth transistor T13. The thirteenth transistor T13 can suppress the transmission of the ultra-low potential from the gate of the fourteenth transistor T14 to the eighth transistor T8 due to the bootstrap effect of the second capacitor C2, thereby reducing the probability of the gate insulating layer of the eighth transistor T8 being broken down and improving the stability of the gate drive circuit. The second output module 3 includes a fifteenth transistor T15 and a third capacitor C3. The first terminal of the fifteenth transistor T15 is connected to the second potential signal VGH, the second terminal of the fifteenth transistor T15 is electrically connected to the first terminal of the second transistor T2, the gate of the fifteenth transistor T15 is electrically connected to the second node N2, and the third capacitor C3 is connected between the gate and the first terminal of the fifteenth transistor T15. All transistors in this embodiment can be either N-type transistors or P-type transistors; this embodiment does not specifically limit them.

[0083] Figure 7This is a driving timing diagram of a gate driving circuit provided in an embodiment of the present invention. Figure 7 Applicable to Figure 6 The circuit shown is exemplary. Figure 6 All transistors included are P-type transistors, see reference. Figure 6 and Figure 7 Optionally, the gate driving circuit includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a threshold adjustment stage t7, a transition stage t8, and a threshold adjustment completion stage t9 within one frame of display.

[0084] In the first stage t1, the first adjustment signal RE1 is high, controlling the first transistor T1 to turn off, and the second adjustment signal RE2 is low, controlling the second transistor T2 to turn on. The second clock signal ECK2 is low, controlling the ninth transistor T9 and the third transistor T3 to turn on. The turned-on ninth transistor T9 transmits the start signal EIN to the first node N1. Since the start signal EIN is high, the potential of the first node N1 is VGH. The turned-on third transistor T3 transmits the third potential signal VGL2 to the first terminal of the fifth transistor T5. The high level of the first node N1 controls the first sub-transistor T4-1, the second sub-transistor T4-2, and the eighth transistor T8 to turn off. Due to the influence of the threshold voltage of the fifth transistor T5, the potential of the third node N3 is equal to VGL2 + VTH, where VTH is the threshold voltage of the fifth transistor T5. In this embodiment, it is exemplarily shown that the threshold voltages of all transistors are the same when not affected by temperature. The potential of node N3 controls the conduction of the tenth transistor T10, but because the first clock signal ECK1 is high, it controls the turn-off of the eleventh transistor T11. Therefore, the second potential signal VGH cannot be transmitted to node N1 via transistors T10 and T11. Furthermore, because the first clock signal ECK1 controls the turn-off of the seventh transistor T7, it cannot be transmitted to node N2 via transistors T6 and T7. Node N2 maintains the high level of the previous frame. The potential of node N1 controls the turn-off of the fourteenth transistor T14, and the potential of node N2 controls the turn-off of the fifteenth transistor T15. The output terminal OUT of the gate drive circuit maintains the low level of the previous frame.

[0085] In the second stage t2, the first adjustment signal RE1 is high, controlling the first transistor T1 to turn off, and the second adjustment signal RE2 is low, controlling the second transistor T2 to turn on. The second clock signal ECK2 is high, controlling the ninth transistor T9 and the third transistor T3 to turn off. The first node N1 maintains the high level of the first stage t1. The third node N3 maintains the potential of the first stage t1. The first clock signal ECK1 is low, controlling the eleventh transistor T11 to turn on. The second potential signal VGH is transmitted to the first node N1 through the turned-on tenth transistor T10 and eleventh transistor T11, and the first node N1 remains high. The first clock signal ECK1 controls the seventh transistor T11 to turn on. The first clock signal ECK1 is transmitted to the second node N2 through the turned-on sixth transistor T6 and seventh transistor T7. Due to the influence of the threshold voltage of the seventh transistor T7, the potential of the second node N2 is equal to VGL2 + VTH. Because the first node N1 controls the eighth transistor T8 to turn off, the second potential signal VGH cannot be transmitted to the second node N2, thus preventing the second potential signal VGH from affecting the potential of the second node N2. The potential of the first node N1 controls the fourteenth transistor T14 to turn off, and the potential of the second node N2 controls the fifteenth transistor T15 to turn on. The second potential signal VGH is transmitted to the output terminal OUT of the gate drive circuit through the turned-on fifteenth transistor T15 and the second transistor T2.

[0086] In the third stage t3, the first adjustment signal RE1 is high, controlling the first transistor T1 to turn off, and the second adjustment signal RE2 is low, controlling the second transistor T2 to turn on. The second clock signal ECK2 is low, controlling the ninth transistor T9 and the third transistor T3 to turn on. The turned-on ninth transistor T9 transmits the start signal EIN to the first node N1. Because the start signal EIN is high, the potential of the first node N1 is VGH. The turned-on third transistor T3 transmits the third potential signal VGL2 to the first terminal of the fifth transistor T5. The high level of the first node N1 controls the first sub-transistor T4-1, the second sub-transistor T4-2, and the eighth transistor T8 to turn off. Due to the influence of the threshold voltage of the fifth transistor T5, the potential of the third node N3 is equal to VGL2 + VTH. The first clock signal ECK1 is high, controlling the seventh transistor T7 to turn off. The first clock signal ECK1 cannot be transmitted to the second node N2 via the sixth transistor T6 and the seventh transistor T7. The potential of the first node N1 controls the eighth transistor T8 to turn off, and the second potential signal VGH cannot be transmitted to the second node N2 via the eighth transistor T8. Therefore, the second node N2 maintains the potential of the second stage t2. The potential of the first node N1 controls the fourteenth transistor T14 to turn off, and the potential of the second node N2 controls the fifteenth transistor T15 to turn on. The second potential signal VGH is transmitted to the output terminal OUT of the gate drive circuit via the turned-on fifteenth transistor T15 and the second transistor T2.

[0087] In the fourth stage t4, the first adjustment signal RE1 is high, controlling the first transistor T1 to turn off, and the second adjustment signal RE2 is low, controlling the second transistor T2 to turn on. The second clock signal ECK2 is high, controlling the ninth transistor T9 and the third transistor T3 to turn off. The first node N1 maintains the potential at the time of the third stage t3, and the third node N3 also maintains the potential at the time of the third stage t3. The first clock signal ECK1 is low, controlling the eleventh transistor T11 to turn on. The second potential signal VGH is transmitted to the first node N1 through the turned-on tenth transistor T10 and eleventh transistor T11, and the first node N1 remains high. The first clock signal ECK1 controls the seventh transistor T7 to turn on. The first clock signal ECK1 is transmitted to the second node N2 through the sixth transistor T6 and the seventh transistor T7, and under the influence of the threshold voltage of the seventh transistor T7, the potential of the second node N2 is ultimately equal to VGL2 + VTH. The potential of the first node N1 controls the eighth transistor T8 to turn off, preventing the second potential signal VGH from being transmitted to the second node N2 via the eighth transistor T8 and affecting the potential of the second node N2. The potential of the first node N1 controls the fourteenth transistor T14 to turn off, and the potential of the second node N2 controls the fifteenth transistor T15 to turn on. The second potential signal VGH is transmitted to the output terminal OUT of the gate drive circuit via the turned-on fifteenth transistor T15 and the second transistor T2.

[0088] In the fifth stage t5, the first adjustment signal RE1 is high, controlling the first transistor T1 to turn off, and the second adjustment signal RE2 is low, controlling the second transistor T2 to turn on. The second clock signal ECK2 is low, controlling the ninth transistor T9 and the third transistor T3 to turn on. The start signal EIN is low, and the start signal is transmitted to the first node N1 through the turned-on ninth transistor T9, causing the potential of the first node N1 to become low. The third potential signal VGL2 is transmitted to the first terminal of the fifth transistor T5 through the third transistor T3. At the same time, the potential of the first node N1 controls the first sub-transistor T4-1 and the second sub-transistor T4-2 to turn on. The second clock signal ECK2 is transmitted to the first terminal of the fifth transistor T5 through the turned-on first sub-transistor T4-1 and the second sub-transistor T4-2, making the potential of the first terminal of the fifth transistor T5 low. The low potential of the fifth transistor T5 is transmitted to the third node N3, and the potential of the third node N3 = VGL2 + VTH. The first clock signal ECK1 is high, turning off the eleventh transistor T11. The second potential signal VGH cannot be transmitted to the first node N1 via the tenth transistor T10 and the eleventh transistor T11, thus avoiding any influence of VGH on the potential of the first node N1. The first clock signal ECK1 also turns off the seventh transistor T7. The potential of the first node N1 turns on the eighth transistor T8, which transmits the second potential signal VGH to the second node N2, making the potential of the second node N2 equal to VGH. The potential of the first node N1 turns on the fourteenth transistor T14, and the potential of the second node N2 turns off the fifteenth transistor T15. The third potential signal VGL2 is then transmitted to the output terminal OUT of the gate drive circuit via the turned-on fourteenth transistor T14.

[0089] In stage t6, the first adjustment signal RE1 is high, turning off the first transistor T1, and the second adjustment signal RE2 is low, turning on the second transistor T2. The second clock signal ECK2 is high, turning off the ninth transistor T9 and the third transistor T3, and the first node N1 maintains the potential of stage t6. The potential of the first node N1 controls the third node N3 to maintain the potential of stage t6. When the first clock signal ECK1 is low, it turns on the first sub-transistor T4-1 and the second sub-transistor T4-2. The second clock signal ECK2 is transmitted to the third node N3 through the turned-on first sub-transistor T4-1, second sub-transistor T4-2, and fifth transistor T5. The potential of the third node N3 becomes high, and it turns off the tenth transistor T10. The second potential signal VGH cannot be transmitted to the first node N1 through the tenth transistor T10 and the eleventh transistor T11, thus avoiding the influence of the second potential signal VGH on the potential of the first node N1. The potential of the third node N3 is high, controlling the sixth transistor T6 to turn off. The first clock signal ECK1 cannot be transmitted to the second node N2 via the sixth transistor T6 and the seventh transistor T7. The potential of the first node N1 controls the eighth transistor T8 to turn on, and the second potential signal VGH is transmitted to the second node N2 via the eighth transistor T8. The potential of the second node N2 is equal to VGH. The potential of the first node N1 controls the fourteenth transistor T14 to turn on, and the potential of the second node N2 controls the fifteenth transistor T15 to turn off. The third potential signal VGL2 is transmitted to the output terminal OUT of the gate drive circuit via the turned-on fourteenth transistor T14.

[0090] From stage 6 to stage 7, the gate drive circuit continuously repeats the operation of stages 5 and 6.

[0091] In the threshold adjustment stage t7, the first adjustment signal RE1 is low, controlling the first transistor T1 to turn on, and the second adjustment signal RE2 is high, controlling the second transistor T2 to turn off. Also in the threshold adjustment stage t7, the states of the gate drive circuit, except for the first transistor T1 and the second transistor T2, are the same as in the fifth stage t5 or the sixth stage t6. Therefore, the potential N2 of the second node N2 is equal to a high level. In this embodiment, the third potential signal VGL2 = -7V, the second potential signal VGH = 7V, and the first potential signal VGL1 = -10V are exemplarily shown. The first potential signal VGL1 is transmitted to the gate of the fifteenth transistor T15 via the turned-on first transistor T1, thereby pulling down the gate voltage of the fifteenth transistor T15. The voltage difference between the gate and the first terminal of the fifteenth transistor T15 decreases, and the threshold voltage of the fifteenth transistor T15 becomes negatively biased, thus compensating for the positive bias of the fifteenth transistor T15 caused by the high-temperature environment. At the same time, the second transistor T2 is turned off to prevent the second potential signal VGH from being transmitted to the output terminal OUT of the gate drive circuit after the fifteenth transistor T15 is turned on during the threshold adjustment stage t7, thus ensuring that the gate drive circuit outputs the third potential signal VGL2 normally.

[0092] During the transition phase t8, the first adjustment signal RE1 is high, controlling the first transistor T1 to turn off, and the threshold voltage of the fifteenth transistor T15 is no longer adjusted. The potential of the second node N2 returns to the second potential signal VGH. The second adjustment signal RE2 is high, controlling the second transistor T2 to turn off.

[0093] In the threshold adjustment completion stage t9, the first adjustment signal RE1 is high, controlling the first transistor T1 to turn off, and the second adjustment signal RE2 is low, controlling the second transistor T2 to turn on. The gate drive circuit continues to cycle through the fifth stage t5 and the sixth stage t6.

[0094] This invention also provides a driving method for a gate driving circuit. Figure 8 A flowchart of a driving method for a gate driving circuit provided in an embodiment of the present invention is shown below. Figure 8 and Figure 2 The gate drive circuit includes an output control module 1, a first output module 2, a second output module 3, and a threshold adjustment module 4. The control terminal of the first output module 2 is electrically connected to the first node N1, and the control terminal of the second output module 3 is electrically connected to the second node N2.

[0095] The driving methods for the gate drive circuit include:

[0096] S10: During the display phase, the output control module controls the potential of the first node and the potential of the second node to alternately transmit the second potential signal or the third potential signal to the output terminal of the gate drive circuit. The first output module controls the transmission of the third potential signal to the output terminal of the gate drive circuit according to the potential of the first node, wherein the third potential signal is a valid control signal. The second output module controls the transmission of the second potential signal to the output terminal of the gate drive circuit according to the potential of the second node, wherein the second potential signal is an invalid control signal. The threshold adjustment module turns off in response to the first adjustment signal.

[0097] The display phase can specifically be... Figure 7 The diagram shows all stages prior to the threshold adjustment stage t7. When the output control module 1 needs to output a valid control signal at the output terminal OUT of the gate drive circuit, it controls the potential of the first node N1 to be low, thereby causing the potential of the first node N1 to control the first output module 2 to conduct and output the third potential signal VGL2. Simultaneously, the output control module 1 controls the potential of the second node N2 to be high, so that the potential of the second node N2 controls the second output module 3 to be turned off. When the output terminal OUT of the gate drive circuit needs to output an invalid potential signal, the operation process is the reverse of the above and will not be described in detail here.

[0098] S20: During the threshold adjustment stage, the threshold adjustment module responds to the first adjustment signal and turns on to transmit the first potential signal to the control terminal of the second output module.

[0099] Optionally, the first potential signal is less than the second potential signal, or the first potential signal is greater than the second potential signal. Optionally, the threshold adjustment stage is located in the display blank area between two adjacent frames. The threshold adjustment module 4 is turned on during the threshold adjustment stage to transmit the first potential signal VGL2 to the second node N2.

[0100] In this embodiment, the end of the second output module 3 connected to the second potential signal VGH is referred to as the first end. The second output module 3 includes a transistor. Under high temperature conditions, the transistor included in the second output module 3 is prone to threshold voltage shift. If the transistor included in the second output module 3 is an N-type transistor, the threshold voltage is prone to negative bias; if the transistor included in the second output module 3 is a P-type transistor, the threshold voltage is prone to positive bias. When the transistor included in the second output module 3 is a P-type transistor, the first potential signal VGL1 is less than the second potential signal VGH, the second potential signal VGH is at a high level (e.g., 7V), and the third potential signal VGL2 is at a low level (e.g., -7V). During the threshold adjustment phase, the threshold adjustment module 4 is turned on to transmit the first potential signal VGL1 to the control terminal of the second output module 3, i.e., the second node N2. Since the first potential signal VGL1 is less than the second potential signal VGH, for example, the first potential signal VGL1 can be 5V, -5V, etc. During the threshold adjustment phase, the potential of the second node N2 is high level, i.e., 7V. After the first potential signal VGL1 is written to the control terminal of the second output module 3, the voltage difference between the control terminal and the first terminal of the second output module 3 is reduced, thereby causing the threshold voltage of the transistors included in the second output module 3 to be negatively biased to partially offset the positive bias of the threshold voltage of the second output module 3 caused by the high temperature environment.

[0101] When the transistors included in the second output module 3 are N-type transistors, the first potential signal VGL1 is greater than the second potential signal VGH, and the second potential signal VGH is at a low level, for example, -7V. The third potential signal VGL2 is at a high level, for example, 7V. During the threshold adjustment stage, the threshold adjustment module 4 is turned on to transmit the first potential signal VGL1 to the control terminal of the second output module 3. Since the first potential signal VGL1 is greater than the second potential signal VGH, for example, the first potential signal VGL1 can be -6V, 8V, etc., during the threshold adjustment stage, the potential of the second node N2 is at a low level, i.e., -7V. After the first potential signal VGL1 is written to the control terminal of the second output module 3, the voltage difference between the control terminal and the first terminal of the second output module 3 increases, thereby causing the threshold voltage of the transistors included in the second output module 3 to be positively biased to partially offset the negative bias of the threshold voltage of the second output module 3 caused by the high temperature environment.

[0102] The driving method of the gate driving circuit provided in this embodiment has the same beneficial effects as the gate driving circuit, and will not be repeated here.

[0103] Figure 9 A flowchart of another driving method for a gate driving circuit provided in an embodiment of the present invention is shown below. Figure 9 and Figure 3Optionally, the gate drive circuit also includes a cutoff module 5, the first terminal of the second output module 3 is connected to the second potential signal VGH, the second terminal of the second output module 3 is electrically connected to the first terminal of the cutoff module 5, the second terminal of the cutoff module 5 is electrically connected to the output terminal OUT of the gate drive circuit, and the control terminal of the cutoff module 5 is electrically connected to the second adjustment signal RE2.

[0104] The driving methods for the gate drive circuit include:

[0105] S101: During the display phase, the output control module controls the potential of the first node and the second node to alternately transmit the second potential signal or the third potential signal to the output terminal of the gate drive circuit. The first output module controls the transmission of the third potential signal to the output terminal of the gate drive circuit according to the potential of the first node, wherein the third potential signal is a valid control signal. The second output module controls the transmission of the second potential signal to the output terminal of the gate drive circuit according to the potential of the second node, wherein the second potential signal is an invalid control signal. The threshold adjustment module turns off in response to the first adjustment signal.

[0106] S201: During the threshold adjustment stage, the threshold adjustment module responds to the first adjustment signal and turns on to transmit the first potential signal to the control terminal of the second output module.

[0107] S301: During the transition phase, the threshold adjustment module turns off in response to the first potential signal, and the cutoff module turns off in response to the second adjustment signal.

[0108] During the transition phase, the threshold adjustment module 4 is turned off, the first potential signal VGL2 is no longer transmitted to the second node N2, and the threshold voltage of the transistors included in the second output module 3 is no longer adjusted.

[0109] S401: During the threshold adjustment completion phase, the threshold adjustment module turns off in response to the first potential signal, and the cutoff module turns on in response to the second adjustment signal. During the threshold adjustment completion phase, the process of adjusting the threshold voltage of the transistors included in the second output module 3 is completely completed. The threshold adjustment module 4 turns off, and the cutoff module 5 turns on, in preparation for entering the display phase of the next frame.

[0110] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0111] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, include: Output control module, first output module, second output module, and threshold adjustment module; The output control module is used to control the potential of the first node and the second node; wherein, the control terminal of the first output module is electrically connected to the first node, and the control terminal of the second output module is electrically connected to the second node; The first output module is used to transmit a third potential signal to the output terminal of the gate drive circuit according to the potential of the first node, wherein the third potential signal is used as a valid control signal. The second output module is used to transmit a second potential signal to the output terminal of the gate drive circuit according to the potential of the second node, wherein the second potential signal is used as an invalid control signal; The threshold adjustment module is used to respond to the first adjustment signal to conduct during the threshold adjustment stage, so as to transmit the first potential signal to the control terminal of the second output module. It also includes: the cutoff module; The first terminal of the second output module is connected to the second potential signal, the second terminal of the second output module is electrically connected to the first terminal of the cutoff module, the second terminal of the cutoff module is electrically connected to the output terminal of the gate drive circuit, the control terminal of the cutoff module is connected to the second adjustment signal, and the cutoff module is used to turn off in response to the second adjustment signal during the threshold adjustment stage.

2. The gate driving circuit according to claim 1, characterized in that, The threshold adjustment module includes a first transistor, the first terminal of the first transistor is connected to the first potential signal, the second terminal of the first transistor is electrically connected to the control terminal of the second output module, and the gate of the first transistor is connected to the first adjustment signal. The cutoff module includes a second transistor, the first terminal of which is electrically connected to the second terminal of the second output module, the second terminal of which is electrically connected to the output terminal of the gate drive circuit, and the gate of the second transistor is connected to the second adjustment signal.

3. The gate driving circuit according to claim 1, characterized in that, The threshold adjustment module is further configured to shut down in response to the first adjustment signal during the transition phase, and the cutoff module is configured to shut down in response to the second adjustment signal during the transition phase.

4. The gate driving circuit according to claim 1, characterized in that, The absolute value of the difference between the first potential signal and the second potential signal is greater than the absolute value of the difference between the third potential signal and the second potential signal.

5. The gate driving circuit according to claim 4, characterized in that, The second output module includes a transistor, and the transistor included in the second output module is a P-type transistor. The absolute value of the difference between the first potential signal and the second potential signal is greater than the absolute value of the difference between the third potential signal and the second potential signal.

6. The gate driving circuit according to claim 5, characterized in that, The second output module includes a transistor, and the transistor included in the second output module is an N-type transistor. The difference between the first potential signal and the second potential signal is greater than the difference between the third potential signal and the second potential signal.

7. The gate driving circuit according to claim 1, characterized in that, The output control module includes a first output control module and a second output control module; The output terminal of the first output control module is electrically connected to the first node. The first output control module is used to transmit to the first node according to the first clock signal, the second clock signal, the potential control start signal of the internal node of the second output control module, and the second potential signal. The output terminal of the second output control module is electrically connected to the second node. The second output control module is used to control the transmission of the first clock signal and the second potential signal to the second node according to the first clock signal, the second clock signal and the potential of the first node.

8. The gate driving circuit according to claim 7, characterized in that, The first output control module includes an input unit and a first node control unit. The input terminal of the input unit is connected to the start signal, the control terminal of the input unit is connected to the second clock signal, and the output terminal of the input unit is electrically connected to the first node. The input unit is used to control the transmission of the start signal to the first node according to the second clock signal. The input terminal of the first node control unit is connected to the second potential signal, the first control terminal of the first node control unit is electrically connected to the internal node of the second output control module, the second control terminal of the first node control unit is connected to the first clock signal, and the output terminal of the first node control unit is electrically connected to the first node. The first node control unit is used to control the transmission of the second potential signal to the first node according to the potential of the internal node of the second output control module and the first clock signal. The second output control module includes: a third node control unit and a second node control unit. The first input terminal of the third node control unit is connected to the third potential signal, the second input terminal of the third node control unit is connected to the second clock signal, the first control terminal of the third node control unit is connected to the second clock signal, the second control terminal of the third node control unit is connected to the first node, and the output terminal of the third node control unit is electrically connected to the third node. The third node control unit is used to control the transmission of the third potential signal and the second clock signal to the third node according to the second clock signal and the potential of the first node. The third node serves as an internal node of the second output control module. The first input terminal of the second node control unit is connected to the first clock signal, the second input terminal of the second node control unit is connected to the second potential signal, the first control terminal of the second node control unit is electrically connected to the third node, the second control terminal of the second node control unit is connected to the first clock signal, the third control terminal of the second node control unit is electrically connected to the first node, and the output terminal of the second node control unit is electrically connected to the second node. The second node control unit is used to control the transmission of the first clock signal and the second potential signal to the second node according to the potential of the third node, the first clock signal, and the potential of the first node.

9. The gate driving circuit according to claim 8, characterized in that, The second node control unit includes a first sub-control unit and a second sub-control unit. The input terminal of the first sub-control unit is connected to the first clock signal, the first control terminal of the first sub-control unit is electrically connected to the third node, the second control terminal of the first sub-control unit is connected to the first clock signal, and the output terminal of the first sub-control unit is electrically connected to the second node. The first sub-control unit is used to control the transmission of the first clock signal to the second node according to the potential of the third node and the first clock signal. The input terminal of the second sub-control unit is connected to the second potential signal, the control terminal of the second sub-control unit is electrically connected to the first node, and the output terminal of the second sub-control unit is electrically connected to the second node. The second sub-control unit is used to control the transmission of the second potential signal to the second node according to the potential of the first node.

10. A driving method for a gate driving circuit, characterized in that, The gate drive circuit includes an output control module, a first output module, a second output module, and a threshold adjustment module; the control terminal of the first output module is electrically connected to the first node, and the control terminal of the second output module is electrically connected to the second node. The driving method of the gate driving circuit includes: During the display phase, the output control module controls the potentials of the first node and the second node to alternately transmit the second potential signal or the third potential signal to the output terminal of the gate driving circuit. The first output module controls the transmission of the third potential signal to the output terminal of the gate driving circuit according to the potential of the first node, wherein the third potential signal is a valid control signal. The second output module controls the transmission of the second potential signal to the output terminal of the gate driving circuit according to the potential of the second node, wherein the second potential signal is an invalid control signal. The threshold adjustment module turns off in response to the first adjustment signal. During the threshold adjustment phase, the threshold adjustment module is turned on in response to the first adjustment signal to transmit the first potential signal to the control terminal of the second output module; The gate driving circuit further includes a cutoff module. A first terminal of the second output module is connected to the second potential signal. A second terminal of the second output module is electrically connected to the first terminal of the cutoff module. The second terminal of the cutoff module is electrically connected to the output terminal of the gate driving circuit. The control terminal of the cutoff module is electrically connected to a second adjustment signal. The driving method of the gate driving circuit further includes: During the transition phase, the threshold adjustment module turns off in response to the first potential signal, and the cutoff module turns off in response to the second adjustment signal. During the threshold adjustment completion phase, the threshold adjustment module turns off in response to the first potential signal, and the cutoff module turns on in response to the second adjustment signal.

11. The driving method for the gate driving circuit according to claim 10, characterized in that, The threshold adjustment stage is located in the display blank area between two adjacent frames.

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