Memory circuit and method of operation thereof

Abstract

Embodiments of the present application provide a memory circuit and a method of operating the same. The memory circuit includes a set of memory cells configured to store data, and a local input-output (LIO) circuit coupled to a global bit line and the set of memory cells. The LIO circuit includes a sense amplifier, a driver circuit, and a boost circuit. The sense amplifier is configured to sense a first signal in response to at least a sense amplifier signal. The first signal corresponds to a value of the data stored in the set of memory cells. The driver circuit is configured to generate a global bit line signal in response to at least the first signal or an inverted first signal. The boost circuit is coupled to the driver circuit and the global bit line, and is configured to adjust the global bit line signal in response to a delayed global bit line signal.

Description

Technical Field

[0001] Embodiments of this application relate to memory circuits and methods of operation thereof. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has developed a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured for data storage. As ICs become smaller and more complex, the resistance of the wires within these digital devices varies, affecting their operating voltage and overall IC performance. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a memory circuit is provided, comprising: a memory cell group configured to store data; and a local input / output (LIO) circuit coupled to a global bit line and the memory cell group, the LIO circuit comprising: a sense amplifier configured to sense a first signal at least in response to a sense amplifier signal, the first signal corresponding to a value of data stored in the memory cell group; a driver circuit configured to generate a global bit line signal at least in response to the first signal or an inverted first signal; and a booster circuit coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal.

[0004] According to one aspect of an embodiment of this application, a memory circuit is provided, comprising: a global bit line; a memory bank group including a first memory bank, the first memory bank including: a first set of memory cells configured to store data; and a first LIO circuit coupled to the global bit line and the first set of memory cells, the first LIO circuit including: a first driver circuit coupled to the global bit line and configured to adjust a global bit line signal in response to at least a first signal, the first signal corresponding to a first value of data stored in the first memory cells of the first set of memory cells; a first booster circuit coupled to the global bit line and configured to adjust a rising edge or falling edge of the global bit line signal in response to a first delayed global bit line signal; and a global input / output (GIO) circuit coupled to the first LIO circuit and the global bit line and configured to output the first value of data stored in the first memory cells of the first set of memory cells in response to a global bit line signal.

[0005] According to one aspect of an embodiment of this application, a method for operating a memory circuit is provided, the method comprising: reading a first memory cell via an LIO circuit in response to at least a sense amplifier signal, wherein reading the first memory cell comprises: sensing a first bit line signal and a second bit line signal via a sense amplifier in response to at least a sense amplifier signal, the sense amplifier being coupled to the first memory cell; generating an inverted second bit line signal via a first inverter in response to the second bit line signal, the inverted second bit line signal corresponding to the first bit line signal, the first inverter being coupled to the sense amplifier; setting a global bit line signal on a global bit line via a driver circuit in response to at least the first bit line signal or the inverted second bit line signal, the driver circuit being coupled to the global bit line, the sense amplifier, and the first inverter; adjusting the rising edge or falling edge of the global bit line signal via a booster circuit in response to a delayed global bit line signal; and outputting the value of first data stored in the first memory cell via a GIO circuit in response to the global bit line signal, the GIO circuit being coupled to the global bit line. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a block diagram of a memory circuit according to some embodiments.

[0008] Figure 2 This is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 3 According to some embodiments Figure 1 and Figure 2 Circuit diagram of the available memory cells.

[0010] Figure 4 This is a circuit diagram of a memory circuit according to some embodiments.

[0011] Figure 5 It is a memory circuit according to some embodiments (such as Figure 4 Memory circuits in Figure 6 The memory circuit in Figure 7 The memory circuit in or Figure 8A or Figure 8B Timing diagram of the waveform of the memory circuit in the memory circuit.

[0012] Figure 6 This is a circuit diagram of a memory circuit according to some embodiments.

[0013] Figure 7 This is a circuit diagram of a memory circuit according to some embodiments.

[0014] Figures 8A-8B These are corresponding circuit diagrams of corresponding memory circuits according to some embodiments.

[0015] Figure 9 This is a circuit diagram of a memory circuit according to some embodiments.

[0016] Figure 10 It is a memory circuit according to some embodiments (such as Figure 2 The circuit or Figure 9 The timing diagram of the waveform of the circuit in the image.

[0017] Figure 11 This is a flowchart of a method for operating circuits according to some embodiments.

[0018] Figure 12 This is a flowchart of a method for operating circuits according to some embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components, materials, values, steps, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, arrangements, etc., may be considered. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0021] According to some embodiments, the memory circuitry includes a group of memory cells configured to store data, and local input / output (LIO) circuitry coupled to the global bit line and the group of memory cells.

[0022] In some embodiments, the LIO circuit includes a sense amplifier configured to sense a first signal at least in response to a sense amplifier signal. In some embodiments, the first signal corresponds to the value of data stored in a group of memory cells.

[0023] In some embodiments, the LIO circuit further includes a driver circuit configured to generate a global bit line signal in response to at least the first signal or an inverted first signal.

[0024] In some embodiments, the LIO circuitry further includes a booster circuit coupled to the driver circuitry and the global bit line. In some embodiments, the booster circuitry is configured to adjust the global bit line signal in response to a delayed global bit line signal.

[0025] In some embodiments, the driver circuitry is configured to cause a rising or falling edge transition of a global bit line signal during a read operation of one or more memory cells in a memory cell group. In some embodiments, in response to a rising or falling edge transition of the global bit line signal, the booster circuitry 406 causes the rising or falling edge transition of the read global bit line signal to occur faster than other methods without the booster circuitry, resulting in a faster read operation than other methods without the booster circuitry.

[0026] Figure 1 This is a block diagram of a memory circuit 100 according to some embodiments.

[0027] For the purpose of explanation, Figure 1 The design has been simplified. In some embodiments, the memory circuitry 100 includes, in addition to Figure 1 Various elements other than those described herein, or arranged in other ways, to perform the operations discussed below.

[0028] The memory circuit 100 is an IC that includes memory partitions 102A-102D, a global control circuit 100GC, and a global input / output (GIO) circuit 100BL.

[0029] Each memory partition 102A-102D includes memory banks 110U and 110L adjacent to word line (WL) driver circuitry 110AC and local control circuitry 110LC. Each memory bank 110U and 110L includes memory cell array 110AR and local input / output (LIO) circuitry 110BS.

[0030] Memory partitions (e.g., memory partitions 102A-102D) are portions of memory circuitry 100, and memory partitions include subsets of memory devices. Figure 1 (Not shown) and adjacent circuitry, the adjacent circuitry being configured to selectively access a subset of the memory device during programming and read operations. Figure 1 In the illustrated embodiment, the memory circuit 100 includes a total of four partitions. In some embodiments, the memory circuit 100 includes a total number of partitions greater than or less than four.

[0031] GIO circuit 100BL is a circuit configured to control access to one or more electrical paths (e.g., bit lines) to each memory device of a corresponding memory bank 110U or 110L in each memory partition 102A-102D, for example, by generating one or more bit line signals. In some embodiments, GIO circuit 100BL includes global bit line driver circuitry. In some embodiments, GIO circuit 100BL accesses the corresponding global bit line (e.g., in...) via a corresponding global bit line (e.g., in...) Figure 2 (Displayed as RGBL or RGBLB) is coupled to each memory bank 110U and 110L.

[0032] The global control circuit 100GC is a circuit configured to control some or all programming and read operations on each memory partition 102A-102D, for example, by generating and / or outputting one or more control signals and / or enable signals.

[0033] In some embodiments, the global control circuit 100GC includes one or more analog circuits configured to interface with memory partitions 102A-102D to program data in one or more memory devices and / or use data received from one or more memory devices in one or more circuit operations. In some embodiments, the global control circuit 100GC includes one or more global address decoder or pre-decoder circuits configured to output one or more address signals to the WL driver circuit 110AC of each memory partition 102A-102D.

[0034] Each WL driver circuit 110AC is configured to generate a word line signal on the corresponding word line WL. In some embodiments, each WL driver circuit 110AC is configured to output the word line signal on the corresponding word line WL to adjacent memory banks 110U and 110L of the corresponding memory partitions 102A-102D.

[0035] Each local control circuit 110LC is an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate a signal corresponding to a subset of adjacent memory devices identified by one or more address signals. In some embodiments, the adjacent subset of memory devices corresponds to a column of memory devices. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary signal pair. In some embodiments, each local control circuit 110LC is configured to output a signal to a corresponding word line driver circuit within the adjacent WL driver circuit 110AC of the corresponding memory partitions 102A-102D. In some embodiments, the local control circuit 110LC includes a volume decoder circuit.

[0036] For example, based on one or more BL control signals, each LIO circuit 110BS is configured to selectively access one or more bit lines (e.g., ...) of an adjacent subset coupled to the memory device in response to the GIO circuit 100BL. Figure 2 (As shown). In some embodiments, adjacent subsets of the memory device correspond to rows of the memory device. In some embodiments, the LIO circuit 110BS includes a bit line selection circuit.

[0037] Each memory bank 110U and 110L includes a corresponding memory cell array 110AR, which includes memory cells or memory devices 112 configured to be accessed in programming and reading operations via adjacent LIO circuits 110BS and adjacent WL driver circuits 110AC.

[0038] Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. The cell rows in the memory cell array 102 are arranged in a first direction X. The cell columns in the memory cell array 102 are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (e.g., ...). Figure 2 (As shown).

[0039] Memory device 112 is shown in memory banks 110U and 110L of memory partition 102A. For ease of illustration, memory device 112 is not shown in memory banks 110U and 110L of memory partitions 102B, 102C and 102D.

[0040] Memory device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logical states. At least one logical state of memory device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, the logical state corresponds to the voltage level of a charge stored in a given memory device 112. In some embodiments, the logical state corresponds to a physical property of a component of a given memory device 112, such as voltage, current, resistance, or magnetic direction.

[0041] In some embodiments, memory device 112 includes one or more single-port (SP) static random access memory (SRAM) cells. In some embodiments, memory device 112 includes one or more dual-port (DP) SRAM cells. In some embodiments, memory device 112 includes one or more multi-port SRAM cells. Different types of memory cells in memory device 112 are within the scope of this invention. In some embodiments, memory device 112 includes one or more dynamic random access memory (DRAM) cells. In some embodiments, memory device 112 includes one or more one-time programmable (OTP) memory devices, such as electronically fused (eFuse) or anti-fuse devices, flash memory devices, random access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, etc. In some embodiments, memory device 112 is an OTP memory device including one or more OTP memory cells.

[0042] Other configurations of the memory circuit 100 are within the scope of this disclosure.

[0043] Figure 2 This is a circuit diagram of a memory circuit 200 according to some embodiments.

[0044] Memory circuit 200 is Figure 1 The embodiment of memory circuit 100 is described in detail below, therefore similar detailed descriptions are omitted. For example, the LIO circuit 210BS of memory circuit 200 is an embodiment of LIO circuit 110BS.

[0045] The memory circuit 200 includes memory partitions 102A-102D, a global control circuit 100GC, a GIO circuit 100BL, and wires 260.

[0046] Each memory partition 102A-102D includes memory banks 110U and 110L adjacent to WL driver circuitry 212 and local control circuitry 110LC. Each memory bank 110U and 110L includes memory cell array 210 and LIO circuitry 210BS.

[0047] and Figure 1 Compared to the memory circuit 100, each memory cell array 210 is an embodiment of memory cell array 110AR, each LIO circuit 210BS is an embodiment of LIO circuit 110BS, and each WL driver circuit 212 is an embodiment of WL driver circuit 110AC, therefore similar detailed descriptions are omitted.

[0048] and Figure 1 Compared to each memory cell array 110AR, each memory cell array 210 is divided into an upper region of memory cell 210a and a lower region of memory cell 210b, therefore a similar detailed description is omitted.

[0049] and Figure 1 Compared to each WL driver circuit 110AC, each WL driver circuit 212 is divided into WL driver circuit 212a and WL driver circuit 212b, therefore a similar detailed description is omitted.

[0050] The LIO circuit 210BS in memory partition 102A includes a booster circuit 206d and an RGBL driver circuit 230d. The LIO circuit 210BS in memory partition 102B includes a booster circuit 206c and an RGBL driver circuit 230c. The LIO circuit 210BS in memory partition 102C includes a booster circuit 206b and an RGBL driver circuit 230b. The LIO circuit 210BS in memory partition 102D includes a booster circuit 206a and an RGBL driver circuit 230a.

[0051] Each booster circuit 206a, 206b, 206c, or 206d is coupled to the corresponding RGBL driver circuit 230a, 230b, 230c, or 230d. Each of the booster circuits 206a, 206b, 206c, or 206d and the corresponding RGBL driver circuit 230a, 230b, 230c, or 230d is coupled to the GIO circuit 100BL via wire 260.

[0052] A conductor 260 extends in a second direction Y. The conductor 260 extends from the GIO circuit 100BL to the memory partition 102A. The conductor 260 overlaps with at least a portion of the GIO circuit 100BL, at least a portion of the memory partitions 102B-102D, and at least a portion of the memory partition 102A. In some embodiments, the conductor 260 is referred to as a global bit line GBL. The global bit line GBL has a global bit line signal GBL'. In some embodiments, the conductor 260 is referred to as a read global bit line RGBL and has a corresponding read global bit line signal RGBL'. In some embodiments, the conductor 260 is referred to as a global inverted bit line GBLB. The global inverted bit line GBLB has a global inverted bit line signal GBLB'. In some embodiments, the conductor 260 is referred to as a read global inverted bit line RGBLB and has a corresponding read global inverted bit line signal RGBLB'. In some embodiments, the conductor 260 extends in the second direction Y across each memory partition 102A-102D of the memory circuit 200.

[0053] Each RGBL driver circuit 230a, 230b, 230c, or 230d is coupled to read the global bit line RGBL or read the global inverted bit line RGBLB. Each RGBL driver circuit 230a, 230b, 230c, or 230d is configured to generate a global bit line signal GBL' or a global inverted bit line signal GBLB'. In some embodiments, each RGBL driver circuit 230a, 230b, 230c, or 230d is configured to set the global bit line signal GBL' or the global inverted bit line signal GBLB' in response to the value of corresponding data stored in a corresponding memory cell within a corresponding memory partition 102A, 102B, 102C, or 102D. In some embodiments, at least one of the RGBL driver circuits 230a, 230b, 230c or 230d is configured to cause a change in the global bit line signal GBL' or the global inverted bit line signal GBLB' in response to the value of the corresponding data stored in the corresponding memory cell within the corresponding memory partition 102A, 102B, 102C or 102D.

[0054] Each booster circuit 206a, 206b, 206c, or 206d is coupled to the read global bit line RGBL or the read global inverted bit line RGBLB. In some embodiments, during a read operation of one or more memory cells in corresponding memory partitions 102A, 102B, 102C, or 102D, the corresponding booster circuit 206a, 206b, 206c, or 206d is configured to respond to the corresponding read global bit line signal RGBL' and a read global bit line signal with a corresponding delay (e.g., Figures 4-7The transition of signal S2 in the corresponding memory partition 102A, 102B, 102C, or 102D is used to adjust the read global bit line signal RGBL'. In some embodiments, during a read operation of one or more memory cells in the corresponding memory partition 102A, 102B, 102C, or 102D, the corresponding boost circuits 206a, 206b, 206c, or 206d are configured to respond to the corresponding read global bit line signal RGBL' and the read global bit line signal with a corresponding delay (e.g., Figures 4-7 The transition of signal S2) is used to adjust the rise or fall edge of the global bit line signal RGBL'.

[0055] In some embodiments, during a read operation of one or more memory cells in corresponding memory partitions 102A, 102B, 102C, or 102D, corresponding booster circuits 206a, 206b, 206c, or 206d are configured to respond to a corresponding read global inverted bit line signal RGBLB' and a corresponding delayed read global inverted bit line signal (e.g., Figures 4-7 The transition of signal S2 in the corresponding memory partition 102A, 102B, 102C, or 102D is used to adjust the read global inverted bit line signal RGBLB'. In some embodiments, during a read operation of one or more memory cells in the corresponding memory partition 102A, 102B, 102C, or 102D, the corresponding boost circuits 206a, 206b, 206c, or 206d are configured to respond to the corresponding read global inverted bit line signal RGBLB' and the corresponding delayed read global inverted bit line signal (e.g., Figures 4-7 The rise or fall edge of the global inverted bit line signal RGBLB' is adjusted by changing the signal S2 in the signal.

[0056] In some embodiments, during a read operation of one or more memory cells in corresponding memory partitions 102A, 102B, 102C, or 102D, an increased or improved transition from logic low to logic high of the corresponding read global bit line signal RGBL' or read global inverted bit line signal RGBLB' compared to other methods causes corresponding booster circuits 206a, 206b, 206c, or 206d to cause a transition from logic low to logic high (e.g., a rising edge) of the corresponding read global bit line signal RGBL' or read global inverted bit line signal RGBLB', thereby resulting in timing improvements of the memory circuitry 200 during one or more read operations.

[0057] In some embodiments, during a read operation of one or more memory cells in corresponding memory partitions 102A, 102B, 102C, or 102D, an increased or improved transition from logic high to logic low of the corresponding read global bit line signal RGBL' or read global inverted bit line signal RGBLB' compared to other methods causes corresponding booster circuits 206a, 206b, 206c, or 206d to cause a transition from logic high to logic low (e.g., a falling edge) of the corresponding read global bit line signal RGBL' or read global inverted bit line signal RGBLB', thereby resulting in timing improvements of the memory circuitry 200 during one or more read operations.

[0058] In some embodiments, for ease of illustration, booster circuits 206a, 206b, 206c, and 206d, RGBL driver circuits 230a, 230b, 230c, and 230d, and wire 260 are shown configured for the left-hand portion of the memory circuit 200. However, in some embodiments, the memory circuit 200 is configured such that circuitry similar to booster circuits 206a, 206b, 206c, and 206d, RGBL driver circuits 230a, 230b, 230c, and 230d, and wire 260 are included in the right-hand portion of the memory circuit 200, and is not shown for ease of illustration; therefore, such detailed descriptions are omitted.

[0059] Other configurations of the memory circuitry 200 are within the scope of this disclosure.

[0060] memory unit

[0061] Figure 3 According to some embodiments Figure 1 and Figure 2 The circuit diagram of the available memory unit 300.

[0062] Memory unit 300 can be used as Figure 1 Memory cell array 110AR, Figure 1 Memory device 112, Figure 2 Memory cell array 210a or Figure 2 One or more memory cells MCB in at least one of the memory cell arrays 210b.

[0063] Memory cell 300 is a six-transistor (6T) single-port (SP) SRAM memory cell for illustration. In some embodiments, memory cell 300 employs multiple transistors in addition to six. Other types of memory are within the scope of various embodiments.

[0064] Memory cell 300 includes two P-type metal-oxide-semiconductor (PMOS) transistors P1 and P2, and four N-type metal-oxide-semiconductor (NMOS) transistors N1, N2, N3, and N4. Transistors P1, P2, N1, and N2 form a cross-latch or a cross-coupled inverter pair. For example, PMOS transistor P1 and NMOS transistor N1 form a first inverter, while PMOS transistor P2 and NMOS transistor N2 form a second inverter.

[0065] The source terminal of each of PMOS transistors P1 and P2 is configured as a supply voltage node NODE_1. Each supply voltage node NODE_1 is coupled to a first supply voltage VDDI. The drain terminal of PMOS transistor P1 is coupled to the drain terminal of NMOS transistor N1, the gate terminal of PMOS transistor P2, the gate terminal of NMOS transistor N2, and the source terminal of NMOS transistor N3, and is configured as a storage node ND.

[0066] The drain terminal of PMOS transistor P2 is coupled to the drain terminal of NMOS transistor N2, the gate terminal of PMOS transistor P1, the gate terminal of NMOS transistor N1, and the source terminal of NMOS transistor N4, and is configured as a storage node NDB. The source terminal of each of NMOS transistors N1 and N2 is configured as a supply reference voltage node (unlabeled) with a supply reference voltage VSS. The source terminal of each of NMOS transistors N1 and N2 is also coupled to the supply reference voltage VSS.

[0067] Word line WL is coupled to the gate terminal of each of NMOS transistors N3 and N4. Word line WL is also referred to as the write control line because NMOS transistors N3 and N4 are configured to be controlled by signals on word line WL to transfer data between bit lines BL, BLB and the corresponding nodes ND, NDB.

[0068] The drain terminal of NMOS transistor N3 is coupled to bit line BL. The drain terminal of NMOS transistor N4 is coupled to bit line BLB. Bit lines BL and BLB are configured for data input and output of memory cell 300. In some embodiments, during a write operation, applying a logic value to the first bit line BL and applying the opposite logic value to the other bit line BLB enables the logic value on the bit line to be written to memory cell 300. Each of bit lines BL and BLB is referred to as a data line because the data carried on bit lines BL and BLB is written to and read from the corresponding nodes ND and NDB.

[0069] The word line WL corresponds to Figure 2 One or more word lines WL in the code. Bit line BL corresponds to... Figure 2One or more bit lines BL in the array. The inverted bit line BLB corresponds to... Figure 2 One or more inverted bit lines (BLBs) in the middle.

[0070] Other configurations of the memory unit 300 are within the scope of this disclosure.

[0071] Memory circuit

[0072] Figure 4 This is a circuit diagram of a memory circuit 400 according to some embodiments.

[0073] Memory circuit 400 is Figure 2 Examples of the LIO circuit 210BS and GIO circuit 100BL are shown, therefore similar detailed descriptions are omitted. For example, the memory circuit 400 is illustrated therein. Figure 4 The LIO circuit 402 is Figure 2 The LIO circuit 210BS, and Figure 4 The GIO circuit 404 is Figure 2 The embodiment of the GIO circuit 100BL is a non-limiting example, and therefore a similar detailed description is omitted.

[0074] Memory circuit 400 includes LIO circuit 402 coupled to GIO circuit 404 via wire 260. In some embodiments, wire 260 is a read global inverted bit line RGBLB. For ease of illustration and simplicity, Figures 4-7 The description uses wire 260 as the read global inverted bit line RGBLB. In some embodiments, wire 260 is the read global bit line RGBL.

[0075] LIO circuit 402 includes boost circuit 406, sense amplifier 420, inverter I3 and driver circuit 430.

[0076] and Figure 2 Compared to the memory circuit 200, the booster circuit 406 is an embodiment of at least one of the booster circuits 206a, 206b, 206c or 206d, and the driver circuit 430 is an embodiment of at least one of the driver circuits 230a, 230b, 230c or 230d, therefore similar detailed descriptions are omitted.

[0077] The booster circuit 406 is coupled to the read global inverted bit line RGBLB. The booster circuit 406 is configured to adjust the rising or falling edge of the read global inverted bit line signal RGBLB' in response to the transition of signal S2 and the corresponding read global inverted bit line signal RGBLB'.

[0078] The booster circuit 406 includes an inverter I1, a delay circuit 410, an inverter I2, and a feedback circuit 416.

[0079] Inverter I1 is configured to generate signal RGBL' in response to the read global inverted bit line signal RGBLB'. In some embodiments, signal RGBL' is inverted by the read global inverted bit line signal RGBLB'. The input terminal of inverter I1 is coupled to the read global inverted bit line RGBLB and configured to receive the read global inverted bit line signal RGBLB'. The output terminal of inverter I1 is coupled to the input terminal of delay circuit 410 and the first input terminal of feedback circuit 416 and configured to output signal RGBL'.

[0080] Delay circuit 410 is coupled between inverter I1 and inverter I2. Delay circuit 410 is configured to generate a delayed signal S1 in response to signal RGBL'. In some embodiments, the delayed signal S1 is delayed from signal RGBL'. The input terminal of delay circuit 410 is configured to receive signal RGBL'. The output terminal of delay circuit 410 is coupled to the input terminal of inverter I2 via conductive path 412. The output terminal of delay circuit 410 is coupled to the input terminal of inverter I2 and is configured to output signal RGBL'. In some embodiments, conductive path 412 is a conductive coil that introduces delay to the delayed signal S1. In some embodiments, delay circuit 410 is replaced by conductive path 412, and therefore a similar detailed description is omitted.

[0081] Other configurations of the delay circuit 410 are within the scope of this disclosure.

[0082] Inverter I2 is configured to generate signal S2 in response to a delayed signal S1. In some embodiments, signal S2 is the inverse of the delayed signal S1. The input terminal of inverter I2 is configured to receive the delayed signal S1. The output terminal of inverter I2 is coupled to the second input terminal of feedback circuit 416 and is configured to output signal S2. In some embodiments, signal S2 corresponds to reading a delayed version of the global inverted bit line signal RGBLB'.

[0083] Feedback circuit 416 is coupled between inverter I2 and read global inverted bit line RGBLB. Feedback circuit 416 is configured to adjust the rising or falling edge of read global inverted bit line signal RGBLB' in response to transitions in signal S2 and signal RGBL'. In some embodiments, feedback circuit 416 is configured to adjust the rising or falling edge of read global inverted bit line signal RGBLB' in response to transitions in signal S2 and the corresponding read global inverted bit line signal RGBLB'.

[0084] The feedback circuit 416 includes PMOS transistors MP1 and MP2, and NMOS transistors MN1 and MN2. The gates of NMOS transistor MN2 and PMOS transistor MP2 correspond to the first input terminals of the feedback circuit 416. The gates of NMOS transistor MN1 and PMOS transistor MP1 correspond to the second input terminals of the feedback circuit 416.

[0085] The source of PMOS transistor MP1 is coupled to the supply voltage VDD. The gate of PMOS transistor MP1 is configured to receive signal S2 and is coupled to the output terminal of inverter I2 and the gate of NMOS transistor MN1. The drain of PMOS transistor MP1 and the source of PMOS transistor MP2 are coupled together at least through a node (unlabeled).

[0086] The gate of PMOS transistor MP2 is configured to receive signal RGBL' and is coupled to the output terminal of inverter 11 and the gate of NMOS transistor MN2. The drains of PMOS transistor MP2 and NMOS transistor MN2 are coupled together through an output node (unlabeled), which is further coupled to the read global inverted bit line RGBLB. Therefore, the drains of PMOS transistor MP2 and NMOS transistor MN2 are coupled to the read global inverted bit line RGBLB.

[0087] The gate of NMOS transistor MN2 is configured to receive signal RGBL' and is coupled to the output terminal of inverter 11 and the gate of PMOS transistor MP2. The source of NMOS transistor MN2 and the drain of NMOS transistor MN1 are coupled together at least through a node (unlabeled).

[0088] The gate of NMOS transistor MN1 is configured to receive signal S2 and is coupled to the output terminal of inverter I2 and the gate of PMOS transistor MP1. The source of NMOS transistor MN1 is coupled to the reference supply voltage VSS.

[0089] Other configurations, number of transistors, or types of transistors in the feedback circuit 416 are within the scope of this disclosure.

[0090] Sensing amplifier 420 is coupled to driver circuit 430 and inverter I3. In some embodiments, sensing amplifier 420 is further coupled to one or more memory cells in memory cell array 210a or 210b. Sensing amplifier 420 is configured to sense inverted bit line signal RBLB and bit line signal RBL, at least in response to sensing amplifier signal SAE. In some embodiments, inverted bit line signal RBLB is a partially inverted bit line signal, and bit line signal RBL is a partially inverted bit line signal. In some embodiments, inverted bit line signal RBLB corresponds to the value of data stored in one or more memory cells in memory cell array 210a or 210b.

[0091] Inverter I3 is coupled to sense amplifier 420 and driver circuit 430. Inverter I3 is configured to generate an inverted bit line signal RBLN in response to bit line signal RBL. In some embodiments, the inverted bit line signal RBLN is inverted compared to bit line signal RBL. The input terminal of inverter I3 is coupled to sense amplifier 420 via a local bit line. The input terminal of inverter I3 is configured to receive bit line signal RBL from sense amplifier 420. The output terminal of inverter I3 is coupled to the gate of NMOS transistor MN3 of driver circuit 430 and is configured to output an inverted bit line signal RBLN. In some embodiments, the inverted bit line signal RBLN corresponds to the inverted bit line signal RBLB. In some embodiments, the inverted bit line signal RBLN corresponds to the value of data stored in one or more memory cells in memory cell array 210a or 210b.

[0092] Driver circuitry 430 is coupled to the read global inverted bit line GBLB, sense amplifier 420, and inverter I3. Driver circuitry 430 is configured to adjust the read global inverted bit line signal RGBLB' in response to at least the inverted bit line signal RBLN or the inverted bit line signal RBLB. In some embodiments, driver circuitry 430 is configured to cause a transition of the read global inverted bit line signal RGBLB' to logic 1 or logic 0 based on the value of data stored in a memory cell (not shown) coupled to the sense amplifier. In some embodiments, driver circuitry 430 is configured to cause a transition of the read global inverted bit line signal RGBLB' to logic 1 or logic 0 in response to at least the inverted bit line signal RBLN or the inverted bit line signal RBLB.

[0093] The driver circuit 430 includes a PMOS transistor MP3 and an NMOS transistor MN3.

[0094] The source of PMOS transistor MP3 is coupled to the supply voltage VDD. The gate of PMOS transistor MP3 is configured to receive the inverted bit line signal RBLB and is coupled to sense amplifier 420 via a local inverted bit line. The drains of PMOS transistor MP3 and NMOS transistor MP3 are coupled together at least through an output node (unlabeled). The drains of PMOS transistor MP3 and NMOS transistor MP3 are coupled to the read global inverted bit line RGBLB.

[0095] The gate of NMOS transistor MN3 is configured to receive the inverted bit line signal RBLN and is coupled to the output terminal of inverter I3. The source of NMOS transistor MN3 is coupled to the reference supply voltage VSS.

[0096] Although Figures 4-7 The description uses conductor 260 as the read global inverted bit line RGBLB, but in some embodiments, conductor 260 is used to read the global bit line RGBL, and therefore similar detailed descriptions are omitted. In these embodiments, the local bit line and the local inverted bit line, as well as the bit line signal RBL of the local bit line and the inverted bit line signal RBLB of the local inverted bit line, are interchanged.

[0097] Other configurations, number of transistors, or types of transistors in the driver circuit 430 are within the scope of this disclosure.

[0098] Other configurations, other circuit elements, number of transistors, or transistor types in the LIO circuit 402 are within the scope of this disclosure.

[0099] GIO circuit 404 is coupled to read global inverted bit line RGBLB and LIO circuit 402. GIO circuit 404 is configured to output data signal Q in response to read global inverted bit line signal RGBLB. In some embodiments, data signal Q corresponds to the value of data stored in one or more memory cells in memory cell array 210a or 210b.

[0100] GIO circuit 404 includes inverter I6 and latch circuit 408.

[0101] Inverter I6 is configured to generate a data signal Q in response to a read global inverted bit line signal RGBLB'. In some embodiments, the data signal Q is inverted from the read global inverted bit line signal RGBLB'. The input terminal of inverter I6 is coupled to the read global inverted bit line RGBLB and is configured to receive the read global inverted bit line signal RGBLB'. The output terminal of inverter I6 is configured to output the data signal Q. In some embodiments, the data signal Q corresponds to the inverted bit line signal RBLB.

[0102] Latch circuit 408 is coupled to the input terminals of the read global inverted bit line RGBLB and inverter I6. Latch circuit 408 is configured to latch the state or value of the read global inverted bit line signal RGBLB'. In some embodiments, latch circuit 408 is enabled or disabled by enable signal RGBLEN and inverted enable signal RGBLENB. In some embodiments, latch circuit 408 is disabled immediately before driver circuit 430 begins driving read global inverted bit line RGBLB. In some embodiments, latch circuit 408 is enabled after driver circuit 430 drives read global inverted bit line RGBLB.

[0103] The latch circuit 408 includes inverter I4 and inverter I5.

[0104] Inverter I4 is configured to generate signal S3 in response to the read global inverted bit line signal RGBLB'. In some embodiments, signal S3 is inverted by the read global inverted bit line signal RGBLB'. The input terminal of inverter I4 is coupled to the read global inverted bit line RGBLB and is configured to receive the read global inverted bit line signal RGBLB'. The output terminal of inverter I4 is coupled to the input terminal of inverter I5 and is configured to output signal S3.

[0105] Inverter I5 is configured to generate a read global inverted bit line signal RGBLB' in response to signal S3. The first input terminal of inverter I5 is coupled to the output terminal of inverter I4 and configured to receive signal S3. The second input terminal of inverter I5 is configured to receive an enable signal RGBLEN. The third input terminal of inverter I5 is configured to receive an inversion enable signal RGBLENB. The output terminal of inverter I5 is coupled to the input terminal of inverter I6 and configured to output the read global inverted bit line signal RGBLB'.

[0106] In some embodiments, inverter I5 is enabled or disabled by the enable signal RGBLEN and the inverted enable signal RGBLENB. In some embodiments, inverter I5 is disabled immediately before the driver circuit 430 begins driving the read global inverted bit line RGBLB. In some embodiments, inverter I5 is enabled after the driver circuit 430 drives the read global inverted bit line RGBLB. In some embodiments, inverter I5 is disabled during a memory cell read operation. In some embodiments, inverter I5 is enabled before or after a memory cell read operation.

[0107] Other configurations, other types of circuit elements, or the number of circuit elements in GIO circuit 404 are within the scope of this disclosure.

[0108] Non-limiting examples of read operations of memory cells coupled to LIO circuit 402 are described with respect to driver circuit 430, sense amplifier 420, inverter I3, and GIO circuit 404. For brevity, the following describes... Figure 5 Describe at least the operation of booster circuit 406.

[0109] For example, in some embodiments, if the memory cell coupled to LIO circuit 402 is configured to store logic 1, and the difference between the voltages of the inverted bit line signal RBLB and the bit line signal RBL is greater than 0 (e.g., V(RBLB)V(RBL)>0), then when sense amplifier 420 is turned on in response to sense amplifier signal SAE, bit line signal RBL becomes logic 0, and inverted bit line signal RBLB remains logic 1. In response to bit line signal RBL becoming logic 0, inverter I3 sets signal RBLN to logic 1, thereby turning on NMOS transistor N3. In response to turning on NMOS transistor N3, NMOS transistor N3 pulls the read global inverted bit line RGBLB and read global inverted bit line signal RGBLB' to the reference supply voltage VSS, and they become logic 0. In response to read global inverted bit line signal RGBLB' becoming logic 0, inverter I6 sets output signal Q to logic 1, and output signal Q corresponds to the data stored in the memory cell coupled to LIO circuit 402.

[0110] For example, in some embodiments, if the memory cell coupled to the LIO circuit 402 is configured to store logic 0, and the difference between the voltages of the bit line signal RBL and the inverted bit line signal RBLB is greater than 0 (e.g., V(RBL)V(RBLB)>0), then when the sense amplifier 420 is turned on in response to the sense amplifier signal SAE, the bit line signal RBL becomes logic 1, and the inverted bit line signal RBLB becomes logic 0. In response to the bit line signal RBL becoming logic 1, the inverter I3 sets the signal RBLN to logic 0, thereby turning off the NMOS transistor N3. In response to the inverted bit line signal RBLB becoming logic 0, the PMOS transistor P3 is turned on. In response to turning on the PMOS transistor P3, the PMOS transistor P3 pulls the read global inverted bit line RGBLB and the read global inverted bit line signal RGBLB' to the supply voltage VDD, and sets them to logic 1. In response to the read global inverted bit line signal RGBLB' being read as logic 1, inverter I6 sets the output signal Q to logic 0. The output signal Q corresponds to the data stored in the memory cell coupled to LIO circuit 402.

[0111] In some embodiments, memory circuitry 400 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100 or 200.

[0112] Other configurations of the memory circuit 400 are within the scope of this disclosure.

[0113] waveform

[0114] Figure 5 It is a memory circuit according to some embodiments (such as Figure 4 The memory circuit 400 in Figure 6 The memory circuit 600 in the middle Figure 7 The memory circuit 700 or Figures 8A-8B Timing diagram 500 shows the waveforms of the memory circuits 800A-800B in the memory circuit.

[0115] In some embodiments, Figure 5 It is at least memory circuit 100-200, memory circuit 400 or according to some embodiments Figures 6 to 9 Timing diagram 500 for memory circuits 600-900.

[0116] In some embodiments, at least memory circuit 200 or Figure 9 One or more read operations of the memory bank in the memory circuit 900 can be applied to at least one of the memory partitions 102A, 102B, 102C or 102D, and the timing diagram 500 corresponds to the waveform during the read operation of at least one of the memory partitions 102A, 102B, 102C or 102D.

[0117] Timing diagram 500 includes waveforms for reading the global inverted bit line signal RGBLB', reading the global bit line signal RGBL', signal S1, and signal S2.

[0118] At time T0, the global inverted bit line signal RGBLB' is read as logic low, the global bit line signal RGBL' is read as logic high, signal S1 is logic high, and signal S2 is logic low.

[0119] At time T0, in response to the global bit line signal RGBL' being read as logic high and in response to signal S2 being read as logic low, feedback circuit 416 is turned off. For example, at time T0, in response to the global bit line signal RGBL' being read as logic high, NMOS transistor MN2 is turned on and PMOS transistor MP2 is turned off, and in response to signal S2 being read as logic low, NMOS transistor MN1 is turned off and PMOS transistor MP1 is turned on.

[0120] At time Tl, driver circuit 430 causes the read global bit line signal RGBLB' to change from logic low to logic high, and inverter Il causes the read global bit line signal RGBL' to change from logic high to logic low.

[0121] At time T2, delay circuit 410 causes signal S1 to change from logic high to logic low, and inverter I2 causes signal S2 to change from logic low to logic high.

[0122] In some embodiments, signal S1 is delayed relative to the read global bit line signal RGBL' by at least a delay D1. In some embodiments, delay D1 is caused by delay circuitry 410. In some embodiments, signal S2 is delayed relative to the read global inverted bit line signal RGBLB' by at least a delay D1.

[0123] At time T3, the transition of the global bit line signal RGBL' to logic low is sufficient to enable the feedback circuit 416. For example, in some embodiments, at time T3, the transition of the global bit line signal RGBL' to logic low is sufficient to turn on the PMOS transistor MP2 and turn off the NMOS transistor MN2.

[0124] At time T3, because signal S2 is delayed by delay D1 relative to the transition of the global inverted bit line signal RGBLB', signal S2 keeps PMOS transistor MP1 on and NMOS transistor MN1 off at time T3.

[0125] At time T3, in response to the activation of feedback circuit 416, the read global inverted bit line signal RGBLB' is boosted, thus transitioning to logic high faster than before time T3. For example, at time T3, in response to the conduction of PMOS transistor MP2 and the already conducted conduction of PMOS transistor MP1, feedback circuit 416 is activated, thereby electrically coupling the output node of feedback circuit 416 to the supply voltage VDD, and PMOS transistors MP1 and MP2 pull the output node and the read global inverted bit line signal RGBLB' to the supply voltage VDD.

[0126] At time T4, the global inverted bit line signal RGBLB' is read as logic high, and the global bit line signal RGBL' is read as logic low.

[0127] Between times T4 and T5, the transition of signal S2 to logic high is sufficient to turn off PMOS transistor MP1 and turn on NMOS transistor MN1, and feedback circuit 416 is turned off, and the read global inverted bit line signal RGBLB' is no longer boosted by feedback circuit 416. In some embodiments, the read global inverted bit line signal RGBLB' is boosted until delay D1 has elapsed. For example, in some embodiments, PMOS transistors MP1 and MP2 pull the output node and the read global inverted bit line signal RGBLB' to the supply voltage VDD until the transition of signal S2 to logic high is sufficient to turn off PMOS transistor MP1 and turn on NMOS transistor MN1 (e.g., between times T4 and T5).

[0128] At time T5, the global bit line signal RGBLB' is read as logic high, the global bit line signal RGBL' is read as logic low, signal S1 is logic low, and signal S2 is logic high. For example, at time T5, in response to the global bit line signal RGBL' being read as logic low, NMOS transistor MN2 is turned off and PMOS transistor MP2 is turned on, and in response to signal S2 being logic high, NMOS transistor MN1 is turned on and PMOS transistor MP1 is turned off.

[0129] At time T6, driver circuit 430 causes the read global bit line signal RGBLB' to change from logic high to logic low, and inverter Il causes the read global bit line signal RGBL' to change from logic low to logic high.

[0130] At time T7, delay circuit 410 causes signal S1 to change from logic low to logic high, and inverter I2 causes signal S2 to change from logic high to logic low.

[0131] In some embodiments, signal S1 is delayed by at least delay D1 relative to the read global bit line signal RGBL'.

[0132] At time T8, the transition of the global bit line signal RGBL' to logic high is sufficient to enable the feedback circuit 416. For example, in some embodiments, at time T8, the transition of the global bit line signal RGBL' to logic high is sufficient to turn off the PMOS transistor MP2 and turn on the NMOS transistor MN2.

[0133] At time T8, because signal S2 is delayed by delay D1 relative to the transition of the global inverted bit line signal RGBLB', signal S2 keeps PMOS transistor MP1 off and NMOS transistor MN1 on at time T8.

[0134] At time T8, in response to the activation of feedback circuit 416, the read global inverted bit line signal RGBLB' is boosted, thus transitioning to logic low faster than before time T8. For example, at time T8, in response to the conduction of NMOS transistor MN2 and the already conducted conduction of NMOS transistor MN1, feedback circuit 416 is activated, thereby electrically coupling the output node of feedback circuit 416 to the reference supply voltage VSS, and NMOS transistors MN1 and MN2 pull the output node and the read global inverted bit line signal RGBLB' towards the reference supply voltage VSS.

[0135] At time T9, the global inverted bit line signal RGBLB' is read as logic low, and the global bit line signal RGBL' is read as logic high.

[0136] Between times T9 and T10, the transition of signal S2 to logic low is sufficient to turn on PMOS transistor MP1 and turn off NMOS transistor MN1, and feedback circuit 416 is turned off, and the read global inverted bit line signal RGBLB' is no longer boosted by feedback circuit 416. In some embodiments, the read global inverted bit line signal RGBLB' is boosted until delay D1 has elapsed. For example, in some embodiments, NMOS transistors MN1 and MN2 pull the output node and the read global inverted bit line signal RGBLB' towards the reference supply voltage VSS until the transition of signal S2 to logic low is sufficient to turn on PMOS transistor MP1 and turn off NMOS transistor MN1 (e.g., between times T9 and T10).

[0137] At time T10, the global bit line signal RGBLB' is read as logic low, the global bit line signal RGBL' is read as logic high, signal S1 is logic high, and signal S2 is logic low. For example, at time T10, in response to the global bit line signal RGBL' being read as logic high, NMOS transistor MN2 is turned on and PMOS transistor MP2 is turned off, and in response to signal S2 being logic low, NMOS transistor MN1 is turned off and PMOS transistor MP1 is turned on.

[0138] As shown at least between times T3 and T4, booster circuit 406 enables the read global inverted bit line signal RGBLB' to transition from logic low to logic high faster than methods without booster circuit 406, resulting in a faster read operation than other methods without booster circuit 406.

[0139] As shown at least between time T8 and T9, booster circuit 406 enables the read global inverted bit line signal RGBLB' to transition from logic high to logic low faster than methods without booster circuit 406, resulting in a faster read operation than other methods without booster circuit 406.

[0140] In some embodiments, although timing diagram 500 is described relative to memory bank 110U, timing diagram 500 is also applied to memory bank 110L in a similar manner and is not described for the sake of brevity.

[0141] Other configurations of timing diagram 500 are within the scope of this disclosure.

[0142] Figure 6 This is a circuit diagram of a memory circuit 600 according to some embodiments.

[0143] Memory circuit 600 is Figure 2Examples of LIO circuit 210BS and GIO circuit 100BL are shown, and therefore similar detailed descriptions are omitted. For example, memory circuit 600 shows a non-limiting example in which delay circuit 610 includes inverter pairs (e.g., inverter I6 and inverter I7), and therefore similar detailed descriptions are omitted.

[0144] The memory circuit 600 includes an LIO circuit 602 coupled to the GIO circuit 404 via a wire 260. The memory circuit 600 is... Figure 4 A variant of the memory circuit 400, therefore a similar detailed description is omitted. Figure 4 Compared to the memory circuit 400, Figure 6 The LIO circuit 602 replaces the LIO circuit 402, therefore a similar detailed description is omitted.

[0145] LIO circuit 602 includes boost circuit 606, sense amplifier 420, inverter I3 and driver circuit 430.

[0146] Boost circuit 606 is a variation of boost circuit 406. For example, boost circuit 606 replaces boost circuit 406, therefore a similar detailed description is omitted. Boost circuit 606 includes inverter I1, delay circuit 610, inverter I2, and feedback circuit 416.

[0147] Figure 6 The delay circuit 610 of the booster circuit 606 is an embodiment of the delay circuit 410, and therefore a similar detailed description is omitted.

[0148] The delay circuit 610 includes inverter I6 and inverter I7.

[0149] Inverter I6 is configured to generate signal S4 in response to signal RGBL'. In some embodiments, signal S4 is inverted by signal RGBL'. The input terminal of inverter I6 is coupled to the output terminal of inverter I1 and is configured to receive signal RGBL'. The output terminal of inverter I6 is coupled to the input terminal of inverter I7 and is configured to output signal S4.

[0150] Inverter I7 is configured to generate signal S1 in response to signal S4. In some embodiments, signal S4 is inverted compared to signal S1. The input terminal of inverter I7 is coupled to the output terminal of inverter I6 and is configured to receive signal S4. The output terminal of inverter I7 is coupled to the input terminal of inverter I2 and is configured to output signal S1.

[0151] Other configurations, other circuit elements, the number of inverters, the number of transistors, or the type of transistors in the LIO circuit 602 are within the scope of this disclosure.

[0152] In some embodiments, memory circuitry 600 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100, 200, or 400.

[0153] Other configurations of the memory circuitry 600 are within the scope of this disclosure.

[0154] Figure 7 This is a circuit diagram of a memory circuit 700 according to some embodiments.

[0155] Memory circuit 700 is Figure 2 Embodiments of the LIO circuit 210BS and GIO circuit 100BL are shown, therefore similar detailed descriptions are omitted. For example, a memory circuit 700 is shown as a non-limiting example in which the delay circuit 710 includes a buffer circuit B1, therefore similar detailed descriptions are omitted.

[0156] The memory circuit 700 includes an LIO circuit 702 coupled to the GIO circuit 404 via a wire 260. The memory circuit 700 is... Figure 4 A variant of the memory circuit 400, therefore a similar detailed description is omitted. Figure 4 Compared to the memory circuit 400, Figure 7 The LIO circuit 702 replaces the LIO circuit 402, therefore a similar detailed description is omitted.

[0157] LIO circuit 702 includes boost circuit 706, sense amplifier 420, inverter I3 and driver circuit 430.

[0158] Boost circuit 706 is a variant of boost circuit 406. For example, boost circuit 706 replaces boost circuit 406, so a similar detailed description is omitted. Boost circuit 706 includes inverter I1, delay circuit 710, inverter I2, and feedback circuit 416.

[0159] Figure 7 The delay circuit 710 of the booster circuit 706 is an embodiment of the delay circuit 410, therefore a similar detailed description is omitted.

[0160] The delay circuit 710 includes a buffer circuit B1.

[0161] Buffer circuit B1 is configured to generate a delayed signal S1 in response to signal RGBL'. The input terminal of buffer circuit B1 is coupled to the output terminal of inverter I1 and is configured to receive signal RGBL'. The output terminal of buffer circuit B1 is coupled to the input terminal of inverter I2 and is configured to output the delayed signal S1.

[0162] Other configurations, other circuit elements, number of buffer circuits, number of transistors, or transistor types in the LIO circuit 702 are within the scope of this disclosure.

[0163] In some embodiments, memory circuitry 700 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100, 200, or 400.

[0164] Other configurations of the memory circuit 700 are within the scope of this disclosure.

[0165] Figures 8A-8B These are corresponding circuit diagrams of memory circuits 800A-800B according to some embodiments.

[0166] Memory circuits 800A-800B are Figure 6 Variations of the memory circuit 600 are shown, and therefore similar detailed descriptions are omitted. For example, memory circuit 800A is illustrated in a non-limiting example in which feedback circuit 816a does not include NMOS transistors MN1 and MN2, and memory circuit 800B is illustrated in a non-limiting example in which feedback circuit 816b does not include PMOS transistors MP1 and MP2, and therefore similar detailed descriptions are omitted.

[0167] Memory circuits 800A-800B are Figure 2 Examples of the LIO circuit 210BS and GIO circuit 100BL are described, and therefore similar detailed descriptions are omitted.

[0168] Memory circuit 800A includes an LIO circuit 802a coupled to GIO circuit 404 via wire 260. Memory circuit 800B includes an LIO circuit 802b coupled to GIO circuit 404 via wire 260. Memory circuits 800A-800B are variant diagrams of memory circuit 600, and therefore similar detailed descriptions are omitted. Figure 6 Compared to the memory circuit 600, Figure 8A The LIO circuit 802a replaced the LIO circuit 602, and Figure 8B The LIO circuit 802b replaces the LIO circuit 602, and therefore a similar detailed description is omitted.

[0169] LIO circuit 802a includes boost circuit 806a, sense amplifier 420, inverter I3 and driver circuit 430. LIO circuit 802b includes boost circuit 806b, sense amplifier 420, inverter I3 and driver circuit 430.

[0170] Boost circuits 806a-806b are variations of boost circuit 606. For example, boost circuits 806a and 806b replace boost circuit 606, and therefore similar detailed descriptions are omitted. Boost circuit 806a includes an inverter I1, a delay circuit 710, an inverter I2, and a feedback circuit 816a. Boost circuit 806b includes an inverter I1, a delay circuit 710, an inverter I2, and a feedback circuit 816b.

[0171] and Figure 6 compared to, Figure 8A The feedback circuit 816a and Figure 8B The feedback circuit 816b replaces the feedback circuit 616, and therefore a similar detailed description is omitted.

[0172] The feedback circuit 816a includes PMOS transistors MP1 and MP2.

[0173] Compared to feedback circuit 416, feedback circuit 816a does not include NMOS transistors MN1 and MN2. By omitting NMOS transistors MN1 and MN2, memory circuit 800A includes fewer transistors and therefore occupies less area than other methods.

[0174] The feedback circuit 816b includes NMOS transistors MN1 and MN2.

[0175] Compared to feedback circuit 416, feedback circuit 816b does not include PMOS transistors MP1 and MP2. By omitting PMOS transistors MP1 and MP2, memory circuit 800B includes fewer transistors and therefore occupies less area than other methods.

[0176] Other configurations, number of transistors, or transistor types in the feedback circuits 816a-816b are within the scope of this disclosure.

[0177] Other configurations, other circuit elements, number of inverters, number of transistors, or transistor type in the LIO circuit 802a or 802b are within the scope of this disclosure.

[0178] In some embodiments, memory circuits 800A-800B operate to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuits 100, 200, or 400.

[0179] Other configurations of the memory circuits 800A-800B are within the scope of this disclosure.

[0180] Figure 9 This is a circuit diagram of a memory circuit 900 according to some embodiments.

[0181] Memory circuit 900 is Figure 2Variations of memory circuit 200 are shown, and therefore similar detailed descriptions are omitted. For example, memory circuit 900 illustrates a non-limiting example in which at least one LIO circuit (e.g., LIO circuit 210BS) does not include a booster circuit, and therefore similar detailed descriptions are omitted.

[0182] The memory circuit 900 includes memory partitions 102A-102D, a global control circuit 100GC, a GIO circuit 100BL, and wires 260.

[0183] Memory circuit 900 is Figure 2 A variant of the memory circuit 200, and therefore a similar detailed description is omitted. Figure 2 Compared to the memory circuit 200, the LIO circuit 210BS in memory partition 102A does not include the booster circuit 206d.

[0184] The LIO circuit 210BS in memory partition 102A includes RGBL driver circuit 230d.

[0185] Memory banks 110U and 110L in memory partition 102D are located adjacent to GIO circuit 100BL. Memory banks 110U and 110L in memory partition 102A are located adjacent to the first end or edge of memory circuit 900 opposite to the second end of memory circuit 900. The second end of memory circuit 900 is the end of memory circuit 900 located by GIO circuit 100BL.

[0186] In some embodiments, one or more read operations on the memory bank in the memory circuit 900 are as follows: Figure 10 The sequential operation is shown. For example, a read operation is applied to memory banks 110U and 110L in memory partition 102A, then a read operation is applied to memory banks 110U and 110L in memory partition 102B, then a read operation is applied to memory banks 110U and 110L in memory partition 102C, and then a read operation is applied to memory banks 110U and 110L in memory partition 102D.

[0187] In some embodiments, since the read operations of memory banks 110U and 110L in memory partition 102A occur before the read operations of memory banks 110U and 110L in memory partitions 102B-102D, the global inverted bit line signal RGBLB' (e.g., as shown in the image) is read. Figure 10 The waveform 1002 in the memory circuit 900 (shown in the waveform 1002) was not damaged by noise and resistive / capacitive load, therefore the memory partition 102A in the memory circuit 900 does not include the booster circuit 206d.

[0188] Other configurations, other circuit elements, number of inverters, number of transistors, or transistor type in the LIO circuit 802 are within the scope of this disclosure.

[0189] In some embodiments, memory circuitry 900 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100, 200, or 400.

[0190] Other configurations of the memory circuitry 900 are within the scope of this disclosure.

[0191] waveform

[0192] Figure 10 It is a memory circuit according to some embodiments (such as Figure 2 Circuit 200 or Figure 9 The waveform timing diagram of circuit 900 in the circuit is shown in Figure 1000.

[0193] In some embodiments, Figure 10 It is at least memory circuit 100-200, memory circuit 400 or according to some embodiments Figures 6-9 Timing diagram 1000 for memory circuits 600-900.

[0194] In some embodiments, one or more read operations on the memory bank in at least memory circuitry 200 or 900 are performed sequentially (e.g., time T1-time T5), such as Figure 10 As shown, waveforms 1002, 1004a, 1004b, 1006a, 1006b, 1008a, 1008b, 1010a, and 1010b correspond to waveforms during the sequential read operation of memory partitions 102A, 102B, 102C, and 102D.

[0195] Timing diagram 1000 includes waveforms 1002, 1004a, 1004b, 1006a, 1006b, 1008a, 1008b, 1010a, and 1010b.

[0196] In some embodiments, waveform 1002 corresponds to a waveform having booster circuit 206d. Figure 2 The read global bit line RGBL during a read operation of the memory bank 110U of memory partition 102A. In some embodiments, waveform 1002 corresponds to a state without booster circuit 206d. Figure 8A or Figure 8B The global bit line RGBL is read during the read operation of the memory body 110U of the memory partition 102B.

[0197] In some embodiments, waveform 1004a corresponds to the read global bit line RGBL during a read operation of the memory bank 110U of the memory partition 102B with boost circuit 206c, and waveform 1004b corresponds to the read global bit line RGBL during a read operation of the memory bank 110U of the memory partition 102B without boost circuit 206c.

[0198] In some embodiments, waveform 1006a corresponds to the read global bit line RGBL during a read operation of the memory bank 110U of the memory partition 102C having booster circuit 206b, and waveform 1006b corresponds to the read global bit line RGBL during a read operation of the memory bank 110U of the memory partition 102C without booster circuit 206b.

[0199] In some embodiments, waveform 1008a corresponds to the read global bit line RGBL during a read operation of a memory bank 110U with memory partition 102D having booster circuit 206a, and waveform 1008b corresponds to the read global bit line RGBL during a read operation of a memory bank 110U without booster circuit 206a.

[0200] In some embodiments, waveform 1010a corresponds to waveform 1008a at the GIO circuit 100BL, and waveform 1010b corresponds to waveform 1008a at the GIO circuit 100BL.

[0201] In some embodiments, waveforms 1002, 1004a, 1004b, 1006a, 1006b, 1008a, 1008b, 1010a, and 1010b correspond to a read "1" when reading the global bit line RGBL. In some embodiments, waveforms 1002, 1004a, 1004b, 1006a, 1006b, 1008a, 1008b, 1010a, and 1010b correspond to a read "0" when reading the global bit line RGBL.

[0202] At time Tl, waveform 1002 transitions from logic low to logic high, and since the read operation of memory bank 110U in memory partition 102A occurs before the read operation of memory bank 110U in memory partitions 102B-102D, the read of the global inverted bit line signal RGBLB' (e.g., shown as waveform 1002) is not corrupted by noise and resistive / capacitive load. In some embodiments, since waveform 1002 is not corrupted by noise and resistive / capacitive load, memory bank 110U in memory partition 102A can be configured without booster circuitry 206d.

[0203] At time T2, waveforms 1004a and 1004b transition from logic low to logic high. In some embodiments, by including a booster circuit 206c in the memory bank 110U in memory partition 102B, waveform 1004a transitions from logic low to logic high faster than waveform 1004b, resulting in a faster read operation than a method without booster circuit 206c.

[0204] At time T3, waveforms 1006a and 1006b transition from logic low to logic high. In some embodiments, by including a booster circuit 206b in the memory bank 110U in memory partition 102C, waveform 1006a transitions from logic low to logic high faster than waveform 1006b, resulting in a faster read operation than a method without booster circuit 206b.

[0205] At time T4, waveforms 1008a and 1008b transition from logic low to logic high. In some embodiments, by including a booster circuit 206a in the memory bank 110U in memory partition 102D, waveform 1008a transitions from logic low to logic high faster than waveform 1008b, resulting in a faster read operation than a method without booster circuit 206a.

[0206] At time T5, waveforms 1010a and 1010b transition from logic low to logic high.

[0207] At time T6, waveform 1002 changes from logic high to logic low.

[0208] At time T7, waveforms 1004a and 1004b transition from logic high to logic low. In some embodiments, by including a booster circuit 206c in the memory bank 110U in memory partition 102B, waveform 1004a transitions from logic high to logic low faster than waveform 1004b, resulting in a faster read operation than a method without booster circuit 206c.

[0209] At time T8, waveforms 1006a and 1006b transition from logic high to logic low. In some embodiments, by including a booster circuit 206b in the memory bank 110U in memory partition 102C, waveform 1006a transitions from logic high to logic low faster than waveform 1006b, resulting in a faster read operation than a method without booster circuit 206b.

[0210] At time T9, waveforms 1008a and 1008b transition from logic high to logic low. In some embodiments, by including a booster circuit 206a in the memory bank 110U in memory partition 102D, waveform 1008a transitions from logic high to logic low faster than waveform 1008b, resulting in a faster read operation than a method without booster circuit 206a.

[0211] At time T10, waveforms 1010a and 1010b transition from logic high to logic low.

[0212] In some embodiments, although timing diagram 1000 is described relative to memory bank 110U, timing diagram 1000 is also applied to memory bank 110L in a similar manner and is not described for the sake of brevity.

[0213] Other configurations of timing diagram 1000 are within the scope of this disclosure.

[0214] method

[0215] Figure 11 This is a flowchart of a method 1100 for operating circuits according to some embodiments.

[0216] In some embodiments, Figure 11 It is an operation Figure 1 Memory circuit 100 Figure 2 Memory circuit 200, Figure 4 Memory circuit 400, Figures 6-9 Memory circuits 600, 700, 800A, 800B, or 900, or Figure 3 A flowchart of a method for at least one of the memory units 300.

[0217] It should be understood that it is possible Figure 11 Additional operations are performed before, during, and / or after the method 1100 described herein, and some other operations are only briefly described here. It should be understood that method 1100 utilizes features of one or more of memory circuits 100, 200, 400, 600, 700, 800A, 800B, or 900 or memory cell 300, and similar detailed descriptions are omitted for brevity.

[0218] In some embodiments, the order of other operations of method 1100 is within the scope of this disclosure. Method 1100 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated in accordance with the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of method 1100 are not performed.

[0219] In operation 1102 of method 1100, a first memory cell is read at least in response to a sense amplifier signal SAE. In some embodiments, the first memory cell is read by an LIO circuit.

[0220] In some embodiments, the first memory cell includes at least one of the memory cells 112, or at least one or more memory cells in the memory cell arrays 210a, 210b or 110AR.

[0221] In some embodiments, the LIO circuit includes at least one of LIO circuit 110BS, LIO circuit 210BS, LIO circuit 402, LIO circuit 602, LIO circuit 702 or LIO circuit 802.

[0222] In some embodiments, operation 1102 includes at least one of operations 1104, 1106, 1108, or 1110.

[0223] In operation 1104 of method 1100, at least the first bit line signal and the second bit line signal are sensed in response to the sense amplifier signal.

[0224] In some embodiments, the first bit line signal includes the inverted bit line signal RBLB, and the second bit line signal includes the bit line signal RBL. In some embodiments, the second bit line signal includes the inverted bit line signal RBLB, and the first bit line signal includes the bit line signal RBL.

[0225] In some embodiments, the sense amplifier 420 senses the first bit line signal and the second bit line signal. In some embodiments, the sense amplifier is coupled to the first memory cell.

[0226] In operation 1106 of method 1100, an inverted second bit line signal is generated in response to the second bit line signal.

[0227] In some embodiments, the inverted second bit line signal includes at least the inverted bit line signal RBLN. In some embodiments, the inverted second bit line signal corresponds to the first bit line signal.

[0228] In some embodiments, the inverted second bit line signal is generated by the first inverter. In some embodiments, the first inverter includes at least inverter I3. In some embodiments, the first inverter is coupled to a sense amplifier.

[0229] In operation 1108 of method 1100, the global bit line signal is set in response to at least the first bit line signal or the inverted second bit line signal.

[0230] In some embodiments, the global bit line signal is on the global bit line. In some embodiments, the global bit line signal includes reading the global bit line signal RGBL' or reading the global inverted bit line signal RGBLB'. In some embodiments, the global bit line includes reading the global bit line RGBL or reading the global inverted bit line RGBLB.

[0231] In some embodiments, the global bit line signal is set by driver circuitry 430. In some embodiments, driver circuitry is coupled to the global bit line, a sense amplifier, and a first inverter.

[0232] In operation 1110 of method 1100, the rising or falling edge of the global bit line signal is adjusted in response to the delayed global bit line signal.

[0233] In some embodiments, the delayed global bitline signal includes at least signal S2.

[0234] In some embodiments, the rising or falling edge of the global bit line signal is adjusted by a booster circuit. In some embodiments, the booster circuit includes at least one of booster circuits 206a, 206b, 206c, 206d, 406, 606, 706, or 806.

[0235] In some embodiments, operation 1110 includes method 1200 ( Figure 12 At least one of operations 1202, 1204, 1206 or 1208 (as shown).

[0236] In operation 1112 of method 1100, in response to a global bit line signal, a first value of at least data stored in a first memory cell is output.

[0237] In some embodiments, the first value of the data stored in the first memory cell is output by the GIO circuit 100BL. In some embodiments, the first value of the data stored in the first memory cell is output by the GIO circuit 404. In some embodiments, the GIO circuit is coupled to a global bit line. In some embodiments, the first value of the data stored in the first memory cell is logic 1 or logic 0.

[0238] Figure 12 This is a flowchart of a method 1200 for operating circuits according to some embodiments.

[0239] In some embodiments, method 1200 is Figure 1 The implementation of method 1100 and operation 1110 are described in detail below for the sake of brevity.

[0240] In some embodiments, Figure 12 It is an operation Figure 1 Memory circuit 100 Figure 2In the memory circuit 200, Figure 4 Memory circuit 400, Figures 6-9 Memory circuits 600, 700, 800A, 800B or 900 or Figure 3 A flowchart of a method for at least one memory unit 300.

[0241] It should be understood that it is possible Figure 12 Additional operations are performed before, during, and / or after the method 1200 described herein, and some other operations are only briefly described here. It is understood that method 1200 utilizes features of one or more of memory circuits 100, 200, 400, 600, 700, 800A, 800B, or 900 or memory cell 300, and similar detailed descriptions are omitted for brevity.

[0242] In some embodiments, the order of other operations of method 1200 is within the scope of this disclosure. Method 1200 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated in accordance with the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of method 1200 are not performed.

[0243] In operation 1202 of method 1200, a second signal is generated in response to the global bit line signal.

[0244] In some embodiments, the second signal includes the signal RGBL' or RGBLB'.

[0245] In some embodiments, the second signal is generated by the first inverter. In some embodiments, the first inverter includes inverter I1. In some embodiments, the first inverter is coupled to a global bit line.

[0246] In operation 1204 of method 1200, a second signal with a delay is generated in response to the second signal.

[0247] In some embodiments, the delayed second signal includes signal S1.

[0248] In some embodiments, the delayed second signal is generated by a delay circuit. In some embodiments, the delay circuit includes at least one of delay circuits 410, 610, or 710, or conductive path 412. In some embodiments, the delay circuit is coupled to a first inverter.

[0249] In operation 1206 of method 1200, a third signal is generated in response to the delayed second signal.

[0250] In some embodiments, the third signal includes signal S2. In some embodiments, the third signal corresponds to a delayed global bitline signal.

[0251] In some embodiments, a third signal is generated by a second inverter. In some embodiments, the second inverter includes inverter I2. In some embodiments, the second inverter is coupled to a delay circuit.

[0252] In operation 1208 of method 1200, the rising or falling edge of the global bit line signal is adjusted in response to the third and second signals.

[0253] In some embodiments, the rising or falling edge of the global bit line signal is adjusted in response to a transition in the global bit line signal or the global inverse bit line signal caused by the driver circuit 402.

[0254] In some embodiments, the rising or falling edge of the global bit line signal is adjusted by a feedback circuit. In some embodiments, the feedback circuit includes at least one of feedback circuits 416 or 816. In some embodiments, the feedback circuit includes at least one of PMOS transistor MP1, PMOS transistor MP2, NMOS transistor MN1, NMOS transistor MN2, or NMOS transistor MN4. In some embodiments, the feedback circuit is coupled between the second inverter and the global bit line.

[0255] Although methods 1100 and 1200 are described with respect to the global bit line GBL and the global bit line signal GBL', at least one of methods 1100 or 1200 is similarly applicable to the global inverted bit line GBLB and the global inverted bit line signal GBLB', and similar detailed descriptions are omitted for brevity.

[0256] The circuit operates to achieve the above-mentioned... through at least one of operation methods 1100 or 1200. Figure 1 Memory circuit 100 Figure 2 Memory circuit 200, Figure 4 Memory circuit 400, Figures 6-9 Memory circuits 600, 700, 800A, 800B or 900 or Figure 3 The benefits discussed in at least one of the memory cells 300.

[0257] In some embodiments, one or more of the operations of at least one of methods 1100 or 1200 are not performed. Furthermore, Figure 1 , Figure 2 , Figures 3-4 and Figures 6-8B The various PMOS or NMOS transistors shown have specific dopant types (e.g., N-type or P-type) for illustrative purposes. The embodiments of this disclosure are not limited to specific transistor types. Figure 1 , Figure 2 , Figures 3-4 and Figures 6-8B One or more of the PMOS or NMOS transistors shown can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are for illustrative purposes only. The embodiments of this disclosure are not limited to specific logic values ​​when signals are activated and / or deactivated. Different logic values ​​are chosen within the range of various embodiments. Figures 3-4 and Figures 6-8B Different numbers of inverters or buffers can be selected within a range of various embodiments. Figures 3-4 and Figures 6-8B Different numbers of transistors are selected within a range of various embodiments. Figures 3-12 Different numbers of delay circuits are selected within the range of various embodiments.

[0258] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to influence various modifications, substitutions of equivalents, and various other embodiments widely disclosed herein. Therefore, the protection granted herein is intended to be limited only to the definitions contained in this disclosure and its equivalents.

[0259] One aspect of this description relates to a memory circuit. The memory circuit includes a group of memory cells configured to store data, and local input / output (LIO) circuitry coupled to a global bit line and the group of memory cells. The LIO circuitry includes a sense amplifier, a driver circuit, and a booster circuit. The sense amplifier is configured to sense a first signal at least in response to a sense amplifier signal. The first signal corresponds to the value of data stored in the group of memory cells. The driver circuitry is configured to generate a global bit line signal at least in response to the first signal or an inverted first signal. The booster circuitry is coupled to the driver circuitry and the global bit line and is configured to adjust the global bit line signal in response to a delayed global bit line signal. In some embodiments, the booster circuitry further includes a first inverter configured to generate a second signal in response to the global bit line signal, the first inverter including a first input terminal coupled to the global bit line and a first output terminal. In some embodiments, the booster circuitry further includes a delay circuit coupled to the first output terminal of the first inverter and configured to generate a delayed second signal in response to the second signal. In some embodiments, the booster circuit further includes a second inverter configured to generate a third signal in response to a delayed second signal. The second inverter includes a second input terminal and a second output terminal, the second input terminal being coupled to the output terminal of the delay circuit, and the third signal corresponding to a delayed global bit line signal. In some embodiments, the booster circuit further includes a feedback circuit coupled between the second output terminal of the second inverter and the global bit line, and configured to adjust the global bit line signal in response to the third signal and the second signal. In some embodiments, the feedback circuit further includes a first P-type transistor having a first source coupled to a first supply voltage, a first gate of the first P-type transistor configured to receive the third signal and coupled to the second output terminal of the second inverter, and a first drain of the first P-type transistor coupled to at least a first node. In some embodiments, the feedback circuit further includes a second P-type transistor having a second source coupled to the first drain of the first P-type transistor and the first node, a second gate of the second P-type transistor configured to receive the second signal and coupled to the first output terminal of the first inverter, and a second drain of the second P-type transistor coupled to at least the global bit line via a second node. In some embodiments, the feedback circuit further includes a first N-type transistor having a third source coupled to at least a third node, the third gate of the first N-type transistor being configured to receive a second signal and coupled to a first output terminal of a first inverter and a second gate of a second P-type transistor, and the third drain of the first N-type transistor being coupled to at least the second drain of the second P-type transistor, a global bit line, and a second node.In some embodiments, the feedback circuit further includes a second N-type transistor having a fourth source coupled to at least a fourth node, the fourth gate of the second N-type transistor being configured to receive a third signal and coupled to a second output terminal of a second inverter and a first gate of a first P-type transistor, and the fourth drain of the second N-type transistor being coupled to a third source of the first N-type transistor and a third node. In some embodiments, the feedback circuit further includes a third N-type transistor having a fifth source coupled to a reference supply voltage, the fifth gate of the third N-type transistor being configured to receive a sense amplifier signal, and the fifth drain of the third N-type transistor being coupled to a fourth source of the second N-type transistor and a fourth node. In some embodiments, the fourth source and fourth node of the second N-type transistor are coupled to a reference supply voltage. In some embodiments, the delay circuit includes a third inverter configured to generate a first intermediate signal in response to a second signal, the third inverter including a third input terminal coupled to a first output terminal of the first inverter and a third output terminal. In some embodiments, the delay circuit further includes a fourth inverter configured to generate a delayed second signal in response to a first intermediate signal. The fourth inverter includes a fourth input terminal coupled to a third output terminal of a third inverter and a fourth output terminal coupled to a second input terminal of a second inverter. In some embodiments, the delay circuit includes a first buffer configured to generate a delayed second signal in response to a second signal. The first buffer includes a third input terminal coupled to a first output terminal of a first inverter and a third output terminal coupled to a second input terminal of a second inverter. In some embodiments, the memory circuit further includes a global input / output (GIO) circuit coupled to the LIO circuit and a global bit line, and configured to output the value of data stored in a memory cell of a memory cell group in response to a global bit line signal. In some embodiments, the GIO circuit includes a first inverter configured to generate the value of data stored in a memory cell in response to a global bit line signal. The first inverter includes a first input terminal coupled to a global bit line and a first output terminal configured to output the value of data stored in the memory cell. In some embodiments, the GIO circuit further includes a latch circuit configured to latch a global bit line signal in response to at least an enable signal and coupled to the global bit line and a first inverter. In some embodiments, the latch circuit includes a second inverter configured to generate a first intermediate signal in response to the global bit line signal. The second inverter includes a second input terminal coupled to the global bit line and a second output terminal configured to output the first intermediate signal. In some embodiments, the latch circuit further includes a third inverter configured to generate a latched global bit line signal in response to the first intermediate signal. The third inverter includes a third input terminal coupled to the second output terminal of the second inverter, a first enable terminal configured to receive an enable signal, a second enable terminal configured to receive an inverted enable signal, and a third output terminal coupled to the first input terminal of the first inverter.

[0260] Another aspect of this specification relates to memory circuitry. Memory circuitry includes a global bit line, a group of memory cells including a first memory cell, and global input / output (GIO) circuitry. In some embodiments, the first memory cell includes a first group of memory cells configured to store data, and a first local input / output (LIO) circuit coupled to the global bit line and the first group of memory cells. In some embodiments, the first LIO circuitry includes a first driver circuit and a first booster circuit. In some embodiments, the first driver circuit is coupled to the global bit line and configured to adjust the global bit line signal in response to at least a first signal. In some embodiments, the first signal corresponds to a first value of data stored in the first memory cell of the first group of memory cells. In some embodiments, the first booster circuit is coupled to the global bit line and configured to adjust the rising or falling edge of the global bit line signal in response to a first-delayed global bit line signal. In some embodiments, the GIO circuitry is coupled to the first LIO circuitry and the global bit line and configured to output the first value of data stored in the first memory cell of the first group of memory cells in response to the global bit line signal. In some embodiments, the first LIO circuit further includes a first sense amplifier coupled to the first driver circuit and configured to sense a first bit line signal and a second bit line signal in response to at least a first sense amplifier signal, the first signal corresponding to either the first bit line signal or the second bit line signal. In some embodiments, the first LIO circuit further includes a first inverter coupled to the first sense amplifier and the first driver circuit, configured to generate an inverted second bit line signal in response to the second bit line signal, the inverted second bit line signal corresponding to the first bit line signal. In some embodiments, the memory bank group further includes a second memory bank separated from the first memory bank in a first direction. In some embodiments, the second memory bank includes a second set of memory cells configured to store data. In some embodiments, the second memory bank further includes a second LIO circuit coupled to the global bit line and the second set of memory cells. In some embodiments, the second LIO circuit includes a second driver circuit coupled to the global bit line and configured to adjust the global bit line signal in response to at least a third bit line signal, the third bit line signal corresponding to a first value of data stored in the first memory cell of the second set of memory cells. In some embodiments, the second LIO circuit further includes a second sense amplifier coupled to the second driver circuit and configured to sense a third bit line signal and a fourth bit line signal in response to at least a second sense amplifier signal. In some embodiments, the second LIO circuit further includes a second inverter coupled to the second sense amplifier and the second driver circuit, and is configured to generate an inverted fourth bit line signal in response to the fourth bit line signal, the inverted fourth bit line signal corresponding to the third bit line signal.In some embodiments, a first memory bank is located adjacent to the GIO circuit; a second memory bank is located adjacent to a first end of the memory circuit opposite to the GIO circuit; the second LIO circuit does not include a booster circuit. In some embodiments, the second LIO circuit further includes a second booster circuit coupled to a global bit line and configured to adjust the rising or falling edge of the global bit line signal in response to a second delayed global bit line signal. In some embodiments, the first memory bank is located adjacent to the GIO circuit; and the second memory bank is located adjacent to a first end of the memory circuit opposite to the GIO circuit. In some embodiments, the first booster circuit includes a first inverter configured to generate a second signal in response to a global bit line signal, the first inverter including a first input terminal and a first output terminal coupled to the global bit line. In some embodiments, the first booster circuit further includes a delay circuit coupled to the first output terminal of the first inverter and configured to generate a delayed second signal in response to the second signal. In some embodiments, the first booster circuit further includes a second inverter configured to generate a third signal in response to the delayed second signal, the second inverter including a second input terminal and a second output terminal, the second input terminal coupled to the output terminal of the delay circuit, the third signal corresponding to the first delayed global bit line signal. In some embodiments, the first booster circuit further includes a feedback circuit coupled between the second output terminal of the second inverter and the global bit line, and configured to adjust the rising or falling edge of the global bit line signal in response to the third signal and the second signal. In some embodiments, the delay circuit includes a third inverter configured to generate a first intermediate signal in response to the second signal, the third inverter including a third input terminal coupled to the first output terminal of the first inverter and a third output terminal. In some embodiments, the delay circuit further includes a fourth inverter configured to generate a delayed second signal in response to the first intermediate signal, the fourth inverter including a fourth input terminal coupled to the third output terminal of the third inverter and a fourth output terminal coupled to the second input terminal of the second inverter. In some embodiments, the delay circuit includes a first buffer configured to generate a delayed second signal in response to the second signal, the first buffer including a third input terminal coupled to the first output terminal of the first inverter and a third output terminal coupled to the second input terminal of the second inverter.

[0261] Another aspect of this specification relates to a method of operating a memory circuit. The method includes reading a first memory cell via a local input / output (LIO) circuit in response to at least a sense amplifier signal, and outputting a first value of data stored in the first memory cell via a global input / output (GIO) circuit in response to a global bit line signal, the GIO circuit being coupled to a global bit line. In some embodiments, reading the first memory cell includes sensing a first bit line signal and a second bit line signal via a sense amplifier in response to at least a sense amplifier signal, the sense amplifier being coupled to the first memory cell. In some embodiments, reading the first memory cell further includes generating an inverted second bit line signal via a first inverter in response to a second bit line signal, the inverted second bit line signal corresponding to the first bit line signal, the first inverter being coupled to the sense amplifier. In some embodiments, reading the first memory cell further includes setting a global bit line signal on a global bit line via a driver circuit in response to at least the first bit line signal or the inverted second bit line signal, the driver circuit being coupled to the global bit line, the sense amplifier, and the first inverter. In some embodiments, reading the first memory cell further includes adjusting the rising or falling edge of the global bit line signal via a booster circuit in response to a delayed global bit line signal.

[0262] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A memory circuit, comprising: A group of memory cells is configured to store data; as well as Local input / output circuitry, coupled to the global bit line and the memory cell group, the local input / output circuitry comprising: A sensing amplifier is configured to sense a first signal in response to at least a sensing amplifier signal, the first signal corresponding to the value of the data stored in the memory cell group; The driver circuitry is configured to generate a global bit line signal in response to at least the first signal or its inverted form; and A booster circuit, coupled to the driver circuit and the global bit line, is configured to adjust the global bit line signal in response to a delayed global bit line signal. The booster circuit includes: A first inverter is configured to generate a second signal in response to the global bit line signal, the first inverter including a first input terminal and a first output terminal coupled to the global bit line; A delay circuit, coupled to the first output terminal of the first inverter, and configured to generate a delayed second signal in response to the second signal; and A second inverter is configured to generate a third signal in response to the delayed second signal. The second inverter includes a second input terminal and a second output terminal. The second input terminal is coupled to the output terminal of the delay circuit. The third signal corresponds to the global bit line signal of the delay.

2. The memory circuit according to claim 1, wherein, The booster circuit also includes: A feedback circuit is coupled between the second output terminal of the second inverter and the global bit line, and is configured to adjust the global bit line signal in response to the third signal and the second signal.

3. The memory circuit according to claim 2, wherein, The feedback circuit includes: A first P-type transistor has a first source coupled to a first supply voltage, a first gate of the first P-type transistor is configured to receive the third signal and coupled to the second output terminal of the second inverter, and a first drain of the first P-type transistor is coupled to at least a first node. The second P-type transistor has a second source coupled to the first drain and the first node of the first P-type transistor, the second gate of the second P-type transistor is configured to receive the second signal and coupled to the first output terminal of the first inverter, and the second drain of the second P-type transistor is coupled to the global bit line through the second node. A first N-type transistor has a third source coupled to at least a third node, a third gate of the first N-type transistor configured to receive the second signal and coupled to the first output terminal of the first inverter and the second gate of the second P-type transistor, and a third drain of the first N-type transistor coupled to at least the second drain of the second P-type transistor, the global bit line, and the second node; and The second N-type transistor has a fourth source coupled to at least a fourth node, the fourth gate of the second N-type transistor is configured to receive the third signal and coupled to the second output terminal of the second inverter and the first gate of the first P-type transistor, and the fourth drain of the second N-type transistor is coupled to the third source of the first N-type transistor and the third node.

4. The memory circuit according to claim 3, wherein, The feedback circuit also includes: The third N-type transistor has a fifth source coupled to a reference supply voltage, the fifth gate of the third N-type transistor is configured to receive the sense amplifier signal, and the fifth drain of the third N-type transistor is coupled to the fourth source and the fourth node of the second N-type transistor.

5. The memory circuit according to claim 3, wherein, The fourth source and the fourth node of the second N-type transistor are coupled to a reference supply voltage.

6. The memory circuit according to claim 2, wherein, The delay circuit includes: A third inverter, configured to generate a first intermediate signal in response to the second signal, includes a third input terminal and a third output terminal coupled to the first output terminal of the first inverter; and A fourth inverter is configured to generate the delayed second signal in response to the first intermediate signal. The fourth inverter includes a fourth input terminal coupled to the third output terminal of the third inverter and a fourth output terminal coupled to the second input terminal of the second inverter.

7. The memory circuit according to claim 2, wherein, The delay circuit includes: A first buffer is configured to generate the delayed second signal in response to the second signal. The first buffer includes a third input terminal coupled to the first output terminal of the first inverter and a third output terminal coupled to the second input terminal of the second inverter.

8. The memory circuit according to claim 1, further comprising: A global input / output circuit, coupled to the local input / output circuit and the global bit line, is configured to output the value of the data stored in the memory cells of the memory cell group in response to the global bit line signal.

9. The memory circuit according to claim 8, wherein, The global input / output circuit includes: A third inverter, configured to generate the value of the data stored in the memory cell in response to the global bit line signal, the third inverter including a third input terminal coupled to the global bit line and a third output terminal configured to output the value of the data stored in the memory cell; and A latch circuit is configured to latch the global bit line signal in response to at least an enable signal and is coupled to the global bit line and the third inverter.

10. The memory circuit according to claim 9, wherein, The latching circuit includes: A fourth inverter, configured to generate a first intermediate signal in response to the global bit line signal, includes a fourth input terminal coupled to the global bit line and a fourth output terminal configured to output the first intermediate signal; and The fifth inverter is configured to generate a latched global bit line signal in response to the first intermediate signal. The fifth inverter includes a fifth input terminal coupled to the fourth output terminal of the fourth inverter, a first enable terminal configured to receive the enable signal, a second enable terminal configured to receive an inverted enable signal, and a fifth output terminal coupled to the third input terminal of the third inverter.

11. A memory circuit, comprising: Global bitline; The memory bank group includes a first memory bank, the first memory bank comprising: The first set of memory cells is configured to store data; and A first local input / output circuit is coupled to the global bit line and the first group of memory cells, and the first local input / output circuit includes: A first driver circuit, coupled to the global bit line, is configured to adjust the global bit line signal at least in response to a first signal corresponding to a first value of the data stored in a first memory cell within the first set of memory cells; and A first booster circuit, coupled to the global bit line, and configured to adjust the rising or falling edge of the global bit line signal in response to a first delayed global bit line signal; and A global input / output circuit, coupled to the first local input / output circuit and the global bit line, is configured to output the first value of the data stored in the first memory cell of the first set of memory cells in response to the global bit line signal. The first booster circuit includes: A first inverter is configured to generate a second signal in response to the global bit line signal, the first inverter including a first input terminal and a first output terminal coupled to the global bit line; A delay circuit is coupled to the first output terminal of the first inverter and configured to generate a delayed second signal in response to the second signal; A second inverter is configured to generate a third signal in response to the second delayed signal. The second inverter includes a second input terminal and a second output terminal. The second input terminal is coupled to the output terminal of the delay circuit. The third signal corresponds to the first delayed global bit line signal.

12. The memory circuit according to claim 11, wherein, The first partial input / output circuit further includes: A first sensing amplifier, coupled to the first driver circuit, and configured to sense at least a first bit line signal and a second bit line signal in response to a first sensing amplifier signal, the first signal corresponding to either the first bit line signal or the second bit line signal; and A third inverter, coupled to the first sense amplifier and the first driver circuit, is configured to generate an inverted second bit line signal in response to the second bit line signal, the inverted second bit line signal corresponding to the first bit line signal.

13. The memory circuit according to claim 12, wherein, The memory bank group further includes: A second memory bank is separated from the first memory bank in a first direction, wherein the second memory bank includes: The second set of memory units is configured to store the data; and A second local input / output circuit is coupled to the global bit line and the second group of memory cells. The second local input / output circuit includes: A second driver circuit is coupled to the global bit line and configured to adjust the global bit line signal in response to at least a third bit line signal, the third bit line signal corresponding to a first value of the data stored in a first memory cell of the second set of memory cells; A second sensing amplifier, coupled to the second driver circuit, is configured to sense at least the third bit line signal and the fourth bit line signal in response to a second sensing amplifier signal; and A fourth inverter is coupled to the second sense amplifier and the second driver circuit, and is configured to generate an inverted fourth bit line signal in response to the fourth bit line signal, the inverted fourth bit line signal corresponding to the third bit line signal.

14. The memory circuit according to claim 13, wherein, The first memory bank is located adjacent to the global input / output circuit. The second memory bank is located adjacent to the first end of the memory circuit opposite to the global input / output circuit; and The second local input / output circuit does not include a booster circuit.

15. The memory circuit according to claim 13, wherein, The second partial input / output circuit also includes: A second booster circuit is coupled to the global bit line and configured to adjust the rising or falling edge of the global bit line signal in response to a global bit line signal with a second delay.

16. The memory circuit according to claim 15, wherein, The first memory bank is located adjacent to the global input / output circuit; and The second memory bank is located adjacent to the first end of the memory circuit opposite to the global input / output circuit.

17. The memory circuit according to claim 11, wherein, The first booster circuit also includes: A feedback circuit is coupled between the second output terminal of the second inverter and the global bit line, and is configured to adjust the rising or falling edge of the global bit line signal in response to the third signal and the second signal.

18. The memory circuit according to claim 17, wherein, The delay circuit includes: A third inverter, configured to generate a first intermediate signal in response to the second signal, includes a third input terminal and a third output terminal coupled to the first output terminal of the first inverter; and A fourth inverter is configured to generate the delayed second signal in response to the first intermediate signal, the fourth inverter including a fourth input terminal coupled to the third output terminal of the third inverter and a fourth output terminal coupled to the second input terminal of the second inverter.

19. The memory circuit according to claim 17, wherein, The delay circuit includes: A first buffer is configured to generate the delayed second signal in response to the second signal. The first buffer includes a third input terminal coupled to the first output terminal of the first inverter and a third output terminal coupled to the second input terminal of the second inverter.

20. A method of operating a memory circuit, the method comprising: Reading a first memory cell via a local input / output circuit in response to at least a sensing amplifier signal, wherein reading the first memory cell includes: The first bit line signal and the second bit line signal are sensed by a sensing amplifier in response to a sensing amplifier signal, the sensing amplifier being coupled to the first memory cell; A first inverter generates an inverted second bit line signal in response to the second bit line signal, the inverted second bit line signal corresponding to the first bit line signal, and the first inverter is coupled to the sense amplifier. A global bit line signal is set on the global bit line by a driver circuit that is at least responsive to the first bit line signal or the inverted second bit line signal, the driver circuit being coupled to the global bit line, the sense amplifier, and the first inverter; and The rising or falling edge of the global bit line signal is adjusted by a booster circuit in response to a delayed global bit line signal; and A global input / output circuit, in response to the global bit line signal, outputs a first value of the data stored in the first memory cell, wherein the global input / output circuit is coupled to the global bit line. The booster circuit includes: A first inverter is configured to generate a first signal in response to the global bit line signal, the first inverter including a first input terminal and a first output terminal coupled to the global bit line; A delay circuit, coupled to the first output terminal of the first inverter, and configured to generate a delayed first signal in response to the first signal; and A second inverter is configured to generate a second signal in response to a first signal of the delay. The second inverter includes a second input terminal and a second output terminal. The second input terminal is coupled to the output terminal of the delay circuit. The second signal corresponds to a global bit line signal of the delay.

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