Misadjustment cancellation circuit, charge management chip and charger

Abstract

The present disclosure provides a kind of imbalance elimination circuit, charging management chip and charger, in the imbalance elimination circuit, its input stage can respond to the frequency control of timing control signal, the differential input port of equivalent operational amplifier (error amplifier) to operational amplifier (error amplifier) is controlled to be equivalent to operational amplifier (error amplifier) by the level conversion of timing control signal, and bias current is output as first current and second current;Its output stage can control the first current and second current follow the level conversion of timing control signal, utilize the frequency control of timing control signal to be equivalent to the differential input port of operational amplifier (error amplifier) to operational amplifier (error amplifier) to generate output voltage in the mean value of the output voltage of the timing control signal period, equivalent operational amplifier (error amplifier) is added and offset after voltage, and the output voltage is used to drive the on charging path of charging management chip, so operational amplifier (error amplifier) voltage can be eliminated, thereby improve charging current precision, reduce power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to an offset cancellation circuit, a charging management chip, and a charger. Background Technology

[0002] A power bank is a portable charger that integrates power supply and charging functions. Like electronic products, it has undergone various developments over the years, and the core charging and discharging chip of the power bank is constantly being upgraded and evolved, with the best being replaced by the best. As mobile devices tend to have larger screens but are also thinner and lighter, they consume more power. When users are out for extended periods, the battery capacity of these devices becomes insufficient. Traditional 5V USB adapters, due to their limited output capacity, can no longer meet today's fast charging and discharging needs, and various fast charging solutions are constantly emerging in the market.

[0003] In existing charging management chips (such as the BQ25895 charging chip), charging the battery requires controlling a built-in transistor (batfet) with charging current detection function. A common approach is to maintain a constant system power supply voltage and then use an error comparator to compare the actual charging current (ichg) with the charging reference (vref_ichg) to dynamically adjust the batfet's gate voltage, thereby regulating the charging current.

[0004] Input offset voltage is an important electrical parameter of a voltage comparator. It is defined as the DC compensation voltage applied between the two input terminals to achieve a specified output voltage. The input offset voltage reflects the symmetry of the comparator's internal circuitry; better symmetry results in a smaller input offset voltage. The presence of comparator circuit offset significantly affects the precise comparison of small signals. Therefore, circuit techniques are needed to compensate for or eliminate it to achieve accurate comparison and signal processing.

[0005] Traditional charging management chips use error comparators, which have the disadvantage of high offset voltage. This results in low accuracy of the charging current and affects the chip performance. Summary of the Invention

[0006] To address the aforementioned technical problems, this disclosure provides an offset cancellation circuit, a charging management chip, and a charger.

[0007] On the one hand, this disclosure provides an offset cancellation circuit for a charging management chip, which includes:

[0008] The input stage has a first input terminal connected to a first voltage signal and a second input terminal connected to a first reference voltage signal. The input stage responds to the frequency control of the timing control signal to convert the operational amplifier offset to the differential input port of the operational amplifier, and responds to the level conversion of the aforementioned timing control signal to mirror the bias current into a first current and a second current.

[0009] The output stage has a third input terminal connected to the battery output port of the charging management chip and a fourth input terminal for receiving a second voltage signal. This output stage follows the level shifts of the timing control signal and generates an output voltage that eliminates the aforementioned operational amplifier offset based on the first and second currents.

[0010] The aforementioned first voltage signal represents the actual battery charging current of the charging management chip, the aforementioned first reference voltage signal represents the preset battery charging current of the charging management chip, and the aforementioned output voltage is used to drive the charging path of the charging management chip to be turned on.

[0011] Furthermore, the aforementioned timing control signals include a first timing signal and a second timing signal that are inverses of each other, and the aforementioned input stage includes:

[0012] A first chopper switch, wherein the first input terminal of the first chopper switch is connected to the aforementioned first voltage signal, the second input terminal is connected to the aforementioned first reference voltage signal, and the first control terminal of the first chopper switch is connected to the aforementioned first timing signal, and the second control terminal is connected to the aforementioned second timing signal;

[0013] An error amplifier, the differential input ports of which are respectively connected to the first output terminal and the second output terminal of the aforementioned first chopper switch.

[0014] Furthermore, the aforementioned first chopper switch includes:

[0015] A first switch and a second switch, wherein the first end of the first switch serves as the aforementioned first output terminal and the second end serves as the aforementioned first input terminal, and the control terminal of the first switch is connected to the control terminal of the second switch and serves as the aforementioned first control terminal, and the first end of the second switch serves as the aforementioned second output terminal and the second end serves as the aforementioned second input terminal;

[0016] The third switch and the fourth switch are connected in the following ways: the first end of the third switch is connected to the first end of the second switch, the second end is connected to the second end of the first switch, and the control terminal is connected to the control terminal of the fourth switch and serves as the second control terminal. The first end of the fourth switch is connected to the first end of the first switch, and the second end is connected to the second end of the second switch.

[0017] Furthermore, the aforementioned error amplifier includes:

[0018] A first transistor and a second transistor are connected together, with the first terminal of the first transistor and the first terminal of the second transistor being connected together. The connection node of the first transistor and the second transistor are connected in series to the third transistor and the fourth transistor to the power supply terminal, and the power supply voltage is applied. The control terminal of the first transistor serves as the first differential input port of the aforementioned error amplifier and is connected to the first terminal of the aforementioned second transistor. The control terminal of the second transistor serves as the second differential input port of the aforementioned error amplifier and is connected to the first terminal of the aforementioned first transistor.

[0019] The second terminal of the first transistor is connected in series with the fifth and sixth transistors to ground, and the second terminal of the fifth transistor is connected to the control terminal of the aforementioned sixth transistor.

[0020] The second terminal of the second transistor is connected in series with the seventh and eighth transistors to ground. The second terminal of the seventh transistor is connected to the control terminal of the aforementioned eighth transistor, and the control terminal of the fifth transistor is connected to the control terminal of the aforementioned seventh transistor.

[0021] Furthermore, the aforementioned input level also includes:

[0022] A first resistor, a ninth transistor, and a tenth transistor. The first end of the first resistor is connected to the aforementioned bias current, and the second end of the first resistor is connected in series with the ninth and tenth transistors to ground. The control terminal of the ninth transistor is connected to the first end of the aforementioned first resistor and is also connected to the control terminal of the aforementioned seventh transistor. The control terminal of the tenth transistor is connected to the connection node of the aforementioned first resistor and the aforementioned ninth transistor.

[0023] The eleventh transistor and the twelfth transistor are connected together to the first terminal of the first resistor.

[0024] The thirteenth transistor and the fourteenth transistor have their first terminals connected to ground. The control terminal of the thirteenth transistor is connected to the control terminal of the aforementioned twelfth transistor, and the control terminal of the fourteenth transistor is connected to the control terminal of the aforementioned sixth transistor.

[0025] Furthermore, the aforementioned input level also includes:

[0026] The second chopper switch has its fifth input terminal connected to the second terminal of the aforementioned thirteenth transistor, its sixth input terminal connected to the second terminal of the aforementioned fourteenth transistor, its third output terminal connected to the first terminal of the aforementioned eleventh transistor, its fourth output terminal connected to the first terminal of the aforementioned twelfth transistor, and its third control terminal connected to the aforementioned second timing signal, and its fourth control terminal connected to the aforementioned first timing signal.

[0027] Furthermore, the aforementioned second chopper switch includes:

[0028] The fifth and sixth switching transistors, the first end of the fifth switching transistor serves as the aforementioned fifth input terminal, the second end serves as the aforementioned fourth output terminal, the control terminal is connected together with the control terminal of the aforementioned sixth switching transistor and serves as the aforementioned third control terminal, the first end of the sixth switching transistor serves as the aforementioned sixth input terminal, the second end serves as the aforementioned third output terminal;

[0029] The seventh and eighth switches are connected as follows: the first end of the seventh switch is connected to the first end of the aforementioned fifth switch, the second end is connected to the second end of the aforementioned sixth switch, and the control terminal is connected together with the control terminal of the aforementioned eighth switch and serves as the aforementioned fourth control terminal. The first end of the eighth switch is connected to the first end of the aforementioned sixth switch, and the second end is connected to the second end of the aforementioned fifth switch.

[0030] Furthermore, the aforementioned input level also includes:

[0031] The fifteenth transistor, the sixteenth transistor, and the second resistor are connected in series. The first terminal of the fifteenth transistor is connected to the first terminal of the aforementioned fourth transistor, and the control terminal is connected to the control terminal of the aforementioned fourth transistor. The second terminal of the fifteenth transistor is connected to the aforementioned sixteenth transistor and the aforementioned second resistor in series. The connection node of the sixteenth transistor and the aforementioned second resistor is connected to the control terminal of the aforementioned fifteenth transistor. The control terminal of the aforementioned sixteenth transistor is connected to the control terminal of the aforementioned third transistor.

[0032] The seventeenth transistor and the eighteenth transistor, the first terminal of the seventeenth transistor is connected to the aforementioned second resistor, the second terminal is connected in series with the aforementioned eighteenth transistor to ground, the control terminal is connected to the control terminal of the aforementioned seventh transistor, and the control terminal of the eighteenth transistor is connected to the control terminal of the aforementioned tenth transistor.

[0033] Furthermore, the aforementioned input level also includes:

[0034] The nineteenth transistor and the twentieth transistor are connected together. The first terminal of the nineteenth transistor is connected to the second terminal of the eleventh transistor. The second terminal is used to output the first current. The control terminal of the twentieth transistor and the control terminal of the twentieth transistor are connected to the power supply terminal. The first terminal of the twentieth transistor is connected to the second terminal of the twelfth transistor. The second terminal is used to output the second current.

[0035] Furthermore, the aforementioned output stage includes:

[0036] The third resistor, the twenty-first transistor, and the twenty-second transistor are connected in series. The first end of the third resistor is connected to the second end of the nineteenth transistor and the control terminal of the twenty-first transistor. The second end of the third resistor is connected in series with the twenty-first transistor and the twenty-second transistor to the fourth input terminal. The connection node between the third resistor and the twenty-first transistor is connected to the control terminal of the twenty-second transistor.

[0037] The 23rd transistor and the 24th transistor are connected in series between the fourth input terminal and the output terminal of the offset cancellation circuit. The control terminal of the 23rd transistor is connected to the control terminal of the 22nd transistor, and the control terminal of the 24th transistor is connected to the control terminal of the 21st transistor.

[0038] The 25th transistor and the 26th transistor are connected in series between the second terminal of the 24th transistor and the third input terminal, and the connection node of the 24th transistor and the 25th transistor serves as the output terminal of the offset cancellation circuit to provide the output voltage.

[0039] Furthermore, the aforementioned output stage also includes:

[0040] The fourth resistor, the twenty-seventh transistor, and the twenty-eighth transistor are provided. The first end of the fourth resistor is connected to the second end of the aforementioned twentyth transistor and the control terminal of the twenty-seventh transistor. The second end of the aforementioned fourth resistor is connected in series with the aforementioned twenty-seventh transistor and the aforementioned twenty-eighth transistor to the aforementioned fourth input terminal. The connection node between the aforementioned fourth resistor and the aforementioned twenty-seventh transistor is connected to the control terminal of the aforementioned twenty-eighth transistor.

[0041] The twenty-ninth transistor and the thirtieth transistor, wherein the control terminal of the twenty-ninth transistor is connected to the control terminal of the aforementioned twenty-eighth transistor, and the control terminal of the aforementioned thirtieth transistor is connected to the control terminal of the aforementioned twenty-seventh transistor.

[0042] The fifth resistor, the thirty-first transistor, and the thirty-second transistor are connected in series. The first end of the fifth resistor is connected to the second end of the aforementioned thirty-first transistor and the control end of the thirty-first transistor. The control end of the aforementioned thirty-first transistor is connected to the control end of the aforementioned twenty-fifth transistor. The second end of the aforementioned fifth resistor is connected in series with the aforementioned thirty-first transistor and the aforementioned thirty-second transistor to the aforementioned third input terminal. The connection node of the fifth resistor and the aforementioned thirty-first transistor is connected to the control end of the aforementioned thirty-second transistor. The control end of the thirty-second transistor is connected to the control end of the aforementioned twenty-sixth transistor.

[0043] Furthermore, the aforementioned input level also includes:

[0044] The nineteenth transistor and the twentieth transistor are connected together. The first terminal of the nineteenth transistor is connected to the second terminal of the eleventh transistor. The second terminal is used to output the first current. The control terminal of the twentieth transistor and the control terminal of the twentieth transistor are connected to the power supply terminal. The first terminal of the twentieth transistor is connected to the second terminal of the twelfth transistor. The second terminal is used to output the second current.

[0045] Furthermore, the aforementioned output stage includes:

[0046] The third resistor, the twenty-first transistor, and the twenty-second transistor are connected in series. The first end of the third resistor is connected to the second end of the nineteenth transistor and the control terminal of the twenty-first transistor. The second end of the third resistor is connected in series with the twenty-first transistor and the twenty-second transistor to the fourth input terminal. The connection node between the third resistor and the twenty-first transistor is connected to the control terminal of the twenty-second transistor.

[0047] The 23rd transistor and the 24th transistor are connected in series between the fourth input terminal and the output terminal of the offset cancellation circuit. The control terminal of the 23rd transistor is connected to the control terminal of the 22nd transistor, and the control terminal of the 24th transistor is connected to the control terminal of the 21st transistor.

[0048] The sixth resistor, the twenty-fifth transistor, and the twenty-sixth transistor are connected in series with the twenty-fourth transistor via the first end of the sixth resistor as the sixth input terminal and the twenty-fifth transistor and the twenty-sixth transistor via the second end as the fourth output terminal. The resistor is connected in series with the twenty-fifth transistor and the twenty-sixth transistor to the third input terminal.

[0049] Furthermore, the aforementioned output stage also includes:

[0050] The fourth resistor, the twenty-seventh transistor, and the twenty-eighth transistor are provided. The first end of the fourth resistor is connected to the second end of the aforementioned twentyth transistor and the control terminal of the twenty-seventh transistor. The second end of the aforementioned fourth resistor is connected in series with the aforementioned twenty-seventh transistor and the aforementioned twenty-eighth transistor to the aforementioned fourth input terminal. The connection node between the fourth resistor and the aforementioned twenty-seventh transistor is connected to the control terminal of the aforementioned twenty-eighth transistor.

[0051] The twenty-ninth transistor and the thirtieth transistor, the control terminal of the twenty-ninth transistor is connected to the control terminal of the aforementioned twenty-eighth transistor, and the control terminal of the thirtieth transistor is connected to the control terminal of the aforementioned twenty-seventh transistor;

[0052] The fifth resistor, the thirty-first transistor, and the thirty-second transistor are connected in series with the first end of the fifth resistor as the fifth input terminal and the third end as the third output terminal. The control terminal of the thirty-first transistor is connected to the control terminal of the twenty-fifth transistor, and the control terminal of the thirty-second transistor is connected to the control terminal of the twenty-sixth transistor.

[0053] Furthermore, the aforementioned timing control signals also include a third timing signal and a fourth timing signal that are inverses of each other, and the aforementioned output stage also includes:

[0054] The second chopper switch has its fifth input terminal connected to the first terminal of the aforementioned fifth resistor, its sixth input terminal connected to the first terminal of the aforementioned sixth resistor, its third output terminal connected to the second terminal of the aforementioned fifth resistor, its fourth output terminal connected to the second terminal of the aforementioned sixth resistor, and its third control terminal connected to the aforementioned third timing signal, its fourth control terminal connected to the aforementioned fourth timing signal, and provides the aforementioned output voltage through the output node.

[0055] Furthermore, the aforementioned second chopper switch includes:

[0056] The fifth switch and the sixth switch, the first end of the fifth switch serves as the aforementioned fifth input terminal, the second end is connected to the second end of the aforementioned sixth switch, and the connection node of the two is connected to the control terminal of the aforementioned thirty-first transistor. The control terminal of the fifth switch serves as the aforementioned third control terminal, the first end of the sixth switch serves as the aforementioned sixth input terminal, and the control terminal of the sixth switch serves as the aforementioned fourth control terminal.

[0057] The seventh and eighth switching transistors, the first end of the seventh switching transistor serves as the aforementioned third output terminal, the second end of the seventh switching transistor is connected to the second end of the aforementioned eighth switching transistor, and the connection node of the two is connected to the control terminal of the aforementioned thirty-second transistor. The control terminal of the seventh switching transistor is connected to the aforementioned third control terminal. The first end of the eighth switching transistor serves as the aforementioned fourth output terminal, and the control terminal of the aforementioned eighth switching transistor is connected to the aforementioned fourth control terminal.

[0058] The ninth and tenth switches are connected as follows: the first end of the ninth switch is connected to the aforementioned fifth input terminal, the second end of the ninth switch is connected to the second end of the aforementioned tenth switch, and the connection node of the two switches serves as the aforementioned output node to provide the aforementioned output voltage. The control terminal of the tenth switch is connected to the control terminal of the aforementioned eighth switch. The first end of the tenth switch is connected to the aforementioned sixth input terminal, and the control terminal of the tenth switch is connected to the control terminal of the aforementioned seventh switch.

[0059] Furthermore, the aforementioned offset cancellation circuit also includes:

[0060] A level conversion unit is connected to the aforementioned third input terminal, the aforementioned fourth input terminal, and the power supply terminal, respectively, and is used to generate the aforementioned third timing signal and the aforementioned fourth timing signal based on the aforementioned second voltage signal and the battery voltage, and to generate the aforementioned first timing signal and the aforementioned second timing signal based on the aforementioned power supply voltage and the reference ground voltage.

[0061] Furthermore, the aforementioned offset cancellation circuit also includes:

[0062] The charge pump has its input terminal serving as the aforementioned third input terminal, connected to the battery output port of the aforementioned charging management chip, and its output terminal serving as the aforementioned fourth input terminal, used to provide the aforementioned second voltage signal after DC regulation.

[0063] Furthermore, the duty cycle of the aforementioned first timing signal and the aforementioned second timing signal is 50%.

[0064] Furthermore, the duty cycle of the aforementioned first timing signal and the aforementioned second timing signal is 50%, the duty cycle of the aforementioned third timing signal and the aforementioned fourth timing signal is 50%, and the period of the aforementioned first timing signal and the aforementioned third timing signal is the same.

[0065] Furthermore, the average voltage provided during the aforementioned timing control signal period is the aforementioned output voltage after offset elimination.

[0066] On the other hand, this disclosure also provides a charging management chip, which includes:

[0067] Power transistors; and

[0068] As described above, the offset cancellation circuit has its output terminal connected to the control terminal of the aforementioned power transistor. It is used to provide an output voltage after offset cancellation during the timing control signal period. The aforementioned output voltage is used to drive the charging path connected by the aforementioned power transistor to conduct.

[0069] On the other hand, this disclosure also provides a charger, which includes:

[0070] The charging management chip as described above.

[0071] This disclosure provides an offset cancellation circuit, a charging management chip, and a charger. In the offset cancellation circuit, its input stage can respond to frequency control of a timing control signal to equate the operational amplifier offset to the differential input port of the operational amplifier, and respond to level shifts of the timing control signal to mirror the bias current into a first current and a second current. Its output stage can follow the level shifts of the timing control signal to generate an output voltage that cancels the operational amplifier offset, based on the aforementioned first current and the aforementioned second current. This output voltage is used to drive the charging path of the charging management chip. By using the average value of the output voltage within a period of the timing control signal to superimpose and cancel the equivalent operational amplifier offset voltage, the operational amplifier offset voltage can be eliminated, thereby improving the charging current accuracy and reducing power consumption. Attached Figure Description

[0072] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0073] Figure 1 A circuit block diagram of an offset cancellation circuit for a charging management chip provided in an embodiment of this disclosure is shown.

[0074] Figure 2 Show Figure 1 The circuit diagram shown is a circuit structure diagram of the offset cancellation circuit in the first embodiment.

[0075] Figure 3 Show Figure 2 The circuit structure diagram of the first chopper switch in the offset cancellation circuit shown;

[0076] Figure 4 Show Figure 2 The circuit diagram of the second chopper switch in the offset cancellation circuit shown;

[0077] Figure 5 Show Figure 1 The circuit diagram shown is a circuit structure diagram of the offset cancellation circuit in the second embodiment.

[0078] Figure 6 Show Figure 5 The circuit structure diagram of the first chopper switch in the offset cancellation circuit shown;

[0079] Figure 7 Show Figure 5 The circuit diagram of the second chopper switch in the offset cancellation circuit shown;

[0080] Figure 8 Show Figure 5 A schematic diagram of the level conversion unit in the offset cancellation circuit shown in the embodiment;

[0081] Figure 9Show Figure 8 The diagram shows the waveforms of the timing signals output by the level conversion unit.

[0082] Figure 10a A schematic block diagram of the charging management chip provided in an embodiment of this disclosure is shown.

[0083] Figure 10b Show Figure 10a A partial structural diagram of the charging control module. Detailed Implementation

[0084] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the contents of this disclosure.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0086] The present disclosure will now be described in detail with reference to the accompanying drawings.

[0087] Figure 1 This diagram shows a circuit block diagram of an offset cancellation circuit for a charging management chip provided in an embodiment of the present disclosure. Figure 2 Show Figure 1 The circuit diagram shown is a circuit structure diagram of the offset cancellation circuit in the first embodiment. Figure 3 Show Figure 2 The circuit diagram shown is of the first chopper switch in the offset cancellation circuit. Figure 4 Show Figure 2 The circuit diagram of the second chopper switch in the offset cancellation circuit is shown.

[0088] refer to Figure 1 This disclosure provides an offset cancellation circuit 100 for a charging management chip, comprising:

[0089] Input stage 110 has a first input terminal A connected to a first voltage signal ichg and a second input terminal B connected to a first reference voltage signal Vref_ichg. Input stage 110 responds to frequency control of timing control signals to convert operational amplifier offset to the differential input port of the operational amplifier, and responds to level conversion of the aforementioned timing control signals (including at least the first timing signal Clk and the second timing signal clkb) to mirror the bias current Ibn into a first current Ia and a second current Ib.

[0090] Output stage 120 has a third input terminal connected to the battery output port BAT of the aforementioned charging management chip and a fourth input terminal connected to the second voltage signal VPUMP. Output stage 120 follows the level shift of the aforementioned timing control signal and generates an output voltage BATDRV that eliminates the aforementioned operational amplifier offset based on the aforementioned first current Ia and second current Ib.

[0091] The first voltage signal ichg represents the actual battery charging current of the aforementioned charging management chip, the first reference voltage signal Vref_ichg represents the preset battery charging current of the aforementioned charging management chip, and the output voltage BATDRV is used to drive the charging path of the charging management chip to be turned on.

[0092] Further reference Figure 2 and Figure 3 In the first embodiment of this example, the aforementioned timing control signals include a first timing signal Clk and a second timing signal Clkb that are inverses of each other. The input stage 110 includes:

[0093] A first chopper switch 111 has a first input terminal A connected to a first voltage signal ichg, a second input terminal B connected to a first reference voltage signal Vref_ichg, and a first control terminal connected to a first timing signal Clk, and a second control terminal connected to a second timing signal Clkb.

[0094] Error amplifier 112, the differential input ports of which are respectively connected to the first output terminal C and the second output terminal D of the first chopper switch 111.

[0095] refer to Figure 3 In this embodiment, the first chopper switch 111 includes:

[0096] The first switch MS2 and the second switch MS3 are as follows: the first terminal of the first switch MS2 is the first output terminal C, the second terminal is the first input terminal A, and the control terminal is connected to the control terminal of the second switch MS3 and serves as the aforementioned first control terminal. The first terminal of the second switch MS3 is the second output terminal D, and the second terminal is the second input terminal B.

[0097] The third switch MS1 and the fourth switch MS4 are connected together. The first end of the third switch MS1 is connected to the first end of the second switch MS3, and the second end is connected to the second end of the first switch MS2. The control terminal of the third switch MS1 is connected to the control terminal of the fourth switch MS4 and serves as the aforementioned second control terminal. The first end of the fourth switch MS4 is connected to the first end of the first switch MS2, and the second end is connected to the second end of the second switch MS3.

[0098] Furthermore, in this embodiment, the error amplifier 112 includes:

[0099] The first transistor MP1 and the second transistor MP2 are connected together, with their first terminals connected in series to the third transistor MP6 and the fourth transistor MP5, which are connected to the power supply terminal and supplied with the power supply voltage VDDA. The control terminal of the first transistor MP1 serves as the first differential input port of the error amplifier 112 and is connected to the first terminal of the second switch MS3. The control terminal of the second transistor MP2 serves as the second differential input port of the error amplifier 112 and is connected to the first terminal of the first switch MS2.

[0100] The second terminal of the first transistor MP1 is connected in series with the fifth transistor MN9 and the sixth transistor MN7 to ground. The second terminal of the fifth transistor MN9 is connected to the control terminal of the sixth transistor MN7.

[0101] The second terminal of the second transistor MP2 is connected in series with the seventh transistor MN10 and the eighth transistor MN8 to ground. The second terminal of the seventh transistor MN10 is connected to the control terminal of the eighth transistor MN8, and the control terminal of the fifth transistor MN9 is connected to the control terminal of the seventh transistor MN10.

[0102] Further reference Figure 2 and Figure 4 In this embodiment, the input stage 110 further includes:

[0103] The first resistor R1, the ninth transistor MN2, and the tenth transistor MN1 are connected in series with the first terminal of the first resistor R1 to the aforementioned bias current Ibn, and the second terminal of the first resistor R1 is connected in series with the ninth transistor MN2 and the tenth transistor MN1 to ground. The control terminal of the ninth transistor MN2 is connected to the first terminal of the first resistor R1 and is connected to the control terminal of the seventh transistor MN10. The control terminal of the tenth transistor MN1 is connected to the connection node of the first resistor R1 and the ninth transistor MN2.

[0104] The eleventh transistor MN4 and the twelfth transistor MN6 are connected together to the first terminal of the first resistor R1.

[0105] The thirteenth transistor MN3 and the fourteenth transistor MN5 are connected together to ground, and the control terminal of the thirteenth transistor MN3 is connected to the control terminal of the twelfth transistor MN6, and the control terminal of the fourteenth transistor MN5 is connected to the control terminal of the sixth transistor MN7.

[0106] The second chopper switch 113 has its fifth input terminal E connected to the second terminal of the thirteenth transistor MN3, its sixth input terminal F connected to the second terminal of the fourteenth transistor MN5, its third output terminal G connected to the first terminal of the eleventh transistor MN4, its fourth output terminal H connected to the first terminal of the twelfth transistor MN6, and its third control terminal connected to the aforementioned second timing signal Clkb, and its fourth control terminal connected to the aforementioned first timing signal Clk.

[0107] Further reference Figure 4 In this embodiment, the second chopper switch 113 includes:

[0108] The fifth switch MS6 and the sixth switch MS7 are connected together. The first terminal of the fifth switch MS6 is the fifth input terminal E, and the second terminal is the fourth output terminal H. The control terminal of the fifth switch MS6 is connected together with the control terminal of the sixth switch MS7 and serves as the aforementioned third control terminal. The first terminal of the sixth switch MS7 is the sixth input terminal F, and the second terminal is the third output terminal G.

[0109] The seventh switch MS5 and the eighth switch MS8 are connected. The first end of the seventh switch MS5 is connected to the first end of the fifth switch MS6, and the second end is connected to the second end of the sixth switch MS7. Its control end is connected together with the control end of the eighth switch MS8 and serves as the aforementioned fourth control end. The first end of the eighth switch MS8 is connected to the first end of the sixth switch MS3, and the second end is connected to the second end of the fifth switch MS6.

[0110] Further reference Figure 2 In this embodiment, the input stage 110 further includes:

[0111] The fifteenth transistor MP4, the sixteenth transistor MP3, and the second resistor R2 are connected in series. The first terminal of the fifteenth transistor MP4 is connected to the first terminal of the fourth transistor MP5, and its control terminal is connected to the control terminal of the fourth transistor MP5. The second terminal of the fifteenth transistor MP4 is connected to the sixteenth transistor MP3 and the second resistor R2 in series. The connection node of the sixteenth transistor MP3 and the second resistor R2 is connected to the control terminal of the fifteenth transistor MP4. The control terminal of the sixteenth transistor MP3 is connected to the control terminal of the aforementioned third transistor MP6.

[0112] The seventeenth transistor MN12 and the eighteenth transistor MN11 are connected in series with the eighteenth transistor MN11 to ground. The first terminal of the seventeenth transistor MN12 is connected to the second resistor R2, and the second terminal is connected to the eighteenth transistor MN11 to ground. Its control terminal is connected to the control terminal of the seventh transistor MN10. The control terminal of the eighteenth transistor MN11 is connected to the control terminal of the tenth transistor MN1.

[0113] Furthermore, in this embodiment, the input stage 110 also includes:

[0114] The nineteenth transistor MC1 and the twentieth transistor MC2 are connected. The first terminal of the nineteenth transistor MC1 is connected to the second terminal of the eleventh transistor MN4. The second terminal is used to output the aforementioned first current Ia. Its control terminal and the control terminal of the twentieth transistor MC2 are connected to the power supply terminal. The first terminal of the twentieth transistor MC2 is connected to the second terminal of the twelfth transistor MN6. The second terminal is used to output the aforementioned second current Ib.

[0115] Further reference Figure 2 In this embodiment, the output stage 120 includes:

[0116] The third resistor R3, the twenty-first transistor MP11, and the twenty-second transistor MP7 are connected in series. The first end of the third resistor R3 is connected to the second end of the nineteenth transistor MC1 and the control end of the twenty-first transistor MP11. The second end of the third resistor R3 is connected in series with the twenty-first transistor MP11 and the twenty-second transistor MP7 to the aforementioned fourth input end. The connection node between the third resistor R3 and the twenty-first transistor MP11 is connected to the control end of the twenty-second transistor MP7.

[0117] The 23rd transistor MP8 and the 24th transistor MP12 are connected in series between the aforementioned fourth input terminal and the output terminal of the offset cancellation circuit 100. The control terminal of the 23rd transistor MP8 is connected to the control terminal of the 22nd transistor MP7, and the control terminal of the 24th transistor MP12 is connected to the control terminal of the 21st transistor MP11.

[0118] The twenty-fifth transistor MN16 and the twenty-sixth transistor MN14 are connected in series between the second terminal of the twenty-fourth transistor MP12 and the aforementioned third input terminal. The connection node of the twenty-fourth transistor MP12 and the twenty-fifth transistor MN16 serves as the output terminal of the offset cancellation circuit 100, which is used to provide the output voltage BATDRV.

[0119] Furthermore, in this embodiment, the output stage 120 also includes:

[0120] The fourth resistor R4, the twenty-seventh transistor MP13, and the twenty-eighth transistor MP9 are connected in series. The first end of the fourth resistor R4 is connected to the second end of the twentieth transistor MC2 and the control end of the twenty-seventh transistor MP13. The second end of the fourth resistor R4 is connected in series with the twenty-seventh transistor MP13 and the twenty-eighth transistor MP9 to the aforementioned fourth input terminal. The connection node between the fourth resistor R4 and the twenty-seventh transistor MP13 is connected to the control end of the twenty-eighth transistor MP9.

[0121] The twenty-ninth transistor MP10 and the thirtieth transistor MP14 are connected to the control terminal of the twenty-eighth transistor MP9 and the control terminal of the thirtieth transistor MP14 is connected to the control terminal of the twenty-seventh transistor MP13.

[0122] The fifth resistor R5, the thirty-first transistor MN15, and the thirty-second transistor MN13 are connected together. The first end of the fifth resistor R5 is connected to the second end of the thirtieth transistor MP14 and the control end of the thirty-first transistor MN15. The control end of the thirty-first transistor MN15 is connected to the control end of the twenty-fifth transistor MN16. The second end of the fifth resistor R5 is connected in series with the thirty-first transistor MN15 and the thirty-second transistor MN13 to the aforementioned third input terminal. The connection node of the fifth resistor R5 and the thirty-first transistor MN15 is connected to the control end of the thirty-second transistor MN13. The control end of the thirty-second transistor MN13 is connected to the control end of the twenty-sixth transistor MN14.

[0123] Furthermore, in this embodiment, the output stage 120 of the offset cancellation circuit 100 further includes:

[0124] The charge pump 121 has its input terminal serving as the aforementioned third input terminal, connected to the battery output port of the charging management chip, and connected to the battery voltage BAT. The output terminal of the charge pump 121 serves as the aforementioned fourth input terminal, used to provide the second voltage signal VPUMP after DC regulation.

[0125] Furthermore, in this embodiment, the duty cycle of the aforementioned first timing signal Clk and the second timing signal Clkb is 50%, and the average voltage provided during the timing control signal period is the output voltage BATDRV after offset elimination.

[0126] Furthermore, in this embodiment, the first transistor MP1, the second transistor MP2, the third transistor MP6, the fourth transistor MP5, the fifth transistor MN9, the sixth transistor MN7, the seventh transistor MN10, the eighth transistor MN8, the ninth transistor MN2, the tenth transistor MN1, the eleventh transistor MN4, the twelfth transistor MN6, the thirteenth transistor MN3, the fourteenth transistor MN5, the fifteenth transistor MP4, the sixteenth transistor MP3, the seventeenth transistor MN12, the eighteenth transistor MN11, the nineteenth transistor MC1, the twentieth transistor MC2, the twenty-first transistor MP11, and the twentieth transistor MP2 are all transistors that are not ... The transistors MP7, MP8, MP12, MN16, MN14, MP13, MP9, MP10, MP14, MN15, MN13, MS2, MS3, MS1, MS4, MS6, MS7, MS5, and MS8 are all metal-oxide-semiconductor field-effect transistors (MOSFETs, hereinafter referred to as MOS transistors).

[0127] In this embodiment, the first transistor MP1, the second transistor MP2, the third transistor MP6, the fourth transistor MP5, the fifteenth transistor MP4, the sixteenth transistor MP3, the twenty-first transistor MP11, the twenty-second transistor MP7, the twenty-third transistor MP8, the twenty-fourth transistor MP12, the twenty-seventh transistor MP13, the twenty-eighth transistor MP9, the twenty-ninth transistor MP10, and the thirtieth transistor MP14 are all P-channel MOSFETs; and the fifth transistor MN9, the sixth transistor MN7, the seventh transistor MN10, the eighth transistor MN8, the ninth transistor MN2, and the tenth transistor MP14 are all P-channel MOSFETs. Transistor MN1, transistor MN4 (eleventh), transistor MN6 (twelfth), transistor MN3 (thirteenth), transistor MN5 (fourteenth), transistor MN12 (seventeenth), transistor MN11 (eighteenth), transistor MC1 (nineteenth), transistor MC2 (twentieth), transistor MN16 (twenty-fifth), transistor MN14 (twenty-sixth), transistor MN15 (thirty-first), transistor MN13 (thirty-second), and switching transistors MS2, MS3, MS1, MS4, MS6, MS7, MS5, and MS8 are all N-channel MOSFETs.

[0128] Combination Figure 10a and Figure 10b The offset cancellation circuit 100 is applied in the structural distribution of the charging management chip 10 (taking the BQ25895 charging chip as an example). We can understand that in existing technologies, the battery needs to be charged by controlling the power transistor battery (Q4). A common approach is to keep the voltage at the SYS system terminal constant, and then compare the actual charging current (ichg) with the charging reference (vref_ichg) using an error amplifier to dynamically adjust the gate voltage of Q4, thereby regulating the charging current. However, the error amplifier used in traditional methods has the disadvantage of high offset voltage, which results in low accuracy of the charging current and affects chip performance.

[0129] by Figure 2 Taking the offset cancellation circuit 100 in the illustrated embodiment as an example, in the input stage 110, the tenth transistor MN1, the ninth transistor MN2, the thirteenth transistor MN3, the eleventh transistor MN4, the eighteenth transistor MN11, and the seventeenth transistor MN12 form a first current mirror structure, the sixteenth transistor MP3, the fifteenth transistor MP4, the fourth transistor MP5, and the third transistor MP6 form a second current mirror structure, the first transistor MP1 and the second transistor MP2 are the input transistor pair of the error amplifier 112, the sixth transistor MN7, the eighth transistor MN8, the fifth transistor MN9, and the seventh transistor MN10 are the active loads of the error amplifier 112, and at the same time, the sixth transistor MN7, the fourteenth transistor MN5, the fifth transistor MN9, and the twelfth transistor MN6 can also form a third current mirror structure, and the nineteenth transistor MC1 and the twentieth transistor MC2 are high-voltage clamping transistors used to protect the MOS transistors below their source terminals.

[0130] In output stage 120, transistors MP7 (22nd), MP8 (23rd), MP11 (21st), and MP12 (24th) can form a fourth current mirror structure. Considering the overall circuit structure (ignoring the on-resistance of the switching transistors), transistors MP9 (28th), MP1 (1st), MN13 (32nd), and MP14 (30th) can also form a fifth current mirror structure. Furthermore, transistors MN13 (32nd), MN15 (31st), MN16 (25th), and MN14 (26th) can form a sixth current mirror structure. Resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5 are all resistors required for their respective current mirror structures. ibn is the bias current, VDDA is the supply voltage (e.g., 5V) connected to the power supply terminal, BAT is the battery voltage provided by the battery output port of the charging management chip 10, and the charge pump 121 connected to it outputs the second voltage signal VPUMP, so VPUMP = BAT + 5V; the output voltage BATDRV is connected to the gate of the power transistor (Q4); the first timing signal Clk and the second timing signal Clkb are clock signals that are inversely related and have a duty cycle of 50%. The offset cancellation circuit 100 provided in this embodiment is mainly applicable to N-channel MOS transistors (Q4), so when the output voltage BATDRV increases, the first voltage signal ichg will increase.

[0131] like Figure 2 As shown, the operational amplifier offset (voltage) mainly comes from the mismatch between the first transistor MP1 and the second transistor MP2, the mismatch between the sixth transistor MN7 and the eighth transistor MN8, and the mismatch between the fourteenth transistor MN5 and the sixth transistor MN7 and the thirteenth transistor MN3.

[0132] When the first timing signal Clk is high, the second timing signal Clkb is low. Therefore, the first switch MS2, the second switch MS3, the seventh switch MS5, and the eighth switch MS8 are turned on, while the third switch MS1, the fourth switch MS4, the fifth switch MS6, and the sixth switch MS7 are turned off. The first voltage signal ichg is connected to the control terminal of the second transistor MP2, and the first reference voltage signal Vref_ichg is connected to the control terminal of the first transistor MP1. The thirteenth transistor MN3 is connected to the eleventh transistor MN4, and the fourteenth transistor MN5 is connected to the twelfth transistor MN6. At this time, the control terminal of the second transistor MP2 is a negative input (i.e., when the gate voltage of the second transistor MP2 increases, the output voltage BATDRV decreases, thus causing the first voltage signal ichg to decrease), and the control terminal of the first transistor MP1 is a positive input.

[0133] When the first timing signal Clk is low, the second timing signal Clkb is high. Therefore, the first switch MS2, the second switch MS3, the seventh switch MS5, and the eighth switch MS8 are turned off, while the third switch MS1, the fourth switch MS4, the fifth switch MS6, and the sixth switch MS7 are turned on. The first voltage signal ichg is connected to the control terminal of the first transistor MP1, and the first reference voltage signal Vref_ichg is connected to the control terminal of the second transistor MP2. The thirteenth transistor MN3 is connected to the sixth transistor MN7, and the fourteenth transistor MN5 is connected to the eleventh transistor MN4. At this time, the control terminal of the first transistor MP1 is the negative input terminal, and the control terminal of the second transistor MP2 is the positive input terminal.

[0134] During operation, when the first timing signal Clk switches from high to low, the charging loop of the offset cancellation circuit 100 always maintains a negative feedback structure. The function of the first chopper switch 111 is to shift the frequency of the input signal from DC to the chopper (timing control signal) frequency, and the function of the second chopper switch 123 is to restore the frequency of the input signal from the chopper frequency back to DC, and to shift the operational amplifier offset from DC to the chopper frequency. The result is that the input signal remains unchanged after two chopping cycles, but the offset frequency is shifted from DC to the chopping frequency. Therefore, the mismatch generated by each MOS transistor in the range from the control terminals of the first transistor MP1 and the second transistor MP2 to the first terminal (source terminal) of the eleventh transistor MN4 and the twelfth transistor MN6 can be uniformly equivalent to the control terminal of the first transistor MP1. Assuming this mismatch is equivalent to a positive offset voltage vos at the gate terminal of the first transistor MP1, when the first timing signal Clk is high, since the control terminal of the first transistor MP1 is at a positive input, the output voltage BATDRV is: BATDRV = Video - vos. When the first timing signal Clk is low, since the control terminal of the first transistor MP1 is at a negative input, the output voltage BATDRV is: BATDRV = Video + vos. Since the duty cycle of the first timing signal Clk is 50%, the average value of the output voltage BATDRV over time is equal to Video, where Video is the output voltage BATDRV without any mismatch.

[0135] Therefore, the offset cancellation circuit 100 can eliminate operational amplifier offset (voltage), thereby improving the charging current accuracy of the charging management chip 10.

[0136] Figure 5 Show Figure 1 The circuit diagram shown is a circuit structure diagram of the offset cancellation circuit in the second embodiment. Figure 6 Show Figure 5 The circuit diagram shown is of the first chopper switch 111 in the offset cancellation circuit. Figure 7 Show Figure 5 The circuit diagram of the second chopper switch 113 in the offset cancellation circuit shown is shown. Figure 8 Show Figure 5 The schematic diagram of the level conversion unit in the offset cancellation circuit shown in the embodiment is as follows. Figure 9 Show Figure 8 The diagram shows the waveforms of the various timing signals output by the level conversion unit.

[0137] In this embodiment, its main circuit structure is as follows: Figure 5 As shown, for reference Figures 5-9 In the input stage 110 of the offset cancellation circuit 100, the circuit structure of the first chopper switch 111 and the error amplifier 112, as well as the structure of their auxiliary circuits, are the same as in the aforementioned embodiment, and will not be repeated here. The difference is:

[0138] The second chopper switch 122 is not located in the input stage 110, but is set on the high side of the output terminal of the output stage 120. At the same time, some branches of the output stage 120 are modified, but the working principle of the op-amp offset elimination of the two is similar. The above-mentioned beneficial effects can also be achieved by using the circuit structure in this embodiment.

[0139] Specifically, the structural changes of the offset cancellation circuit 100 in the output stage 120 are explained in detail:

[0140] refer to Figure 5 The output stage 120 includes:

[0141] The third resistor R3, the twenty-first transistor MP11, and the twenty-second transistor MP7 are connected in series. The first end of the third resistor R3 is connected to the second end of the nineteenth transistor MC1 and the control end of the twenty-first transistor MP11. The second end of the third resistor R3 is connected in series with the twenty-first transistor MP11 and the twenty-second transistor MP7 to the aforementioned fourth input end. The connection node between the third resistor R3 and the twenty-first transistor MP11 is connected to the control end of the twenty-second transistor MP7.

[0142] The 23rd transistor MP8 and the 24th transistor MP12 are connected in series between the aforementioned fourth input terminal and the output terminal of the offset cancellation circuit 100. The control terminal of the 23rd transistor MP8 is connected to the control terminal of the 22nd transistor MP7, and the control terminal of the 24th transistor MP12 is connected to the control terminal of the 21st transistor MP11.

[0143] The sixth resistor R6, the twenty-fifth transistor MN16, and the twenty-sixth transistor MN14 are connected in series with the second end of the sixth resistor R6 as the sixth input terminal H connected to MP12, and the second end as the fourth output terminal F connected in series with the twenty-fifth transistor MN16 and the twenty-sixth transistor MN14 to the aforementioned third input terminal.

[0144] Furthermore, in this embodiment, the output stage 120 also includes:

[0145] The fourth resistor R4, the twenty-seventh transistor MP13, and the twenty-eighth transistor MP9 are connected in series. The first end of the fourth resistor R4 is connected to the second end of the twentieth transistor MC2 and the control end of the twenty-seventh transistor MP13. The second end of the fourth resistor R4 is connected in series with the twenty-seventh transistor MP13 and the twenty-eighth transistor MP9 to the aforementioned fourth input terminal. The connection node between the fourth resistor R4 and the twenty-seventh transistor MP13 is connected to the control end of the twenty-eighth transistor MP9.

[0146] The twenty-ninth transistor MP10 and the thirtieth transistor MP14 are connected to the control terminal of the twenty-eighth transistor MP9 and the control terminal of the thirtieth transistor MP14 is connected to the control terminal of the twenty-seventh transistor MP13.

[0147] The fifth resistor R5, the thirty-first transistor MN15, and the thirty-second transistor MN13 are connected in series. The first end of the fifth resistor serves as the fifth input terminal G and is connected to the thirtieth transistor MP14. The second end serves as the third output terminal E and is connected in series with the thirty-first transistor MN15 and the thirty-second transistor MN13 to the aforementioned third input terminal. The control terminal of the thirty-first transistor MN15 is connected to the control terminal of the twenty-fifth transistor MN16, and the control terminal of the thirty-second transistor MN13 is connected to the control terminal of the twenty-sixth transistor MN14.

[0148] Furthermore, in this embodiment, the aforementioned timing control signals also include a third timing signal hClk and a fourth timing signal hClkb that are inverses of each other, and the output stage 120 further includes:

[0149] The second chopper switch 122 has its fifth input terminal G connected to the first terminal of the fifth resistor R5, its sixth input terminal H connected to the first terminal of the sixth resistor R6, its third output terminal E connected to the second terminal of the fifth resistor R5, its fourth output terminal F connected to the second terminal of the sixth resistor R6, and its third control terminal connected to the aforementioned third timing signal hClk, its fourth control terminal connected to the aforementioned fourth timing signal hClkb, and provides the aforementioned output voltage BATDRV through the output node.

[0150] Further reference Figure 7 In this embodiment, the second chopper switch 122 includes:

[0151] The fifth switch MS6 and the sixth switch MS9 are connected. The first terminal of the fifth switch MS6 is used as the fifth input terminal G, and the second terminal is connected to the second terminal of the sixth switch MS9. The connection node I of the two is connected to the control terminal of the thirty-first transistor MN15. The control terminal of the fifth switch MS6 is used as the aforementioned third control terminal. The first terminal of the sixth switch MS9 is used as the sixth input terminal H, and the control terminal of the sixth switch MS9 is used as the aforementioned fourth control terminal.

[0152] The seventh switch MS5 and the eighth switch MS8, the first terminal of the seventh switch MS5 is used as the third output terminal E, the second terminal is connected to the second terminal of the eighth switch MS8, and the connection node J of the two is connected to the control terminal of the thirty-second transistor MN13. The control terminal of the seventh switch MS5 is connected to the aforementioned third control terminal. The first terminal of the eighth switch MS8 is used as the fourth output terminal F, and the control terminal of the eighth switch MS8 is connected to the aforementioned fourth control terminal.

[0153] The ninth switch MS10 and the tenth switch MS7 are connected. The first terminal of the ninth switch is connected to the fifth input terminal G, and the second terminal is connected to the second terminal of the tenth switch MS7. The connection node of the two switches serves as the aforementioned output node to provide the output voltage BATDRV. Its control terminal is connected to the control terminal of the eighth switch MS8. The first terminal of the tenth switch MS7 is connected to the sixth input terminal H, and its control terminal is connected to the control terminal of the seventh switch MS5.

[0154] Further reference Figure 8 In this embodiment, the misalignment cancellation circuit 100 further includes:

[0155] A level conversion unit 130 is connected to the aforementioned third and fourth input terminals and the power supply terminal, respectively, and is respectively connected to the second voltage signal VPUMP, the battery voltage BAT, and the power supply voltage VDDA. The level conversion unit 130 is used to generate the aforementioned third timing signal hClk and fourth timing signal hClkb based on the second voltage signal VPUMP and the battery voltage BAT, and to generate the aforementioned first timing signal Clk and second timing signal Clkb based on the power supply voltage VDDA and the reference ground voltage GND. Specifically, the second timing signal clkb and the first timing signal clk are shifted from signals with a power supply range from VDDA to GND to the third timing signal hclk and the fourth timing signal hclkb with a power supply range from VPUMP to BAT.

[0156] Further reference Figure 5In this embodiment, the output stage 120 of the offset cancellation circuit 100 further includes:

[0157] The charge pump 121 has its input terminal serving as the aforementioned third input terminal, connected to the battery output port of the aforementioned charging management chip 10, and connected to the battery voltage BAT. The output terminal of the charge pump 121 serves as the aforementioned fourth input terminal, used to provide the second voltage signal VPUMP after DC voltage regulation.

[0158] Further reference Figure 9 In this embodiment, the duty cycle of the first timing signal Clk and the second timing signal Clkb is 50%, the duty cycle of the third timing signal hClk and the fourth timing signal hClkb is 50%, and the first timing signal Clk and the third timing signal hClk have the same period. The average voltage provided within the period of the timing control signal is the output voltage BATDRV after offset elimination.

[0159] Furthermore, in this embodiment, the first transistor MP1, the second transistor MP2, the third transistor MP6, the fourth transistor MP5, the fifth transistor MN9, the sixth transistor MN7, the seventh transistor MN10, the eighth transistor MN8, the ninth transistor MN2, the tenth transistor MN1, the eleventh transistor MN4, the twelfth transistor MN6, the thirteenth transistor MN3, the fourteenth transistor MN5, the fifteenth transistor MP4, the sixteenth transistor MP3, the seventeenth transistor MN12, the eighteenth transistor MN11, the nineteenth transistor MC1, the twentieth transistor MC2, the twenty-first transistor MP11, the twenty-second transistor MP7, and the second... The thirteenth transistor MP8, the twenty-fourth transistor MP12, the twenty-fifth transistor MN16, the twenty-sixth transistor MN14, the twenty-seventh transistor MP13, the twenty-eighth transistor MP9, the twenty-ninth transistor MP10, the thirtieth transistor MP14, the thirty-first transistor MN15, the thirty-second transistor MN13, the first switch MS2, the second switch MS3, the third switch MS1, the fourth switch MS4, the fifth switch MS6, the sixth switch MS9, the seventh switch MS5, the eighth switch MS8, the ninth switch MS10, and the tenth switch MS7 are all metal-oxide-semiconductor field-effect transistors (MOSFETs, hereinafter referred to as MOS transistors).

[0160] In this embodiment, the first transistor MP1, the second transistor MP2, the third transistor MP6, the fourth transistor MP5, the fifteenth transistor MP4, the sixteenth transistor MP3, the twenty-first transistor MP11, the twenty-second transistor MP7, the twenty-third transistor MP8, the twenty-fourth transistor MP12, the twenty-seventh transistor MP13, the twenty-eighth transistor MP9, the twenty-ninth transistor MP10, and the thirtieth transistor MP14 are all P-channel MOSFETs; and the fifth transistor MN9, the sixth transistor MN7, the seventh transistor MN10, the eighth transistor MN8, the ninth transistor MN2, the tenth transistor MN1, and the eleventh transistor MP14 are all P-channel MOSFETs. Transistors MN4, MN6, MN3, MN5, MN12, MN11, MC1, MC2, MN16, MN14, MN15, MN13, MS2, MS3, MS1, MS4, MS6, MS9, MS5, MS8, MS10, and MS7 are all N-channel MOSFETs.

[0161] like Figure 5 As shown, in the input stage 110, the tenth transistor MN1, the ninth transistor MN2, the thirteenth transistor MN3, the eleventh transistor MN4, the eighteenth transistor MN11, and the seventeenth transistor MN12 form the first current mirror structure. The sixteenth transistor MP3, the fifteenth transistor MP4, the fourth transistor MP5, and the third transistor MP6 form the second current mirror structure. The first transistor MP1 and the second transistor MP2 are the input transistor pairs of the error amplifier 112. The sixth transistor MN7, the eighth transistor MN8, the fifth transistor MN9, and the seventh transistor MN10 are the active loads of the error amplifier 112. At the same time, the sixth transistor MN7, the fourteenth transistor MN5, the fifth transistor MN9, and the twelfth transistor MN6 can also form the third current mirror structure. The nineteenth transistor MC1 and the twentieth transistor MC2 are high-voltage clamping transistors used to protect the MOS transistors below their source terminals.

[0162] In output stage 120, transistors MP7 (22nd), MP8 (23rd), MP11 (21st), and MP12 (24th) can form a fourth current mirror structure. Considering the overall circuit structure (ignoring the on-resistance of the switching transistors), transistors MP9 (28th), MP1 (1st), MN13 (32nd), and MP14 (30th) can also form a fifth current mirror structure. Transistors MN13 (32nd), MN15 (31st), MN16 (25th), and MN14 (26th) can also form a sixth current mirror structure. The first resistor is R1, the second resistor is R2, the third resistor is R3, and the fourth resistor is R4. The fifth resistor R5 and the sixth resistor R6 are the resistors required for their corresponding current mirror structures. ibn is the bias current, VDDA is the supply voltage (e.g., 5V) connected to the power supply terminal, and BAT is the battery voltage provided by the battery output port of the charging management chip 10. The charge pump 121 connected to it outputs the second voltage signal VPUMP, so VPUMP = BAT + 5V. The output voltage BATDRV is connected to the gate of the power transistor (Q4). The first timing signal Clk and the second timing signal Clkb are clock signals that are inversely related and have a duty cycle of 50%. The third timing signal hClk and the fourth timing signal hClkb are clock signals that are inversely related and have a duty cycle of 50%. The first timing signal Clk and the third timing signal hClk are in phase. The offset cancellation circuit 100 provided in this embodiment is mainly applicable to N-channel MOS transistors (Q4). Therefore, when the output voltage BATDRV increases, the first voltage signal ichg will increase.

[0163] like Figure 5 As shown, the operational amplifier offset (voltage) mainly comes from the mismatch between the first transistor MP1 and the second transistor MP2, the mismatch between the sixth transistor MN7 and the eighth transistor MN8, the mismatch between the fourteenth transistor MN5 and the sixth transistor MN7 and the thirteenth transistor MN3, the mismatch between the twenty-second transistor MP7 and the twenty-first transistor MP11, the twenty-third transistor MP8 and the twenty-fourth transistor MP12, the mismatch between the twenty-eighth transistor MP9 and the thirty-second transistor MN13, the twenty-ninth transistor MP10 and the thirtieth transistor MP14, and the mismatch between the thirty-second transistor MN13 and the thirty-first transistor MN15, the twenty-sixth transistor MN14 and the twenty-fifth transistor MN16.

[0164] When the first timing signal Clk is high, the second timing signal Clkb is low. Therefore, the first switch MS2, the second switch MS3, the seventh switch MS5, the fifth switch MS6, and the tenth switch MS7 are closed and conducting, while the third switch MS1, the fourth switch MS4, the eighth switch MS8, the sixth switch MS9, and the ninth switch MS10 are turned off. The first voltage signal ichg is connected to the control terminal of the second transistor MP2, and the first reference voltage signal Vref_ichg is connected to the control terminal of the first transistor MP1. The thirteenth transistor MN3 and the thirty-first transistor MN15 are connected as the mirror source of the current mirror. The output voltage BATDRV is output from the second terminal (drain terminal) node of the twenty-fourth transistor MP12. At this time, the control terminal of the second transistor MP2 is a negative input terminal (i.e., when the gate voltage of the second transistor MP2 increases, the output voltage BATDRV decreases, thereby causing the first voltage signal ichg to decrease), and the control terminal of the first transistor MP1 is a positive input terminal.

[0165] When the first timing signal Clk is low, the second timing signal Clkb is high. Therefore, the first switch MS2, the second switch MS3, the seventh switch MS5, the fifth switch MS6, and the tenth switch MS7 are turned off, while the third switch MS1, the fourth switch MS4, the eighth switch MS8, the sixth switch MS9, and the ninth switch MS10 are turned on. The first voltage signal ichg is connected to the control terminal of the first transistor MP1, and the first reference voltage signal Vref_ichg is connected to the control terminal of the second transistor MP2. The twenty-fifth transistor MN16 and the twenty-sixth transistor MN14 are connected as the source of the current mirror. The output voltage BATDRV is output from the second terminal (drain terminal) node of the thirtieth transistor MP14. At this time, the control terminal of the first transistor MP1 is the negative input terminal, and the control terminal of the second transistor MP2 is the positive input terminal.

[0166] During operation, when the first timing signal Clk switches from high to low, the charging loop of the offset cancellation circuit 100 always maintains a negative feedback structure. The function of the first chopper switch 111 is to shift the frequency of the input signal from DC to the chopper (timing control signal) frequency, and the function of the second chopper switch 123 is to restore the frequency of the input signal from the chopper frequency back to DC, and to shift the operational amplifier offset from DC to the chopper frequency. The result is that the input signal remains unchanged after two chopping cycles, but the offset frequency is shifted from DC to the chopping frequency. Therefore, the mismatch generated by each MOS transistor from the control terminal of the first transistor MP1 to the output node can be uniformly equated to the control terminal of the first transistor MP1. Assuming this mismatch is equivalent to a positive offset voltage vos at the gate terminal of the first transistor MP1, when the first timing signal Clk is high, since the control terminal of the first transistor MP1 is at a positive input, the output voltage BATDRV is: BATDRV = Video - vos. When the first timing signal Clk is low, since the control terminal of the first transistor MP1 is at a negative input, the output voltage BATDRV is: BATDRV = Video + vos. Since the duty cycle of the first timing signal Clk is 50%, the average value of the output voltage BATDRV over time is equal to Video, where Video is the output voltage BATDRV without any mismatch.

[0167] Therefore, the offset cancellation circuit 100 can eliminate operational amplifier offset (voltage), thereby improving the charging current accuracy of the charging management chip 10.

[0168] In summary, the offset cancellation circuit 100 provided in this embodiment has an input stage 110 that responds to the frequency control of a timing control signal to convert the operational amplifier offset to the differential input port of the operational amplifier (error amplifier 112), and responds to the level shift of the timing control signal to mirror the bias current Ibn into a first current Ia and a second current Ib. Its output stage 120 can control the first current Ia and the second current Ib to follow the level shift of the timing control signal. The average value of the output voltage of the timing control signal within the period is used to superimpose and cancel the equivalent operational amplifier offset voltage to generate an output voltage BATDRV. The output voltage BATDRV is used to drive the charging path of the charging management chip 10, thereby eliminating the operational amplifier offset voltage, improving the charging current accuracy, and reducing power consumption.

[0169] Figure 10a This diagram shows a schematic block diagram of the charging management chip provided in an embodiment of the present disclosure. Figure 10b Show Figure 10a A partial structural diagram of the charging control module.

[0170] refer to Figure 10a and Figure 10b This disclosure also provides a charging management chip 10. In this embodiment, the charging management chip 10 takes the BQ25895 charging chip as an example, and its simplified circuit working principle is as follows: Figure 10a As shown, the circuit structure of the charging control module 200, which connects the system terminal SYS, the battery terminal BAT, and the enable / reset terminal QON inside the chip, is illustrated in the figure below. Figure 10b As shown, it may include:

[0171] Power transistor Q4 (BATFET); and

[0172] As described in the foregoing embodiment, the offset cancellation circuit 100 has its output terminal connected to the control terminal of the power transistor Q4. It is used to provide an offset-cancelled output voltage BATDRV during the timing control signal period. The output voltage BATDRV is used to drive the charging path connected by the power transistor Q4 to conduct.

[0173] On the other hand, this disclosure also provides a charger (not shown), which may include: a charging management chip 10 as described in the above embodiments.

[0174] It should be noted that, in the description of this disclosure, the terms "upper," "lower," "inner," etc., which indicate orientation or positional relationship, are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0175] Furthermore, throughout this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0176] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

Claims

1. An offset cancellation circuit for a charging management chip, characterized in that, include: The input stage has a first input terminal connected to a first voltage signal and a second input terminal connected to a first reference voltage signal. The input stage responds to frequency control of a timing control signal to convert the operational amplifier offset to the differential input port of the operational amplifier, and responds to level conversion of the timing control signal to mirror the bias current into a first current and a second current. The output stage has a third input terminal connected to the battery output port of the charging management chip and a fourth input terminal connected to a second voltage signal provided by a charge pump. The input terminal of the charge pump is connected to the battery output port as the third input terminal, and the output terminal of the charge pump is used to provide the second voltage signal after DC regulation. The output stage follows the level shift of the timing control signal and generates an output voltage that eliminates the offset of the operational amplifier based on the first current and the second current. Wherein, the first voltage signal represents the actual battery charging current of the charging management chip, the first reference voltage signal represents the preset battery charging current of the charging management chip, and the output voltage is used to drive the charging path of the charging management chip to be turned on.

2. The offset cancellation circuit according to claim 1, characterized in that, The timing control signal includes a first timing signal and a second timing signal that are inverses of each other, and the input stage includes: A first chopper switch, wherein the first input terminal of the first chopper switch is connected to the first voltage signal, the second input terminal is connected to the first reference voltage signal, and the first control terminal of the first chopper switch is connected to the first timing signal, and the second control terminal is connected to the second timing signal; An error amplifier, wherein the differential input ports of the error amplifier are respectively connected to the first output terminal and the second output terminal of the first chopper switch.

3. The offset cancellation circuit according to claim 2, characterized in that, The first chopper switch includes: A first switch and a second switch, wherein the first end of the first switch is the first output terminal, the second end is the first input terminal, the control terminal is connected to the control terminal of the second switch and serves as the first control terminal, and the first end of the second switch is the second output terminal and the second end is the second input terminal; The third switch and the fourth switch are connected in the following ways: the first end of the third switch is connected to the first end of the second switch, the second end of the third switch is connected to the second end of the first switch, and the control terminal of the third switch is connected to the control terminal of the fourth switch and serves as the second control terminal. The first end of the fourth switch is connected to the first end of the first switch, and the second end of the fourth switch is connected to the second end of the second switch.

4. The offset cancellation circuit according to claim 3, characterized in that, The error amplifier includes: A first transistor and a second transistor are connected together, with their first terminals connected in series. The connection point of the first transistor and the second transistor are then connected in series to a third transistor and a fourth transistor, which are connected to the power supply. The control terminal of the first transistor serves as the first differential input port of the error amplifier and is connected to the first terminal of the second transistor. The control terminal of the second transistor serves as the second differential input port of the error amplifier and is connected to the first terminal of the first transistor. The second terminal of the first transistor is connected in series with the fifth and sixth transistors to ground, and the second terminal of the fifth transistor is connected to the control terminal of the sixth transistor. The second terminal of the second transistor is connected in series with the seventh transistor and the eighth transistor to ground. The second terminal of the seventh transistor is connected to the control terminal of the eighth transistor, and the control terminal of the fifth transistor is connected to the control terminal of the seventh transistor.

5. The offset cancellation circuit according to claim 4, characterized in that, The input level also includes: A first resistor, a ninth transistor, and a tenth transistor are connected. The first end of the first resistor is connected to the bias current, and the second end of the first resistor is connected in series with the ninth transistor and the tenth transistor to ground. The control terminal of the ninth transistor is connected to the first end of the first resistor and is also connected to the control terminal of the seventh transistor. The control terminal of the tenth transistor is connected to the connection node of the first resistor and the ninth transistor. The eleventh transistor and the twelfth transistor are connected together to the first terminal of the first resistor. The thirteenth transistor and the fourteenth transistor are connected together to ground. The control terminal of the thirteenth transistor is connected to the control terminal of the twelfth transistor, and the control terminal of the fourteenth transistor is connected to the control terminal of the sixth transistor.

6. The offset cancellation circuit according to claim 5, characterized in that, The input level also includes: The second chopper switch has its fifth input terminal connected to the second terminal of the thirteenth transistor, its sixth input terminal connected to the second terminal of the fourteenth transistor, its third output terminal connected to the first terminal of the eleventh transistor, its fourth output terminal connected to the first terminal of the twelfth transistor, and its third control terminal connected to the second timing signal, and its fourth control terminal connected to the first timing signal.

7. The offset cancellation circuit according to claim 6, characterized in that, The second chopper switch includes: The fifth and sixth switching transistors are provided. The first end of the fifth switching transistor serves as the fifth input terminal, the second end serves as the fourth output terminal, and the control terminal is connected to the control terminal of the sixth switching transistor and serves as the third control terminal. The first end of the sixth switching transistor serves as the sixth input terminal, and the second end serves as the third output terminal. The seventh and eighth switches are connected as follows: the first end of the seventh switch is connected to the first end of the fifth switch, the second end is connected to the second end of the sixth switch, and the control terminal is connected to the control terminal of the eighth switch and serves as the fourth control terminal. The first end of the eighth switch is connected to the first end of the sixth switch, and the second end is connected to the second end of the fifth switch.

8. The offset cancellation circuit according to claim 5 or 7, characterized in that, The input level also includes: The fifteenth transistor, the sixteenth transistor, and the second resistor are connected in series. The first terminal of the fifteenth transistor is connected to the first terminal of the fourth transistor, and the control terminal is connected to the control terminal of the fourth transistor. The second terminal of the fifteenth transistor is connected to the sixteenth transistor and the second resistor in series. The connection node of the sixteenth transistor and the second resistor is connected to the control terminal of the fifteenth transistor. The control terminal of the sixteenth transistor is connected to the control terminal of the third transistor. The seventeenth transistor and the eighteenth transistor, wherein the first terminal of the seventeenth transistor is connected to the second resistor, the second terminal of the seventeenth transistor is connected in series with the eighteenth transistor to ground, the control terminal is connected to the control terminal of the seventh transistor, and the control terminal of the eighteenth transistor is connected to the control terminal of the tenth transistor.

9. The offset cancellation circuit according to claim 7, characterized in that, The input level also includes: The nineteenth transistor and the twentieth transistor are connected together. The first terminal of the nineteenth transistor is connected to the second terminal of the eleventh transistor, and the second terminal is used to output the first current. The control terminal of the nineteenth transistor and the control terminal of the twentieth transistor are connected to the power supply terminal. The first terminal of the twentieth transistor is connected to the second terminal of the twelfth transistor, and the second terminal is used to output the second current.

10. The offset cancellation circuit according to claim 9, characterized in that, The output stage includes: The third resistor, the twenty-first transistor, and the twenty-second transistor are connected together. The first end of the third resistor is connected to the second end of the nineteenth transistor and the control terminal of the twenty-first transistor. The second end of the third resistor is connected in series with the twenty-first transistor and the twenty-second transistor to the fourth input terminal. The connection node between the third resistor and the twenty-first transistor is connected to the control terminal of the twenty-second transistor. The 23rd transistor and the 24th transistor are connected in series between the fourth input terminal and the output terminal of the offset cancellation circuit. The control terminal of the 23rd transistor is connected to the control terminal of the 22nd transistor, and the control terminal of the 24th transistor is connected to the control terminal of the 21st transistor. The 25th and 26th transistors are connected in series between the second terminal of the 24th transistor and the third input terminal, and the connection node of the 24th and 25th transistors serves as the output terminal of the offset cancellation circuit to provide the output voltage.

11. The offset cancellation circuit according to claim 10, characterized in that, The output stage also includes: The fourth resistor, the twenty-seventh transistor, and the twenty-eighth transistor are provided. The first end of the fourth resistor is connected to the second end of the twentyth transistor and the control terminal of the twenty-seventh transistor. The second end of the fourth resistor is connected in series with the twenty-seventh transistor and the twenty-eighth transistor to the fourth input terminal. The connection node between the fourth resistor and the twenty-seventh transistor is connected to the control terminal of the twenty-eighth transistor. The twenty-ninth transistor and the thirtieth transistor, wherein the control terminal of the twenty-ninth transistor is connected to the control terminal of the twenty-eighth transistor, and the control terminal of the thirtieth transistor is connected to the control terminal of the twenty-seventh transistor; The fifth resistor, the thirty-first transistor, and the thirty-second transistor are provided. The first end of the fifth resistor is connected to the second end of the thirty-first transistor and the control terminal of the thirty-first transistor. The control terminal of the thirty-first transistor is connected to the control terminal of the twenty-fifth transistor. The second end of the fifth resistor is connected in series with the thirty-first transistor and the thirty-second transistor to the third input terminal. The connection node of the fifth resistor and the thirty-first transistor is connected to the control terminal of the thirty-second transistor. The control terminal of the thirty-second transistor is connected to the control terminal of the twenty-sixth transistor.

12. The offset cancellation circuit according to claim 5, characterized in that, The input level also includes: The nineteenth transistor and the twentieth transistor are connected together. The first terminal of the nineteenth transistor is connected to the second terminal of the eleventh transistor, and the second terminal is used to output the first current. The control terminal of the nineteenth transistor and the control terminal of the twentieth transistor are connected to the power supply terminal. The first terminal of the twentieth transistor is connected to the second terminal of the twelfth transistor, and the second terminal is used to output the second current.

13. The offset cancellation circuit according to claim 12, characterized in that, The output stage includes: The third resistor, the twenty-first transistor, and the twenty-second transistor are connected together. The first end of the third resistor is connected to the second end of the nineteenth transistor and the control terminal of the twenty-first transistor. The second end of the third resistor is connected in series with the twenty-first transistor and the twenty-second transistor to the fourth input terminal. The connection node between the third resistor and the twenty-first transistor is connected to the control terminal of the twenty-second transistor. The 23rd transistor and the 24th transistor are connected in series between the fourth input terminal and the output terminal of the offset cancellation circuit. The control terminal of the 23rd transistor is connected to the control terminal of the 22nd transistor, and the control terminal of the 24th transistor is connected to the control terminal of the 21st transistor. The sixth resistor, the twenty-fifth transistor, and the twenty-sixth transistor are connected in series with the second end of the sixth resistor as the sixth input terminal to the twenty-fourth transistor, and the second end of the sixth resistor as the fourth output terminal to the third input terminal.

14. The offset cancellation circuit according to claim 13, characterized in that, The output stage also includes: The fourth resistor, the twenty-seventh transistor, and the twenty-eighth transistor are provided. The first end of the fourth resistor is connected to the second end of the twentyth transistor and the control terminal of the twenty-seventh transistor. The second end of the fourth resistor is connected in series with the twenty-seventh transistor and the twenty-eighth transistor to the fourth input terminal. The connection node between the fourth resistor and the twenty-seventh transistor is connected to the control terminal of the twenty-eighth transistor. The twenty-ninth transistor and the thirtieth transistor, wherein the control terminal of the twenty-ninth transistor is connected to the control terminal of the twenty-eighth transistor, and the control terminal of the thirtieth transistor is connected to the control terminal of the twenty-seventh transistor; The fifth resistor, the thirty-first transistor, and the thirty-second transistor are configured such that the first end of the fifth resistor is connected to the thirtieth transistor as the fifth input terminal, and the second end of the fifth resistor is connected in series with the thirty-first transistor and the thirty-second transistor as the third output terminal to the third input terminal. The control terminal of the thirty-first transistor is connected to the control terminal of the twenty-fifth transistor, and the control terminal of the thirty-second transistor is connected to the control terminal of the twenty-sixth transistor.

15. The offset cancellation circuit according to claim 14, characterized in that, The timing control signals also include a third timing signal and a fourth timing signal that are inverses of each other, and the output stage further includes: The second chopper switch has its fifth input terminal connected to the first terminal of the fifth resistor, its sixth input terminal connected to the first terminal of the sixth resistor, its third output terminal connected to the second terminal of the fifth resistor, its fourth output terminal connected to the second terminal of the sixth resistor, and its third control terminal connected to the third timing signal, its fourth control terminal connected to the fourth timing signal, and provides the output voltage through the output node.

16. The offset cancellation circuit according to claim 15, characterized in that, The second chopper switch includes: The fifth switch and the sixth switch, the first end of the fifth switch serves as the fifth input terminal, the second end of the fifth switch is connected to the second end of the sixth switch, and the connection node of the two is connected to the control terminal of the thirty-first transistor. The control terminal of the fifth switch serves as the third control terminal, the first end of the sixth switch serves as the sixth input terminal, and the control terminal of the sixth switch serves as the fourth control terminal. The seventh and eighth switching transistors are provided. The first end of the seventh switching transistor serves as the third output terminal, and the second end of the seventh switching transistor is connected to the second end of the eighth switching transistor. The connection node of the seven transistors is connected to the control terminal of the thirty-second transistor. The control terminal of the seventh switching transistor is connected to the third control terminal. The first end of the eighth switching transistor serves as the fourth output terminal, and the control terminal of the eighth switching transistor is connected to the fourth control terminal. The ninth and tenth switching transistors are configured such that the first end of the ninth switching transistor is connected to the fifth input terminal, and the second end of the ninth switching transistor is connected to the second end of the tenth switching transistor. The connection node of the two transistors serves as the output node to provide the output voltage. The control terminal of the ninth switching transistor is connected to the control terminal of the eighth switching transistor. The first end of the tenth switching transistor is connected to the sixth input terminal, and the control terminal of the tenth switching transistor is connected to the control terminal of the seventh switching transistor.

17. The offset cancellation circuit according to claim 16, characterized in that, The offset cancellation circuit further includes: A level conversion unit is connected to the third input terminal, the fourth input terminal, and the power supply terminal, respectively, and is used to generate the third timing signal and the fourth timing signal according to the second voltage signal and the battery voltage, and to generate the first timing signal and the second timing signal according to the power supply voltage and the reference ground voltage.

18. The offset cancellation circuit according to claim 12, characterized in that, The duty cycle of the first timing signal and the second timing signal is 50%.

19. The offset cancellation circuit according to claim 17, characterized in that, The duty cycle of the first timing signal and the second timing signal is 50%, the duty cycle of the third timing signal and the fourth timing signal is 50%, and the first timing signal and the third timing signal have the same period.

20. The offset cancellation circuit according to claim 18 or 19, characterized in that, The average voltage provided during the timing control signal period is the output voltage after offset elimination.

21. A charging management chip, characterized in that, include: Power transistors; as well as The offset cancellation circuit as described in any one of claims 1 to 20, wherein the output terminal of the offset cancellation circuit is connected to the control terminal of the power transistor, and is used to provide an output voltage after offset cancellation within the timing control signal period, the output voltage being used to drive the charging path connected by the power transistor to conduct.

22. A charger, characterized in that, include: The charging management chip as described in claim 21.

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