Integrated high voltage management unit and high voltage sampling method thereof

Abstract

The application discloses an integrated high-voltage management unit and a high-voltage sampling method thereof, comprising an ADC chip, an MCU processor, a communication bus and a multiplexer; the ADC chip and the MCU processor are in communication connection through the communication bus; two ADC units are integrated in the ADC chip, wherein the first ADC unit is connected to a current input / output point through a current sampling device, and the second ADC unit is divided into a PACK channel, a LINK channel and an insulation channel through the multiplexer and then connected with a PACK voltage sampler, a LINK voltage sampler and an insulation sampler respectively. The application realizes the purpose of simultaneously sampling current, PACK voltage, LINK circuit voltage and insulation detection through the single ADC chip integrated with the two ADC units and in combination with the multiplexer, guarantees the periodicity of each signal detection, effectively simplifies a schematic diagram and PCB wiring and reduces cost.

Description

Technical Field

[0001] This invention relates to the field of battery management technology, and in particular to an integrated high-voltage management unit and its high-voltage sampling method. Background Technology

[0002] Global warming has become a major challenge facing humanity. To achieve carbon neutrality, utilizing new energy sources (wind and solar power) is the most effective approach. However, these new energy sources must be combined with energy storage technology to achieve stable output. In lithium-ion battery energy storage's BMS (Battery Management System), the "High Voltage Management Unit" is a crucial module that requires special consideration and design. It mainly includes three sub-functions: total voltage detection, total current detection, and insulation detection.

[0003] Existing technical solutions mostly use multiple ADC front-end chips to implement the three sub-functions of the high-voltage management unit. For example, total voltage detection and total current detection share one ADC, while insulation detection uses a separate ADC. Some even use separate ADC chips for total voltage detection and total current detection. This technical solution has the following problems:

[0004] Disadvantage 1: High cost. Not only does it require multiple ADC acquisition chips, but because the MCU operates at a low voltage while the ADC operates at a high voltage, they are at different potentials and cannot communicate directly via the SPI bus. Instead, the bus needs to be converted through an electromagnetic-to-photoelectric converter using a digital isolator before communication can occur. Therefore, using more ADC chips means requiring more digital isolators.

[0005] Disadvantage 2: Complex wiring. More ADC chips and matching digital isolators mean more complex wiring, which not only requires a larger PCB area and a longer bus length, but also poses a greater challenge to electromagnetic compatibility. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an integrated high-voltage management unit and its high-voltage sampling method, which enables a limited ADC to acquire more signals while ensuring the periodicity of each signal detection, and effectively simplifies the schematic diagram and reduces costs.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] An integrated high-voltage management unit includes an ADC chip, an MCU processor, a communication bus, and a multiplexer;

[0009] The ADC chip and the MCU processor are connected via the communication bus.

[0010] The ADC chip integrates two ADC units. The first ADC unit is connected to the current input / output point through a current sampling device. The second ADC unit is divided into a PACK channel, a LINK channel, and an isolation channel by a multiplexer and then connected to the PACK voltage sampler, the LINK voltage sampler, and the isolation sampler, respectively.

[0011] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:

[0012] A high-voltage sampling method, applied to the aforementioned integrated high-voltage management unit, includes the following steps:

[0013] S1. Preset the first sampling period T1, the second sampling period T2 and the third sampling period T3, where T1 < T3 and T2 < T3;

[0014] S2. The MCU processor reads the total current value calculated by the first ADC unit once every T1 interval;

[0015] S3. Read the LINK voltage U calculated by the second ADC unit every T2 interval. link and PACK voltage U pack ;

[0016] S4. Read the insulation resistance calculated by the second ADC unit every T3 interval.

[0017] The beneficial effects of this invention are as follows: This invention provides an integrated high-voltage management unit, which integrates a single ADC chip with two ADC units and combines it with a multiplexer to achieve the purpose of simultaneously detecting current, PACK voltage, LINK circuit voltage and insulation resistance with a limited number of ADCs, ensuring the periodicity of each signal detection, and effectively simplifying the schematic diagram and PCB layout, thereby reducing costs. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall structure of an integrated high-voltage management unit according to an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the sampling and pre-charging principle of PACK voltage and LINK voltage according to an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram illustrating the insulation resistance detection principle of an embodiment of the present invention.

[0021] Figure 4 This is an overall flowchart of a high-voltage sampling method according to an embodiment of the present invention.

[0022] Label Explanation:

[0023] 1. ADC chip; 11. First ADC unit; 12. Second ADC unit; 2. MCU processor; 3. Communication bus; 4. Multiplexer; 5. Current sampling device; 6. PACK voltage sampler; 7. LINK voltage sampler; 8. Insulation sampler. Detailed Implementation

[0024] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0025] Please refer to Figures 1 to 3 An integrated high-voltage management unit includes an ADC chip, an MCU processor, a communication bus, and a multiplexer;

[0026] The ADC chip and the MCU processor are connected via the communication bus.

[0027] The ADC chip integrates two ADC units. The first ADC unit is connected to the current input / output point through a current sampling device. The second ADC unit is divided into a PACK channel, a LINK channel, and an isolation channel by a multiplexer and then connected to the PACK voltage sampler, the LINK voltage sampler, and the isolation sampler, respectively.

[0028] As can be seen from the above description, the beneficial effects of the present invention are as follows: by integrating a single ADC chip with two ADC units and combining it with a multiplexer, the purpose of simultaneously detecting current, PACK voltage, LINK circuit voltage and insulation resistance can be achieved, ensuring the periodicity of each signal detection, effectively simplifying the schematic diagram and PCB layout, and reducing costs.

[0029] Furthermore, the current sampler is a sampling resistor or a Hall sensor used to collect current input.

[0030] As described above, the input current is sampled using a sampling resistor or a Hall sensor to ensure current sampling accuracy.

[0031] Furthermore, it also includes a battery pre-charging circuit;

[0032] The battery pre-charge circuit includes a battery pack, a PACK voltage divider resistor, a LINK voltage divider resistor, a pre-charge relay, a pre-charge resistor, a main positive relay, and a main negative relay;

[0033] The PACK voltage divider resistor and the LINK voltage divider resistor are connected in parallel across the positive and negative terminals of the battery pack;

[0034] The pre-charge resistor and the pre-charge relay are connected in sequence and in series in the circuit where the LINK voltage divider resistor is connected to the positive terminal of the battery pack. The two ends of the main positive relay are respectively connected to the end of the pre-charge relay away from the pre-charge resistor and the end of the pre-charge resistor away from the pre-charge relay. The main negative relay is connected in series in the circuit where the LINK voltage divider resistor is connected to the negative terminal of the battery pack.

[0035] As described above, a pre-charge circuit is added to the battery pack to ensure the performance of the high-voltage management unit.

[0036] Furthermore, the PACK voltage divider resistor includes a first PACK voltage divider resistor and a second PACK voltage divider resistor, and the LINK voltage divider resistor includes a first LINK voltage divider resistor and a second LINK voltage divider resistor;

[0037] The first PACK voltage divider resistor and the second PACK voltage divider resistor have the same resistance value and are connected in series and then in parallel across the positive and negative terminals of the battery pack. The PACK voltage sampler is set in the line connecting the first PACK voltage divider resistor and the second PACK voltage divider resistor to collect the PACK voltage.

[0038] The first LINK voltage divider resistor and the second LINK voltage divider resistor have the same resistance value and are connected in series. Then, they are connected in series in the line that connects the end of the precharge resistor away from the precharge relay and the main negative relay away from the negative terminal of the battery pack. The LINK voltage sampler is set in the line that connects the first LINK voltage divider resistor and the second LINK voltage divider resistor and is used to collect the LINK voltage.

[0039] As described above, both the PACK voltage divider resistor and the LINK voltage divider resistor consist of two voltage divider resistors with the same resistance value. The PACK voltage sampler and the LINK voltage sampler can be connected to the circuit to perform PACK voltage sampling and LINK voltage sampling after the voltage is reduced to a suitable range by the resistors, thus ensuring the stability and accuracy of PACK voltage sampling and LINK voltage sampling.

[0040] Furthermore, it also includes an insulation detection circuit;

[0041] The insulation detection circuit includes an insulation resistor, a bridge arm resistor, and an insulation relay;

[0042] The bridge arm resistor and the insulating relay are connected in series, and then connected in parallel with the insulating resistor across the positive and negative terminals of the battery pack.

[0043] As described above, adding an insulation relay to the insulation detection circuit ensures the safety of insulation detection.

[0044] Furthermore, the insulation resistance includes a positive insulation resistance and a negative insulation resistance, the bridge arm resistance includes an upper bridge arm resistance and a lower bridge arm resistance, and the insulation relay includes a positive relay and a negative relay;

[0045] The positive electrode insulation resistor and the negative electrode insulation resistor are connected in series and then connected in parallel across the positive and negative terminals of the battery pack.

[0046] The upper bridge arm resistor, the positive relay, the negative relay, and the lower bridge arm resistor are connected in series and then in parallel across the positive and negative terminals of the battery pack.

[0047] The lower bridge arm resistor includes a first lower bridge arm voltage divider resistor and a second lower bridge arm voltage divider resistor. The first lower bridge arm voltage divider resistor and the second lower bridge arm voltage divider resistor have the same resistance value and are connected in sequence. The insulation sampler is installed in the line where the first lower bridge arm voltage divider resistor and the second lower bridge arm voltage divider resistor are connected, and is used to collect the voltage of the lower bridge arm resistor and the voltage of the lower bridge arm resistor connected in series with the negative relay.

[0048] A line is connected between the positive relay and the negative relay, and between the insulating positive resistor and the insulating negative resistor, and leads out to the PACK box.

[0049] As described above, the insulation sampler is set at the lower bridge arm resistor and, in conjunction with the on / off state of the positive and negative relays, first measures the voltage drop including the negative relay and the lower bridge arm resistor, then measures the voltage drop of the lower bridge arm resistor alone, and finally calculates the positive and negative insulation resistances based on the measured voltage drops, thus obtaining the insulation resistance.

[0050] Please refer to Figure 4 A high-voltage sampling method, applied to the aforementioned integrated high-voltage management unit, includes the following steps:

[0051] S1. Preset the first sampling period T1, the second sampling period T2 and the third sampling period T3, where T1 < T3 and T2 < T3;

[0052] S2. The MCU processor reads the total current value calculated by the first ADC unit once every T1 interval;

[0053] S3. Read the LINK voltage U calculated by the second ADC unit every T2 interval. link and PACK voltage U pack ;

[0054] S4. Read the insulation resistance calculated by the second ADC unit every T3 interval.

[0055] As can be seen from the above description, the beneficial effects of the present invention are as follows: Based on the same technical concept, and in conjunction with the aforementioned integrated high-voltage management unit, a high-voltage sampling method is provided. By integrating a single ADC chip with two ADC units and combining it with a multiplexer, the purpose of simultaneously detecting current, PACK voltage, LINK circuit voltage, and insulation resistance can be achieved, ensuring the periodicity of each signal detection and effectively simplifying the schematic diagram and PCB layout, thus reducing costs. At the same time, to ensure real-time performance and safety requirements, the sampling period of each current or voltage signal is required in practical applications. Since current sampling occupies a dedicated ADC chip, its data processing speed is fast, while PACK voltage, LINK voltage, and insulation resistance share a single ADC chip, resulting in slower data processing speed. Therefore, a first sampling period T1, a second sampling period T2, and a third sampling period T3 are preset, and T1 < T3 and T2 < T3 are limited to ensure that the sampling data collected by each channel does not interfere with each other and proceeds smoothly.

[0056] Further, step S3 specifically includes:

[0057] The MCU processor acquires the chip lock of the second ADC unit every T2 interval, then switches to the LINK channel via a multiplexer, and delays for a first preset delay time T. ch The LINK voltage calculated by the second ADC unit is read, then switched to the PACK channel via the multiplexer, and delayed by T. ch Read the PACK voltage U calculated by the second ADC unit pack And release the chip lock of the second ADC unit.

[0058] Further, step S4 specifically includes:

[0059] S41. Every T3 interval, the MCU processor closes the positive relay K in the insulation detection circuit. p and negative relay K n Delay T ch Then, the chip lock of the second ADC unit is acquired, and then the multiplexer is used to switch to the isolated channel, with a delay of T. y K was then measured using an insulation sampler. n Near K p One end is connected to the second voltage divider resistor R in the lower bridge arm resistor R2. 22 The first voltage divider resistor R of the lower bridge arm is far away from the bridge arm. 21 The voltage U1 between one end;

[0060] Because after R n ||R2 and R p If the current in R1 is the same, then:

[0061]

[0062] Where R1 is the upper bridge arm resistor, R2 is the lower bridge arm resistor, and R 21 and R 22 These are the first and second voltage divider resistors of the lower bridge arm of R2, respectively.

[0063] S42. Release the chip lock of the second ADC unit and disconnect K. p Keep K n closure;

[0064] S43, Delay T y Then, the chip lock of the second ADC unit is acquired again, and the multiplexer is used to switch to the isolation channel again, with a delay of T. ch R was then measured using the insulation sampler. 21 The end closer to Kn and R 22 Stay away from R 21 The voltage U2 between one end of T, where T ch <T y ;

[0065] Because after R n ||R2 and R2||R p Since the currents are equal, then:

[0066]

[0067] Simplified to:

[0068]

[0069] S44. Release the chip lock of the second ADC unit and disconnect K. p and K n ;

[0070] S45. Substitute formula (3) into formula (1) to obtain R. p and R n .

[0071] Furthermore, T1 is 10ms, T2 is 50ms, and T3 is 200ms;

[0072] T ch For 4ms, T y It takes 80ms.

[0073] As described above, since the second ADC unit shares the sampling PACK voltage, LINK voltage, and insulation resistance, it needs to continuously switch channels. After a channel switch within the second ADC unit, a first preset delay time T is required. chOnly then can the correct voltage be read, which takes approximately 4ms; while K p or K n A longer settling time is required when switching on or off, namely the second preset time T. y This time is mainly related to the distributed capacitance Y between the insulation detection circuit and the PACK enclosure. If the capacitance Y is too large, the measured R... n With R p It will take longer, therefore T y If the time limit is set to 80ms, the second ADC unit will not be occupied by different measurement tasks. At the same time, in order to prevent conflicts, the program needs to lock the second ADC unit, and only the task that acquires the lock is allowed to read the second ADC unit.

[0074] This invention provides an integrated high-voltage management unit and its high-voltage sampling method, suitable for high-voltage management of battery management systems for energy storage batteries, enabling effective detection of current, PACK voltage, LINK voltage, and insulation resistance. The following detailed description is provided with reference to embodiments.

[0075] Please refer to Figure 1 Embodiment 1 of the present invention is as follows:

[0076] An integrated high-voltage management unit, such as Figure 1 As shown, it includes an ADC chip 1, an MCU processor 2, a communication bus 3, and a multiplexer 4.

[0077] The ADC chip 1 and the MCU processor 2 are connected via a communication bus 3. The ADC chip 1 integrates two ADC units. The first ADC unit 11 is connected to the current input / output point via a current sampling device 5. The second ADC unit 12 is divided into a PACK channel, a LINK channel, and an insulation channel via a multiplexer 4 and then connected to the PACK voltage sampler 6, the LINK voltage sampler 7, and the insulation sampler 8, respectively.

[0078] In this embodiment, by integrating a single ADC chip 1 with two ADC units and combining it with a multiplexer 4, the purpose of simultaneously detecting current, PACK voltage, LINK circuit voltage, and insulation resistance can be achieved. This allows a limited number of ADC conversion units to collect more analog signals, ensures the periodicity of each signal detection, and effectively simplifies the schematic diagram and PCB layout, thereby reducing costs.

[0079] In this embodiment, the current sampler is a sampling resistor or a Hall sensor, used to collect the current input and ensure the accuracy of current sampling.

[0080] It is worth noting that in this embodiment, the ADC chip can be the AS8510, which has two built-in 16-bit Σ-Δ A / D converters and can simultaneously acquire two analog signals, which is suitable for the technical concept of this invention. In other equivalent embodiments, other ADC conversion chips capable of simultaneously acquiring two analog signals can also be used.

[0081] like Figure 2 As shown, Embodiment 2 of the present invention is as follows:

[0082] An integrated high-voltage management unit, based on the above embodiment one, in this embodiment, as follows: Figure 2 As shown, it also includes a battery pre-charging circuit.

[0083] The battery pre-charge circuit includes a battery pack, a PACK voltage divider resistor, a LINK voltage divider resistor, a pre-charge relay, a pre-charge resistor, a main positive relay, and a main negative relay; the PACK voltage divider resistor and the LINK voltage divider resistor are connected in parallel across the positive and negative terminals of the battery pack.

[0084] The precharge resistor and precharge relay are connected in sequence and in series in the circuit where the LINK voltage divider resistor is connected to the positive terminal of the battery pack. The two ends of the main positive relay are connected to the end of the precharge relay away from the precharge resistor and the end of the precharge resistor away from the precharge relay, respectively. The main negative relay is connected in series in the circuit where the LINK voltage divider resistor is connected to the negative terminal of the battery pack.

[0085] In this embodiment, a pre-charge circuit is added to the battery pack to ensure the performance of the high-voltage management unit.

[0086] In this embodiment, the PACK voltage divider resistor includes a first PACK voltage divider resistor and a second PACK voltage divider resistor, and the LINK voltage divider resistor includes a first LINK voltage divider resistor and a second LINK voltage divider resistor.

[0087] The first PACK voltage divider resistor and the second PACK voltage divider resistor have the same resistance value and are connected in series, then in parallel across the positive and negative terminals of the battery pack. A PACK voltage sampler is set in the circuit where the first PACK voltage divider resistor and the second PACK voltage divider resistor are connected to collect the PACK voltage. The first LINK voltage divider resistor and the second LINK voltage divider resistor have the same resistance value and are connected in series, then in series across the end of the precharge resistor furthest from the precharge relay and the end of the main negative relay furthest from the negative terminal of the battery pack. A LINK voltage sampler is set in the circuit where the first LINK voltage divider resistor and the second LINK voltage divider resistor are connected to collect the LINK voltage.

[0088] That is, both the PACK voltage divider resistor and the LINK voltage divider resistor are composed of two voltage divider resistors with the same resistance value. The PACK voltage sampler and the LINK voltage sampler can be connected to the circuit to sample the PACK voltage and LINK voltage after the voltage is reduced to a suitable range by the resistors, so as to ensure the stability and accuracy of the PACK voltage sampling and LINK voltage sampling. It is worth noting that in this embodiment, the PACK voltage refers to the voltage on the front-end battery pack, and the LINK voltage refers to the back-end voltage after the front-end voltage passes through the "pre-charge, main positive and main negative" relays.

[0089] Please refer to Figure 3 Embodiment 3 of the present invention is as follows:

[0090] An integrated high-voltage management unit, based on the above-described embodiment two, in this embodiment, as follows: Figure 3 As shown, it also includes an insulation detection circuit.

[0091] The insulation detection circuit includes an insulation resistor, a bridge arm resistor, and an insulation relay. The bridge arm resistor and the insulation relay are connected in series and then connected in parallel with the insulation resistor to the positive and negative terminals of the battery pack.

[0092] This involves adding an insulation relay to the insulation detection circuit to ensure the safety of insulation detection.

[0093] In this embodiment, the insulation resistance includes the positive insulation resistance and the negative insulation resistance, which are the final results to be tested.

[0094] Meanwhile, the bridge arm resistors include the upper bridge arm resistors and the lower bridge arm resistors, and the insulation relays include the positive relays and the negative relays.

[0095] The positive and negative insulation resistors are connected in series and then in parallel across the positive and negative terminals of the battery pack. The upper bridge arm resistor, positive relay, negative relay, and lower bridge arm resistor are connected in series and then in parallel across the positive and negative terminals of the battery pack. The lower bridge arm resistor includes a first lower bridge arm voltage divider resistor and a second lower bridge arm voltage divider resistor. The first lower bridge arm voltage divider resistor and the second lower bridge arm voltage divider resistor have the same resistance value and are connected in series. An insulation sampler is installed in the line connecting the first lower bridge arm voltage divider resistor and the second lower bridge arm voltage divider resistor to collect the voltage of the lower bridge arm resistor and the voltage after the lower bridge arm resistor and the negative relay are connected in series. In this embodiment, the first lower bridge arm voltage divider resistor and the second lower bridge arm voltage divider resistor play a voltage dividing role to ensure the stability and accuracy of insulation detection. The first lower bridge arm voltage divider resistor and the second lower bridge arm voltage divider resistor can be considered equivalent to the lower bridge arm resistor. A line is connected between the positive and negative relays and between the positive and negative insulation resistors, and is led out to the PACK box.

[0096] The insulation sampler is set at the lower bridge arm resistor and, in conjunction with the on / off state of the positive and negative relays, first measures the voltage drop including the negative relay and the lower bridge arm resistor, then measures the voltage drop of the lower bridge arm resistor alone, and finally calculates the positive and negative insulation resistances based on the measured voltage drops, thus obtaining the insulation resistance.

[0097] Please refer to Figure 4 Embodiment four of the present invention is as follows:

[0098] A high-voltage sampling method 1 is applied to an integrated high-voltage management unit in Embodiment 3 above, such as... Figure 4 As shown, the steps include:

[0099] S1. Preset a first sampling period T1, a second sampling period T2 and a third sampling period T3, where T1 < T3 and T2 < T3. In this embodiment, T1 is 10ms, T2 is 50ms and T3 is 200ms.

[0100] S2, the MCU processor reads the total current value calculated by the first ADC unit once every T1 interval.

[0101] S3. Read the LINK voltage U calculated by the second ADC unit every T2 interval. link and PACK voltage U pack .

[0102] In this embodiment, step S3 specifically includes:

[0103] The MCU processor acquires the chip lock of the second ADC unit every T2 interval, then switches to the LINK channel via a multiplexer, and delays for a first preset delay time T. ch Read the LINK voltage calculated by the second ADC unit, then switch to the PACK channel via a multiplexer, and delay for T. ch Read the PACK voltage U calculated by the second ADC unit pack And release the chip lock of the second ADC unit; where T ch It takes 4ms.

[0104] S4. Read the insulation resistance calculated by the second ADC unit every T3 interval.

[0105] In this embodiment, step S4 specifically includes:

[0106] S41, the MCU processor closes the positive relay K in the insulation detection circuit every interval T3. p and negative relay K n Delay T ch Then, the chip lock of the second ADC unit is acquired, and then switched to the isolated channel via a multiplexer, with a delay of T.y K was then measured using an insulation sampler. n Near K p One end is connected to the second voltage divider resistor R in the lower bridge arm resistor R2. 22 The first voltage divider resistor R of the lower bridge arm is far away from the bridge arm. 21 The voltage U1 between one end;

[0107] Because after R n ||R2 and R p If the current in R1 is the same, then:

[0108]

[0109] Where R1 is the upper bridge arm resistor, R2 is the lower bridge arm resistor, and R 21 and R 22 These are the first and second voltage divider resistors of the lower bridge arm of R2, respectively. In this embodiment, R1 can be 2MΩ. 21 and R 22 The values ​​can be 2MΩ and 3.3KΩ respectively;

[0110] S42. Release the chip lock of the second ADC unit and disconnect K. p Keep K n closure;

[0111] S43, Delay T y Then, the chip lock of the second ADC unit is acquired again, and the device is switched to the isolated channel again via the multiplexer, with a delay of T. ch R was then measured using an insulation sampler. 21 The end closer to Kn and R 22 Stay away from R 21 The voltage U2 between one end of T, where T ch <T y And T y It takes 80ms;

[0112] Because after R n ||R2 and R2||R p Since the currents are equal, then:

[0113]

[0114] Simplified to:

[0115]

[0116] S44. Release the chip lock of the second ADC unit and disconnect K. p and K n ;

[0117] S45. Substitute formula (3) into formula (1) to obtain R. p and R n .

[0118] Table 1 below shows the high-voltage signal sampling period requirements:

[0119] Table 1

[0120]

[0121]

[0122] In this embodiment, a single ADC chip integrating two ADC units, combined with a multiplexer, is used to simultaneously detect current, PACK voltage, LINK circuit voltage, and insulation resistance. This ensures the periodicity of each signal detection and effectively simplifies the schematic and PCB layout, reducing costs. To ensure real-time performance and safety, as shown in Table 1, practical applications require high sampling periods for each current or voltage signal. Since current sampling uses a dedicated ADC chip, its data processing speed is fast, while PACK voltage, LINK voltage, and insulation resistance share a single ADC chip, resulting in slower data processing. Therefore, a first sampling period T1, a second sampling period T2, and a third sampling period T3 are preset, with T1 < T3 and T2 < T3, ensuring that each channel's data acquisition proceeds smoothly and without interference. Furthermore, since the second ADC unit shares the sampling of PACK voltage, LINK voltage, and insulation resistance, continuous channel switching is required. After channel switching within the second ADC unit, a first preset delay time T is needed. ch Only then can the correct voltage be read, which takes approximately 4ms; while K p or K n A longer settling time is required when switching on or off, namely the second preset time T. y This time is mainly related to the distributed capacitance Y between the insulation detection circuit and the PACK enclosure. If the capacitance Y is too large, the measured R... n With R p It will take longer, therefore T y If the time limit is set to 80ms, the second ADC unit will not be occupied by different measurement tasks. In addition, to prevent conflicts, the program needs to lock the second ADC unit, and only the task that acquires the lock is allowed to read from the second ADC unit.

[0123] In summary, the integrated high-voltage management unit and its high-voltage sampling method provided by this invention have the following beneficial effects:

[0124] 1. Achieving the goal of simultaneously acquiring multiple analog signals such as current, PACK voltage, LINK voltage, and insulation resistance using a single ADC chip that integrates two ADC units, effectively saving costs;

[0125] 2. It can ensure the periodicity of each signal detection;

[0126] 3. Effectively simplifies schematic diagrams and PCB routing.

[0127] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A high-voltage sampling method, applied to an integrated high-voltage management unit, characterized in that, The integrated high-voltage management unit includes an ADC chip, an MCU processor, a communication bus, and a multiplexer; The ADC chip and the MCU processor are connected via the communication bus. The ADC chip integrates two ADC units. The first ADC unit is connected to the current input / output point through a current sampling device. The second ADC unit is divided into a PACK channel, a LINK channel, and an isolation channel by a multiplexer and then connected to the PACK voltage sampler, the LINK voltage sampler, and the isolation sampler, respectively. The method includes the following steps: S1. Preset the first sampling period T1, the second sampling period T2 and the third sampling period T3, where T1 < T3 and T2 < T3; S2. The MCU processor reads the total current value calculated by the first ADC unit once every T1 interval; S3. Read the LINK voltage calculated by the second ADC unit every T2 interval. U link and PACK voltage U pack ; S4. Read the insulation resistance calculated by the second ADC unit every T3 interval; Step S4 specifically involves: S41. The MCU processor closes the positive relay in the insulation detection circuit every T3 intervals. K p and negative relay K n Delay T ch Then, the chip lock of the second ADC unit is acquired, and then the multiplexer is used to switch to the isolated channel, with a delay of T. y Then measured by an insulation sampler K n near K p One end is connected to the lower bridge arm resistor R The second voltage divider resistor in the lower bridge arm of 2 R 22 away from the first voltage divider resistor of the lower bridge arm R 21 voltage between one end U 1; Due to the passage R n || R 2 and R p || R Since the currents in the first 1 are equal, then: （1）； in, R 1 represents the resistance of the upper bridge arm. R 2 is the lower bridge arm resistor. R 21 and R 22 They are respectively R The first voltage divider resistor and the second voltage divider resistor of the lower bridge arm of the 2nd bridge arm; S42. Release the chip lock of the second ADC unit and disconnect. K p ,Keep K n closure; S43, Delay T y Then, the chip lock of the second ADC unit is acquired again, and the multiplexer is used to switch to the isolation channel again, with a delay of T. ch Then measured by the insulation sampler R 21 The end closer to Kn and R 22 keep away R 21 voltage between one end U 2, where T ch <T y ; Due to the passage R n || R 2 and R 2|| R p Since the currents are equal, then: （2）； Simplified to: （3）； S44. Release the chip lock of the second ADC unit and disconnect. K p and K n ; S45. Substitute formula (3) into formula (1) to obtain... R p and R n .

2. The high-voltage sampling method according to claim 1, characterized in that, The current sampler is a sampling resistor or a Hall sensor used to collect current input.

3. The high-voltage sampling method according to claim 1, characterized in that, The integrated high-voltage management unit also includes a battery pre-charging circuit; The battery pre-charge circuit includes a battery pack, a PACK voltage divider resistor, a LINK voltage divider resistor, a pre-charge relay, a pre-charge resistor, a main positive relay, and a main negative relay; The PACK voltage divider resistor and the LINK voltage divider resistor are connected in parallel across the positive and negative terminals of the battery pack; The pre-charge resistor and the pre-charge relay are connected in sequence and in series in the circuit where the LINK voltage divider resistor is connected to the positive terminal of the battery pack. The two ends of the main positive relay are respectively connected to the end of the pre-charge relay away from the pre-charge resistor and the end of the pre-charge resistor away from the pre-charge relay. The main negative relay is connected in series in the circuit where the LINK voltage divider resistor is connected to the negative terminal of the battery pack.

4. The high-voltage sampling method according to claim 3, characterized in that, The PACK voltage divider resistor includes a first PACK voltage divider resistor and a second PACK voltage divider resistor, and the LINK voltage divider resistor includes a first LINK voltage divider resistor and a second LINK voltage divider resistor. The first PACK voltage divider resistor and the second PACK voltage divider resistor have the same resistance value and are connected in series and then in parallel across the positive and negative terminals of the battery pack. The PACK voltage sampler is set in the line connecting the first PACK voltage divider resistor and the second PACK voltage divider resistor to collect the PACK voltage. The first LINK voltage divider resistor and the second LINK voltage divider resistor have the same resistance value and are connected in series. Then, they are connected in series in the line that connects the end of the precharge resistor away from the precharge relay and the main negative relay away from the negative terminal of the battery pack. The LINK voltage sampler is set in the line that connects the first LINK voltage divider resistor and the second LINK voltage divider resistor and is used to collect the LINK voltage.

5. The high-voltage sampling method according to claim 3, characterized in that, The integrated high-voltage management unit also includes an insulation detection circuit; The insulation detection circuit includes an insulation resistor, a bridge arm resistor, and an insulation relay; The bridge arm resistor and the insulating relay are connected in series, and then connected in parallel with the insulating resistor across the positive and negative terminals of the battery pack.

6. The high-voltage sampling method according to claim 5, characterized in that, The insulation resistance includes a positive insulation resistance and a negative insulation resistance; the bridge arm resistance includes an upper bridge arm resistance and a lower bridge arm resistance; and the insulation relay includes a positive relay and a negative relay. The positive electrode insulation resistor and the negative electrode insulation resistor are connected in series and then connected in parallel across the positive and negative terminals of the battery pack. The upper bridge arm resistor, the positive relay, the negative relay, and the lower bridge arm resistor are connected in series and then in parallel across the positive and negative terminals of the battery pack. The lower bridge arm resistor includes a first lower bridge arm voltage divider resistor and a second lower bridge arm voltage divider resistor. The first lower bridge arm voltage divider resistor and the second lower bridge arm voltage divider resistor have the same resistance value and are connected in sequence. The insulation sampler is installed in the line where the first lower bridge arm voltage divider resistor and the second lower bridge arm voltage divider resistor are connected, and is used to collect the voltage of the lower bridge arm resistor and the voltage of the lower bridge arm resistor connected in series with the negative relay. A line is connected between the positive relay and the negative relay, and between the insulating positive resistor and the insulating negative resistor, and leads out to the PACK box.

7. The high-voltage sampling method according to claim 1, characterized in that, Step S3 specifically involves: The MCU processor acquires the chip lock of the second ADC unit every T2 interval, then switches to the LINK channel via a multiplexer, and delays for a first preset delay time T. ch The LINK voltage calculated by the second ADC unit is read, then switched to the PACK channel via the multiplexer, and delayed by T. ch Read the PACK voltage calculated by the second ADC unit U pack And release the chip lock of the second ADC unit.

8. The high-voltage sampling method according to claim 1, characterized in that, T1 is 10ms, T2 is 50ms, and T3 is 200ms; T ch For 4ms, T y It takes 80ms.

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