A digitized off-chip resistor-capacitor-less step-down DC-DC converter

Abstract

This invention relates to a digital, on-chip resistor- and capacitor-free buck DC-DC converter, belonging to the field of power management technology. It includes digital control logic, a driver module, an error comparator, a high-clamp comparator, a low-clamp comparator, a delay module, and power switching transistors. A digital structure based on comparators and digital units is proposed, using pure MOSFETs and eliminating on-chip resistors and capacitors to achieve a low-power, high-efficiency DC-DC converter. The circuit implementation is simple, without complex analog modules, consisting of only three comparators, one digital control logic, one digital driver stage, one power stage, and three identical delay modules, reducing the overall power consumption and hardware cost of the power chip. The DC-DC converter can achieve a stable output voltage of 1.2–2.8V within an input voltage range of 1.8–3.6V, with a peak-to-peak ripple of less than 7mV under load current of 0–50mA and variations in process angle and temperature. The power efficiency can reach over 90% under heavy load (50mA) and over 73% under light load (1mA).

Description

Technical Field

[0001] This invention relates to a digital step-down DC-DC converter without on-chip resistors and capacitors, belonging to the field of power management technology. Background Technology

[0002] In recent years, with the rise of various battery-powered wearable devices and Internet of Things devices, small electronic networks centered on the human body, such as portable mobile devices and wearable electronic products, have led to an increasing demand for electronic devices, especially portable devices. This has placed higher demands on power chips, requiring them to be more efficient and capable of achieving longer battery life.

[0003] Existing power supply types, in terms of technical solutions, mainly include three types: linear regulators, charge pumps, and DC-DC regulators. Traditional linear regulators, while simple in circuit structure and easy to design, suffer from low efficiency and poor load-carrying capacity. Charge pump converters, although lacking magnetic components and small in size, have low output current, large ripple, and high output voltage noise, and only achieve high conversion efficiency under certain input voltages. DC-DC converters offer the highest conversion efficiency, have various topologies, can perform both boost and buck conversions, and can provide large load drive currents. Therefore, DC-DC products are commonly used as power supplies for portable electronic devices.

[0004] Traditional DC-DC converter control technologies can be summarized into three types: Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and hybrid PWM / PFM modulation. Due to the demand for high efficiency in power supply chips, mainstream DC-DC converter chips on the market generally employ hybrid PWM / PFM modulation, using PWM modulation under heavy load and PFM modulation or reducing the switching frequency under light load, with the two control methods automatically switching according to load changes. However, this implementation involves numerous analog sub-modules and digital control logic, a large number of comparators and operational amplifiers, resulting in a complex circuit structure and requiring large capacitors and resistors, leading to relatively high power consumption and cost. Therefore, this invention aims to research and solve the problem of how to adopt a digital implementation method, a simpler structure, and use only pure MOSFETs to reduce chip manufacturing costs and overall circuit power consumption. Summary of the Invention

[0005] This invention proposes a digital step-down DC-DC converter without on-chip resistors and capacitors. The aim is to achieve a low-power, high-efficiency DC-DC converter by adopting a digital implementation method based on comparators and digital units. It uses pure MOSFETs, and the on-chip circuit does not contain resistors or capacitors. The circuit structure is simple and has no complex analog modules, thereby reducing the overall power consumption and hardware cost of the power chip.

[0006] The core idea of ​​this invention is to employ a simple error comparator, a clamp comparator, and a digital logic unit. The error comparator compares the output voltage feedback value with the reference voltage to generate a control signal, which, together with the output signal of the clamp comparator, controls the on / off state of the push-pull power transistor to obtain a stable output voltage. The error comparator replaces the traditional error amplifier, PWM comparator, and ramp generator, eliminating the need for on-chip capacitor compensation. The clamp comparator directly introduces offset through the size mismatch of the input transistors, replacing traditional resistor sampling and eliminating the need for on-chip resistors. Soft-switching technology based on dead-time control is used, employing a MHz switching frequency under heavy load and a kHz switching frequency under light load, ensuring high converter efficiency. The circuit structure contains only 3 comparators, 1 digital control logic, 1 digital driver stage, 1 power stage, and 3 identical delay modules, without complex analog modules, ensuring low power consumption, extremely low cost, and digital implementation.

[0007] The present invention is achieved through the following technical solution.

[0008] The digital buck DC-DC converter without on-chip resistors and capacitors includes digital control logic, a drive module, an error comparator, a high-clamp comparator, a low-clamp comparator, a delay module, and power switching transistors.

[0009] The digital control logic module consists of basic digital units, which realize the DC-DC converter function through digital logic and reduce the overall power consumption of the system.

[0010] The driving module includes an inverter chain and an AND gate;

[0011] The power switching transistor adopts a basic push-pull structure, including a PMOS power transistor M. P and an NMOS power transistor M N Using NMOS transistors instead of diodes for synchronous rectification reduces power consumption and improves efficiency.

[0012] The error comparator is implemented using a two-stage structure of NMOS type input pair transistors. It compares the output feedback voltage with the reference voltage and generates a signal to control the operation of the power transistor.

[0013] The high-clamp comparator employs a two-stage structure with NMOS input transistors. The input transistors have the same width-to-length ratio. By setting the finger ratio to 10:2, an offset voltage V is generated at the comparator's input. OS1；

[0014] The low-clamp comparator employs a two-stage structure with PMOS input transistors. The input transistors have the same width-to-length ratio. By setting the finger ratio to 10:8, an offset voltage V is generated at the comparator's input. OS2；

[0015] The delay module consists of delay units and AND gates;

[0016] The connection relationships of the modules in the aforementioned digital buck DC-DC converter without on-chip resistors and capacitors are as follows:

[0017] The digital control logic is connected to the drive module and the delay module. The drive module is connected to the push-pull power switch, and the power switch is connected to the high-clamp comparator and the low-clamp comparator. The high-clamp comparator, the low-clamp comparator, and the error comparator are each connected to three identical delay modules, which are then connected to the digital control logic. The error comparator is also connected to an external passive feedback network. The power switch is also connected to an external LC filter. The digital control logic outputs five digital signals H. EN Z EN R EN P CTRL N CTRL H EN Z EN R EN These are the enable control signals for the high-clamp comparator, low-clamp comparator, and error comparator, respectively. CTRL N CTRL The input signal to the driver module; the driver module outputs three digital signals P. GATE N GATE P PRE , where P GATE N GATE These are power transistors M and M respectively. P M N The gate drive signal, P PRE As the positive inverting input of the high-clamp comparator;

[0018] The functions of each module in the aforementioned digital buck DC-DC converter without on-chip resistors and capacitors are as follows:

[0019] The function of digital control logic is to generate drive signals to control the operation of the drive module, and at the same time generate enable signals to control the delay module.

[0020] The function of the driver module is to drive the high-power switching transistor M through an inverter chain. P and M N Alternate conduction, and during the synchronous switching of the two power transistors, a dead time in which neither transistor is conducting is inserted to avoid the risk of simultaneous conduction. The dead time is set by the delay of the inverter chain.

[0021] The function of a push-pull power switch is to utilize the energy storage inductor, filter capacitor, and load of an external filter to complete the conversion and transfer of electrical energy through alternating on and off operating states, so that the output voltage reaches the set value.

[0022] The function of the error comparator is to sample and feedback the output signal to the voltage V. FB and reference voltage V REF By comparing the values, the output voltage is stabilized at a preset value under the regulation of the loop negative feedback;

[0023] The function of the high-clamp comparator is to convert the power transistor output signal V SW Compared to the high level, the offset voltage V set between the input transistors is... OS1 Make V SW exist When the comparator output level flips, it avoids the risk of inductor current flowing backward through the body diode of the power transistor and backflowing into the power supply.

[0024] The function of the low-clamp comparator is to convert the power transistor output signal V SW Compared to the low level, the offset voltage V set between the input pair transistors is... OS2 Make V SW In -V OS2 When the comparator output level flips, it avoids the risk of inductor current flowing backward through the body diode of the power transistor and back to ground.

[0025] The function of the delay module is to control whether the comparator's comparison level is output to the digital control logic and to perform a delay processing on it;

[0026] The operation of the aforementioned digital buck DC-DC converter without on-chip resistors and capacitors specifically includes the following steps:

[0027] Step 1: Determine the input and output voltages, as well as the load current, and make power supply and signal connections. This step includes the following sub-steps:

[0028] Step 1.1 Determine the input voltage V as needed. DD and output voltage V OUT Preset value, V OUT The preset value depends on the external passive feedback network and the reference voltage V. REF；

[0029]

[0030] Step 1.2 Determine whether the load current is heavy or light. The magnitude of the load current is determined by the output voltage and the external load resistor R. L Decide;

[0031] Step 1.3 Bias current setting: The bias current of the three comparators is set directly by an external current source.

[0032] Step 2: Power transistor M P With M N Alternating on and off, output voltage V OUT The value increases, specifically including the following sub-steps:

[0033] Step 2.1 Set NRST to low level to reset the circuit, then set NRST to high level for normal circuit operation; initially, power transistor M... P and M N All off, R EN When it is high level, the output voltage V OUT Initially 0, its feedback value V FB It is 0, which is less than the reference voltage V. REF Error comparator compares level V EA The E signal is high, after being delayed by delay module I. OUT A high-level output is sent to the digital control logic;

[0034] Step 2.2 Digital control logic output H EN High level, Z EN Low level, R EN Low level, P CTRL Low level, N CTRL When the level is low, the output P of the driver module is low. GATE Low level, N GATE Low level, P PRE High level, power transistor M P On, M N Off; Input voltage V DD The inductor L supplies power to the load R. L Power is supplied, inductor L and capacitor C store energy, the inductor current gradually increases from its minimum value to its maximum value, and the output voltage value V OUT Rise; power transistor output signal V SW Rise to level V DD -V OS1 The comparison level V of the high-clamp comparator HCOMP The output is H after a high level and a delay of time after delay module II. OUT The low-level to high-level transition is fed back to the control logic;

[0035] Step 2.3 Digital control logic output Z EN High level, H EN Low level, R EN Low level, P CTRL High level, N CTRL When the signal is high, the output P of the driver module is... GATE High level, N GATE High level, P PRE When the power transistor M is at a low level, N On, M P Turn off; power transistor output signal V SW When the voltage drops to a low level, the inductor current cannot change abruptly; instead, it gradually decreases from its maximum value, and the energy storage inductor L continues to supply power to the load R. L Power supply; Comparison level V of the low-clamp comparator ZCOMP The output is Z after a high level and a delay of time after delay module III. OUT The low-level to high-level transition is fed back to the control logic;

[0036] Step 2.4 Digital control logic output R EN High level, H EN Low level, Z EN Low level, P CTRL High level, N CTRL When the level is low, the output P of the driver module is low. GATE High level, N GATE Low level, P PRE When the power transistor M is at a low level, P Shutdown, M N Turn-off; at this time, during the dead time when both transistors are off, the inductor current continues to decrease to its minimum value, the capacitor discharges, and the output voltage V... OUT A slight decrease; output voltage V OUT The set value was not reached, and the feedback voltage V was returned. FB Less than the reference voltage V REF Error comparator compares level V EA The output is E after a high level and a delay of time after delay module I. OUT The low-level to high-level transition is fed back to the control logic;

[0037] Repeat the above steps to output voltage value V OUT Overall increase;

[0038] Step 3: Output voltage V OUT Once the set value in step 1.1 is reached, a steady state is established, and the output voltage is maintained stably. This process includes the following sub-steps:

[0039] Step 3.1 After step two, the output voltage V OUTWhen the set value is reached, the feedback value V is obtained. FB Greater than or equal to the reference voltage V REF In R EN When the level is high, the error comparator compares the level V. EA When the signal is low, the delay output E of delay module I is used. OUT It remains low and has not toggled, providing feedback to the control logic.

[0040] Step 3.2 Establish steady state, and use digital control logic to control the power transistor M. P M N The circuit alternates between on and off, causing the output voltage to fluctuate within a set value. Depending on the load current, different scenarios are defined for heavy load and light load conditions, as detailed below:

[0041] 3.2.1 If the load current is heavy load, in M P During the conduction phase, the input voltage is supplied to the load R through the inductor L. L Power is supplied, and energy is stored in inductor L and capacitor C. The inductor current gradually increases from its minimum value to its maximum value; in M N During the conduction phase, the inductor current cannot change abruptly; it gradually decreases from its maximum value, and the energy storage inductor L continues to supply power to the load R. L Power supply; in M P M N When both are turned off, the inductor current decreases to its minimum value of zero, and the filter capacitor C flows to the load R. L It provides current to maintain the load current stable at the set value; the larger the load current, the shorter the capacitor discharge time, the shorter the switching cycle, and the higher the switching frequency. The heavy-load switching frequency is in the MHz range.

[0042] 3.2.2 If the load current is light, in M P M N When both transistors are off, because the load current is smaller, the capacitor discharges for a longer time to maintain the load current, and the time when both transistors are off is longer; the switching frequency of one switching cycle increases as the load current decreases, and the switching frequency under light load is on the order of kHz.

[0043] Power transistor M P M N Employing a push-pull structure with alternating on / off switching, and using three simple comparators, it can quickly respond to the above steps, achieving a high-efficiency, low-output-voltage-ripple DC-DC converter without on-chip resistors and capacitors.

[0044] Beneficial effects

[0045] A digital, on-chip resistor- and capacitor-free step-down DC-DC converter offers the following advantages compared to existing technologies:

[0046] 1. An error comparator is used to replace the traditional error amplifier, PWM comparator and ramp generator, eliminating the slope compensation stage and eliminating the need for on-chip capacitors;

[0047] 2. The potential detection of the two clamping comparators is achieved by detecting the offset of the input pair transistors, eliminating the need for traditional resistor sampling and on-chip resistors;

[0048] 3. Based on the soft-switching technology of dead-time control, the switching frequency of MHz is used under heavy load and the switching frequency of kHz is used under light load, which ensures the high efficiency of the converter.

[0049] 4. It has no complex analog modules, only 3 comparators, 1 digital control logic, 1 digital driver stage, 1 power stage, and 3 identical delay modules, ensuring low power consumption, extremely low cost, and digital implementation;

[0050] 5. The output signals of the clamp comparator and the error comparator jointly control and drive the power transistor, thereby stabilizing the output voltage and optimizing the operating mechanism to reduce voltage ripple. Attached Figure Description

[0051] Figure 1 This is a system block diagram of a digital step-down DC-DC converter without on-chip resistors and capacitors according to the present invention.

[0052] Figure 2 This is a digital control logic state diagram of a digital step-down DC-DC converter without on-chip resistors and capacitors according to the present invention.

[0053] Figure 3 This is a circuit diagram of the drive module in a digital step-down DC-DC converter without on-chip resistors and capacitors according to the present invention.

[0054] Figure 4 This is a circuit diagram of the error comparator and high-clamp comparator in a digital step-down DC-DC converter without on-chip resistors and capacitors according to the present invention.

[0055] Figure 5 This is a circuit diagram of a low-clamp comparator in a digital step-down DC-DC converter without on-chip resistors and capacitors, according to the present invention.

[0056] Figure 6 This is a circuit diagram of the delay module in a digital step-down DC-DC converter without on-chip resistors and capacitors according to the present invention.

[0057] Figure 7 This invention relates to a digital step-down DC-DC converter without on-chip resistors and capacitors, whose output voltage V under light load is... OUT and power transistor output V SW Transient simulation waveforms;

[0058] Figure 8 This invention relates to a digital step-down DC-DC converter without on-chip resistors and capacitors, whose output voltage V under heavy load is... OUT and power transistor output V SW Transient simulation waveforms. Detailed Implementation

[0059] The following description, in conjunction with embodiments and accompanying drawings, further illustrates and details the various circuit modules and working process of the digital step-down DC-DC converter without on-chip resistors and capacitors according to the present invention.

[0060] Example 1

[0061] A digital buck DC-DC converter without on-chip resistors and capacitors is based on comparators and digital units. The on-chip circuit does not contain resistors and capacitors, which reduces the overall power consumption and hardware cost of the circuit.

[0062] The operation process of the digital buck DC-DC converter without on-chip resistors and capacitors is as follows:

[0063] Step A: Determine the input and output voltages, as well as the load current, and make power supply and signal connections. This step includes the following sub-steps:

[0064] Step A.1 Determine the input voltage V as needed. DD and output voltage V OUT Preset value, V OUT The preset value depends on the external passive feedback network and the reference voltage V. REF ;

[0065]

[0066] Specifically in this embodiment, V DD The range is 1.8V to 3.6V, V REF The voltage is fixed at 1V, the output voltage is 1.2V to 2.8V, R1 is a fixed value of 100kΩ, and R2 is obtained according to the output voltage, with a range of 20kΩ to 180kΩ;

[0067] Step A.2: Determine whether the load current is heavy or light. The magnitude of the load current is determined by the output voltage and the external load resistor R. L Decide;

[0068] Specifically, in this embodiment, the load current range is 0–50mA;

[0069] Step A.3 Bias current setting: The bias current of the three comparators is set directly by an external current source.

[0070] Step B: Power transistor M P With M N Alternating on and off, output voltage V OUT The ascent specifically includes the following sub-steps:

[0071] Step B.1 Set NRST to low level to reset the circuit, then set NRST to high level for normal circuit operation; initially, power transistor M... P and M N All off, R EN When it is high level, the output voltage V OUT Initially 0, its feedback value V FB It is 0, which is less than the reference voltage V. REF Error comparator compares level V EA The E signal is high, after being delayed by delay module I. OUT A high-level output is sent to the digital control logic;

[0072] Specifically in this embodiment, the NRST trigger circuit starts working. Initially, the power transistor M... P and M N All off, R EN It is a high level, that is, the comparison level V of the error comparator. EA The feedback value V is output normally through delay module I. FB Less than V REF ;

[0073] Step B.2 Digital control logic output H EN High level, Z EN Low level, R EN When PCTRL is low and NCTRL is low, the output P of the driver module is low. GATE Low level, N GATE Low level, P PRE High level, power transistor M P On, M N Off; Input voltage V DD The inductor L supplies power to the load R. L Power is supplied, inductor L and capacitor C store energy, the inductor current gradually increases from its minimum value to its maximum value, and the output voltage value V OUT Rise; power transistor output signal V SW Rise to level V DD -V OS1 The comparison level V of the high-clamp comparator HCOMP The output is H after a high level and a delay of time after delay module II. OUT The low-level to high-level transition is fed back to the control logic;

[0074] Specifically in this embodiment, the digital control logic enables MP On, M N Off, H EN When the input voltage is high, it is supplied to the load R through the inductor L. L Power is supplied, and energy is stored in inductor L and capacitor C. The inductor current gradually increases from its minimum value to its maximum value, and the output voltage value V... OUT Rise, power transistor output signal V SW The comparator starts rising to a high level, and the low-high clamp comparator compares the level V. HCOMP The delay module II outputs signal H. OUT ;

[0075] Step B.3 Digital control logic output Z EN High level, H EN Low level, R EN When P is low, PCTRL is high, and NCTRL is high, the output of the driver module is P. GATE High level, N GATE High level, P PRE When the power transistor M is at a low level, N On, M P Turn off; power transistor output signal V SW When the voltage drops to a low level, the inductor current cannot change abruptly; instead, it gradually decreases from its maximum value, and the energy storage inductor L continues to supply power to the load R. L Power supply, low clamp comparator comparison level V ZCOMP The output is Z after a high level and a delay of time after delay module III. OUT The low-level to high-level transition is fed back to the control logic;

[0076] Specifically in this embodiment, M P Shutdown, M N On, Z EN When the voltage level is high, the inductor current gradually decreases from its maximum value, and the energy storage inductor L continues to supply power to the load R. L Power supply, power transistor output signal V SW The voltage level begins to drop to low, and the low-clamp comparator comparison level V... ZCOMP The delay module III outputs signal Z. OUT ;

[0077] Step B.4 Digital control logic output R EN High level, H EN Low level, Z EN When P is low, PCTRL is high, and NCTRL is low, the output of the driver module is P. GATE High level, N GATE Low level, P PRE When the power transistor M is at a low level, P Shutdown, M NTurn-off; during this dead time when both transistors are off, the inductor current continues to decrease to its minimum value; output voltage V OUT The set value was not reached, and the feedback voltage V was returned. FB Less than the reference voltage V REF Error comparator compares level V EA The output is E after a high level and a delay of time after delay module I. OUT The low-level to high-level transition is fed back to the control logic;

[0078] Specifically in this embodiment, M P Shutdown, M N Shutdown, Z EN When the voltage is high, the output feedback voltage V is... FB Less than the reference voltage V REF Error comparator compares level V EA The delay module I outputs signal E. OUT Feedback is sent to the control logic;

[0079] Repeat the above steps to output voltage value V OUT rise;

[0080] Step C: Output voltage V OUT Once the set value is reached, a steady state is established, and the output voltage is maintained stably. This process includes the following sub-steps:

[0081] Step C.1 After step B, the output voltage V OUT When the set value is reached, the feedback value V is obtained. FB Greater than or equal to the reference voltage V REF In R EN When high, the error comparator compares the level V. EA The output signal E of delay module I is low. OUT It remains low and has not toggled, providing feedback to the control logic.

[0082] Step C.2 Establish steady state, digital control logic controls power transistor M P M N The circuit alternates between on and off, causing the output voltage to fluctuate around a set stable value. Depending on the load current, different scenarios exist for heavy load and light load, as detailed below:

[0083] C.2.1 If the load current is heavy load, in M P During the conduction phase, the input voltage is supplied to the load R through the inductor L. L Power is supplied, and energy is stored in inductor L and capacitor C. The inductor current gradually increases from its minimum value to its maximum value; in M N During the conduction phase, the inductor current cannot change abruptly; it gradually decreases from its maximum value, and the energy storage inductor L continues to supply power to the load R. L Power supply; in MP M N When both are turned off, the inductor current decreases to its minimum value of zero, and the filter capacitor C flows to the load R. L It provides current to maintain the load current stable at the set value; the larger the load current, the shorter the capacitor discharge time, the shorter the switching cycle, and the higher the switching frequency. The heavy-load switching frequency is in the MHz range.

[0084] C.2.2 If the load current is light, in M P M N When both transistors are off, because the load current is smaller, the capacitor discharges for a longer time to maintain the load current, and the time when both transistors are off is longer; the switching frequency of one switching cycle increases as the load current decreases, and the switching frequency under light load is on the order of kHz.

[0085] Power transistor M P M N Employing a push-pull structure with alternating on / off switching, and using three simple comparators for rapid response to the aforementioned steps, a high-efficiency, low-output-voltage-ripple DC-DC converter is achieved without on-chip resistors and capacitors. Specifically, in this embodiment, without on-chip resistors and capacitors, the output voltage V... OUT The peak-to-peak ripple is less than 7mV under the load current range of 0 to 50mA, process angle and temperature changes; the efficiency can reach more than 90% under heavy load (50mA) and more than 73% under light load (1mA).

[0086] Example 2

[0087] The system block diagram of a digital buck DC-DC converter without on-chip resistors and capacitors according to the present invention is as follows: Figure 1 As shown, the on-chip circuitry includes digital control logic, a driver module, an error comparator, a high-clamp comparator, a low-clamp comparator, a delay module, and a power switch. With the help of an off-chip passive feedback network and a low-pass filter, a stable output voltage is obtained.

[0088] The state diagram of digital control logic is as follows: Figure 2 As shown. R EN H is the enable signal for delay module I connected to the error comparator. EN Z is the enable signal for delay module II connected to the high-clamp comparator. EN This is the enable signal for delay module III connected to the low-clamp comparator. P CTRL For power transistor M P The gate drive signal, N CTRL For M N The gate drive signal serves as the input to the drive module, controlling the on / off state of the drive power transistor. CTRL When M is 0, i.e., low level, P The tube is conducting; NCTRL When M is 1, i.e., high level, N The tube is conducting. M is in state 0. P and M N With both transistors off, the error comparator compares the voltage level V. EA Output E through delay module I OUT M in state 1 P On, M N Turn off, high-clamp comparator comparison level V HCOMP Output H via delay module II OUT M in state 2 P Shutdown, M N On, low clamp comparator comparison level V ZCOMP Output Z via delay module III OUT .

[0089] The circuit structure of the drive module is as follows Figure 3 As shown, it includes an inverter chain and an AND gate. An inverter chain is used to drive the power transistors. MOSFETs have bidirectional conduction characteristics, meaning that two power transistors may be conducting simultaneously. To avoid this, a dead time period where neither transistor is conducting is inserted during the switching process. This dead time is set by using a delay through the inverter chain. The signal P generated by the digital control logic... CTRL N CTRL The input signal is used to generate P through an inverter chain and an AND gate. GATE N GATE and P PRE Signal, where P PRE Signal and P GATE Invert the signal. P PRE P is the non-inverting input of the high-clamp comparator. GATE and N GATE There is a time delay between the signals, as indicated by the power transistor M. P M N The gate voltage controls the power transistor's on and off states.

[0090] The circuit structure of the error comparator and the high-clamp comparator is as follows: Figure 4 As shown. Both the error comparator and the high-clamp comparator adopt a two-stage structure with NMOS input transistor pairs. The first stage is a folded cascode structure, with M1 and M2 being NMOS input transistor pairs, and M9 and M... 10 Provides self-biasing voltages for M3, M4, and M7. The two inputs of the error comparator are the output voltage feedback value V. FB and reference voltage V REF By using an off-chip passive feedback network, V FB Feedback is sent to the inverting input of the error comparator, and the non-inverting input of the error comparator is V. REF The bias current I is a fixed value.E It is directly supplied from an external source. The NMOS input pair transistors M1 and M2 are matched, i.e., the offset voltage V0 is... OS =0, using an error comparator instead of the amplifier in a traditional DC-DC converter, eliminating the need for on-chip capacitor compensation.

[0091] The two inputs of the high-clamp comparator are the power transistor output signal V. SW and the output signal P of the drive module PRE Bias current I H Directly supplied from external sources. PRE The signal is related to the power transistor M. P Gate voltage control signal P GATE The opposite square wave signal. Power transistor M P Low voltage conduction, M P When conducting, P PRE The signal is high; M P When P is turned off PRE The signal is low. Therefore, in M P When on, the high-clamp comparator operates normally. The NMOS input pair transistors M1 and M2 have an offset voltage V. OS =V OS1 The comparator in V SW Reaching V DD -V OS1 Flip it over.

[0092] The circuit structure of the low-clamp comparator is as follows: Figure 5 As shown. The two input terminals of the comparator are the power transistor output signal V. SW And zero voltage signal GND, bias current I Z It is directly supplied from an external source. The comparator is implemented using a two-stage structure with PMOS input transistors. The first stage is a folded cascode structure, and the PMOS input transistors M1 and M2 have an offset voltage V. OS =V OS2 The comparator in V SW Reaching -V OS2 Time flip, M9, M 10 Provide self-biasing voltage for M3, M4, and M7.

[0093] The circuit structure of the delay module is as follows: Figure 6 As shown, it includes delay units and AND gates. Three identical delay modules A, B, and C are connected after the comparator, and the digital control logic generates H. EN Z EN R EN The signals are used as inputs to control the enable outputs of the three comparators, resulting in the output signal H. OUT Z OUT E OUT .

[0094] Figure 7 This shows the output voltage V under typical light load conditions. OUT With power transistor output signal V SW The transient simulation waveform. Input voltage V DD =3.3V, output voltage set to V OUT =1.2V (R2=20kΩ), under light load, the load current is 1mA (load R L =1.2kΩ). The simulated power supply efficiency is 78.1%. As can be seen from the graph, the output voltage V... OUT The peak-to-peak value of the ripple is 2.896 mV.

[0095] Figure 8 This shows the output voltage V under typical heavy load conditions. OUT With power transistor output signal V SW The transient simulation waveform. Input voltage V DD =3.3V, output voltage set to V OUT =1.2V (R2=20kΩ), under heavy load, the load current is 50mA (load R L =24Ω). The simulated power supply efficiency is 90.68%. As can be seen from the graph, the output voltage V... OUT The peak-to-peak value of the ripple is 1.712 mV.

[0096] The above description is merely a preferred embodiment of the present invention, and the present invention should not be limited to the content disclosed in this embodiment and the accompanying drawings. Any equivalent or modified embodiments made without departing from the spirit of the present invention fall within the scope of protection of the present invention.

Claims

1. A digitally controlled, on-chip resistorless, step-down DC-DC converter, characterized by: The circuit structure comprises digital control logic, a driving module, an error comparator, a high clamping comparator, a low clamping comparator, a delay module and a power switch tube; The digital control logic is composed of basic digital units; The driving module comprises an inverter chain and an AND gate; The power switch tube comprises a PMOS type power tube M P and an NMOS type power tube M N ; The error comparator adopts a two-stage structure of NMOS input pair to compare the output feedback voltage with a reference voltage, and the generated signal controls the power tube operation; The high clamping comparator adopts two-stage structure of NMOS input tube, the width-length ratio of input tubes is same, and by setting the number ratio of fingers as 10:2, an offset voltage V OS1 is generated at the input end of the comparator. The low clamp comparator adopts two-stage structure of PMOS input tube, the width-length ratio of input tubes is same, and by setting the ratio of finger number as 10:8, an offset voltage V OS2 is generated at the input end of the comparator. The delay module is composed of a delay unit and an AND gate; The connection relationship of the modules in the digitalized DC-DC converter without internal resistance and capacitor is as follows: The digital control logic is connected with the driving module and the delay module, the driving module is connected with the push-pull power switch tube, the power switch tube is connected with the high clamping comparator and the low clamping comparator; the high clamping comparator, the low clamping comparator and the error comparator are connected with three same delay modules respectively, the delay modules are connected with the digital control logic; the error comparator is connected with the passive feedback network outside the chip; the power switch tube is connected with the LC filter outside the chip; the digital control logic outputs five digital signals H EN , Z EN , R EN , P CTRL , N CTRL , wherein H EN , Z EN , R EN are the enable control signals of the high clamping comparator, the low clamping comparator and the error comparator respectively, P CTRL , N CTRL are the input signals of the driving module; the driving module outputs three digital signals P GATE , N GATE , P PRE , wherein P GATE , N GATE are the gate driving signals of the power tubes M P , M N , and P PRE is the positive input end of the high clamping comparator; The working process of the digitalized DC-DC converter without internal resistance and capacitor comprises the following steps: Step one: determine the input voltage and output voltage, and the load current size, and perform power supply and signal connection, which specifically comprises the following sub-steps: Step 1.1 Determine the input voltage V DD and the output voltage V OUT pre-set value, V OUT The pre-set value size depends on the off-chip passive feedback network and the reference voltage V REF ; Step 1.2 Determine if the load current is heavy or light, the magnitude of the load current is determined by the output voltage and the off-chip load resistance R L determination; Step 1.3 bias current setting, the bias current of the three comparators is directly set by an external current source; Step two: power tube M P with M N alternately on-off, output voltage V OUT value rises, and specifically includes the following sub-steps: Step 2.1 Set NRST to low level, circuit reset, then set NRST to high level, circuit normal work; initially, power tube M P and M N are off, R EN is high level, output voltage V OUT is initially 0, its feedback value V FB is 0, less than reference voltage V REF , error comparator comparison level V EA is high level, E OUT delayed by delay module I is high level output to digital control logic; Step 2.2 Digital control logic output H EN High, Z EN Low, R EN Low, P CTRL Low, N CTRL Low, drive module output P GATE Low, N GATE Low, P PRE High, power tube M P On, M N Off; input voltage V DD Through the inductor L to the load R L Power supply, inductor L, capacitor C energy storage, inductor current gradually increases from the minimum to the maximum, the output voltage value V OUT Rise; power tube output signal V SW Rise to the level V DD -V OS1 , high clamping comparator comparison level V HCOMP High, output H after the delay of delay module II OUT From low to high flip feedback to the control logic; Step 2.3 Digital control logic output Z EN High level, H EN Low level, R EN Low level, P CTRL High level, N CTRL High level, drive module output P GATE High level, N GATE High level, P PRE Low level, power tube M N Conduct, M P Turn off; power tube output signal V SW Fall to low level, inductance current cannot jump, inductance current gradually decreases from maximum value, energy storage inductance L continues to supply load R L Supply; comparison level V of low clamping comparator ZCOMP High level, output Z after delay of delay module III OUT Flip from low level to high level feedback to control logic Step 2.4 Digital control logic output R EN high, H EN low, Z EN low, P CTRL high, N CTRL low, driving the output P of the module GATE high, N GATE low, P PRE low, power transistor M P off, M N off; at this time, in the dead time when both transistors are off, the inductance current continues to decrease to the minimum value, the capacitor discharges, and the output voltage V OUT decreases slightly; the output voltage V OUT does not reach the set value, the feedback voltage V FB is less than the reference voltage V REF , the error comparator compares the level V EA is high, and after the delay of the delay module I, the output E OUT is flipped from low to high and fed back to the control logic The above steps are repeated, outputting voltage values V OUT Overall rise; Step three: output voltage V OUT Reaching the set value of step 1.1, establishing steady state, maintaining the output voltage stable, which further includes the following sub-steps: Step 3.1 The output voltage V OUT reaches the set value, the feedback value V FB is greater than or equal to the reference voltage V REF , the error comparator compares the level V EN is high, the error comparator compares the level V EA is low, the delay output E OUT of the delay module I is still low and has not flipped, and the feedback is given to the control logic; Step 3.2 Establishing steady state, digital control logic controls power transistor M P , M N Alternately on-off, output voltage fluctuates at set value; according to the size of the load current, it is divided into heavy load and light load different cases, as follows: 3.2.1 If the load current is heavy, in M P The input voltage is supplied to the load R through the inductor L in the on phase L The inductor L and the capacitor C store energy, and the inductor current gradually increases from the minimum value to the maximum value in the on phase N The inductor current cannot be suddenly changed, and gradually decreases from the maximum value in the off phase L The inductor L continues to supply power to the load R, and the inductor L and the capacitor C store energy in the off phase P , M N The inductor current decreases to the minimum value of zero when both the inductor L and the capacitor C are off L The capacitor C supplies current to the load R, and the load current is maintained at the set value; the greater the load current, the smaller the capacitor discharge time, the smaller the switching period, and the greater the switching frequency, which is in the order of MHz 3.2.2 If the load current is light, in M P , M N both off, because the smaller the load current, the longer the time for the capacitor discharge to maintain the size of the load current, the longer the time for both tubes to be off; a switching cycle increases with the decrease of the load current, and the light load switching frequency is in the order of kHz; Power tube M P , M N Alternately on-off, three comparators adopt simple structure, can fast response above-mentioned step, realize DC-DC converter.

2. The digitally controlled off-chip resistorless buck DC-DC converter of claim 1, wherein: The digital implementation is based on comparators and digital units, only pure MOS tubes are used, no resistance and capacitor are contained in the internal circuit, no complex analog module, the overall architecture only has three comparators, one digital control logic, one digital driving stage, one power stage and three same delay modules, which ensures the realization of digitalization, low power consumption and low cost.

3. The digitally controlled off-chip resistor-capacitor-less step-down DC-DC converter of claim 1, wherein: The digital control logic does not contain complex units, and only realizes the DC-DC converter function through digital logic, which is simple to realize.

4. The digitally controlled off-chip resistor-capacitor-less step-down DC-DC converter of claim 1, wherein: The power switch tube is of push-pull structure, and a diode is replaced by an NMOS tube for synchronous rectification. The power tube completes the conversion and transmission of electric energy through the alternate change of the on and off working states, so as to make the output voltage V OUT Stable at the set value.

5. The digitally controlled off-chip resistor-capacitor-less step-down DC-DC converter of claim 1, wherein: The driving module is composed of an inverter chain and an AND gate. The input signal is P CTRL , N CTRL generated by digital control logic. The output signal is P GATE , N GATE and P PRE , wherein the P PRE signal is opposite to the P GATE signal, the P PRE is used for the positive phase input of the high clamping comparator, and the P GATE and N GATE signals are the gate end voltages of the power tubes M P , M N , which control the conduction and turn-off of the power tubes. Through the delay of the inverter chain, a dead time is inserted during the synchronous conversion of the two power tubes, i.e. the P GATE and N GATE signals have a delay. The soft switching technology based on the dead time control uses MHz switching frequency under heavy load and kHz switching frequency under light load, thereby improving the efficiency of the converter.

6. The digitally controlled off-chip resistor-capacitor-less step-down DC-DC converter of claim 1, wherein: The error comparator adopts two-stage structure of NMOS input pair to realize the output voltage feedback sampling value V FB Comparing with the reference voltage V REF The generated signal controls the power transistor to work; the comparator is used to replace the traditional error amplifier, PWM comparator and slope generator, and there is no need for on-chip capacitor compensation.

7. The digitally controlled off-chip resistor-capacitor-less step-down DC-DC converter of claim 1, wherein: The high clamping comparator adopts a two-stage structure of NMOS input tube, the low clamping comparator adopts a two-stage structure of PMOS input tube, and the input pair tubes of the two comparators are set to have different sizes to have a deviation value, without the help of traditional resistance sampling form, without internal resistance.

8. The digitally controlled off-chip resistor-capacitor-less step-down DC-DC converter of claim 1, wherein: The comparator enable signal generated by the digital control logic plays an enabling role through the delay module input end; the three comparators are output through the delay module and fed back to the digital control logic; the output signals of the two clamping comparators and the error comparator are controlled and driven by the digital control logic to make the output voltage stable, realizing high efficiency and low output voltage ripple.

Images