A low-power RC oscillator applied to a temperature sensor

Abstract

The present invention relates to a low-power RC oscillator applied to a temperature sensor. By means of capacitance multiplication technology and high-order temperature compensation technology, the oscillator reduces the layout area and the output frequency drift caused by temperature changes. In addition, the present invention reduces the influence of non-linear factors caused by the manufacturing process in mass production of the oscillator through multi-range frequency trimming technology. Through structural optimization and technological innovation, the invention can achieve a highly stable effect at low power consumption and is applicable to temperature sensor systems.

Description

Technical Field

[0001] The present invention relates to a low-power RC oscillator applied to a temperature sensor. Background Art

[0002] The requirements for the chip size of Internet of Things nodes with continuously shrinking volume are becoming increasingly stringent. To save external clock crystals, on-chip RC oscillators have become an effective alternative. However, temperature, voltage variations, and internal noise can all cause frequency deviations in RC oscillators. When the frequency deviations accumulate to cause large timing errors, serious problems such as signal transceiver mismatch and data packet loss will occur. The traditional comparator-type RC oscillator consists of a reference current, a charge-discharge capacitor, a comparator, and an RS flip-flop. Its working principle is to use a constant current to periodically charge and discharge the capacitor, and then compare it with the reference voltage at the inverting input terminal of the comparator. When it is lower or higher than the reference voltage, the state of the output terminal changes, and finally a clock signal with a certain frequency is obtained. However, due to factors such as delay and temperature in the actual circuit, it will seriously affect the oscillation frequency. Summary of the Invention

[0003] The purpose of the present invention is to provide a low-power RC oscillator applied to a temperature sensor. The oscillator reduces the layout area and the output frequency drift caused by temperature changes through capacitance multiplication technology and high-order temperature compensation technology. In addition, the present invention reduces the influence of non-linear factors caused by the manufacturing process in mass production of the oscillator through multi-range frequency trimming technology.

[0004] To achieve the above purpose, the technical solution of the present invention is: a low-power RC oscillator applied to a temperature sensor, including a chopper operational amplifier, a capacitance multiplier, a voltage-controlled oscillator, a two-phase non-overlapping signal generation circuit, a calibration circuit, a resistor calibration and temperature compensation circuit connected in sequence, and further including a current bias circuit for providing current bias for the entire RC oscillator.

[0005] In an embodiment of the present invention, the current bias circuit itself is a bandgap reference source inside. The bias current ratio of two PNP transistors in the current bias circuit is 5:1. The current mirror adopts a cascode structure. The bandgap reference circuit makes the input terminal voltages of the operational amplifier equal, and the ΔVBE voltage is applied to the bias resistor Rbias, thereby generating a PTAT bias current Ibias = ΔVBE / Rbias; the current bias circuit also adopts a finite current gain compensation technology, that is, a Rbias / m resistor is connected in series on the base stage of the BJT transistor with large current bias for compensation.

[0006] In an embodiment of the present invention, the voltage-controlled oscillator adopts a leakage-based differential ring oscillator, which uses the leakage of transistors to complete signal inversion and generate a clock. By using a differential structure, the common-mode noise suppression ability of the oscillator is improved, and it can operate at a low supply voltage of 0.7V, is insensitive to voltage changes, and generates a more stable clock with lower power consumption.

[0007] In an embodiment of the present invention, the voltage-controlled oscillator includes transistors M1 to M10, and capacitors C1 and C2. The gates of M1 and M2 are respectively connected to the gates of M7 and M8, and are respectively used as two inputs of the voltage-controlled oscillator. The sources of M1 and M2 are both connected to the power supply terminal. The drains of M1 and M2 are respectively connected to the sources of M3 and M4. The gates of M3 and M4 are respectively connected to the gates of M5 and M6. And the gate of M3 is also connected to the drains of M4, M6, and M10 and one end of C2, and serves as the first output of the voltage-controlled oscillator. The gate of M4 is also connected to the drains of M3, M5, and M9 and one end of C1, and serves as the second output of the voltage-controlled oscillator. The sources of M5 and M6 are respectively connected to the drains of M7 and M8. The sources of M7 and M8 are connected to the sources of M9 and M10 and the other ends of C1 and C2 and are connected to the ground terminal. The gates of M9 and M10 are both used as the control voltage input terminals of the voltage-controlled oscillator.

[0008] In an embodiment of the present invention, the working mode of the voltage-controlled oscillator is as follows: when the control voltage VCTRL is valid, the two high-threshold nmos transistors M9 and M10 are in the sub-threshold conduction state, and the first output OUTP of the voltage-controlled oscillator and the second output OUTN of the voltage-controlled oscillator are complementary signals. When they are used as two inputs INP and INN of the next-stage voltage-controlled oscillator, they are also complementary signals. Its working process is: when INP is a high signal, the nmos transistor M7 conducts, and M9 and M7 form a discharge path to discharge the charge stored on the capacitor C to the ground. VCTRL always remains constant in the locked state, and the corresponding branch always discharges with a constant current. Therefore, the OUTN signal drops at a constant slope of I M9 / C, where I M9 is the current flowing through the nmos transistor M9, and C is the capacitance value of the capacitor C1; when OUTN drops to the inverter threshold voltage, under the action of the conducting M2, the OUTP signal will be quickly charged to the power supply voltage, that is, OUTN quickly flips to high, causing the complementary signal OUTN to be quickly pulled down from the threshold voltage to the ground, and the delay unit completes one flip; during this process, the left branch actually only plays a pulling-down role, and only the pmos transistor in the right branch plays a pulling-up role, and uses the positive feedback of the reciprocal relationship between OUTN and OUTP to complete the quick flip; ignoring the short flip time promoted by the positive feedback, a same-direction delay of ΔVC / I M9 is achieved from the input signal INP to the output signal OUTP, where ΔVC is the voltage difference between the capacitors C1 and C2.

[0009] In an embodiment of the present invention, the two-phase non-overlapping signal generation circuit includes transistors M1 to M8. The gates of M1 and M2 are respectively used as two inputs of the two-phase non-overlapping signal generation circuit. The sources of M1 and M2 are connected to the ground terminal in common with the sources of M3 and M4. The drains of M1 and M2 are respectively connected to the gates of M3 and M4, the sources of M5 and M6, and the gates of M7 and M8. The drain of M1 is further connected to the drains of M4, M6, and M8 as the first output of the two-phase non-overlapping signal generation circuit. The drain of M2 is further connected to the drains of M3, M5, and M7 as the second output of the two-phase non-overlapping signal generation circuit. The gates of M5 and M6 are connected to the sources of M7 and M8 and then connected to the power supply terminal.

[0010] In an embodiment of the present invention, the two-phase non-overlapping signal generation circuit operates as follows:

[0011] Let the first input VCOCLK and the second input VCOCLKN of the two-phase non-overlapping signal generation circuit be a set of inverted signals of the clock signal output by the VCO, and φ+ and φ- be two-phase non-overlapping clock signals generated by the two-phase non-overlapping signal generation circuit. When VCOCLK is high, φ+ is low, and M7 will gradually pull up the φ- signal, and a short non-overlapping time is generated between φ+ and φ-. During this pulling-up process, M2 and M3 are in the off state, and there is no direct current path between the power supply terminal and the ground terminal. Therefore, the circuit has extremely low static power consumption.

[0012] In an embodiment of the present invention, the capacitor multiplier is an operational amplifier-based capacitor multiplier circuit, including resistors R1 and R2, capacitor C1, and an operational amplifier. One end of R1 is connected to one end of R2 as the input terminal of the capacitor multiplier. The other end of R1 is connected to the ground terminal through C1, and the other end of R1 is also connected to the non-inverting input terminal of the operational amplifier. The other end of R2 is connected to the inverting input terminal and the output terminal of the operational amplifier and serves as the output terminal of the capacitor multiplier. If the gain of the operational amplifier is large, according to the "virtual short" principle, U + =U - =U o ; the current flowing through R1 is I1 = (U i -U o ) / R1, and U i , U o are the input voltage and output voltage of the capacitor multiplier respectively. Then, according to the "virtual open" principle, it can be obtained that:

[0013]

[0014] The output equivalent capacitance is

[0015]

[0016] From formulas (1) and (2), the equivalent capacitance can be obtained as

[0017] In an embodiment of the present invention, the calibration circuit is a gated capacitor array circuit for coarsely adjusting the oscillator frequency.

[0018] In an embodiment of the present invention, the resistor calibration and temperature compensation circuit adopts a high-order temperature compensation technique. By mixing polysilicon resistors with negative temperature coefficients and diffusion resistors with positive temperature coefficients in a predetermined ratio, a resistor with a relatively small change in resistance value with temperature is obtained. However, due to the non-linearity of the resistor temperature coefficient at this time, the mixed resistor still has a temperature coefficient. Therefore, in order to obtain a resistor with a lower temperature coefficient, a second-order compensation is performed on it using a compensation current.

[0019] Compared with the prior art, the present invention has the following beneficial effects: Aiming at the contradiction between temperature and power supply voltage stability in the charge and discharge branches of the oscillator, the present invention proposes an operational amplifier with a chopper structure and a circuit structure with temperature compensation, and uses a capacitor multiplication technique to reduce problems such as frequency error introduced by the delay of the operational amplifier, high-temperature leakage, and large layout area, and ensures a constant proportional relationship of the charge and discharge current. For resistors and offset voltages with obvious linear temperature coefficients, a resistor array with linear temperature compensation is designed to obtain the minimum frequency temperature drift, and a two-point trimming circuit is designed to improve the mismatch of the linear coefficient caused by process mismatch, ensuring high stability under various process corners. Description of the Drawings

[0020] Figure 1 It is a block diagram of a low-power RC oscillator structure.

[0021] Figure 2 It is a schematic diagram of a chopper operational amplifier.

[0022] Figure 3 It is a schematic diagram of a capacitor multiplier circuit.

[0023] Figure 4 It is a schematic diagram of a capacitor multiplier operational amplifier.

[0024] Figure 5 It is a schematic diagram of a voltage-controlled oscillator.

[0025] Figure 6 It is a schematic diagram of a two-phase non-overlapping signal generation circuit.

[0026] Figure 7 It is a schematic diagram of a calibration circuit.

[0027] Figure 8 It is a schematic diagram of a current bias circuit.

[0028] Figure 9 It is a schematic diagram of a resistance calibration and temperature compensation circuit.

[0029] In the figure, 1 is a chopper operational amplifier, 2 is a capacitor multiplier, 3 is a voltage-controlled oscillator, 4 is a two-phase non-overlapping signal generation circuit, 5 is a calibration circuit, 6 is a resistance calibration and temperature compensation circuit, 7 is a current bias circuit, and 201 is a capacitor multiplier operational amplifier. Specific implementation mode

[0030] The technical solution of the present invention will be specifically described below with reference to the accompanying drawings.

[0031] As Figures 1-9 shown, a low-power RC oscillator applied to a temperature sensor according to the present invention includes a chopper operational amplifier 1, a capacitor multiplier 2, a voltage-controlled oscillator 3, a two-phase non-overlapping signal generation circuit 4, a calibration circuit 5, a resistance calibration and temperature compensation circuit 6 connected in sequence, and also includes a current bias circuit 7 for providing current bias for the entire RC oscillator.

[0032] The present invention proposes a low-power RC oscillator applied to a temperature sensor. The oscillator reduces the layout area and the output frequency drift caused by temperature changes through capacitor multiplication technology and high-order temperature compensation technology. In addition, the present invention reduces the influence of non-linear factors caused by the manufacturing process in mass production of the oscillator through multi-range frequency trimming technology.

[0033] As shown in the attached Figure 1 figure, in the present invention, the oscillation frequency of the voltage-controlled oscillator is controlled by the output DC voltage of the error amplifier. Its output generates a non-overlapping clock signal through a non-overlapping clock generation module to control the switched capacitor. The switched capacitor converts the frequency quantity into a voltage quantity (the voltage quantity here is the average voltage), and the generated voltage change is used to adjust the output voltage of the error amplifier, and finally completes the locking of the frequency, making the frequency gradually tend to be stable.

[0034] In the present invention, the current bias circuit provides current bias for the entire RC oscillator. It is itself a bandgap reference source inside. The bias current ratio of the two PNP transistors in the circuit is 5:1, and the current mirror adopts a cascode structure to improve the output current accuracy of the current mirror. The traditional bandgap reference circuit makes the input voltages of the operational amplifier equal, and applies the ΔVBE voltage to the bias resistor Rbias, thereby generating a PTAT bias current Ibias = ΔVBE / Rbias. In addition, the current bias circuit also adopts a limited current gain compensation technology. The limited current gain compensation technology of the present invention is very simple in circuit structure. As Figure 8 shown, compensating can be achieved by connecting an Rbias / m resistor in series on the base of the BJT transistor with a large current bias.

[0035] As Figure 5 shown, the voltage-controlled oscillator in the present invention adopts a differential ring oscillator based on leakage, uses the leakage of transistors to complete signal inversion and generate a clock; uses a differential structure to improve the common-mode noise suppression ability of the oscillator, and can operate at a low supply voltage of 0.7V, is insensitive to voltage changes, and generates a more stable clock with lower power consumption.

[0036] When VCTRL is an effective control voltage, the two high-threshold nmos transistors M9 and M10 are in the sub-threshold conduction state, and OUTP and OUTN are complementary signals, and they are also complementary signals when used as the inputs INP and INN of the next stage. Its working process is as follows: when INP is a high signal, the nmos transistor M7 conducts, and M9 and M7 form a discharge path to discharge the charge stored on the capacitor C to the ground. VCTRL always remains constant in the locked state, and this branch always discharges with a constant current. Therefore, the OUTN signal drops at a constant slope of I M9 / C; where I M9 is the current flowing through the nmos transistor M9, and C is the capacitance value of the capacitor C1. When OUTN drops to the threshold voltage of the inverter, under the action of the conducting M2, the OUTP signal will be quickly charged to the supply voltage, that is, OUTN quickly flips to high, causing the complementary signal OUTN to be quickly pulled low from the threshold voltage to the ground, and the delay unit completes one flip. During this process, the left branch of the delay unit only plays a pulling-down role in fact, and only the pmos transistor in the right branch plays a pulling-up role, and uses the positive feedback of the reciprocal relationship between OUTN and OUTP to complete the quick flip. Ignoring the short transient flip time promoted by the positive feedback, the delay unit realizes a co-directional delay of ΔVC / I M9 from the input signal INP to the output signal OUTP, where ΔVC is the voltage difference between the capacitors C1 and C2.

[0037] The two-phase non-overlapping signal generation circuit of the present invention is as Figure 6 , where VCOCLK and VCOCLKN are a set of complementary signals of the clock signal output by the VCO, and φ+ and φ- are the two-phase non-overlapping clock signals generated. When VCOCLK is high, φ+ is low, and M7 will gradually pull up the φ- signal, and φ+ and φ- generate a short non-overlapping time. During this pulling-up process, M2 and M3 are in the off state, and there is no direct current path between VDD and VSS. Therefore, the circuit has extremely low static power consumption.

[0038] As Figure 3 , 4 The capacitor multiplier of the present invention is a capacitor multiplier circuit based on an operational amplifier. If the gain of the operational amplifier 201 is large, then according to the principle of "virtual short", U + =U - =U o。The current flowing through R1 is I1 = (U i -U o ) / R1. Then, according to the "virtual open" principle, it can be obtained that:

[0039]

[0040] The output equivalent capacitance is

[0041]

[0042] From formulas (2-1) and (2-2), the equivalent capacitance can be obtained as

[0043] As Figure 8 shown, the calibration circuit of the present invention is a gated capacitor array circuit, and its function is to coarsely adjust the oscillator frequency.

[0044] The resistance calibration and temperature compensation circuit of the present invention adopts a high-order temperature compensation technology. By mixing polysilicon resistors with negative temperature coefficients and diffusion resistors with positive temperature coefficients in a certain proportion, a resistor with a relatively small resistance change with temperature can be obtained. However, at this time, due to the non-linearity of the resistor temperature coefficient, the mixed resistor still has a certain temperature coefficient.

[0045] Therefore, in order to obtain a resistor with a lower temperature coefficient, a compensation current is used to perform second-order compensation on it. The circuit is as Figure 9 。

[0046] The above are the preferred embodiments of the present invention. All changes made according to the technical solution of the present invention, when the functions and effects generated do not exceed the scope of the technical solution of the present invention, shall fall within the protection scope of the present invention.

Claims

1. A low-power RC oscillator applied to a temperature sensor, characterized in that, It includes a chopper operational amplifier, a capacitor multiplier, a voltage-controlled oscillator, a two-phase non-overlapping signal generation circuit, a calibration circuit, a resistor calibration and temperature compensation circuit connected in sequence, and also includes a current bias circuit for providing current bias for the entire RC oscillator; the current bias circuit itself is a bandgap reference source internally. The bias current ratio of the two PNP transistors in the current bias circuit is 5:

1. The current mirror adopts a cascode structure. The bandgap reference circuit makes the input voltages of the operational amplifier equal, and applies the ΔVBE voltage across the bias resistor Rbias, thereby generating a PTAT bias current Ibias = ΔVBE / Rbias; the current bias circuit also adopts a finite current gain compensation technique, that is, a Rbias / m resistor is connected in series at the base of the BJT transistor with large current bias for compensation; the voltage-controlled oscillator adopts a leakage-based differential ring oscillator, uses the leakage of the transistor to complete signal inversion, and generates a clock; by using a differential structure, it improves the common-mode noise suppression ability of the oscillator and can operate at a low supply voltage of 0.7V and is insensitive to voltage changes; the voltage-controlled oscillator includes transistors M1 to M10, capacitors C1, C2. The gates of M1 and M2 are respectively connected to the gates of M7 and M8 and serve as the two inputs of the voltage-controlled oscillator. The sources of M1 and M2 are both connected to the power supply terminal. The drains of M1 and M2 are respectively connected to the sources of M3 and M4. The gates of M3 and M4 are respectively connected to the gates of M5 and M6. And the gate of M3 is also connected to the drains of M4, M6, M10 and one end of C2 and serves as the first output of the voltage-controlled oscillator. The gate of M4 is also connected to the drains of M3, M5, M9 and one end of C1 and serves as the second output of the voltage-controlled oscillator. The sources of M5 and M6 are respectively connected to the drains of M7 and M8. The sources of M7 and M8 are connected to the sources of M9 and M10 and the other ends of C1 and C2 and then connected to the ground terminal. The gates of M9 and M10 both serve as the control voltage input terminals of the voltage-controlled oscillator.

2. The low-power RC oscillator applied to a temperature sensor according to claim 1, characterized in that, The working mode of the voltage-controlled oscillator is as follows: when the control voltage VCTRL is valid, the two high-threshold nmos transistors M9 and M10 are in sub-threshold conduction states, and the first output OUTP of the voltage-controlled oscillator and the second output OUTN of the voltage-controlled oscillator are complementary signals, and they are also complementary signals when serving as the two inputs INP and INN of the next-stage voltage-controlled oscillator; Its working process is as follows: When INP is a high signal, the nmos transistor M7 conducts, and M9 and M7 form a discharge path to discharge the charge stored on the capacitor C to the ground. VCTRL always remains constant in the locked state, and the corresponding branch always discharges with a constant current. Therefore, the OUTN signal decreases at a constant slope of I M9 / C, where I M9 is the current flowing through the nmos transistor M9, and C is the capacitance value of the capacitor C1; when OUTN drops to the inverter threshold voltage, under the action of the conducting M2, the OUTP signal will be quickly charged to the power supply voltage, that is, OUTN quickly flips to high, causing the inverse signal OUTN to be quickly pulled down from the threshold voltage to the ground, and the delay unit completes one flip; during this process, the left branch actually only plays a pulling-down role, and only the pmos transistor in the right branch plays a pulling-up role, and uses the positive feedback of the reciprocal relationship between OUTN and OUTP to complete a quick flip; ignoring the short flip time promoted by the positive feedback, a positive delay of ΔVC / I M9 is achieved from the input signal INP to the output signal OUTP, where ΔVC is the voltage difference between the capacitors C1 and C2.

3. The low-power RC oscillator applied to a temperature sensor according to claim 1, characterized in that, The two-phase non-overlapping signal generation circuit includes transistors M1 to M8. The gates of M1 and M2 respectively serve as the two inputs of the two-phase non-overlapping signal generation circuit. The sources of M1 and M2 are connected to the sources of M3 and M4 and then connected to the ground terminal. The drains of M1 and M2 are respectively connected to the gates of M3 and M4, the sources of M5 and M6, and the gates of M7 and M8. The drain of M1 is also connected to the drains of M4, M6, M8 and serves as the first output of the two-phase non-overlapping signal generation circuit. The drain of M2 is also connected to the drains of M3, M5, M7 and serves as the second output of the two-phase non-overlapping signal generation circuit. The gates of M5 and M6 are connected to the sources of M7 and M8 and then connected to the power supply terminal.

4. A low-power RC oscillator applied to a temperature sensor according to claim 3, characterized in that, The operation mode of the two-phase non-overlapping signal generation circuit is as follows: Let the first input VCOCLK and the second input VCOCLKN of the two-phase non-overlapping signal generation circuit be a set of inverted signals of the clock signal output by the VCO, and φ+ and φ- be the two-phase non-overlapping clock signals generated by the two-phase non-overlapping signal generation circuit. When VCOCLK is high, φ+ is low, and M7 will gradually pull up the φ- signal, creating a short non-overlapping time between φ+ and φ-. During this pulling-up process, M2 and M3 are in the off state, and there is no direct current path between the power supply terminal and the ground terminal.

5. A low-power RC oscillator applied to a temperature sensor according to claim 1, characterized in that, The capacitor multiplier is an operational amplifier-based capacitor multiplier circuit, including resistors R1 and R2, capacitor C1, and an operational amplifier. One end of R1 is connected to one end of R2 as the input end of the capacitor multiplier. The other end of R1 is connected to the ground through C1, and the other end of R1 is also connected to the non-inverting input end of the operational amplifier. The other end of R2 is connected to the inverting input end and the output end of the operational amplifier and serves as the output end of the capacitor multiplier. If the gain of the operational amplifier is greater than a preset value, according to the "virtual short" principle, U + = U - = U o ; The current flowing through R1 is I1 = (U i - U o ) / R1, where U i and U o are the input voltage and output voltage of the capacitor multiplier respectively. Then, according to the "virtual open" principle, we can get: The output equivalent capacitance is The equivalent capacitance can be obtained from equations (1) and (2) as 6. A low-power RC oscillator applied to a temperature sensor according to claim 1, characterized in that, The calibration circuit is a gated capacitor array circuit for coarsely adjusting the oscillator frequency.

7. A low-power RC oscillator applied to a temperature sensor according to claim 1, characterized in that, The resistor calibration and temperature compensation circuit adopts a high-order temperature compensation technique. By mixing polysilicon resistors with negative temperature coefficients and diffusion resistors with positive temperature coefficients in a predetermined ratio, a resistor with a relatively small resistance change with temperature is obtained. However, due to the non-linearity of the resistor temperature coefficient, the mixed resistor still has a temperature coefficient. Therefore, to obtain a resistor with a lower temperature coefficient, a second-order compensation is performed using a compensation current.

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